Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wake_events_cdc	57.45	82.35	30.77			66.67	50.00
tb.dut.u_reg.u_wake_control_cdc	97.73	100.00	90.91			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wake_events_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
57.45	82.35	30.77			66.67	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
47.09	75.78	29.41			63.16	20.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.47	99.76	98.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	39.21	72.45	28.57			55.81	0.00
u_src_to_dst_req	56.41	92.31	33.33			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_wake_control_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	96.08	96.43			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.47	99.76	98.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.88	87.50	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Unreachable
1	0	Covered	T1,T58,T59

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T58,T59
1	1	Covered	T1,T58,T59

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T58,T59

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T58,T59
1	1	Covered	T1,T58,T59

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T4
0	1	-	Covered	T1,T58,T59
0	0	1	Covered	T1,T58,T59
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T4
0	1	-	Covered	T1,T58,T59
0	0	1	Covered	T1,T58,T59
0	0	0	Covered	T2,T3,T4

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1047637542	237579	0	0
DstReqKnown_A	23604910	23572752	0	0
SrcAckBusyChk_A	1047637542	986	0	0
SrcBusyKnown_A	1047637542	1047314966	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047637542	237579	0	0
T1	4318	301	0	0
T51	3476	133	0	0
T58	10889	4763	0	0
T59	50173	17741	0	0
T93	3219	118	0	0
T94	2427	575	0	0
T95	4653	2181	0	0
T96	4276	1100	0	0
T97	4071	1542	0	0
T98	21995	8532	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23604910	23572752	0	0
T2	10042	10032	0	0
T3	30030	30018	0	0
T4	21398	21368	0	0
T5	26720	26702	0	0
T10	21178	21168	0	0
T11	16006	15994	0	0
T17	21092	21080	0	0
T18	6088	6070	0	0
T19	11340	11326	0	0
T20	8508	8490	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047637542	986	0	0
T1	4318	2	0	0
T51	3476	2	0	0
T58	10889	23	0	0
T59	50173	62	0	0
T93	3219	2	0	0
T94	2427	6	0	0
T95	4653	17	0	0
T96	4276	12	0	0
T97	4071	13	0	0
T98	21995	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047637542	1047314966	0	0
T2	806220	806080	0	0
T3	803096	802912	0	0
T4	803118	802826	0	0
T5	802638	802438	0	0
T10	803614	803482	0	0
T11	811284	811112	0	0
T17	804760	804608	0	0
T18	816446	816284	0	0
T19	810080	809960	0	0
T20	805742	805608	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	14	82.35
CONT_ASSIGN	65	0	0
ALWAYS	71	5	4	80.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	7	5	71.43
CONT_ASSIGN	150	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65		unreachable
71	1	1
72	1	1
73	1	1
74		unreachable
75	1	1
76	0	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123		unreachable
124		unreachable
125	1	1
134	0	1
135	0	1
			MISSING_ELSE
150		unreachable
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Total	Covered	Percent
Conditions	13	4	30.77
Logical	13	4	30.77
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Line No.	Total	Covered	Percent
Branches		6	4	66.67
IF	71	3	2	66.67
IF	115	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T4
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T4
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	523818771	0	0	0
DstReqKnown_A	11802455	11786376	0	0
SrcAckBusyChk_A	523818771	0	0	0
SrcBusyKnown_A	523818771	523657483	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11802455	11786376	0	0
T2	5021	5016	0	0
T3	15015	15009	0	0
T4	10699	10684	0	0
T5	13360	13351	0	0
T10	10589	10584	0	0
T11	8003	7997	0	0
T17	10546	10540	0	0
T18	3044	3035	0	0
T19	5670	5663	0	0
T20	4254	4245	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Unreachable
1	0	Covered	T1,T58,T59

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T58,T59
1	1	Covered	T1,T58,T59

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Unreachable
1	0	Covered	T1,T58,T59

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T58,T59
1	1	Covered	T1,T58,T59

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T4
0	1	-	Covered	T1,T58,T59
0	0	1	Covered	T1,T58,T59
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T4
0	1	-	Covered	T1,T58,T59
0	0	1	Covered	T1,T58,T59
0	0	0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	523818771	237579	0	0
DstReqKnown_A	11802455	11786376	0	0
SrcAckBusyChk_A	523818771	986	0	0
SrcBusyKnown_A	523818771	523657483	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	237579	0	0
T1	4318	301	0	0
T51	3476	133	0	0
T58	10889	4763	0	0
T59	50173	17741	0	0
T93	3219	118	0	0
T94	2427	575	0	0
T95	4653	2181	0	0
T96	4276	1100	0	0
T97	4071	1542	0	0
T98	21995	8532	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11802455	11786376	0	0
T2	5021	5016	0	0
T3	15015	15009	0	0
T4	10699	10684	0	0
T5	13360	13351	0	0
T10	10589	10584	0	0
T11	8003	7997	0	0
T17	10546	10540	0	0
T18	3044	3035	0	0
T19	5670	5663	0	0
T20	4254	4245	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	986	0	0
T1	4318	2	0	0
T51	3476	2	0	0
T58	10889	23	0	0
T59	50173	62	0	0
T93	3219	2	0	0
T94	2427	6	0	0
T95	4653	17	0	0
T96	4276	12	0	0
T97	4071	13	0	0
T98	21995	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0