Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	318177	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	516449	1		T1	6		T2	5		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	563885	1		T1	4		T2	2		T3	3
values[0x0]	135022	1		T1	4		T2	4		T3	4
values[0x1]	135719	1		T1	3		T2	3		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	242763	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	591863	1		T1	7		T2	7		T3	7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4028	1		T12	52		T37	1		T53	3
valid_sources[0x01]	2509	1		T12	37		T53	5		T13	1
valid_sources[0x02]	3987	1		T12	52		T285	1		T53	10
valid_sources[0x03]	2978	1		T12	39		T53	1		T13	32
valid_sources[0x04]	2624	1		T16	2		T12	53		T31	2
valid_sources[0x05]	3045	1		T12	72		T83	1		T53	4
valid_sources[0x06]	2967	1		T12	51		T53	4		T13	86
valid_sources[0x07]	2675	1		T12	54		T192	1		T53	1
valid_sources[0x08]	3723	1		T2	9		T12	77		T53	2
valid_sources[0x09]	2817	1		T12	22		T37	1		T286	1
valid_sources[0x0a]	3177	1		T12	74		T81	1		T53	6
valid_sources[0x0b]	2985	1		T12	57		T53	4		T13	1
valid_sources[0x0c]	4003	1		T12	65		T287	2		T53	7
valid_sources[0x0d]	2794	1		T12	37		T53	17		T54	11
valid_sources[0x0e]	2361	1		T12	33		T53	6		T23	3
valid_sources[0x0f]	2922	1		T12	35		T38	2		T53	1
valid_sources[0x10]	2862	1		T1	2		T17	1		T12	49
valid_sources[0x11]	2844	1		T12	51		T83	1		T53	6
valid_sources[0x12]	2495	1		T12	31		T53	2		T14	32
valid_sources[0x13]	2701	1		T12	77		T30	12		T53	14
valid_sources[0x14]	3241	1		T12	37		T85	1		T53	4
valid_sources[0x15]	2968	1		T12	49		T53	2		T13	2
valid_sources[0x16]	3452	1		T12	53		T84	7		T53	10
valid_sources[0x17]	2442	1		T1	2		T12	25		T53	3
valid_sources[0x18]	3019	1		T12	49		T53	4		T13	2
valid_sources[0x19]	2349	1		T12	46		T53	6		T13	3
valid_sources[0x1a]	3025	1		T12	41		T31	1		T32	4
valid_sources[0x1b]	3233	1		T12	55		T53	3		T288	1
valid_sources[0x1c]	2476	1		T20	2		T12	43		T39	6
valid_sources[0x1d]	6229	1		T12	63		T53	4		T13	3014
valid_sources[0x1e]	2798	1		T12	52		T15	10		T53	3
valid_sources[0x1f]	3383	1		T12	50		T53	9		T14	36
valid_sources[0x20]	3077	1		T12	30		T53	2		T54	6
valid_sources[0x21]	2440	1		T18	1		T12	42		T53	3
valid_sources[0x22]	5848	1		T18	1		T12	63		T53	3
valid_sources[0x23]	3127	1		T12	40		T81	1		T53	2
valid_sources[0x24]	2619	1		T12	36		T286	1		T53	6
valid_sources[0x25]	2818	1		T16	2		T20	1		T12	39
valid_sources[0x26]	2538	1		T12	25		T53	3		T13	48
valid_sources[0x27]	2607	1		T12	34		T286	1		T84	1
valid_sources[0x28]	3285	1		T19	11		T12	43		T38	1
valid_sources[0x29]	2428	1		T12	56		T53	2		T23	1
valid_sources[0x2a]	6582	1		T12	51		T53	1		T14	35
valid_sources[0x2b]	2587	1		T1	1		T12	48		T53	6
valid_sources[0x2c]	2732	1		T1	1		T12	63		T82	1
valid_sources[0x2d]	2957	1		T12	49		T85	1		T54	4
valid_sources[0x2e]	3158	1		T12	39		T38	1		T53	11
valid_sources[0x2f]	4789	1		T20	1		T12	56		T22	2
valid_sources[0x30]	3524	1		T12	74		T41	1		T34	1
valid_sources[0x31]	3098	1		T12	53		T41	1		T53	2
valid_sources[0x32]	2832	1		T12	52		T53	5		T13	3
valid_sources[0x33]	3029	1		T12	75		T37	1		T53	2
valid_sources[0x34]	2634	1		T12	47		T48	6		T235	1
valid_sources[0x35]	2511	1		T12	41		T286	1		T53	4
valid_sources[0x36]	2497	1		T16	1		T12	59		T53	5
valid_sources[0x37]	3681	1		T12	49		T81	2		T53	4
valid_sources[0x38]	3299	1		T12	47		T31	1		T81	1
valid_sources[0x39]	2692	1		T12	28		T53	5		T288	1
valid_sources[0x3a]	2489	1		T12	52		T53	6		T14	56
valid_sources[0x3b]	2621	1		T12	30		T53	1		T13	3
valid_sources[0x3c]	3282	1		T18	1		T12	48		T37	1
valid_sources[0x3d]	3340	1		T12	53		T53	1		T23	1
valid_sources[0x3e]	2719	1		T18	1		T12	50		T54	1
valid_sources[0x3f]	2821	1		T12	49		T53	3		T289	8
valid_sources[0x40]	3443	1		T12	33		T81	1		T53	3
valid_sources[0x41]	2694	1		T12	67		T131	1		T53	4
valid_sources[0x42]	2876	1		T1	2		T12	45		T33	3
valid_sources[0x43]	3445	1		T12	41		T53	8		T13	2
valid_sources[0x44]	3806	1		T12	77		T37	1		T32	1
valid_sources[0x45]	2393	1		T12	54		T53	9		T13	2
valid_sources[0x46]	3149	1		T12	58		T22	1		T53	1
valid_sources[0x47]	5834	1		T12	48		T287	2		T85	1
valid_sources[0x48]	4186	1		T12	60		T37	1		T53	8
valid_sources[0x49]	3266	1		T12	53		T8	1		T32	1
valid_sources[0x4a]	2700	1		T12	38		T37	1		T54	4
valid_sources[0x4b]	2598	1		T12	24		T286	1		T53	3
valid_sources[0x4c]	2519	1		T12	51		T31	1		T53	7
valid_sources[0x4d]	3339	1		T12	60		T5	7		T53	5
valid_sources[0x4e]	5935	1		T12	33		T22	1		T53	3
valid_sources[0x4f]	3130	1		T12	43		T85	1		T53	6
valid_sources[0x50]	2879	1		T12	65		T53	8		T13	1
valid_sources[0x51]	2639	1		T12	40		T290	1		T53	5
valid_sources[0x52]	3406	1		T12	50		T53	8		T13	12
valid_sources[0x53]	2617	1		T16	2		T12	52		T53	6
valid_sources[0x54]	3645	1		T12	44		T53	3		T289	6
valid_sources[0x55]	3469	1		T12	42		T34	1		T9	4
valid_sources[0x56]	2911	1		T12	60		T53	3		T23	1
valid_sources[0x57]	2823	1		T12	57		T81	1		T83	1
valid_sources[0x58]	3400	1		T12	52		T291	10		T53	9
valid_sources[0x59]	4895	1		T12	49		T53	6		T13	175
valid_sources[0x5a]	2702	1		T12	38		T53	9		T13	2
valid_sources[0x5b]	3079	1		T12	55		T53	6		T23	1
valid_sources[0x5c]	3526	1		T16	1		T12	57		T85	1
valid_sources[0x5d]	4090	1		T16	2		T12	61		T53	6
valid_sources[0x5e]	2779	1		T12	41		T38	1		T39	1
valid_sources[0x5f]	3101	1		T12	55		T13	3		T54	7
valid_sources[0x60]	3771	1		T16	1		T18	1		T12	59
valid_sources[0x61]	2954	1		T12	64		T53	8		T13	2
valid_sources[0x62]	3410	1		T12	69		T53	1		T14	47
valid_sources[0x63]	2861	1		T12	59		T53	7		T13	3
valid_sources[0x64]	3970	1		T12	68		T85	1		T53	3
valid_sources[0x65]	2784	1		T12	53		T53	4		T54	18
valid_sources[0x66]	2638	1		T12	51		T34	1		T290	1
valid_sources[0x67]	3032	1		T12	42		T53	3		T13	2
valid_sources[0x68]	7150	1		T12	33		T52	209		T53	5
valid_sources[0x69]	5571	1		T12	60		T192	2		T85	1
valid_sources[0x6a]	2881	1		T12	52		T53	8		T54	10
valid_sources[0x6b]	2959	1		T18	1		T12	46		T53	2
valid_sources[0x6c]	3654	1		T12	33		T38	1		T53	5
valid_sources[0x6d]	4423	1		T12	44		T37	1		T286	1
valid_sources[0x6e]	3065	1		T12	62		T286	1		T32	1
valid_sources[0x6f]	2997	1		T12	33		T53	1		T23	1
valid_sources[0x70]	3201	1		T12	37		T53	2		T49	1
valid_sources[0x71]	2588	1		T12	62		T53	3		T54	12
valid_sources[0x72]	2902	1		T16	2		T20	1		T12	44
valid_sources[0x73]	3062	1		T12	43		T53	6		T13	1
valid_sources[0x74]	2858	1		T18	1		T12	36		T13	3
valid_sources[0x75]	6074	1		T12	38		T53	7		T13	3
valid_sources[0x76]	2839	1		T12	26		T81	7		T53	2
valid_sources[0x77]	3068	1		T12	83		T53	10		T14	49
valid_sources[0x78]	3330	1		T12	58		T53	5		T13	2
valid_sources[0x79]	2873	1		T12	34		T53	2		T28	1
valid_sources[0x7a]	2693	1		T12	37		T53	2		T13	3
valid_sources[0x7b]	3511	1		T18	1		T12	68		T34	4
valid_sources[0x7c]	3027	1		T12	43		T53	9		T13	1
valid_sources[0x7d]	2445	1		T12	28		T53	2		T13	1
valid_sources[0x7e]	2677	1		T12	44		T53	4		T23	1
valid_sources[0x7f]	2854	1		T12	57		T53	4		T13	3
valid_sources[0x80]	3320	1		T12	38		T32	1		T53	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

296257

1

T2

1

T3

1

T7

19

values[0x0]

all_enables

biggest_size

113911

1

T1

4

T2

3

T3

4

values[0x1]

all_enables

biggest_size

106281

1

T1

2

T2

1

T16

1