Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	332701	1		T1	5		T2	4		T3	5
full_word	517445	1		T1	6		T2	5		T3	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	849866	1		T1	11		T2	9		T3	10
auto[TlIntgErrCmd]	95	1		T56	4		T57	6		T202	4
auto[TlIntgErrData]	88	1		T56	7		T57	6		T202	3
auto[TlIntgErrBoth]	97	1		T56	9		T57	8		T202	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	565663	1		T1	4		T2	2		T3	3
auto[1]	284483	1		T1	7		T2	7		T3	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	269106	1		T1	4		T2	1		T3	2
auto[TlIntgErrNone]	partial	auto[1]	63338	1		T1	1		T2	3		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	296425	1		T2	1		T3	1		T7	19
auto[TlIntgErrNone]	full_word	auto[1]	220997	1		T1	6		T2	4		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T56	3		T57	4		T202	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T56	1		T57	2		T202	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T232	1		T281	1		T282	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T233	1		T283	1		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1		T56	3		T234	1		T203	2
auto[TlIntgErrData]	partial	auto[1]	43	1		T56	4		T57	4		T202	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T57	1		T202	1		T234	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T57	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T56	4		T57	4		T234	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T56	5		T57	4		T202	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1		T234	1		T281	1		T282	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T232	1		T284	1		T282	1