Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.86	92.59	67.16	92.89		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	521008628	11996	0	0
ep_in_enable_rd_A	521008628	3364	0	0
ep_out_enable_rd_A	521008628	3382	0	0
in_iso_rd_A	521008628	3499	0	0
intr_enable_rd_A	521008628	5295	0	0
out_iso_rd_A	521008628	3726	0	0
phy_config_rd_A	521008628	2240	0	0
phy_pins_drive_rd_A	521008628	3060	0	0
rxenable_setup_rd_A	521008628	3859	0	0
set_nak_out_rd_A	521008628	3554	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521008628	11996	0	0
T55	3770	13	0	0
T56	41563	2	0	0
T57	27369	5	0	0
T97	5621	16	0	0
T201	3938	10	0	0
T202	15560	3	0	0
T203	36220	3	0	0
T206	6112	301	0	0
T207	2580	149	0	0
T234	37110	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521008628	3364	0	0
T55	3770	3	0	0
T56	41563	288	0	0
T64	71047	449	0	0
T98	4601	9	0	0
T202	15560	193	0	0
T249	20174	198	0	0
T255	6613	34	0	0
T261	6762	37	0	0
T262	7582	7	0	0
T263	10494	53	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521008628	3382	0	0
T55	3770	43	0	0
T56	41563	296	0	0
T64	71047	452	0	0
T98	4601	6	0	0
T202	15560	256	0	0
T249	20174	177	0	0
T255	6613	25	0	0
T261	6762	45	0	0
T262	7582	35	0	0
T264	2631	4	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521008628	3499	0	0
T55	3770	15	0	0
T56	41563	345	0	0
T64	71047	432	0	0
T98	4601	1	0	0
T202	15560	264	0	0
T249	20174	231	0	0
T255	6613	10	0	0
T261	6762	32	0	0
T262	7582	45	0	0
T264	2631	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521008628	5295	0	0
T55	3770	12	0	0
T56	41563	354	0	0
T64	71047	448	0	0
T67	1991	18	0	0
T98	4601	2	0	0
T202	15560	548	0	0
T255	6613	15	0	0
T265	1664	13	0	0
T266	3360	9	0	0
T267	3625	10	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521008628	3726	0	0
T55	3770	41	0	0
T56	41563	191	0	0
T64	71047	394	0	0
T98	4601	15	0	0
T202	15560	313	0	0
T209	11999	6	0	0
T249	20174	182	0	0
T255	6613	9	0	0
T261	6762	46	0	0
T264	2631	32	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521008628	2240	0	0
T55	3770	4	0	0
T56	41563	180	0	0
T64	71047	409	0	0
T98	4601	9	0	0
T202	15560	73	0	0
T249	20174	201	0	0
T255	6613	21	0	0
T261	6762	26	0	0
T262	7582	16	0	0
T264	2631	1	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521008628	3060	0	0
T55	3770	47	0	0
T56	41563	175	0	0
T64	71047	443	0	0
T98	4601	13	0	0
T202	15560	145	0	0
T249	20174	195	0	0
T255	6613	30	0	0
T261	6762	21	0	0
T262	7582	60	0	0
T264	2631	44	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521008628	3859	0	0
T55	3770	54	0	0
T56	41563	214	0	0
T64	71047	483	0	0
T98	4601	5	0	0
T202	15560	297	0	0
T249	20174	221	0	0
T255	6613	17	0	0
T261	6762	18	0	0
T262	7582	58	0	0
T264	2631	3	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521008628	3554	0	0
T55	3770	52	0	0
T56	41563	252	0	0
T64	71047	426	0	0
T98	4601	5	0	0
T202	15560	252	0	0
T249	20174	177	0	0
T255	6613	23	0	0
T261	6762	19	0	0
T262	7582	61	0	0
T264	2631	1	0	0