Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	277832	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	474807	1		T1	5		T2	6		T3	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	479032	1		T1	2		T2	6		T3	2
values[0x0]	136798	1		T1	4		T2	4		T3	3
values[0x1]	136809	1		T1	1		T2	5		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	210367	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	542272	1		T1	5		T2	7		T3	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2647	1		T9	133		T46	17		T10	3
valid_sources[0x01]	2509	1		T11	48		T89	45		T87	62
valid_sources[0x02]	2769	1		T3	1		T11	65		T89	43
valid_sources[0x03]	3051	1		T46	2		T11	37		T89	43
valid_sources[0x04]	2602	1		T9	5		T46	1		T10	3
valid_sources[0x05]	2681	1		T9	3		T46	7		T11	23
valid_sources[0x06]	2401	1		T16	2		T18	1		T46	1
valid_sources[0x07]	2943	1		T10	2		T11	47		T89	56
valid_sources[0x08]	2888	1		T46	6		T10	2		T11	29
valid_sources[0x09]	2472	1		T8	1		T9	3		T46	8
valid_sources[0x0a]	2616	1		T46	5		T11	43		T89	46
valid_sources[0x0b]	2733	1		T9	22		T46	4		T11	45
valid_sources[0x0c]	2954	1		T9	4		T13	1		T46	24
valid_sources[0x0d]	2592	1		T9	1		T46	7		T10	1
valid_sources[0x0e]	2743	1		T2	1		T8	1		T9	3
valid_sources[0x0f]	2556	1		T9	25		T46	3		T11	42
valid_sources[0x10]	2474	1		T9	2		T46	1		T11	43
valid_sources[0x11]	5726	1		T9	2969		T46	9		T49	1
valid_sources[0x12]	2753	1		T9	2		T11	71		T89	55
valid_sources[0x13]	2906	1		T9	8		T46	14		T79	2
valid_sources[0x14]	2234	1		T9	92		T46	1		T10	2
valid_sources[0x15]	3002	1		T9	1		T46	7		T10	1
valid_sources[0x16]	2528	1		T9	5		T46	29		T11	48
valid_sources[0x17]	2349	1		T9	6		T10	1		T11	28
valid_sources[0x18]	2562	1		T46	3		T10	2		T11	55
valid_sources[0x19]	2539	1		T9	2		T10	37		T11	42
valid_sources[0x1a]	2422	1		T9	3		T46	3		T10	2
valid_sources[0x1b]	2574	1		T8	1		T9	2		T13	1
valid_sources[0x1c]	5453	1		T9	2		T46	1		T11	19
valid_sources[0x1d]	4471	1		T9	2		T46	15		T10	1
valid_sources[0x1e]	2918	1		T8	2		T9	79		T17	15
valid_sources[0x1f]	3391	1		T15	11		T9	1		T46	10
valid_sources[0x20]	2889	1		T9	1		T44	1		T46	7
valid_sources[0x21]	2848	1		T9	2		T13	1		T46	1
valid_sources[0x22]	2550	1		T10	98		T11	49		T89	49
valid_sources[0x23]	2967	1		T46	7		T10	396		T11	14
valid_sources[0x24]	2607	1		T8	1		T9	2		T46	1
valid_sources[0x25]	2617	1		T9	62		T46	1		T49	2
valid_sources[0x26]	5417	1		T11	34		T81	1		T83	2
valid_sources[0x27]	2436	1		T46	15		T10	2		T11	15
valid_sources[0x28]	2815	1		T46	5		T10	1		T11	29
valid_sources[0x29]	3028	1		T9	7		T10	2		T11	50
valid_sources[0x2a]	2593	1		T1	7		T8	1		T46	4
valid_sources[0x2b]	3059	1		T9	50		T46	2		T10	83
valid_sources[0x2c]	3693	1		T9	2		T46	10		T11	28
valid_sources[0x2d]	2392	1		T9	5		T11	35		T31	1
valid_sources[0x2e]	2534	1		T9	2		T16	1		T46	5
valid_sources[0x2f]	3042	1		T46	15		T79	2		T11	24
valid_sources[0x30]	2609	1		T9	2		T46	19		T10	2
valid_sources[0x31]	2653	1		T8	1		T9	4		T46	6
valid_sources[0x32]	2526	1		T9	89		T46	4		T11	34
valid_sources[0x33]	2841	1		T8	1		T9	2		T46	17
valid_sources[0x34]	3294	1		T9	1		T10	2		T11	27
valid_sources[0x35]	2344	1		T8	1		T46	1		T10	7
valid_sources[0x36]	2624	1		T9	4		T46	5		T10	2
valid_sources[0x37]	2886	1		T9	2		T10	70		T11	29
valid_sources[0x38]	2269	1		T9	3		T46	1		T11	31
valid_sources[0x39]	2417	1		T9	4		T16	2		T10	2
valid_sources[0x3a]	2594	1		T8	1		T9	1		T44	1
valid_sources[0x3b]	3013	1		T44	1		T10	3		T11	34
valid_sources[0x3c]	2550	1		T46	1		T10	130		T11	27
valid_sources[0x3d]	3648	1		T8	1		T9	5		T10	1
valid_sources[0x3e]	2777	1		T16	3		T46	3		T11	44
valid_sources[0x3f]	3554	1		T9	2		T46	2		T10	1
valid_sources[0x40]	2418	1		T9	2		T46	3		T11	29
valid_sources[0x41]	2357	1		T9	2		T13	1		T11	37
valid_sources[0x42]	3227	1		T9	138		T18	2		T46	1
valid_sources[0x43]	2459	1		T46	4		T10	3		T11	40
valid_sources[0x44]	2833	1		T3	2		T30	10		T10	4
valid_sources[0x45]	3464	1		T3	1		T46	13		T10	2
valid_sources[0x46]	3557	1		T46	3		T10	2		T11	59
valid_sources[0x47]	2895	1		T9	4		T10	3		T11	59
valid_sources[0x48]	3856	1		T16	2		T46	13		T10	2
valid_sources[0x49]	2586	1		T9	5		T11	64		T89	50
valid_sources[0x4a]	2724	1		T9	271		T44	1		T11	36
valid_sources[0x4b]	2521	1		T46	4		T11	41		T89	59
valid_sources[0x4c]	2822	1		T8	2		T9	2		T11	21
valid_sources[0x4d]	3861	1		T9	2		T10	2		T11	33
valid_sources[0x4e]	2438	1		T9	5		T46	17		T11	20
valid_sources[0x4f]	2333	1		T8	1		T9	3		T18	3
valid_sources[0x50]	3126	1		T9	614		T11	49		T89	45
valid_sources[0x51]	2401	1		T49	6		T10	2		T11	48
valid_sources[0x52]	2902	1		T9	1		T11	53		T89	61
valid_sources[0x53]	3569	1		T9	1		T11	43		T31	1
valid_sources[0x54]	2529	1		T9	4		T46	9		T11	18
valid_sources[0x55]	3139	1		T9	4		T46	1		T10	1
valid_sources[0x56]	2663	1		T15	1		T9	4		T46	3
valid_sources[0x57]	2573	1		T9	1		T13	1		T46	1
valid_sources[0x58]	2733	1		T8	2		T9	5		T46	1
valid_sources[0x59]	2560	1		T12	5		T9	2		T11	54
valid_sources[0x5a]	2321	1		T9	3		T46	1		T11	69
valid_sources[0x5b]	3085	1		T11	74		T86	1		T89	52
valid_sources[0x5c]	3587	1		T9	2		T18	1		T10	3
valid_sources[0x5d]	2966	1		T9	7		T11	49		T81	1
valid_sources[0x5e]	2601	1		T9	3		T10	1		T11	39
valid_sources[0x5f]	2884	1		T8	1		T9	2		T46	1
valid_sources[0x60]	3253	1		T10	1		T11	17		T81	1
valid_sources[0x61]	6618	1		T8	1		T9	2		T10	4
valid_sources[0x62]	2836	1		T2	2		T8	1		T46	4
valid_sources[0x63]	3519	1		T46	9		T11	36		T89	86
valid_sources[0x64]	2697	1		T9	4		T46	2		T11	30
valid_sources[0x65]	2783	1		T9	2		T13	1		T46	20
valid_sources[0x66]	3086	1		T9	3		T10	1		T11	27
valid_sources[0x67]	2759	1		T46	3		T10	1		T11	23
valid_sources[0x68]	2791	1		T9	3		T10	79		T11	17
valid_sources[0x69]	5684	1		T9	2		T10	1		T11	37
valid_sources[0x6a]	2999	1		T46	2		T11	44		T43	1
valid_sources[0x6b]	2519	1		T8	1		T46	3		T10	1
valid_sources[0x6c]	3158	1		T9	347		T10	2		T11	13
valid_sources[0x6d]	2762	1		T2	1		T9	3		T11	24
valid_sources[0x6e]	3458	1		T9	323		T46	3		T10	2
valid_sources[0x6f]	2535	1		T9	1		T10	2		T11	25
valid_sources[0x70]	2705	1		T9	166		T46	7		T10	2
valid_sources[0x71]	2446	1		T9	4		T46	3		T10	2
valid_sources[0x72]	2712	1		T9	1		T46	1		T11	40
valid_sources[0x73]	2633	1		T9	2		T46	9		T10	3
valid_sources[0x74]	2359	1		T9	3		T46	2		T10	1
valid_sources[0x75]	2542	1		T8	1		T9	3		T46	5
valid_sources[0x76]	2221	1		T9	2		T46	5		T49	2
valid_sources[0x77]	2553	1		T9	61		T44	1		T46	7
valid_sources[0x78]	2767	1		T9	2		T44	1		T46	2
valid_sources[0x79]	2494	1		T2	1		T11	63		T41	1
valid_sources[0x7a]	2567	1		T46	5		T10	2		T79	1
valid_sources[0x7b]	2535	1		T8	1		T11	39		T265	1
valid_sources[0x7c]	2923	1		T9	1		T46	4		T79	2
valid_sources[0x7d]	6280	1		T16	1		T46	7		T11	40
valid_sources[0x7e]	7311	1		T10	2		T11	24		T89	53
valid_sources[0x7f]	2396	1		T9	65		T46	5		T11	49
valid_sources[0x80]	5638	1		T8	2		T49	2		T10	3098

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

252164

1

T1

2

T2

1

T3

1

values[0x0]

all_enables

biggest_size

115495

1

T1

2

T2

4

T3

2

values[0x1]

all_enables

biggest_size

107148

1

T1

1

T2

1

T3

1