Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	292655	1		T1	2		T2	9		T3	4
full_word	475774	1		T1	5		T2	6		T3	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	768089	1		T1	7		T2	15		T3	8
auto[TlIntgErrCmd]	108	1		T50	4		T59	2		T91	2
auto[TlIntgErrData]	127	1		T50	3		T59	4		T91	4
auto[TlIntgErrBoth]	105	1		T50	3		T59	4		T91	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	480856	1		T1	2		T2	6		T3	2
auto[1]	287573	1		T1	5		T2	9		T3	6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	228380	1		T2	5		T3	1		T12	2
auto[TlIntgErrNone]	partial	auto[1]	63962	1		T1	2		T2	4		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	252322	1		T1	2		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	223425	1		T1	3		T2	5		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T50	2		T92	3		T216	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T50	2		T59	2		T91	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T263	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T91	1		T261	1		T263	1
auto[TlIntgErrData]	partial	auto[0]	62	1		T50	1		T59	1		T91	2
auto[TlIntgErrData]	partial	auto[1]	60	1		T50	2		T59	3		T91	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T259	1		T260	1		T261	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T260	1		T215	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T50	2		T59	2		T91	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T50	1		T59	2		T91	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T218	2		T261	1		T264	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T259	1		T261	1		T264	1