Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.77	92.59	67.16	92.43		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	520671905	11965	0	0
ep_in_enable_rd_A	520671905	2714	0	0
ep_out_enable_rd_A	520671905	3032	0	0
in_iso_rd_A	520671905	3406	0	0
intr_enable_rd_A	520671905	4236	0	0
out_iso_rd_A	520671905	2789	0	0
phy_config_rd_A	520671905	1655	0	0
phy_pins_drive_rd_A	520671905	2278	0	0
rxenable_setup_rd_A	520671905	2816	0	0
set_nak_out_rd_A	520671905	3106	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	11965	0	0
T50	15526	1	0	0
T51	9843	424	0	0
T52	4052	16	0	0
T59	22983	3	0	0
T91	12251	4	0	0
T92	26534	3	0	0
T196	8087	527	0	0
T199	4672	974	0	0
T208	4156	565	0	0
T210	4161	725	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	2714	0	0
T50	15526	180	0	0
T59	22983	135	0	0
T93	3228	1	0	0
T218	30065	601	0	0
T228	3250	87	0	0
T230	39724	138	0	0
T242	7005	53	0	0
T243	4327	4	0	0
T244	5814	1	0	0
T245	4197	27	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	3032	0	0
T50	15526	164	0	0
T59	22983	230	0	0
T93	3228	101	0	0
T218	30065	551	0	0
T228	3250	11	0	0
T230	39724	102	0	0
T242	7005	13	0	0
T243	4327	45	0	0
T244	5814	8	0	0
T245	4197	23	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	3406	0	0
T50	15526	252	0	0
T59	22983	274	0	0
T93	3228	7	0	0
T218	30065	594	0	0
T228	3250	9	0	0
T230	39724	108	0	0
T242	7005	72	0	0
T243	4327	53	0	0
T244	5814	13	0	0
T245	4197	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	4236	0	0
T50	15526	358	0	0
T59	22983	363	0	0
T63	3300	5	0	0
T64	1709	6	0	0
T67	1472	4	0	0
T93	3228	120	0	0
T218	30065	894	0	0
T228	3250	118	0	0
T230	39724	158	0	0
T246	2805	6	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	2789	0	0
T50	15526	195	0	0
T59	22983	162	0	0
T93	3228	32	0	0
T218	30065	509	0	0
T228	3250	28	0	0
T230	39724	121	0	0
T242	7005	95	0	0
T243	4327	4	0	0
T244	5814	2	0	0
T245	4197	10	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	1655	0	0
T50	15526	133	0	0
T59	22983	130	0	0
T93	3228	27	0	0
T218	30065	238	0	0
T228	3250	6	0	0
T230	39724	139	0	0
T242	7005	70	0	0
T243	4327	24	0	0
T244	5814	40	0	0
T245	4197	17	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	2278	0	0
T50	15526	193	0	0
T59	22983	137	0	0
T93	3228	32	0	0
T218	30065	397	0	0
T228	3250	44	0	0
T230	39724	138	0	0
T242	7005	17	0	0
T243	4327	50	0	0
T244	5814	13	0	0
T245	4197	9	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	2816	0	0
T50	15526	172	0	0
T59	22983	171	0	0
T93	3228	5	0	0
T218	30065	472	0	0
T228	3250	40	0	0
T230	39724	120	0	0
T242	7005	93	0	0
T243	4327	1	0	0
T244	5814	61	0	0
T245	4197	5	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	3106	0	0
T50	15526	307	0	0
T59	22983	269	0	0
T93	3228	11	0	0
T218	30065	624	0	0
T228	3250	46	0	0
T230	39724	82	0	0
T242	7005	39	0	0
T243	4327	7	0	0
T244	5814	34	0	0
T245	4197	4	0	0