Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.91	100.00	67.63			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_rxfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.usbdev_avsetupfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.usbdev_avoutfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.77	92.59	67.16	92.43		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.77	92.59	67.16	92.43		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.77	92.59	67.16	92.43		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.62	100.00

tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	LINE
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T49,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T9,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T16,T49,T10
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T9,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T16,T49,T10
1	0	Covered	T8,T9,T16
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T8,T9,T16
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
91.07	64.29

tb.dut.usbdev_avsetupfifo

SCORE	COND
91.07	64.29

tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T15

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.usbdev_rxfifo

SCORE	COND
92.19	68.75

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T8,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T8,T15
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T9,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T8,T9,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T9,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T16
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.62	100.00

tb.dut.usbdev_rxfifo

SCORE	BRANCH
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	BRANCH
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	452487290	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	447446706	0	0
gen_passthru_fifo.paramCheckPass	8880	8880	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	452487290	0	0
T1	1606256	90	0	0
T2	2435454	402253	0	0
T3	2411304	401595	0	0
T8	4864296	401338	0	0
T9	10475832	333226	0	0
T10	0	40462	0	0
T11	0	25562	0	0
T12	2413728	62	0	0
T13	4835148	401956	0	0
T15	4874412	405290	0	0
T16	4850316	401131	0	0
T17	4877508	402470	0	0
T18	2410938	400371	0	0
T21	2431278	400568	0	0
T24	2423070	402588	0	0
T30	3217728	400163	0	0
T44	0	15	0	0
T49	0	40	0	0
T79	0	235	0	0
T80	0	10	0	0
T81	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4818768	4817772	0	0
T2	4870908	4870032	0	0
T3	4822608	4821792	0	0
T8	4864296	4863120	0	0
T9	10475832	10474764	0	0
T12	4827456	4825704	0	0
T13	4835148	4833552	0	0
T15	4874412	4873476	0	0
T16	4850316	4849152	0	0
T17	4877508	4876656	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4818768	4817772	0	0
T2	4870908	4870032	0	0
T3	4822608	4821792	0	0
T8	4864296	4863120	0	0
T9	10475832	10474764	0	0
T12	4827456	4825704	0	0
T13	4835148	4833552	0	0
T15	4874412	4873476	0	0
T16	4850316	4849152	0	0
T17	4877508	4876656	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4818768	4817772	0	0
T2	4870908	4870032	0	0
T3	4822608	4821792	0	0
T8	4864296	4863120	0	0
T9	10475832	10474764	0	0
T12	4827456	4825704	0	0
T13	4835148	4833552	0	0
T15	4874412	4873476	0	0
T16	4850316	4849152	0	0
T17	4877508	4876656	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	447446706	0	0
T2	811818	402193	0	0
T3	803768	401523	0	0
T8	2432148	401170	0	0
T9	5237916	299215	0	0
T10	0	23800	0	0
T11	0	13270	0	0
T12	804576	0	0	0
T13	2417574	401814	0	0
T15	2437206	405242	0	0
T16	2425158	401001	0	0
T17	2438754	402298	0	0
T18	1607292	400371	0	0
T21	1620852	400568	0	0
T24	1615380	402588	0	0
T30	2413296	400163	0	0
T31	0	400447	0	0
T44	0	9	0	0
T46	0	2796	0	0
T49	0	26	0	0
T79	0	152	0	0
T80	0	6	0	0
T81	0	6	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	8880	8880	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T8	6	6	0	0
T9	6	6	0	0
T12	6	6	0	0
T13	6	6	0	0
T15	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T8,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T8,T15
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519220601	2244330	0	0
DepthKnown_A	519220601	519104226	0	0
RvalidKnown_A	519220601	519104226	0	0
WreadyKnown_A	519220601	519104226	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519220601	2244330	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	2244330	0	0
T2	405909	101	0	0
T3	401884	0	0	0
T8	405358	202	0	0
T9	872986	22195	0	0
T12	402288	0	0	0
T13	402929	0	0	0
T15	406201	141	0	0
T16	404193	97	0	0
T17	406459	104	0	0
T18	0	771	0	0
T21	0	805	0	0
T24	0	122	0	0
T30	402216	110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	2244330	0	0
T2	405909	101	0	0
T3	401884	0	0	0
T8	405358	202	0	0
T9	872986	22195	0	0
T12	402288	0	0	0
T13	402929	0	0	0
T15	406201	141	0	0
T16	404193	97	0	0
T17	406459	104	0	0
T18	0	771	0	0
T21	0	805	0	0
T24	0	122	0	0
T30	402216	110	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T9,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T8,T9,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T9,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519220601	202734	0	0
DepthKnown_A	519220601	519104226	0	0
RvalidKnown_A	519220601	519104226	0	0
WreadyKnown_A	519220601	519104226	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519220601	202734	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	202734	0	0
T8	405358	5	0	0
T9	872986	2724	0	0
T10	0	1836	0	0
T11	0	3562	0	0
T13	402929	0	0	0
T15	406201	0	0	0
T16	404193	5	0	0
T17	406459	0	0	0
T18	401823	0	0	0
T21	405213	0	0	0
T24	403845	0	0	0
T30	402216	0	0	0
T44	0	3	0	0
T49	0	2	0	0
T79	0	14	0	0
T80	0	2	0	0
T81	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	202734	0	0
T8	405358	5	0	0
T9	872986	2724	0	0
T10	0	1836	0	0
T11	0	3562	0	0
T13	402929	0	0	0
T15	406201	0	0	0
T16	404193	5	0	0
T17	406459	0	0	0
T18	401823	0	0	0
T21	405213	0	0	0
T24	403845	0	0	0
T30	402216	0	0	0
T44	0	3	0	0
T49	0	2	0	0
T79	0	14	0	0
T80	0	2	0	0
T81	0	2	0	0

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T18,T21

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T18,T21

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T18,T21
1	1	0	Not Covered
1	1	1	Covered	T8,T18,T21

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T18,T21
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519220601	60586888	0	0
DepthKnown_A	519220601	519104226	0	0
RvalidKnown_A	519220601	519104226	0	0
WreadyKnown_A	519220601	519104226	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519220601	60586888	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	60586888	0	0
T8	405358	400491	0	0
T9	872986	0	0	0
T13	402929	0	0	0
T15	406201	0	0	0
T16	404193	0	0	0
T17	406459	0	0	0
T18	401823	400371	0	0
T21	405213	400568	0	0
T24	403845	0	0	0
T30	402216	0	0	0
T31	0	400447	0	0
T32	0	400578	0	0
T40	0	400634	0	0
T46	0	2796	0	0
T82	0	400406	0	0
T83	0	400404	0	0
T84	0	400899	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	60586888	0	0
T8	405358	400491	0	0
T9	872986	0	0	0
T13	402929	0	0	0
T15	406201	0	0	0
T16	404193	0	0	0
T17	406459	0	0	0
T18	401823	400371	0	0
T21	405213	400568	0	0
T24	403845	0	0	0
T30	402216	0	0	0
T31	0	400447	0	0
T32	0	400578	0	0
T40	0	400634	0	0
T46	0	2796	0	0
T82	0	400406	0	0
T83	0	400404	0	0
T84	0	400899	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T15

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519220601	383349327	0	0
DepthKnown_A	519220601	519104226	0	0
RvalidKnown_A	519220601	519104226	0	0
WreadyKnown_A	519220601	519104226	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519220601	383349327	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	383349327	0	0
T2	405909	402193	0	0
T3	401884	401523	0	0
T8	405358	648	0	0
T9	872986	289154	0	0
T12	402288	0	0	0
T13	402929	401814	0	0
T15	406201	405242	0	0
T16	404193	400968	0	0
T17	406459	402298	0	0
T24	0	402588	0	0
T30	402216	400163	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	383349327	0	0
T2	405909	402193	0	0
T3	401884	401523	0	0
T8	405358	648	0	0
T9	872986	289154	0	0
T12	402288	0	0	0
T13	402929	401814	0	0
T15	406201	405242	0	0
T16	404193	400968	0	0
T17	406459	402298	0	0
T24	0	402588	0	0
T30	402216	400163	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T9,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T16,T49,T10
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T8,T9,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T9,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519220601	665034	0	0
DepthKnown_A	519220601	519104226	0	0
RvalidKnown_A	519220601	519104226	0	0
WreadyKnown_A	519220601	519104226	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519220601	665034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	665034	0	0
T8	405358	21	0	0
T9	872986	4613	0	0
T10	0	13637	0	0
T11	0	6146	0	0
T13	402929	0	0	0
T15	406201	0	0	0
T16	404193	14	0	0
T17	406459	0	0	0
T18	401823	0	0	0
T21	405213	0	0	0
T24	403845	0	0	0
T30	402216	0	0	0
T44	0	3	0	0
T49	0	12	0	0
T79	0	69	0	0
T80	0	2	0	0
T81	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	665034	0	0
T8	405358	21	0	0
T9	872986	4613	0	0
T10	0	13637	0	0
T11	0	6146	0	0
T13	402929	0	0	0
T15	406201	0	0	0
T16	404193	14	0	0
T17	406459	0	0	0
T18	401823	0	0	0
T21	405213	0	0	0
T24	403845	0	0	0
T30	402216	0	0	0
T44	0	3	0	0
T49	0	12	0	0
T79	0	69	0	0
T80	0	2	0	0
T81	0	2	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T49,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T9,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T16,T49,T10
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T9,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T16,T49,T10
1	0	Covered	T8,T9,T16
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T8,T9,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T9,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519220601	398393	0	0
DepthKnown_A	519220601	519104226	0	0
RvalidKnown_A	519220601	519104226	0	0
WreadyKnown_A	519220601	519104226	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519220601	398393	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	398393	0	0
T8	405358	5	0	0
T9	872986	2724	0	0
T10	0	8327	0	0
T11	0	3562	0	0
T13	402929	0	0	0
T15	406201	0	0	0
T16	404193	14	0	0
T17	406459	0	0	0
T18	401823	0	0	0
T21	405213	0	0	0
T24	403845	0	0	0
T30	402216	0	0	0
T44	0	3	0	0
T49	0	12	0	0
T79	0	69	0	0
T80	0	2	0	0
T81	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	519104226	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519220601	398393	0	0
T8	405358	5	0	0
T9	872986	2724	0	0
T10	0	8327	0	0
T11	0	3562	0	0
T13	402929	0	0	0
T15	406201	0	0	0
T16	404193	14	0	0
T17	406459	0	0	0
T18	401823	0	0	0
T21	405213	0	0	0
T24	403845	0	0	0
T30	402216	0	0	0
T44	0	3	0	0
T49	0	12	0	0
T79	0	69	0	0
T80	0	2	0	0
T81	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520671905	1035310	0	0
DepthKnown_A	520671905	520506610	0	0
RvalidKnown_A	520671905	520506610	0	0
WreadyKnown_A	520671905	520506610	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	1035310	0	0
T1	401564	7	0	0
T2	405909	15	0	0
T3	401884	8	0	0
T8	405358	42	0	0
T9	872986	8565	0	0
T12	402288	9	0	0
T13	402929	10	0	0
T15	406201	12	0	0
T16	404193	16	0	0
T17	406459	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520671905	1516429	0	0
DepthKnown_A	520671905	520506610	0	0
RvalidKnown_A	520671905	520506610	0	0
WreadyKnown_A	520671905	520506610	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	1516429	0	0
T1	401564	38	0	0
T2	405909	15	0	0
T3	401884	28	0	0
T8	405358	42	0	0
T9	872986	8482	0	0
T12	402288	22	0	0
T13	402929	61	0	0
T15	406201	12	0	0
T16	404193	49	0	0
T17	406459	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520671905	375851	0	0
DepthKnown_A	520671905	520506610	0	0
RvalidKnown_A	520671905	520506610	0	0
WreadyKnown_A	520671905	520506610	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	375851	0	0
T8	405358	21	0	0
T9	872986	4613	0	0
T10	0	3025	0	0
T11	0	6146	0	0
T13	402929	0	0	0
T15	406201	0	0	0
T16	404193	5	0	0
T17	406459	0	0	0
T18	401823	0	0	0
T21	405213	0	0	0
T24	403845	0	0	0
T30	402216	0	0	0
T44	0	3	0	0
T49	0	2	0	0
T79	0	14	0	0
T80	0	2	0	0
T81	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520671905	704952	0	0
DepthKnown_A	520671905	520506610	0	0
RvalidKnown_A	520671905	520506610	0	0
WreadyKnown_A	520671905	520506610	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	704952	0	0
T8	405358	21	0	0
T9	872986	4613	0	0
T10	0	13637	0	0
T11	0	6146	0	0
T13	402929	0	0	0
T15	406201	0	0	0
T16	404193	14	0	0
T17	406459	0	0	0
T18	401823	0	0	0
T21	405213	0	0	0
T24	403845	0	0	0
T30	402216	0	0	0
T44	0	3	0	0
T49	0	12	0	0
T79	0	69	0	0
T80	0	2	0	0
T81	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520671905	596565	0	0
DepthKnown_A	520671905	520506610	0	0
RvalidKnown_A	520671905	520506610	0	0
WreadyKnown_A	520671905	520506610	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	596565	0	0
T1	401564	7	0	0
T2	405909	15	0	0
T3	401884	8	0	0
T8	405358	21	0	0
T9	872986	3869	0	0
T12	402288	9	0	0
T13	402929	10	0	0
T15	406201	12	0	0
T16	404193	11	0	0
T17	406459	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520671905	811477	0	0
DepthKnown_A	520671905	520506610	0	0
RvalidKnown_A	520671905	520506610	0	0
WreadyKnown_A	520671905	520506610	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	811477	0	0
T1	401564	38	0	0
T2	405909	15	0	0
T3	401884	28	0	0
T8	405358	21	0	0
T9	872986	3869	0	0
T12	402288	22	0	0
T13	402929	61	0	0
T15	406201	12	0	0
T16	404193	35	0	0
T17	406459	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520671905	520506610	0	0
T1	401564	401481	0	0
T2	405909	405836	0	0
T3	401884	401816	0	0
T8	405358	405260	0	0
T9	872986	872897	0	0
T12	402288	402142	0	0
T13	402929	402796	0	0
T15	406201	406123	0	0
T16	404193	404096	0	0
T17	406459	406388	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0