Module Definition
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Module : prim_ram_1p_adv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_no_stubbed_memory.u_memory_1p 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_1p

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.96 95.83 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.77 92.59 67.16 92.43 91.67 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_mem 95.24 85.71 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_ram_1p_adv
Line No.TotalCoveredPercent
TOTAL1717100.00
ALWAYS10633100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11800
CONT_ASSIGN21000
CONT_ASSIGN21111100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN24111100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24500
CONT_ASSIGN26311100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN26600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
106 1 1
107 1 1
109 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 unreachable
210 unreachable
211 1 1
213 1 1
217 1 1
241 1 1
242 1 1
243 1 1
244 1 1
245 unreachable
263 1 1
264 1 1
266 unreachable


Cond Coverage for Module : prim_ram_1p_adv
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       109
 EXPRESSION (req_q & ((~write_q)))
             --1--   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T15
11CoveredT1,T2,T8

Branch Coverage for Module : prim_ram_1p_adv
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 106 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 106 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_ram_1p_adv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CannotHaveEccAndParity_A 1305 1305 0 0


CannotHaveEccAndParity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1305 1305 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%