Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	314086	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	516327	1		T1	31		T2	346		T3	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	563316	1		T1	15		T2	240		T3	5
values[0x0]	132921	1		T1	11		T2	486		T3	5
values[0x1]	134176	1		T1	16		T2	431		T7	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	239224	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	591189	1		T1	34		T2	442		T3	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2516	1		T12	50		T39	2		T57	3
valid_sources[0x01]	2670	1		T12	44		T152	1		T140	1
valid_sources[0x02]	2950	1		T12	35		T33	4		T147	1
valid_sources[0x03]	3610	1		T12	42		T57	3		T13	69
valid_sources[0x04]	3012	1		T18	3		T12	38		T59	11
valid_sources[0x05]	2804	1		T12	34		T95	1		T137	1
valid_sources[0x06]	4312	1		T15	1		T12	49		T37	1
valid_sources[0x07]	3447	1		T12	32		T99	1		T13	54
valid_sources[0x08]	4126	1		T12	40		T95	1		T57	4
valid_sources[0x09]	2729	1		T16	1		T12	46		T136	1
valid_sources[0x0a]	2824	1		T12	38		T13	77		T275	53
valid_sources[0x0b]	3275	1		T21	1		T12	41		T99	2
valid_sources[0x0c]	3051	1		T1	1		T15	2		T12	43
valid_sources[0x0d]	2865	1		T36	2		T12	33		T152	1
valid_sources[0x0e]	2820	1		T12	54		T57	1		T302	2
valid_sources[0x0f]	3214	1		T12	39		T139	1		T57	2
valid_sources[0x10]	2636	1		T12	38		T92	1		T13	41
valid_sources[0x11]	3134	1		T12	62		T13	65		T275	55
valid_sources[0x12]	3095	1		T12	32		T13	54		T275	59
valid_sources[0x13]	2995	1		T1	1		T12	44		T33	2
valid_sources[0x14]	2794	1		T12	52		T57	2		T137	1
valid_sources[0x15]	2946	1		T12	42		T140	1		T57	2
valid_sources[0x16]	3086	1		T12	48		T60	1		T57	5
valid_sources[0x17]	3268	1		T12	36		T57	2		T13	42
valid_sources[0x18]	2862	1		T21	1		T12	46		T35	4
valid_sources[0x19]	2765	1		T12	35		T154	1		T13	65
valid_sources[0x1a]	3167	1		T12	34		T60	1		T57	7
valid_sources[0x1b]	2932	1		T12	44		T57	1		T137	1
valid_sources[0x1c]	2710	1		T12	31		T130	9		T57	2
valid_sources[0x1d]	2979	1		T20	1		T16	1		T12	39
valid_sources[0x1e]	3270	1		T12	40		T13	79		T14	1
valid_sources[0x1f]	3039	1		T12	34		T33	1		T57	1
valid_sources[0x20]	3318	1		T12	39		T60	1		T13	47
valid_sources[0x21]	3104	1		T1	2		T12	23		T39	1
valid_sources[0x22]	4097	1		T12	40		T57	5		T163	2
valid_sources[0x23]	2849	1		T42	3		T12	35		T137	1
valid_sources[0x24]	3378	1		T12	45		T154	1		T13	64
valid_sources[0x25]	2967	1		T21	1		T12	43		T34	26
valid_sources[0x26]	3447	1		T12	40		T57	4		T137	1
valid_sources[0x27]	2805	1		T12	32		T136	1		T13	62
valid_sources[0x28]	3264	1		T12	48		T57	5		T303	76
valid_sources[0x29]	5156	1		T16	1		T44	14		T12	44
valid_sources[0x2a]	6672	1		T8	2		T12	37		T57	5
valid_sources[0x2b]	3316	1		T1	2		T12	38		T13	75
valid_sources[0x2c]	3174	1		T12	38		T152	1		T304	1
valid_sources[0x2d]	2574	1		T12	42		T37	1		T305	2
valid_sources[0x2e]	5616	1		T18	5		T38	2		T12	33
valid_sources[0x2f]	2674	1		T1	1		T12	35		T39	1
valid_sources[0x30]	2778	1		T12	43		T57	3		T93	1
valid_sources[0x31]	2896	1		T3	1		T20	1		T17	1
valid_sources[0x32]	3039	1		T1	1		T12	35		T306	3
valid_sources[0x33]	3145	1		T20	1		T12	42		T152	1
valid_sources[0x34]	3479	1		T43	7		T12	39		T60	1
valid_sources[0x35]	3623	1		T12	44		T57	3		T93	1
valid_sources[0x36]	2597	1		T12	37		T307	1		T13	66
valid_sources[0x37]	2913	1		T12	42		T60	1		T57	10
valid_sources[0x38]	2810	1		T1	1		T12	49		T304	1
valid_sources[0x39]	3280	1		T12	44		T136	2		T13	67
valid_sources[0x3a]	2998	1		T12	32		T57	1		T134	5
valid_sources[0x3b]	4158	1		T12	44		T13	47		T14	3
valid_sources[0x3c]	2769	1		T12	41		T218	1		T13	53
valid_sources[0x3d]	2887	1		T12	37		T13	67		T275	49
valid_sources[0x3e]	3091	1		T1	1		T12	44		T60	1
valid_sources[0x3f]	3025	1		T17	1		T12	33		T37	1
valid_sources[0x40]	3668	1		T12	41		T40	1		T307	1
valid_sources[0x41]	3664	1		T17	1		T12	39		T57	3
valid_sources[0x42]	5694	1		T12	28		T13	58		T275	51
valid_sources[0x43]	2977	1		T17	1		T12	33		T57	5
valid_sources[0x44]	4840	1		T12	53		T57	6		T308	13
valid_sources[0x45]	2695	1		T12	48		T53	1		T157	1
valid_sources[0x46]	2850	1		T12	35		T169	3		T137	1
valid_sources[0x47]	3420	1		T17	1		T12	38		T57	2
valid_sources[0x48]	2916	1		T12	40		T37	1		T99	1
valid_sources[0x49]	2765	1		T12	34		T136	1		T137	1
valid_sources[0x4a]	3330	1		T8	2		T16	1		T12	36
valid_sources[0x4b]	3373	1		T1	1		T12	45		T13	47
valid_sources[0x4c]	2986	1		T12	34		T92	1		T57	4
valid_sources[0x4d]	2548	1		T42	1		T12	42		T140	1
valid_sources[0x4e]	3821	1		T12	42		T305	1		T13	62
valid_sources[0x4f]	2809	1		T20	1		T12	41		T39	1
valid_sources[0x50]	3478	1		T45	1		T12	39		T95	2
valid_sources[0x51]	2933	1		T45	3		T12	35		T152	1
valid_sources[0x52]	3256	1		T12	47		T134	7		T13	45
valid_sources[0x53]	3234	1		T15	1		T12	43		T6	1
valid_sources[0x54]	3281	1		T61	12		T43	4		T12	40
valid_sources[0x55]	2979	1		T12	43		T13	71		T14	2
valid_sources[0x56]	2984	1		T12	38		T5	4		T13	66
valid_sources[0x57]	2653	1		T12	38		T57	1		T136	1
valid_sources[0x58]	3030	1		T12	35		T144	3		T13	52
valid_sources[0x59]	2902	1		T12	42		T39	1		T157	1
valid_sources[0x5a]	3663	1		T17	1		T12	29		T309	4
valid_sources[0x5b]	2859	1		T12	39		T96	1		T163	1
valid_sources[0x5c]	3515	1		T18	2		T36	1		T12	43
valid_sources[0x5d]	2866	1		T12	23		T152	1		T140	1
valid_sources[0x5e]	3236	1		T12	34		T302	2		T13	62
valid_sources[0x5f]	3062	1		T3	4		T12	44		T152	2
valid_sources[0x60]	2742	1		T15	2		T12	47		T96	5
valid_sources[0x61]	2730	1		T12	43		T57	3		T310	3
valid_sources[0x62]	3370	1		T1	1		T12	36		T57	6
valid_sources[0x63]	2805	1		T12	42		T57	2		T136	1
valid_sources[0x64]	2753	1		T12	39		T57	11		T218	1
valid_sources[0x65]	6351	1		T1	1		T12	42		T4	1
valid_sources[0x66]	2855	1		T12	41		T154	1		T13	55
valid_sources[0x67]	3594	1		T20	1		T12	38		T57	1
valid_sources[0x68]	2971	1		T1	1		T12	41		T155	4
valid_sources[0x69]	2904	1		T12	36		T311	1		T13	58
valid_sources[0x6a]	3525	1		T12	35		T274	1		T57	1
valid_sources[0x6b]	3297	1		T15	1		T12	33		T33	3
valid_sources[0x6c]	3374	1		T12	41		T39	1		T154	1
valid_sources[0x6d]	2881	1		T12	48		T155	4		T57	4
valid_sources[0x6e]	2682	1		T12	52		T13	56		T275	55
valid_sources[0x6f]	3074	1		T12	44		T13	68		T14	10
valid_sources[0x70]	3090	1		T45	1		T36	1		T12	36
valid_sources[0x71]	2923	1		T1	2		T12	40		T57	3
valid_sources[0x72]	2998	1		T17	1		T12	35		T9	8
valid_sources[0x73]	2841	1		T12	31		T147	3		T6	2
valid_sources[0x74]	3227	1		T36	1		T12	44		T4	2
valid_sources[0x75]	3052	1		T12	48		T309	1		T312	1
valid_sources[0x76]	2839	1		T12	47		T57	5		T136	1
valid_sources[0x77]	2728	1		T12	34		T155	1		T57	2
valid_sources[0x78]	2853	1		T41	2		T12	33		T40	1
valid_sources[0x79]	3144	1		T21	1		T12	38		T13	66
valid_sources[0x7a]	3200	1		T17	1		T12	35		T57	8
valid_sources[0x7b]	3586	1		T45	1		T12	39		T57	3
valid_sources[0x7c]	2993	1		T12	45		T305	1		T137	1
valid_sources[0x7d]	2938	1		T12	41		T57	2		T312	1
valid_sources[0x7e]	3089	1		T36	2		T12	43		T139	1
valid_sources[0x7f]	3089	1		T1	1		T12	33		T99	1
valid_sources[0x80]	2749	1		T12	51		T57	1		T137	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

296120

1

T1

10

T2

127

T3

2

values[0x0]

all_enables

biggest_size

113355

1

T1

10

T2

151

T3

2

values[0x1]

all_enables

biggest_size

106852

1

T1

11

T2

68

T7

1