Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	326250	1		T1	11		T2	811		T3	6
full_word	517085	1		T1	31		T2	346		T3	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	843045	1		T1	42		T2	1157		T3	10
auto[TlIntgErrCmd]	102	1		T64	2		T214	6		T210	5
auto[TlIntgErrData]	91	1		T62	3		T64	3		T214	3
auto[TlIntgErrBoth]	97	1		T62	7		T64	5		T214	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	564673	1		T1	15		T2	240		T3	5
auto[1]	278662	1		T1	27		T2	917		T3	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	268304	1		T1	5		T2	113		T3	3
auto[TlIntgErrNone]	partial	auto[1]	57686	1		T1	6		T2	698		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	296245	1		T1	10		T2	127		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	220810	1		T1	21		T2	219		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T64	2		T214	1		T210	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1		T214	5		T210	3		T238	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T210	1		T282	1		T298	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T238	1		T280	2		T211	1
auto[TlIntgErrData]	partial	auto[0]	38	1		T62	2		T64	1		T214	1
auto[TlIntgErrData]	partial	auto[1]	42	1		T64	1		T214	2		T210	5
auto[TlIntgErrData]	full_word	auto[0]	5	1		T62	1		T240	1		T299	2
auto[TlIntgErrData]	full_word	auto[1]	6	1		T64	1		T210	2		T298	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T62	6		T64	1		T210	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T62	1		T64	2		T214	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T282	1		T300	2		T301	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T64	2		T210	1		T299	1