Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.14	92.59	67.16	94.27		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	521076493	10241	0	0
ep_in_enable_rd_A	521076493	2979	0	0
ep_out_enable_rd_A	521076493	3212	0	0
in_iso_rd_A	521076493	3033	0	0
intr_enable_rd_A	521076493	3830	0	0
out_iso_rd_A	521076493	2974	0	0
phy_config_rd_A	521076493	2015	0	0
phy_pins_drive_rd_A	521076493	2940	0	0
rxenable_setup_rd_A	521076493	3034	0	0
set_nak_out_rd_A	521076493	2887	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	10241	0	0
T62	8944	2	0	0
T63	2595	242	0	0
T64	7909	2	0	0
T208	3675	17	0	0
T209	7204	397	0	0
T210	13497	4	0	0
T212	12102	758	0	0
T213	2454	280	0	0
T214	14907	3	0	0
T231	2323	297	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	2979	0	0
T70	14325	46	0	0
T235	2474	1	0	0
T240	26469	250	0	0
T263	31613	223	0	0
T273	6188	15	0	0
T279	16030	218	0	0
T280	29176	203	0	0
T281	8294	45	0	0
T282	34522	220	0	0
T283	4562	26	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	3212	0	0
T70	14325	53	0	0
T235	2474	8	0	0
T240	26469	433	0	0
T263	31613	231	0	0
T273	6188	6	0	0
T279	16030	216	0	0
T280	29176	229	0	0
T281	8294	12	0	0
T282	34522	205	0	0
T283	4562	16	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	3033	0	0
T70	14325	30	0	0
T235	2474	9	0	0
T240	26469	191	0	0
T263	31613	244	0	0
T273	6188	21	0	0
T279	16030	294	0	0
T280	29176	204	0	0
T281	8294	14	0	0
T282	34522	378	0	0
T283	4562	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	3830	0	0
T70	14325	44	0	0
T73	1615	6	0	0
T78	1641	29	0	0
T80	1456	13	0	0
T235	2474	4	0	0
T240	26469	301	0	0
T273	6188	30	0	0
T284	1668	13	0	0
T285	1143	6	0	0
T286	1468	9	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	2974	0	0
T70	14325	55	0	0
T75	2952	4	0	0
T235	2474	9	0	0
T240	26469	260	0	0
T263	31613	181	0	0
T273	6188	25	0	0
T279	16030	194	0	0
T280	29176	230	0	0
T281	8294	61	0	0
T282	34522	343	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	2015	0	0
T70	14325	82	0	0
T235	2474	6	0	0
T240	26469	126	0	0
T263	31613	248	0	0
T273	6188	25	0	0
T279	16030	130	0	0
T280	29176	122	0	0
T281	8294	15	0	0
T282	34522	209	0	0
T283	4562	11	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	2940	0	0
T70	14325	64	0	0
T75	2952	3	0	0
T235	2474	2	0	0
T240	26469	237	0	0
T263	31613	199	0	0
T273	6188	26	0	0
T279	16030	236	0	0
T280	29176	262	0	0
T281	8294	68	0	0
T282	34522	300	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	3034	0	0
T70	14325	55	0	0
T235	2474	10	0	0
T240	26469	258	0	0
T263	31613	228	0	0
T273	6188	29	0	0
T279	16030	265	0	0
T280	29176	260	0	0
T281	8294	57	0	0
T282	34522	188	0	0
T283	4562	43	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	2887	0	0
T70	14325	67	0	0
T75	2952	3	0	0
T235	2474	6	0	0
T240	26469	265	0	0
T263	31613	179	0	0
T279	16030	316	0	0
T280	29176	244	0	0
T281	8294	55	0	0
T282	34522	148	0	0
T283	4562	1	0	0