Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.91	100.00	67.63			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_rxfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.usbdev_avsetupfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.usbdev_avoutfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.14	92.59	67.16	94.27		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.14	92.59	67.16	94.27		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.14	92.59	67.16	94.27		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.62	100.00

tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	LINE
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T34,T92
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T20,T61

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T61

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T20,T61,T29
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T61

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T20,T61

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T20,T61

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T34,T92
1	0	Covered	T1,T20,T61
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T20,T61
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
91.07	64.29

tb.dut.usbdev_avsetupfifo

SCORE	COND
91.07	64.29

tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T57,T58
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T7

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.usbdev_rxfifo

SCORE	COND
92.19	68.75

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T61
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T19

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T61
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T20,T61

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T61

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T61

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T20,T61
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T61
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T20,T61

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T61
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.62	100.00

tb.dut.usbdev_rxfifo

SCORE	BRANCH
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	BRANCH
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	451648907	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	447317858	0	0
gen_passthru_fifo.paramCheckPass	8886	8886	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	451648907	0	0
T1	4866264	401713	0	0
T2	116520	19142	0	0
T3	4822644	400375	0	0
T7	4842780	401771	0	0
T8	4826640	401138	0	0
T12	0	24275	0	0
T15	4843704	400350	0	0
T18	4855176	401653	0	0
T19	4868244	402204	0	0
T20	4829676	400711	0	0
T21	4823484	400462	0	0
T29	0	400725	0	0
T34	0	266	0	0
T41	0	400593	0	0
T56	0	20	0	0
T59	0	402081	0	0
T60	0	401805	0	0
T61	0	10	0	0
T92	0	25	0	0
T93	0	10	0	0
T94	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4866264	4865364	0	0
T2	116520	115872	0	0
T3	4822644	4821588	0	0
T7	4842780	4841856	0	0
T8	4826640	4825512	0	0
T15	4843704	4842144	0	0
T18	4855176	4854360	0	0
T19	4868244	4867212	0	0
T20	4829676	4828956	0	0
T21	4823484	4822356	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4866264	4865364	0	0
T2	116520	115872	0	0
T3	4822644	4821588	0	0
T7	4842780	4841856	0	0
T8	4826640	4825512	0	0
T15	4843704	4842144	0	0
T18	4855176	4854360	0	0
T19	4868244	4867212	0	0
T20	4829676	4828956	0	0
T21	4823484	4822356	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4866264	4865364	0	0
T2	116520	115872	0	0
T3	4822644	4821588	0	0
T7	4842780	4841856	0	0
T8	4826640	4825512	0	0
T15	4843704	4842144	0	0
T18	4855176	4854360	0	0
T19	4868244	4867212	0	0
T20	4829676	4828956	0	0
T21	4823484	4822356	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	447317858	0	0
T1	2433132	401545	0	0
T2	58260	14514	0	0
T3	2411322	400255	0	0
T7	2421390	401727	0	0
T8	2413320	401106	0	0
T12	0	12733	0	0
T15	2421852	400250	0	0
T18	2427588	401555	0	0
T19	2434122	402152	0	0
T20	2414838	400551	0	0
T21	2411742	400332	0	0
T29	0	400693	0	0
T34	0	172	0	0
T41	0	400593	0	0
T56	0	12	0	0
T59	0	402081	0	0
T60	0	401805	0	0
T61	0	6	0	0
T92	0	16	0	0
T93	0	6	0	0
T94	0	6	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886	8886	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T7	6	6	0	0
T8	6	6	0	0
T15	6	6	0	0
T18	6	6	0	0
T19	6	6	0	0
T20	6	6	0	0
T21	6	6	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T19

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519586490	2244108	0	0
DepthKnown_A	519586490	519466039	0	0
RvalidKnown_A	519586490	519466039	0	0
WreadyKnown_A	519586490	519466039	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519586490	2244108	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	2244108	0	0
T1	405522	196	0	0
T2	9710	0	0	0
T3	401887	114	0	0
T7	403565	1120	0	0
T8	402220	0	0	0
T15	403642	0	0	0
T18	404598	2555	0	0
T19	405687	98	0	0
T20	402473	116	0	0
T21	401957	1186	0	0
T41	0	1660	0	0
T42	0	101	0	0
T61	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	2244108	0	0
T1	405522	196	0	0
T2	9710	0	0	0
T3	401887	114	0	0
T7	403565	1120	0	0
T8	402220	0	0	0
T15	403642	0	0	0
T18	404598	2555	0	0
T19	405687	98	0	0
T20	402473	116	0	0
T21	401957	1186	0	0
T41	0	1660	0	0
T42	0	101	0	0
T61	0	100	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T61
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T20,T61

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T61

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T61

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T20,T61
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T20,T61

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T61
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519586490	203161	0	0
DepthKnown_A	519586490	519466039	0	0
RvalidKnown_A	519586490	519466039	0	0
WreadyKnown_A	519586490	519466039	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519586490	203161	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	203161	0	0
T1	405522	8	0	0
T2	9710	0	0	0
T3	401887	0	0	0
T7	403565	0	0	0
T8	402220	0	0	0
T12	0	3481	0	0
T15	403642	0	0	0
T18	404598	0	0	0
T19	405687	0	0	0
T20	402473	2	0	0
T21	401957	0	0	0
T29	0	7	0	0
T34	0	16	0	0
T56	0	4	0	0
T61	0	2	0	0
T92	0	2	0	0
T93	0	2	0	0
T94	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	203161	0	0
T1	405522	8	0	0
T2	9710	0	0	0
T3	401887	0	0	0
T7	403565	0	0	0
T8	402220	0	0	0
T12	0	3481	0	0
T15	403642	0	0	0
T18	404598	0	0	0
T19	405687	0	0	0
T20	402473	2	0	0
T21	401957	0	0	0
T29	0	7	0	0
T34	0	16	0	0
T56	0	4	0	0
T61	0	2	0	0
T92	0	2	0	0
T93	0	2	0	0
T94	0	2	0	0

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T57,T58
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T29

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519586490	60570974	0	0
DepthKnown_A	519586490	519466039	0	0
RvalidKnown_A	519586490	519466039	0	0
WreadyKnown_A	519586490	519466039	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519586490	60570974	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	60570974	0	0
T1	405522	400472	0	0
T2	9710	6927	0	0
T3	401887	0	0	0
T7	403565	401727	0	0
T8	402220	0	0	0
T15	403642	0	0	0
T18	404598	0	0	0
T19	405687	0	0	0
T20	402473	0	0	0
T21	401957	0	0	0
T29	0	400663	0	0
T55	0	400496	0	0
T57	0	1231	0	0
T59	0	402081	0	0
T60	0	401805	0	0
T95	0	400825	0	0
T96	0	401901	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	60570974	0	0
T1	405522	400472	0	0
T2	9710	6927	0	0
T3	401887	0	0	0
T7	403565	401727	0	0
T8	402220	0	0	0
T15	403642	0	0	0
T18	404598	0	0	0
T19	405687	0	0	0
T20	402473	0	0	0
T21	401957	0	0	0
T29	0	400663	0	0
T55	0	400496	0	0
T57	0	1231	0	0
T59	0	402081	0	0
T60	0	401805	0	0
T95	0	400825	0	0
T96	0	401901	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T57,T58
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T18

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519586490	383628781	0	0
DepthKnown_A	519586490	519466039	0	0
RvalidKnown_A	519586490	519466039	0	0
WreadyKnown_A	519586490	519466039	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519586490	383628781	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	383628781	0	0
T1	405522	1036	0	0
T2	9710	7587	0	0
T3	401887	400255	0	0
T7	403565	0	0	0
T8	402220	401106	0	0
T15	403642	400250	0	0
T18	404598	401555	0	0
T19	405687	402152	0	0
T20	402473	400537	0	0
T21	401957	400332	0	0
T41	0	400593	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	383628781	0	0
T1	405522	1036	0	0
T2	9710	7587	0	0
T3	401887	400255	0	0
T7	403565	0	0	0
T8	402220	401106	0	0
T15	403642	400250	0	0
T18	404598	401555	0	0
T19	405687	402152	0	0
T20	402473	400537	0	0
T21	401957	400332	0	0
T41	0	400593	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T61
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T20,T61

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T61

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T20,T61,T29
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T61

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T20,T61
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T20,T61

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T61
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519586490	419774	0	0
DepthKnown_A	519586490	519466039	0	0
RvalidKnown_A	519586490	519466039	0	0
WreadyKnown_A	519586490	519466039	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519586490	419774	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	419774	0	0
T1	405522	21	0	0
T2	9710	0	0	0
T3	401887	0	0	0
T7	403565	0	0	0
T8	402220	0	0	0
T12	0	5771	0	0
T15	403642	0	0	0
T18	404598	0	0	0
T19	405687	0	0	0
T20	402473	6	0	0
T21	401957	0	0	0
T29	0	16	0	0
T34	0	78	0	0
T56	0	4	0	0
T61	0	2	0	0
T92	0	7	0	0
T93	0	2	0	0
T94	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	419774	0	0
T1	405522	21	0	0
T2	9710	0	0	0
T3	401887	0	0	0
T7	403565	0	0	0
T8	402220	0	0	0
T12	0	5771	0	0
T15	403642	0	0	0
T18	404598	0	0	0
T19	405687	0	0	0
T20	402473	6	0	0
T21	401957	0	0	0
T29	0	16	0	0
T34	0	78	0	0
T56	0	4	0	0
T61	0	2	0	0
T92	0	7	0	0
T93	0	2	0	0
T94	0	2	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T34,T92
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T20,T61

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T61

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T20,T61,T29
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T61

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T20,T61

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T20,T61

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T34,T92
1	0	Covered	T1,T20,T61
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T20,T61
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T61
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T20,T61

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T61
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519586490	251060	0	0
DepthKnown_A	519586490	519466039	0	0
RvalidKnown_A	519586490	519466039	0	0
WreadyKnown_A	519586490	519466039	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519586490	251060	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	251060	0	0
T1	405522	8	0	0
T2	9710	0	0	0
T3	401887	0	0	0
T7	403565	0	0	0
T8	402220	0	0	0
T12	0	3481	0	0
T15	403642	0	0	0
T18	404598	0	0	0
T19	405687	0	0	0
T20	402473	6	0	0
T21	401957	0	0	0
T29	0	7	0	0
T34	0	78	0	0
T56	0	4	0	0
T61	0	2	0	0
T92	0	7	0	0
T93	0	2	0	0
T94	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	519466039	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519586490	251060	0	0
T1	405522	8	0	0
T2	9710	0	0	0
T3	401887	0	0	0
T7	403565	0	0	0
T8	402220	0	0	0
T12	0	3481	0	0
T15	403642	0	0	0
T18	404598	0	0	0
T19	405687	0	0	0
T20	402473	6	0	0
T21	401957	0	0	0
T29	0	7	0	0
T34	0	78	0	0
T56	0	4	0	0
T61	0	2	0	0
T92	0	7	0	0
T93	0	2	0	0
T94	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521076493	1058399	0	0
DepthKnown_A	521076493	520909103	0	0
RvalidKnown_A	521076493	520909103	0	0
WreadyKnown_A	521076493	520909103	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	1058399	0	0
T1	405522	42	0	0
T2	9710	1157	0	0
T3	401887	10	0	0
T7	403565	11	0	0
T8	402220	8	0	0
T15	403642	10	0	0
T18	404598	14	0	0
T19	405687	13	0	0
T20	402473	12	0	0
T21	401957	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521076493	1132386	0	0
DepthKnown_A	521076493	520909103	0	0
RvalidKnown_A	521076493	520909103	0	0
WreadyKnown_A	521076493	520909103	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	1132386	0	0
T1	405522	42	0	0
T2	9710	1157	0	0
T3	401887	50	0	0
T7	403565	11	0	0
T8	402220	8	0	0
T15	403642	40	0	0
T18	404598	35	0	0
T19	405687	13	0	0
T20	402473	68	0	0
T21	401957	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521076493	377444	0	0
DepthKnown_A	521076493	520909103	0	0
RvalidKnown_A	521076493	520909103	0	0
WreadyKnown_A	521076493	520909103	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	377444	0	0
T1	405522	21	0	0
T2	9710	0	0	0
T3	401887	0	0	0
T7	403565	0	0	0
T8	402220	0	0	0
T12	0	5771	0	0
T15	403642	0	0	0
T18	404598	0	0	0
T19	405687	0	0	0
T20	402473	2	0	0
T21	401957	0	0	0
T29	0	16	0	0
T34	0	16	0	0
T56	0	4	0	0
T61	0	2	0	0
T92	0	2	0	0
T93	0	2	0	0
T94	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521076493	472573	0	0
DepthKnown_A	521076493	520909103	0	0
RvalidKnown_A	521076493	520909103	0	0
WreadyKnown_A	521076493	520909103	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	472573	0	0
T1	405522	21	0	0
T2	9710	0	0	0
T3	401887	0	0	0
T7	403565	0	0	0
T8	402220	0	0	0
T12	0	5771	0	0
T15	403642	0	0	0
T18	404598	0	0	0
T19	405687	0	0	0
T20	402473	6	0	0
T21	401957	0	0	0
T29	0	16	0	0
T34	0	78	0	0
T56	0	4	0	0
T61	0	2	0	0
T92	0	7	0	0
T93	0	2	0	0
T94	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521076493	630434	0	0
DepthKnown_A	521076493	520909103	0	0
RvalidKnown_A	521076493	520909103	0	0
WreadyKnown_A	521076493	520909103	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	630434	0	0
T1	405522	21	0	0
T2	9710	1157	0	0
T3	401887	10	0	0
T7	403565	11	0	0
T8	402220	8	0	0
T15	403642	10	0	0
T18	404598	14	0	0
T19	405687	13	0	0
T20	402473	10	0	0
T21	401957	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521076493	659813	0	0
DepthKnown_A	521076493	520909103	0	0
RvalidKnown_A	521076493	520909103	0	0
WreadyKnown_A	521076493	520909103	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	659813	0	0
T1	405522	21	0	0
T2	9710	1157	0	0
T3	401887	50	0	0
T7	403565	11	0	0
T8	402220	8	0	0
T15	403642	40	0	0
T18	404598	35	0	0
T19	405687	13	0	0
T20	402473	62	0	0
T21	401957	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521076493	520909103	0	0
T1	405522	405447	0	0
T2	9710	9656	0	0
T3	401887	401799	0	0
T7	403565	403488	0	0
T8	402220	402126	0	0
T15	403642	403512	0	0
T18	404598	404530	0	0
T19	405687	405601	0	0
T20	402473	402413	0	0
T21	401957	401863	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0