Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	278956	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	488818	1		T2	19		T3	6945		T4	7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	486290	1		T2	21		T3	7210		T4	3
values[0x0]	139638	1		T2	2		T3	1547		T4	4
values[0x1]	141846	1		T2	3		T3	1604		T4	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	211360	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	556414	1		T2	20		T3	7804		T4	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2915	1		T3	4		T21	7		T58	3
valid_sources[0x01]	3007	1		T13	2		T32	1		T58	4
valid_sources[0x02]	2634	1		T3	2		T21	2		T58	3
valid_sources[0x03]	2313	1		T21	2		T42	1		T58	4
valid_sources[0x04]	2718	1		T21	2		T58	3		T9	57
valid_sources[0x05]	2852	1		T3	2		T58	9		T90	1
valid_sources[0x06]	6066	1		T3	2		T21	6		T56	1
valid_sources[0x07]	2520	1		T21	2		T58	3		T57	15
valid_sources[0x08]	2677	1		T3	354		T58	8		T9	69
valid_sources[0x09]	2589	1		T3	6		T21	1		T42	2
valid_sources[0x0a]	2845	1		T3	1		T21	1		T15	7
valid_sources[0x0b]	5344	1		T3	3		T21	2		T58	7
valid_sources[0x0c]	3753	1		T3	2		T21	5		T135	1
valid_sources[0x0d]	2705	1		T3	2		T18	2		T21	3
valid_sources[0x0e]	2371	1		T21	2		T58	7		T9	30
valid_sources[0x0f]	2840	1		T3	3		T21	2		T58	2
valid_sources[0x10]	2865	1		T3	3		T21	2		T58	1
valid_sources[0x11]	2204	1		T3	5		T21	2		T39	10
valid_sources[0x12]	3111	1		T3	2		T21	4		T58	8
valid_sources[0x13]	3246	1		T2	2		T3	196		T21	2
valid_sources[0x14]	2439	1		T3	202		T21	4		T58	2
valid_sources[0x15]	2390	1		T3	2		T21	2		T58	3
valid_sources[0x16]	2485	1		T3	20		T21	1		T58	6
valid_sources[0x17]	2614	1		T3	2		T21	2		T58	6
valid_sources[0x18]	3195	1		T3	4		T58	2		T9	89
valid_sources[0x19]	2543	1		T3	2		T58	8		T9	46
valid_sources[0x1a]	6424	1		T3	250		T21	1		T58	2
valid_sources[0x1b]	3002	1		T3	2		T21	5		T56	1
valid_sources[0x1c]	3788	1		T21	1		T58	9		T9	101
valid_sources[0x1d]	2516	1		T3	4		T38	1		T58	3
valid_sources[0x1e]	2769	1		T3	1		T21	2		T58	5
valid_sources[0x1f]	3189	1		T58	4		T9	48		T218	1
valid_sources[0x20]	3148	1		T21	4		T32	1		T58	1
valid_sources[0x21]	5453	1		T3	4		T19	1		T21	1
valid_sources[0x22]	2634	1		T3	3		T21	2		T58	3
valid_sources[0x23]	3325	1		T3	3		T21	2		T32	1
valid_sources[0x24]	2699	1		T3	2		T21	2		T58	4
valid_sources[0x25]	2112	1		T3	3		T21	1		T32	1
valid_sources[0x26]	2308	1		T3	1		T21	2		T58	4
valid_sources[0x27]	2678	1		T3	1		T21	5		T58	5
valid_sources[0x28]	2714	1		T3	164		T21	2		T42	1
valid_sources[0x29]	2734	1		T3	4		T21	2		T58	7
valid_sources[0x2a]	2844	1		T21	2		T58	7		T9	43
valid_sources[0x2b]	3029	1		T3	7		T21	3		T58	7
valid_sources[0x2c]	2783	1		T2	3		T21	2		T58	5
valid_sources[0x2d]	2553	1		T3	1		T31	1		T58	4
valid_sources[0x2e]	2748	1		T21	3		T58	2		T207	1
valid_sources[0x2f]	3048	1		T3	281		T21	5		T58	5
valid_sources[0x30]	2690	1		T3	58		T21	1		T58	3
valid_sources[0x31]	2968	1		T3	467		T20	2		T58	6
valid_sources[0x32]	2566	1		T3	1		T21	4		T58	4
valid_sources[0x33]	2377	1		T3	271		T20	1		T21	2
valid_sources[0x34]	2550	1		T3	2		T21	2		T58	4
valid_sources[0x35]	2922	1		T4	1		T58	5		T9	134
valid_sources[0x36]	2577	1		T3	3		T58	2		T9	44
valid_sources[0x37]	3538	1		T3	47		T19	2		T21	2
valid_sources[0x38]	3292	1		T2	3		T3	8		T21	3
valid_sources[0x39]	2595	1		T3	1		T32	1		T58	6
valid_sources[0x3a]	5736	1		T3	2		T19	1		T20	1
valid_sources[0x3b]	2466	1		T3	1		T21	2		T58	8
valid_sources[0x3c]	4237	1		T3	4		T58	1		T289	1
valid_sources[0x3d]	2378	1		T3	2		T21	2		T13	2
valid_sources[0x3e]	2964	1		T3	142		T21	2		T58	4
valid_sources[0x3f]	2563	1		T3	172		T21	1		T58	6
valid_sources[0x40]	3354	1		T2	1		T4	1		T20	1
valid_sources[0x41]	2483	1		T3	2		T21	3		T56	1
valid_sources[0x42]	2694	1		T3	4		T21	1		T58	4
valid_sources[0x43]	4013	1		T3	3		T21	2		T58	2
valid_sources[0x44]	2644	1		T21	5		T58	4		T9	97
valid_sources[0x45]	2495	1		T3	6		T21	2		T58	5
valid_sources[0x46]	3272	1		T3	2		T21	3		T58	11
valid_sources[0x47]	3410	1		T3	107		T21	5		T58	6
valid_sources[0x48]	2221	1		T3	3		T20	1		T21	1
valid_sources[0x49]	2852	1		T3	3		T21	3		T58	9
valid_sources[0x4a]	2711	1		T3	37		T21	3		T58	1
valid_sources[0x4b]	2594	1		T3	2		T21	3		T58	2
valid_sources[0x4c]	3353	1		T58	7		T53	2		T9	77
valid_sources[0x4d]	2589	1		T3	1		T21	2		T58	6
valid_sources[0x4e]	2552	1		T3	378		T21	3		T58	8
valid_sources[0x4f]	2642	1		T3	1		T21	2		T58	9
valid_sources[0x50]	2996	1		T3	3		T58	4		T9	37
valid_sources[0x51]	2270	1		T3	6		T21	2		T56	1
valid_sources[0x52]	2338	1		T3	5		T58	6		T9	81
valid_sources[0x53]	2649	1		T3	2		T58	8		T124	2
valid_sources[0x54]	2469	1		T2	1		T3	4		T21	1
valid_sources[0x55]	2803	1		T3	4		T21	3		T31	3
valid_sources[0x56]	2727	1		T3	62		T21	2		T41	12
valid_sources[0x57]	2177	1		T3	2		T21	4		T58	8
valid_sources[0x58]	2526	1		T21	2		T58	7		T144	1
valid_sources[0x59]	2837	1		T21	2		T32	1		T58	2
valid_sources[0x5a]	2459	1		T3	6		T19	1		T21	2
valid_sources[0x5b]	3032	1		T3	4		T21	2		T58	2
valid_sources[0x5c]	2677	1		T58	2		T90	1		T9	70
valid_sources[0x5d]	2437	1		T3	2		T14	3		T58	4
valid_sources[0x5e]	3036	1		T21	5		T42	1		T58	6
valid_sources[0x5f]	3142	1		T3	6		T21	4		T32	2
valid_sources[0x60]	2668	1		T3	1		T21	4		T58	5
valid_sources[0x61]	2986	1		T3	1		T21	5		T58	3
valid_sources[0x62]	3819	1		T3	15		T21	3		T58	7
valid_sources[0x63]	3504	1		T2	2		T3	1		T21	1
valid_sources[0x64]	5592	1		T3	3246		T21	3		T58	6
valid_sources[0x65]	3369	1		T3	4		T4	2		T21	1
valid_sources[0x66]	2568	1		T3	4		T21	7		T58	4
valid_sources[0x67]	3032	1		T58	5		T9	69		T93	1
valid_sources[0x68]	3037	1		T3	1		T21	1		T58	7
valid_sources[0x69]	2749	1		T21	2		T58	7		T90	2
valid_sources[0x6a]	6248	1		T3	4		T20	1		T21	2
valid_sources[0x6b]	2969	1		T18	6		T21	1		T58	3
valid_sources[0x6c]	2319	1		T3	2		T21	2		T58	7
valid_sources[0x6d]	3161	1		T3	1		T21	1		T40	2
valid_sources[0x6e]	3068	1		T3	2		T21	1		T40	6
valid_sources[0x6f]	2761	1		T3	6		T21	1		T58	4
valid_sources[0x70]	2652	1		T21	1		T58	10		T9	74
valid_sources[0x71]	2954	1		T3	97		T21	3		T135	2
valid_sources[0x72]	3308	1		T3	6		T21	3		T56	1
valid_sources[0x73]	2504	1		T3	2		T21	2		T58	5
valid_sources[0x74]	2375	1		T3	4		T21	5		T58	3
valid_sources[0x75]	2232	1		T21	1		T58	5		T9	163
valid_sources[0x76]	2777	1		T3	6		T21	1		T58	3
valid_sources[0x77]	5857	1		T3	3		T21	3		T58	7
valid_sources[0x78]	3673	1		T3	4		T21	4		T38	3
valid_sources[0x79]	3096	1		T3	3		T5	1		T58	4
valid_sources[0x7a]	2495	1		T3	3		T21	2		T58	6
valid_sources[0x7b]	3510	1		T3	3		T21	1		T38	1
valid_sources[0x7c]	2479	1		T3	4		T21	5		T58	5
valid_sources[0x7d]	3928	1		T3	1		T21	5		T58	10
valid_sources[0x7e]	4016	1		T3	1		T21	1		T38	2
valid_sources[0x7f]	2422	1		T21	1		T58	3		T90	1
valid_sources[0x80]	2178	1		T3	2		T58	7		T9	74

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

259998

1

T2

18

T3

3999

T4

2

values[0x0]

all_enables

biggest_size

117701

1

T2

1

T3

1458

T4

3

values[0x1]

all_enables

biggest_size

111119

1

T3

1488

T4

2

T16

9