Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	294991	1		T2	7		T3	3416		T4	3
full_word	489964	1		T2	19		T3	6945		T4	7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	784635	1		T2	26		T3	10361		T4	10
auto[TlIntgErrCmd]	128	1		T62	2		T214	9		T215	7
auto[TlIntgErrData]	98	1		T62	5		T214	4		T215	9
auto[TlIntgErrBoth]	94	1		T62	3		T214	7		T215	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	488405	1		T2	21		T3	7210		T4	3
auto[1]	296550	1		T2	5		T3	3151		T4	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	228034	1		T2	3		T3	3211		T4	1
auto[TlIntgErrNone]	partial	auto[1]	66665	1		T2	4		T3	205		T4	2
auto[TlIntgErrNone]	full_word	auto[0]	260213	1		T2	18		T3	3999		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	229723	1		T2	1		T3	2946		T4	5
auto[TlIntgErrCmd]	partial	auto[0]	51	1		T62	1		T214	4		T215	1
auto[TlIntgErrCmd]	partial	auto[1]	62	1		T62	1		T214	5		T215	6
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T210	1		T285	2		T211	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T210	1		T283	1		T286	2
auto[TlIntgErrData]	partial	auto[0]	52	1		T62	2		T214	4		T215	4
auto[TlIntgErrData]	partial	auto[1]	39	1		T62	2		T215	4		T210	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T215	1		T285	1		T286	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T62	1		T285	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T62	1		T214	2		T215	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T62	1		T214	5		T215	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T62	1		T284	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T286	1		T287	1		T288	1