Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.95	92.59	67.16	93.35		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	522769737	12850	0	0
ep_in_enable_rd_A	522769737	4336	0	0
ep_out_enable_rd_A	522769737	3603	0	0
in_iso_rd_A	522769737	3827	0	0
intr_enable_rd_A	522769737	5952	0	0
out_iso_rd_A	522769737	3549	0	0
phy_config_rd_A	522769737	2213	0	0
phy_pins_drive_rd_A	522769737	3212	0	0
rxenable_setup_rd_A	522769737	3949	0	0
set_nak_out_rd_A	522769737	3400	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	12850	0	0
T61	13744	21	0	0
T62	7984	3	0	0
T63	6443	16	0	0
T100	4185	16	0	0
T208	13985	1077	0	0
T209	6003	268	0	0
T213	5629	233	0	0
T234	10748	702	0	0
T235	3301	593	0	0
T239	4659	26	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	4336	0	0
T61	13744	19	0	0
T101	2543	4	0	0
T210	80596	284	0	0
T215	30444	728	0	0
T264	7033	54	0	0
T265	1994	7	0	0
T266	8499	49	0	0
T269	7982	75	0	0
T270	3493	6	0	0
T271	24567	266	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	3603	0	0
T61	13744	2	0	0
T210	80596	209	0	0
T215	30444	318	0	0
T264	7033	63	0	0
T265	1994	28	0	0
T266	8499	20	0	0
T269	7982	17	0	0
T270	3493	35	0	0
T271	24567	127	0	0
T272	16468	229	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	3827	0	0
T61	13744	20	0	0
T101	2543	39	0	0
T210	80596	370	0	0
T215	30444	519	0	0
T264	7033	46	0	0
T265	1994	27	0	0
T266	8499	35	0	0
T269	7982	49	0	0
T270	3493	8	0	0
T271	24567	193	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	5952	0	0
T61	13744	43	0	0
T72	1932	16	0	0
T73	1547	16	0	0
T75	4259	6	0	0
T101	2543	7	0	0
T264	7033	28	0	0
T266	8499	64	0	0
T269	7982	81	0	0
T270	3493	90	0	0
T273	2424	3	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	3549	0	0
T61	13744	51	0	0
T101	2543	46	0	0
T210	80596	187	0	0
T215	30444	352	0	0
T264	7033	31	0	0
T266	8499	30	0	0
T269	7982	32	0	0
T270	3493	9	0	0
T271	24567	83	0	0
T272	16468	327	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	2213	0	0
T61	13744	30	0	0
T101	2543	12	0	0
T210	80596	225	0	0
T215	30444	250	0	0
T256	3632	38	0	0
T264	7033	12	0	0
T266	8499	36	0	0
T269	7982	28	0	0
T271	24567	74	0	0
T272	16468	131	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	3212	0	0
T61	13744	22	0	0
T101	2543	24	0	0
T210	80596	172	0	0
T215	30444	405	0	0
T264	7033	32	0	0
T265	1994	1	0	0
T266	8499	67	0	0
T269	7982	28	0	0
T271	24567	75	0	0
T272	16468	199	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	3949	0	0
T61	13744	9	0	0
T101	2543	30	0	0
T210	80596	252	0	0
T215	30444	433	0	0
T264	7033	82	0	0
T265	1994	23	0	0
T266	8499	32	0	0
T269	7982	15	0	0
T270	3493	47	0	0
T271	24567	136	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	3400	0	0
T61	13744	18	0	0
T101	2543	57	0	0
T210	80596	187	0	0
T215	30444	386	0	0
T264	7033	53	0	0
T265	1994	5	0	0
T266	8499	53	0	0
T269	7982	20	0	0
T270	3493	50	0	0
T271	24567	148	0	0