Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.91	100.00	67.63			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_rxfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.usbdev_avsetupfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.usbdev_avoutfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.95	92.59	67.16	93.35		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.95	92.59	67.16	93.35		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.95	92.59	67.16	93.35		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.62	100.00

tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	LINE
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T87,T56
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T87
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T87,T56
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T4

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
91.07	64.29

tb.dut.usbdev_avsetupfifo

SCORE	COND
91.07	64.29

tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T58,T59
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.usbdev_rxfifo

SCORE	COND
92.19	68.75

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T16
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T16
0	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.62	100.00

tb.dut.usbdev_rxfifo

SCORE	BRANCH
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	BRANCH
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	453918302	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	448602833	0	0
gen_passthru_fifo.paramCheckPass	8886	8886	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	453918302	0	0
T2	4445188	402707	0	0
T3	1107623	457268	0	0
T4	4426180	400321	0	0
T5	4838376	70	0	0
T13	402454	0	0	0
T16	4855920	401616	0	0
T17	4841244	402885	0	0
T18	4853052	403569	0	0
T19	4872804	400756	0	0
T20	4847640	401129	0	0
T21	71904	12072	0	0
T22	0	402341	0	0
T28	0	402089	0	0
T32	0	80	0	0
T37	403349	400321	0	0
T42	402395	0	0	0
T56	0	25	0	0
T58	0	3140	0	0
T59	0	821	0	0
T87	0	206	0	0
T88	0	35	0	0
T89	0	40	0	0
T90	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T2	4849296	4848324	0	0
T3	1208316	1208232	0	0
T4	4828560	4827852	0	0
T5	4838376	4837632	0	0
T16	4855920	4855080	0	0
T17	4841244	4840620	0	0
T18	4853052	4851888	0	0
T19	4872804	4871772	0	0
T20	4847640	4846776	0	0
T21	71904	70908	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T2	4849296	4848324	0	0
T3	1208316	1208232	0	0
T4	4828560	4827852	0	0
T5	4838376	4837632	0	0
T16	4855920	4855080	0	0
T17	4841244	4840620	0	0
T18	4853052	4851888	0	0
T19	4872804	4871772	0	0
T20	4847640	4846776	0	0
T21	71904	70908	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T2	4849296	4848324	0	0
T3	1208316	1208232	0	0
T4	4828560	4827852	0	0
T5	4838376	4837632	0	0
T16	4855920	4855080	0	0
T17	4841244	4840620	0	0
T18	4853052	4851888	0	0
T19	4872804	4871772	0	0
T20	4847640	4846776	0	0
T21	71904	70908	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	448602833	0	0
T2	2020540	402497	0	0
T3	503465	414638	0	0
T4	2011900	400251	0	0
T5	2419188	0	0	0
T13	402454	0	0	0
T16	2427960	401472	0	0
T17	2420622	402779	0	0
T18	2426526	403521	0	0
T19	2436402	400704	0	0
T20	2423820	401019	0	0
T21	35952	8042	0	0
T22	0	402341	0	0
T28	0	402089	0	0
T32	0	48	0	0
T37	403349	400321	0	0
T42	402395	0	0	0
T56	0	16	0	0
T58	0	3140	0	0
T59	0	821	0	0
T87	0	134	0	0
T88	0	21	0	0
T89	0	26	0	0
T90	0	45	0	0
T91	0	400704	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886	8886	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0
T18	6	6	0	0
T19	6	6	0	0
T20	6	6	0	0
T21	6	6	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521136041	2317429	0	0
DepthKnown_A	521136041	521016730	0	0
RvalidKnown_A	521136041	521016730	0	0
WreadyKnown_A	521136041	521016730	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	521136041	2317429	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	2317429	0	0
T2	404108	112	0	0
T3	100693	27931	0	0
T4	402380	1454	0	0
T5	403198	0	0	0
T16	404660	214	0	0
T17	403437	0	0	0
T18	404421	140	0	0
T19	406067	94	0	0
T20	403970	104	0	0
T21	5992	0	0	0
T32	0	106	0	0
T37	0	1267	0	0
T42	0	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	2317429	0	0
T2	404108	112	0	0
T3	100693	27931	0	0
T4	402380	1454	0	0
T5	403198	0	0	0
T16	404660	214	0	0
T17	403437	0	0	0
T18	404421	140	0	0
T19	406067	94	0	0
T20	403970	104	0	0
T21	5992	0	0	0
T32	0	106	0	0
T37	0	1267	0	0
T42	0	106	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T16
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521136041	208845	0	0
DepthKnown_A	521136041	521016730	0	0
RvalidKnown_A	521136041	521016730	0	0
WreadyKnown_A	521136041	521016730	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	521136041	208845	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	208845	0	0
T2	404108	16	0	0
T3	100693	3845	0	0
T4	402380	0	0	0
T5	403198	0	0	0
T16	404660	8	0	0
T17	403437	0	0	0
T18	404421	0	0	0
T19	406067	2	0	0
T20	403970	0	0	0
T21	5992	0	0	0
T32	0	16	0	0
T56	0	2	0	0
T87	0	10	0	0
T88	0	7	0	0
T89	0	2	0	0
T90	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	208845	0	0
T2	404108	16	0	0
T3	100693	3845	0	0
T4	402380	0	0	0
T5	403198	0	0	0
T16	404660	8	0	0
T17	403437	0	0	0
T18	404421	0	0	0
T19	406067	2	0	0
T20	403970	0	0	0
T21	5992	0	0	0
T32	0	16	0	0
T56	0	2	0	0
T87	0	10	0	0
T88	0	7	0	0
T89	0	2	0	0
T90	0	15	0	0

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T58,T59
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T16,T21,T22

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T16,T21,T22

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T16,T21,T22
1	1	0	Not Covered
1	1	1	Covered	T16,T22,T28

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T16,T21,T22
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521136041	60601384	0	0
DepthKnown_A	521136041	521016730	0	0
RvalidKnown_A	521136041	521016730	0	0
WreadyKnown_A	521136041	521016730	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	521136041	60601384	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	60601384	0	0
T5	403198	0	0	0
T9	0	244668	0	0
T13	402454	0	0	0
T16	404660	400432	0	0
T17	403437	0	0	0
T18	404421	0	0	0
T19	406067	0	0	0
T20	403970	0	0	0
T21	5992	4206	0	0
T22	0	402341	0	0
T28	0	402089	0	0
T37	403349	0	0	0
T42	402395	0	0	0
T58	0	3140	0	0
T59	0	821	0	0
T91	0	400704	0	0
T92	0	400467	0	0
T93	0	400418	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	60601384	0	0
T5	403198	0	0	0
T9	0	244668	0	0
T13	402454	0	0	0
T16	404660	400432	0	0
T17	403437	0	0	0
T18	404421	0	0	0
T19	406067	0	0	0
T20	403970	0	0	0
T21	5992	4206	0	0
T22	0	402341	0	0
T28	0	402089	0	0
T37	403349	0	0	0
T42	402395	0	0	0
T58	0	3140	0	0
T59	0	821	0	0
T91	0	400704	0	0
T92	0	400467	0	0
T93	0	400418	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T58,T59
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521136041	384321723	0	0
DepthKnown_A	521136041	521016730	0	0
RvalidKnown_A	521136041	521016730	0	0
WreadyKnown_A	521136041	521016730	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	521136041	384321723	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	384321723	0	0
T2	404108	402405	0	0
T3	100693	400800	0	0
T4	402380	400251	0	0
T5	403198	0	0	0
T16	404660	1009	0	0
T17	403437	402779	0	0
T18	404421	403521	0	0
T19	406067	400698	0	0
T20	403970	401019	0	0
T21	5992	3836	0	0
T37	0	400321	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	384321723	0	0
T2	404108	402405	0	0
T3	100693	400800	0	0
T4	402380	400251	0	0
T5	403198	0	0	0
T16	404660	1009	0	0
T17	403437	402779	0	0
T18	404421	403521	0	0
T19	406067	400698	0	0
T20	403970	401019	0	0
T21	5992	3836	0	0
T37	0	400321	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T87
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T16
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521136041	722069	0	0
DepthKnown_A	521136041	521016730	0	0
RvalidKnown_A	521136041	521016730	0	0
WreadyKnown_A	521136041	521016730	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	521136041	722069	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	722069	0	0
T2	404108	38	0	0
T3	100693	6148	0	0
T4	402380	0	0	0
T5	403198	0	0	0
T16	404660	15	0	0
T17	403437	0	0	0
T18	404421	0	0	0
T19	406067	2	0	0
T20	403970	0	0	0
T21	5992	0	0	0
T32	0	16	0	0
T56	0	7	0	0
T87	0	62	0	0
T88	0	7	0	0
T89	0	12	0	0
T90	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	722069	0	0
T2	404108	38	0	0
T3	100693	6148	0	0
T4	402380	0	0	0
T5	403198	0	0	0
T16	404660	15	0	0
T17	403437	0	0	0
T18	404421	0	0	0
T19	406067	2	0	0
T20	403970	0	0	0
T21	5992	0	0	0
T32	0	16	0	0
T56	0	7	0	0
T87	0	62	0	0
T88	0	7	0	0
T89	0	12	0	0
T90	0	15	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T87,T56
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T87
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T87,T56
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T16
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T16
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521136041	431383	0	0
DepthKnown_A	521136041	521016730	0	0
RvalidKnown_A	521136041	521016730	0	0
WreadyKnown_A	521136041	521016730	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	521136041	431383	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	431383	0	0
T2	404108	38	0	0
T3	100693	3845	0	0
T4	402380	0	0	0
T5	403198	0	0	0
T16	404660	8	0	0
T17	403437	0	0	0
T18	404421	0	0	0
T19	406067	2	0	0
T20	403970	0	0	0
T21	5992	0	0	0
T32	0	16	0	0
T56	0	7	0	0
T87	0	62	0	0
T88	0	7	0	0
T89	0	12	0	0
T90	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	521016730	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	521136041	431383	0	0
T2	404108	38	0	0
T3	100693	3845	0	0
T4	402380	0	0	0
T5	403198	0	0	0
T16	404660	8	0	0
T17	403437	0	0	0
T18	404421	0	0	0
T19	406067	2	0	0
T20	403970	0	0	0
T21	5992	0	0	0
T32	0	16	0	0
T56	0	7	0	0
T87	0	62	0	0
T88	0	7	0	0
T89	0	12	0	0
T90	0	15	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522769737	1055182	0	0
DepthKnown_A	522769737	522596208	0	0
RvalidKnown_A	522769737	522596208	0	0
WreadyKnown_A	522769737	522596208	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	1055182	0	0
T2	404108	26	0	0
T3	100693	11547	0	0
T4	402380	10	0	0
T5	403198	7	0	0
T16	404660	36	0	0
T17	403437	8	0	0
T18	404421	12	0	0
T19	406067	13	0	0
T20	403970	15	0	0
T21	5992	498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522769737	1633335	0	0
DepthKnown_A	522769737	522596208	0	0
RvalidKnown_A	522769737	522596208	0	0
WreadyKnown_A	522769737	522596208	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	1633335	0	0
T2	404108	79	0	0
T3	100693	10361	0	0
T4	402380	25	0	0
T5	403198	28	0	0
T16	404660	36	0	0
T17	403437	45	0	0
T18	404421	12	0	0
T19	406067	13	0	0
T20	403970	40	0	0
T21	5992	1517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522769737	386515	0	0
DepthKnown_A	522769737	522596208	0	0
RvalidKnown_A	522769737	522596208	0	0
WreadyKnown_A	522769737	522596208	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	386515	0	0
T2	404108	16	0	0
T3	100693	6148	0	0
T4	402380	0	0	0
T5	403198	0	0	0
T16	404660	15	0	0
T17	403437	0	0	0
T18	404421	0	0	0
T19	406067	2	0	0
T20	403970	0	0	0
T21	5992	0	0	0
T32	0	16	0	0
T56	0	2	0	0
T87	0	10	0	0
T88	0	7	0	0
T89	0	2	0	0
T90	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522769737	776486	0	0
DepthKnown_A	522769737	522596208	0	0
RvalidKnown_A	522769737	522596208	0	0
WreadyKnown_A	522769737	522596208	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	776486	0	0
T2	404108	38	0	0
T3	100693	6148	0	0
T4	402380	0	0	0
T5	403198	0	0	0
T16	404660	15	0	0
T17	403437	0	0	0
T18	404421	0	0	0
T19	406067	2	0	0
T20	403970	0	0	0
T21	5992	0	0	0
T32	0	16	0	0
T56	0	7	0	0
T87	0	62	0	0
T88	0	7	0	0
T89	0	12	0	0
T90	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522769737	607102	0	0
DepthKnown_A	522769737	522596208	0	0
RvalidKnown_A	522769737	522596208	0	0
WreadyKnown_A	522769737	522596208	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	607102	0	0
T2	404108	10	0	0
T3	100693	4213	0	0
T4	402380	10	0	0
T5	403198	7	0	0
T16	404660	21	0	0
T17	403437	8	0	0
T18	404421	12	0	0
T19	406067	11	0	0
T20	403970	15	0	0
T21	5992	498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522769737	856849	0	0
DepthKnown_A	522769737	522596208	0	0
RvalidKnown_A	522769737	522596208	0	0
WreadyKnown_A	522769737	522596208	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	856849	0	0
T2	404108	41	0	0
T3	100693	4213	0	0
T4	402380	25	0	0
T5	403198	28	0	0
T16	404660	21	0	0
T17	403437	45	0	0
T18	404421	12	0	0
T19	406067	11	0	0
T20	403970	40	0	0
T21	5992	1517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522769737	522596208	0	0
T2	404108	404027	0	0
T3	100693	100686	0	0
T4	402380	402321	0	0
T5	403198	403136	0	0
T16	404660	404590	0	0
T17	403437	403385	0	0
T18	404421	404324	0	0
T19	406067	405981	0	0
T20	403970	403898	0	0
T21	5992	5909	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0