Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	115463	1		T1	4		T2	2		T3	3
all_values[1]	115463	1		T1	4		T2	2		T3	3
all_values[2]	115463	1		T1	4		T2	2		T3	3
all_values[3]	115463	1		T1	4		T2	2		T3	3
all_values[4]	115463	1		T1	4		T2	2		T3	3
all_values[5]	115463	1		T1	4		T2	2		T3	3
all_values[6]	115463	1		T1	4		T2	2		T3	3
all_values[7]	115463	1		T1	4		T2	2		T3	3
all_values[8]	115463	1		T1	4		T2	2		T3	3
all_values[9]	115463	1		T1	4		T2	2		T3	3
all_values[10]	115463	1		T1	4		T2	2		T3	3
all_values[11]	115463	1		T1	4		T2	2		T3	3
all_values[12]	115463	1		T1	4		T2	2		T3	3
all_values[13]	115463	1		T1	4		T2	2		T3	3
all_values[14]	115463	1		T1	4		T2	2		T3	3
all_values[15]	115463	1		T1	4		T2	2		T3	3
all_values[16]	115463	1		T1	4		T2	2		T3	3
all_values[17]	115463	1		T1	4		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2074518	1		T1	72		T2	36		T3	51
auto[1]	3816	1		T3	3		T17	3		T37	4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2073637	1		T1	72		T2	36		T3	54
auto[1]	4697	1		T73	67		T70	68		T74	68

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114480	1		T1	4		T2	2		T13	3
all_values[0]	auto[0]	auto[1]	128	1		T70	5		T74	4		T71	6
all_values[0]	auto[1]	auto[0]	723	1		T3	3		T17	3		T37	4
all_values[0]	auto[1]	auto[1]	132	1		T73	5		T74	1		T71	2
all_values[1]	auto[0]	auto[0]	114876	1		T1	4		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	146	1		T73	3		T70	1		T74	5
all_values[1]	auto[1]	auto[0]	328	1		T33	3		T35	3		T52	3
all_values[1]	auto[1]	auto[1]	113	1		T73	1		T70	3		T71	5
all_values[2]	auto[0]	auto[0]	115187	1		T1	4		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	142	1		T74	1		T71	2		T269	1
all_values[2]	auto[1]	auto[0]	31	1		T73	3		T71	2		T269	1
all_values[2]	auto[1]	auto[1]	103	1		T70	5		T74	4		T71	3
all_values[3]	auto[0]	auto[0]	115187	1		T1	4		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	115	1		T73	4		T70	3		T74	3
all_values[3]	auto[1]	auto[0]	24	1		T70	2		T71	3		T269	1
all_values[3]	auto[1]	auto[1]	137	1		T73	1		T74	1		T72	4
all_values[4]	auto[0]	auto[0]	115178	1		T1	4		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	124	1		T70	3		T71	4		T72	1
all_values[4]	auto[1]	auto[0]	25	1		T73	1		T74	5		T71	2
all_values[4]	auto[1]	auto[1]	136	1		T70	2		T71	2		T72	4
all_values[5]	auto[0]	auto[0]	115165	1		T1	4		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	145	1		T73	5		T70	5		T74	4
all_values[5]	auto[1]	auto[0]	27	1		T72	4		T269	4		T270	1
all_values[5]	auto[1]	auto[1]	126	1		T71	6		T75	2		T76	4
all_values[6]	auto[0]	auto[0]	115173	1		T1	4		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	148	1		T73	1		T74	4		T71	6
all_values[6]	auto[1]	auto[0]	21	1		T72	1		T271	1		T272	1
all_values[6]	auto[1]	auto[1]	121	1		T73	3		T70	5		T71	2
all_values[7]	auto[0]	auto[0]	115178	1		T1	4		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	124	1		T73	4		T71	2		T72	4
all_values[7]	auto[1]	auto[0]	33	1		T74	1		T71	1		T76	1
all_values[7]	auto[1]	auto[1]	128	1		T73	1		T70	5		T74	4
all_values[8]	auto[0]	auto[0]	115167	1		T1	4		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	126	1		T73	3		T74	1		T71	4
all_values[8]	auto[1]	auto[0]	26	1		T70	5		T269	1		T75	2
all_values[8]	auto[1]	auto[1]	144	1		T73	2		T74	3		T71	4
all_values[9]	auto[0]	auto[0]	115176	1		T1	4		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	138	1		T71	4		T72	1		T75	1
all_values[9]	auto[1]	auto[0]	31	1		T73	4		T70	2		T71	2
all_values[9]	auto[1]	auto[1]	118	1		T70	3		T74	5		T72	4
all_values[10]	auto[0]	auto[0]	115167	1		T1	4		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	130	1		T70	1		T74	4		T71	1
all_values[10]	auto[1]	auto[0]	24	1		T71	1		T273	1		T271	4
all_values[10]	auto[1]	auto[1]	142	1		T73	5		T70	4		T74	1
all_values[11]	auto[0]	auto[0]	115182	1		T1	4		T2	2		T3	3
all_values[11]	auto[0]	auto[1]	131	1		T70	2		T71	5		T72	2
all_values[11]	auto[1]	auto[0]	18	1		T270	1		T76	2		T273	1
all_values[11]	auto[1]	auto[1]	132	1		T73	5		T70	3		T71	3
all_values[12]	auto[0]	auto[0]	115169	1		T1	4		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	128	1		T73	2		T74	3		T71	5
all_values[12]	auto[1]	auto[0]	17	1		T70	1		T74	1		T270	1
all_values[12]	auto[1]	auto[1]	149	1		T73	3		T70	4		T74	1
all_values[13]	auto[0]	auto[0]	115181	1		T1	4		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	124	1		T73	4		T74	4		T71	5
all_values[13]	auto[1]	auto[0]	26	1		T70	2		T74	1		T269	2
all_values[13]	auto[1]	auto[1]	132	1		T73	1		T71	3		T72	4
all_values[14]	auto[0]	auto[0]	115180	1		T1	4		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	113	1		T73	1		T74	1		T71	1
all_values[14]	auto[1]	auto[0]	37	1		T70	2		T71	2		T270	1
all_values[14]	auto[1]	auto[1]	133	1		T73	4		T74	4		T71	4
all_values[15]	auto[0]	auto[0]	115188	1		T1	4		T2	2		T3	3
all_values[15]	auto[0]	auto[1]	142	1		T71	4		T269	4		T270	4
all_values[15]	auto[1]	auto[0]	22	1		T73	4		T74	1		T72	1
all_values[15]	auto[1]	auto[1]	111	1		T70	5		T71	2		T72	3
all_values[16]	auto[0]	auto[0]	115174	1		T1	4		T2	2		T3	3
all_values[16]	auto[0]	auto[1]	118	1		T70	5		T74	1		T71	4
all_values[16]	auto[1]	auto[0]	24	1		T71	1		T72	4		T274	1
all_values[16]	auto[1]	auto[1]	147	1		T73	5		T74	4		T71	3
all_values[17]	auto[0]	auto[0]	115173	1		T1	4		T2	2		T3	3
all_values[17]	auto[0]	auto[1]	115	1		T73	4		T70	1		T74	4
all_values[17]	auto[1]	auto[0]	19	1		T73	1		T269	1		T270	1
all_values[17]	auto[1]	auto[1]	156	1		T70	3		T74	1		T71	4