| | | | | | | |
tb.dut.AlertsKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.CIODnEnKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.CIODnKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.CIODpEnKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.CIODpKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 518452614 | 70 | 0 | 0 |
|
tb.dut.TlOAReadyKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.TlODValidKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBAonSuspendReqKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBAonWakeAckKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBDnPUKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBDpPUKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrAvOutEmptyKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrAvOverKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrAvSetupEmptyKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrDisConKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrFrameKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrHostLostKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrLinkInErrKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrLinkOutErrKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrLinkResKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrLinkRstKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrLinkSusKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrPktRcvdKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrPktSentKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrPwrdKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrRxBitstuffErrKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrRxCrCErrKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrRxFullKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBIntrRxPidErrKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBRefPulseKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBRefValKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBRxEnableKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBTxDKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.USBTxSe0Known_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_memory_1p.CannotHaveEccAndParity_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_memory_1p.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_memory_1p.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A
| 0 | 0 | 518452614 | 295026 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_memory_1p.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheck_A
| 0 | 0 | 518452614 | 295026 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_memory_1p.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheck_A
| 0 | 0 | 518452614 | 295026 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_memory_1p.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheck_A
| 0 | 0 | 518452614 | 295026 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.AddrOutKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.DataIntgOptions_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.ReqOutKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.SramDwHasByteGranularity_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.SramDwIsMultipleOfTlulWidth_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.TlOutKnownIfFifoKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.TlOutValidKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.WdataOutKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.WeOutKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.WmaskOutKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.adapterNoReadOrWrite
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.rvalidHighReqFifoEmpty
| 0 | 0 | 518452614 | 209234 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.rvalidHighWhenRspFifoFull
| 0 | 0 | 518452614 | 209234 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_err.dataWidthOnly32_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.DataKnown_A
| 0 | 0 | 518452614 | 550426 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.DepthKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.RvalidKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.WreadyKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 518452614 | 550426 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rsp_gen.DataWidthCheck_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rsp_gen.PayLoadWidthCheck
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.DataKnown_A
| 0 | 0 | 518452614 | 330874 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.DepthKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.RvalidKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.WreadyKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 518452614 | 330874 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.DataKnown_A
| 0 | 0 | 518452614 | 209234 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.DepthKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.RvalidKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.WreadyKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 518452614 | 209234 | 0 | 0 |
|
tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 598059 | 596758 | 0 | 0 |
|
tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 594061 | 592770 | 0 | 0 |
|
tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 598059 | 596758 | 0 | 0 |
|
tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 34767 | 33669 | 0 | 0 |
|
tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 34767 | 33669 | 0 | 0 |
|
tb.dut.intr_av_out_empty.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_av_overflow.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_av_setup_empty.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_disconnected.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_frame.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_host_lost.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_hw_pkt_received.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_hw_pkt_sent.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_link_in_err.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_link_out_err.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_link_reset.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_link_resume.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_link_suspend.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_powered.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_rx_bitstuff_err.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_rx_crc_err.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_rx_full.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.intr_rx_pid_err.IntrTKind_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_A
| 0 | 0 | 519983849 | 1100342 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_AKnownEnable
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.tlul_assert_device.aReadyKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_A
| 0 | 0 | 519983849 | 1342843 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_AKnownEnable
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.tlul_assert_device.dReadyKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 519983849 | 380580 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 519983849 | 4846 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 519983849 | 798798 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 519983849 | 782383 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 519983849 | 5105 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 519983849 | 1100342 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 519983849 | 1342843 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 519983849 | 1100342 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 519983849 | 1342843 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 519983849 | 1342843 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 519983849 | 1342843 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 519983849 | 3286 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 519983849 | 2904 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.en2addrHit
| 0 | 0 | 519983849 | 475903 | 0 | 0 |
|
tb.dut.u_reg.reAfterRv
| 0 | 0 | 519983849 | 475903 | 0 | 0 |
|
tb.dut.u_reg.rePulse
| 0 | 0 | 519983849 | 356010 | 0 | 0 |
|
tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_socket.NotOverflowed_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A
| 0 | 0 | 519983849 | 1100342 | 0 | 0 |
|
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A
| 0 | 0 | 519983849 | 1342843 | 0 | 0 |
|
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 519983849 | 384159 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 519983849 | 594472 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 519983849 | 648027 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 519983849 | 748371 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_socket.maxN
| 0 | 0 | 1476 | 1476 | 0 | 0 |
|
tb.dut.u_reg.u_wake_control_cdc.BusySrcReqChk_A
| 0 | 0 | 519983849 | 179810 | 0 | 0 |
|
tb.dut.u_reg.u_wake_control_cdc.DstReqKnown_A
| 0 | 0 | 11691761 | 11675998 | 0 | 0 |
|
tb.dut.u_reg.u_wake_control_cdc.SrcAckBusyChk_A
| 0 | 0 | 519983849 | 985 | 0 | 0 |
|
tb.dut.u_reg.u_wake_control_cdc.SrcBusyKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 519983849 | 985 | 0 | 0 |
|
tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 11691761 | 985 | 0 | 0 |
|
tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 11691761 | 980 | 0 | 0 |
|
tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 519983849 | 998 | 0 | 0 |
|
tb.dut.u_reg.u_wake_events_cdc.DstReqKnown_A
| 0 | 0 | 11691761 | 11675998 | 0 | 0 |
|
tb.dut.u_reg.u_wake_events_cdc.SrcBusyKnown_A
| 0 | 0 | 519983849 | 519821582 | 0 | 0 |
|
tb.dut.u_reg.wePulse
| 0 | 0 | 519983849 | 119893 | 0 | 0 |
|
tb.dut.usbdev_avoutfifo.DataKnown_A
| 0 | 0 | 518452614 | 382297271 | 0 | 0 |
|
tb.dut.usbdev_avoutfifo.DepthKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_avoutfifo.RvalidKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_avoutfifo.WreadyKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_avoutfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 518452614 | 382297271 | 0 | 0 |
|
tb.dut.usbdev_avsetupfifo.DataKnown_A
| 0 | 0 | 518452614 | 60599764 | 0 | 0 |
|
tb.dut.usbdev_avsetupfifo.DepthKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_avsetupfifo.RvalidKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_avsetupfifo.WreadyKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_avsetupfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 518452614 | 60599764 | 0 | 0 |
|
tb.dut.usbdev_csr_assert.TlulOOBAddrErr_A
| 0 | 0 | 519983849 | 10631 | 0 | 0 |
|
tb.dut.usbdev_csr_assert.ep_in_enable_rd_A
| 0 | 0 | 519983849 | 3747 | 0 | 0 |
|
tb.dut.usbdev_csr_assert.ep_out_enable_rd_A
| 0 | 0 | 519983849 | 3259 | 0 | 0 |
|
tb.dut.usbdev_csr_assert.in_iso_rd_A
| 0 | 0 | 519983849 | 3644 | 0 | 0 |
|
tb.dut.usbdev_csr_assert.intr_enable_rd_A
| 0 | 0 | 519983849 | 4644 | 0 | 0 |
|
tb.dut.usbdev_csr_assert.out_iso_rd_A
| 0 | 0 | 519983849 | 2716 | 0 | 0 |
|
tb.dut.usbdev_csr_assert.phy_config_rd_A
| 0 | 0 | 519983849 | 2173 | 0 | 0 |
|
tb.dut.usbdev_csr_assert.phy_pins_drive_rd_A
| 0 | 0 | 519983849 | 2546 | 0 | 0 |
|
tb.dut.usbdev_csr_assert.rxenable_setup_rd_A
| 0 | 0 | 519983849 | 3180 | 0 | 0 |
|
tb.dut.usbdev_csr_assert.set_nak_out_rd_A
| 0 | 0 | 519983849 | 3123 | 0 | 0 |
|
tb.dut.usbdev_impl.ParamAVFifoWidthValid
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.usbdev_impl.ParamMaxPktSizeByteValid
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.usbdev_impl.ParamNBufValid
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.usbdev_impl.ParamNEndpointsValid
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.usbdev_impl.ParamRXFifoWidthValid
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.usbdev_impl.ParamSramAwValid
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usb_fs_nb_pe.NumOutEpsEqualsNumInEps_A
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usb_fs_nb_pe.ParamMaxPktSizeByteValid
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usb_fs_nb_pe.ParamNumEpsOutAndInEqual
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usb_fs_nb_pe.ParamNumInEpsValid
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usb_fs_nb_pe.ParamNumOutEpsValid
| 0 | 0 | 1301 | 1301 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe.InXactStateValid_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe.OutXactStateValid_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.OutStateValid_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx.StateValid_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usbdev_linkstate.LincInacStateValid_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usbdev_linkstate.LinkRstStateValid_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_impl.u_usbdev_linkstate.LinkStateValid_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_rxfifo.DataKnown_A
| 0 | 0 | 518452614 | 2279760 | 0 | 0 |
|
tb.dut.usbdev_rxfifo.DepthKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_rxfifo.RvalidKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_rxfifo.WreadyKnown_A
| 0 | 0 | 518452614 | 518334354 | 0 | 0 |
|
tb.dut.usbdev_rxfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 518452614 | 2279760 | 0 | 0 |
|