Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.45 95.60 88.87 96.68 50.00 94.10 97.35 96.58


Total test records in report: 1476
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T1329 /workspace/coverage/default/14.usbdev_smoke.487541965 May 07 12:41:45 PM PDT 24 May 07 12:41:55 PM PDT 24 8446504818 ps
T1330 /workspace/coverage/default/19.usbdev_setup_trans_ignored.2603355794 May 07 12:42:23 PM PDT 24 May 07 12:42:32 PM PDT 24 8391665580 ps
T1331 /workspace/coverage/default/20.usbdev_enable.2231472504 May 07 12:42:26 PM PDT 24 May 07 12:42:36 PM PDT 24 8383676011 ps
T1332 /workspace/coverage/default/9.usbdev_setup_stage.976668879 May 07 12:41:51 PM PDT 24 May 07 12:42:01 PM PDT 24 8385227027 ps
T1333 /workspace/coverage/default/37.usbdev_setup_stage.894171494 May 07 12:43:35 PM PDT 24 May 07 12:43:44 PM PDT 24 8382805880 ps
T1334 /workspace/coverage/default/37.random_length_in_trans.2109292247 May 07 12:43:43 PM PDT 24 May 07 12:43:56 PM PDT 24 8429892564 ps
T1335 /workspace/coverage/default/9.usbdev_setup_trans_ignored.3321092807 May 07 12:41:33 PM PDT 24 May 07 12:41:44 PM PDT 24 8368406690 ps
T1336 /workspace/coverage/default/20.usbdev_out_trans_nak.3719973492 May 07 12:42:26 PM PDT 24 May 07 12:42:34 PM PDT 24 8415228372 ps
T1337 /workspace/coverage/default/39.usbdev_random_length_out_trans.2429355239 May 07 12:43:30 PM PDT 24 May 07 12:43:45 PM PDT 24 8396756200 ps
T1338 /workspace/coverage/default/7.random_length_in_trans.3989985914 May 07 12:41:36 PM PDT 24 May 07 12:41:47 PM PDT 24 8432314424 ps
T1339 /workspace/coverage/default/23.min_length_in_transaction.34271264 May 07 12:42:40 PM PDT 24 May 07 12:42:48 PM PDT 24 8378035022 ps
T1340 /workspace/coverage/default/14.min_length_in_transaction.2423777879 May 07 12:41:56 PM PDT 24 May 07 12:42:08 PM PDT 24 8377567727 ps
T1341 /workspace/coverage/default/44.usbdev_in_iso.2075590621 May 07 12:43:46 PM PDT 24 May 07 12:43:57 PM PDT 24 8441756266 ps
T1342 /workspace/coverage/default/34.usbdev_min_length_out_transaction.3805069515 May 07 12:43:37 PM PDT 24 May 07 12:43:47 PM PDT 24 8369915592 ps
T1343 /workspace/coverage/default/29.usbdev_in_stall.693169710 May 07 12:43:10 PM PDT 24 May 07 12:43:21 PM PDT 24 8364245711 ps
T1344 /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2937555482 May 07 12:42:14 PM PDT 24 May 07 12:42:24 PM PDT 24 8367119080 ps
T1345 /workspace/coverage/default/42.usbdev_av_buffer.1737899684 May 07 12:43:47 PM PDT 24 May 07 12:43:57 PM PDT 24 8399533575 ps
T1346 /workspace/coverage/default/6.usbdev_pending_in_trans.2954780941 May 07 12:41:33 PM PDT 24 May 07 12:41:43 PM PDT 24 8419771032 ps
T1347 /workspace/coverage/default/22.usbdev_setup_trans_ignored.1341772919 May 07 12:42:30 PM PDT 24 May 07 12:42:45 PM PDT 24 8401592976 ps
T1348 /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1344645084 May 07 12:43:08 PM PDT 24 May 07 12:43:20 PM PDT 24 8393889069 ps
T1349 /workspace/coverage/default/39.usbdev_pkt_buffer.4290575483 May 07 12:45:05 PM PDT 24 May 07 12:45:50 PM PDT 24 24551232207 ps
T1350 /workspace/coverage/default/2.usbdev_fifo_rst.2241951970 May 07 12:41:21 PM PDT 24 May 07 12:41:24 PM PDT 24 204711885 ps
T1351 /workspace/coverage/default/29.usbdev_max_length_out_transaction.1327297458 May 07 12:43:05 PM PDT 24 May 07 12:43:16 PM PDT 24 8423943374 ps
T1352 /workspace/coverage/default/30.usbdev_in_trans.556423219 May 07 12:42:56 PM PDT 24 May 07 12:43:07 PM PDT 24 8421802072 ps
T1353 /workspace/coverage/default/48.usbdev_pending_in_trans.1709399909 May 07 12:44:08 PM PDT 24 May 07 12:44:19 PM PDT 24 8380546952 ps
T1354 /workspace/coverage/default/33.min_length_in_transaction.3958760373 May 07 12:43:13 PM PDT 24 May 07 12:43:24 PM PDT 24 8379269741 ps
T1355 /workspace/coverage/default/15.usbdev_fifo_rst.2898238908 May 07 12:41:55 PM PDT 24 May 07 12:41:59 PM PDT 24 86180685 ps
T1356 /workspace/coverage/default/34.usbdev_pkt_received.2635827567 May 07 12:43:16 PM PDT 24 May 07 12:43:25 PM PDT 24 8400262238 ps
T1357 /workspace/coverage/default/22.usbdev_nak_trans.8687978 May 07 12:42:46 PM PDT 24 May 07 12:42:56 PM PDT 24 8406664971 ps
T1358 /workspace/coverage/default/35.usbdev_in_iso.2946491810 May 07 12:43:22 PM PDT 24 May 07 12:43:32 PM PDT 24 8451380766 ps
T1359 /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3771540588 May 07 12:44:34 PM PDT 24 May 07 12:44:47 PM PDT 24 8382627818 ps
T1360 /workspace/coverage/default/30.usbdev_phy_pins_sense.3978737648 May 07 12:42:57 PM PDT 24 May 07 12:43:00 PM PDT 24 44588242 ps
T1361 /workspace/coverage/default/32.usbdev_nak_trans.2104186160 May 07 12:43:19 PM PDT 24 May 07 12:43:29 PM PDT 24 8464285416 ps
T1362 /workspace/coverage/default/9.usbdev_random_length_out_trans.2897627391 May 07 12:41:35 PM PDT 24 May 07 12:41:46 PM PDT 24 8401350899 ps
T1363 /workspace/coverage/default/16.usbdev_pending_in_trans.3938402642 May 07 12:41:54 PM PDT 24 May 07 12:42:04 PM PDT 24 8412367065 ps
T1364 /workspace/coverage/default/11.usbdev_setup_stage.3226511437 May 07 12:41:51 PM PDT 24 May 07 12:42:00 PM PDT 24 8377396632 ps
T1365 /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1086984185 May 07 12:42:48 PM PDT 24 May 07 12:42:59 PM PDT 24 8381071900 ps
T1366 /workspace/coverage/default/35.usbdev_fifo_rst.1654915696 May 07 12:43:17 PM PDT 24 May 07 12:43:21 PM PDT 24 178326973 ps
T1367 /workspace/coverage/default/41.usbdev_in_iso.59278541 May 07 12:43:47 PM PDT 24 May 07 12:43:59 PM PDT 24 8431083120 ps
T1368 /workspace/coverage/default/38.usbdev_stall_trans.180851650 May 07 12:43:24 PM PDT 24 May 07 12:43:34 PM PDT 24 8400339281 ps
T1369 /workspace/coverage/default/14.usbdev_pending_in_trans.254012928 May 07 12:41:59 PM PDT 24 May 07 12:42:09 PM PDT 24 8391048689 ps
T1370 /workspace/coverage/default/4.usbdev_in_stall.4042455705 May 07 12:41:14 PM PDT 24 May 07 12:41:24 PM PDT 24 8375980192 ps
T1371 /workspace/coverage/default/40.usbdev_out_stall.2037336047 May 07 12:43:37 PM PDT 24 May 07 12:43:47 PM PDT 24 8414397664 ps
T1372 /workspace/coverage/default/45.usbdev_enable.3296209314 May 07 12:43:59 PM PDT 24 May 07 12:44:09 PM PDT 24 8386779039 ps
T1373 /workspace/coverage/default/0.usbdev_nak_trans.465307035 May 07 12:40:58 PM PDT 24 May 07 12:41:09 PM PDT 24 8428631745 ps
T1374 /workspace/coverage/default/7.usbdev_random_length_out_trans.2984500815 May 07 12:41:51 PM PDT 24 May 07 12:42:01 PM PDT 24 8385702389 ps
T1375 /workspace/coverage/default/17.usbdev_setup_trans_ignored.1646962475 May 07 12:42:11 PM PDT 24 May 07 12:42:23 PM PDT 24 8378843170 ps
T1376 /workspace/coverage/default/48.usbdev_in_stall.323478349 May 07 12:44:13 PM PDT 24 May 07 12:44:23 PM PDT 24 8380678317 ps
T1377 /workspace/coverage/default/12.random_length_in_trans.2675410360 May 07 12:41:45 PM PDT 24 May 07 12:41:57 PM PDT 24 8426854091 ps
T1378 /workspace/coverage/default/27.usbdev_out_stall.2284564652 May 07 12:43:21 PM PDT 24 May 07 12:43:31 PM PDT 24 8409656908 ps
T1379 /workspace/coverage/default/17.usbdev_smoke.3347646578 May 07 12:42:14 PM PDT 24 May 07 12:42:25 PM PDT 24 8406297481 ps
T68 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.618514071 May 07 12:39:30 PM PDT 24 May 07 12:39:33 PM PDT 24 101231928 ps
T73 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2673388111 May 07 12:39:53 PM PDT 24 May 07 12:39:56 PM PDT 24 37736783 ps
T65 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.47329570 May 07 12:39:35 PM PDT 24 May 07 12:39:37 PM PDT 24 74919843 ps
T58 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3247065429 May 07 12:39:41 PM PDT 24 May 07 12:39:45 PM PDT 24 333764888 ps
T66 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2516720902 May 07 12:39:22 PM PDT 24 May 07 12:39:25 PM PDT 24 159173839 ps
T67 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3435072670 May 07 12:39:28 PM PDT 24 May 07 12:39:37 PM PDT 24 981155736 ps
T59 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1637900350 May 07 12:39:32 PM PDT 24 May 07 12:39:34 PM PDT 24 70329461 ps
T99 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2185014281 May 07 12:39:50 PM PDT 24 May 07 12:39:53 PM PDT 24 71356401 ps
T60 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2998981602 May 07 12:39:22 PM PDT 24 May 07 12:39:26 PM PDT 24 73067671 ps
T70 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1987024734 May 07 12:39:43 PM PDT 24 May 07 12:39:45 PM PDT 24 39387123 ps
T74 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3484052993 May 07 12:39:51 PM PDT 24 May 07 12:39:53 PM PDT 24 37011618 ps
T71 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1885152254 May 07 12:39:51 PM PDT 24 May 07 12:39:53 PM PDT 24 54054170 ps
T100 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1599103600 May 07 12:39:23 PM PDT 24 May 07 12:39:26 PM PDT 24 72343801 ps
T101 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4261513315 May 07 12:39:52 PM PDT 24 May 07 12:39:55 PM PDT 24 102613272 ps
T102 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1895194053 May 07 12:39:35 PM PDT 24 May 07 12:39:40 PM PDT 24 659449836 ps
T263 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2258436976 May 07 12:39:38 PM PDT 24 May 07 12:39:40 PM PDT 24 124594158 ps
T1380 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3651863604 May 07 12:39:28 PM PDT 24 May 07 12:39:31 PM PDT 24 159780625 ps
T255 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.566086985 May 07 12:39:35 PM PDT 24 May 07 12:39:44 PM PDT 24 432395548 ps
T209 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1702294961 May 07 12:39:22 PM PDT 24 May 07 12:39:27 PM PDT 24 852748625 ps
T264 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2138663017 May 07 12:39:38 PM PDT 24 May 07 12:39:41 PM PDT 24 182882865 ps
T72 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.469416499 May 07 12:39:55 PM PDT 24 May 07 12:39:58 PM PDT 24 45591475 ps
T269 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3853128493 May 07 12:39:33 PM PDT 24 May 07 12:39:35 PM PDT 24 31060430 ps
T75 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2756773925 May 07 12:39:35 PM PDT 24 May 07 12:39:37 PM PDT 24 45623769 ps
T270 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3441288951 May 07 12:39:54 PM PDT 24 May 07 12:39:57 PM PDT 24 31459559 ps
T210 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1710340447 May 07 12:39:38 PM PDT 24 May 07 12:39:46 PM PDT 24 2266180664 ps
T212 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1877814608 May 07 12:39:38 PM PDT 24 May 07 12:39:43 PM PDT 24 249757672 ps
T76 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3668654261 May 07 12:39:44 PM PDT 24 May 07 12:39:46 PM PDT 24 40623871 ps
T213 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3596039273 May 07 12:39:45 PM PDT 24 May 07 12:39:48 PM PDT 24 133435365 ps
T268 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.35356149 May 07 12:39:41 PM PDT 24 May 07 12:39:43 PM PDT 24 52510970 ps
T256 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.593807302 May 07 12:39:35 PM PDT 24 May 07 12:39:40 PM PDT 24 110435705 ps
T274 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3206056437 May 07 12:39:32 PM PDT 24 May 07 12:39:34 PM PDT 24 28116880 ps
T249 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3065624235 May 07 12:39:47 PM PDT 24 May 07 12:39:51 PM PDT 24 435910049 ps
T273 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.952752051 May 07 12:39:44 PM PDT 24 May 07 12:39:51 PM PDT 24 34038780 ps
T237 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1424196564 May 07 12:39:37 PM PDT 24 May 07 12:39:40 PM PDT 24 135848681 ps
T1381 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3681620076 May 07 12:39:29 PM PDT 24 May 07 12:39:40 PM PDT 24 1218330107 ps
T236 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4254828745 May 07 12:39:16 PM PDT 24 May 07 12:39:20 PM PDT 24 69938186 ps
T248 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.140037215 May 07 12:39:52 PM PDT 24 May 07 12:39:55 PM PDT 24 168066998 ps
T286 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2640637730 May 07 12:39:30 PM PDT 24 May 07 12:39:34 PM PDT 24 231561337 ps
T1382 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.966793273 May 07 12:39:23 PM PDT 24 May 07 12:39:28 PM PDT 24 371378006 ps
T271 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3880924161 May 07 12:39:36 PM PDT 24 May 07 12:39:38 PM PDT 24 37640532 ps
T1383 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2575095031 May 07 12:39:49 PM PDT 24 May 07 12:39:58 PM PDT 24 164995092 ps
T272 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.982602537 May 07 12:39:57 PM PDT 24 May 07 12:40:00 PM PDT 24 25692741 ps
T1384 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.812554553 May 07 12:39:51 PM PDT 24 May 07 12:39:54 PM PDT 24 152943473 ps
T247 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1309186757 May 07 12:39:52 PM PDT 24 May 07 12:39:56 PM PDT 24 78072284 ps
T276 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1100490272 May 07 12:39:45 PM PDT 24 May 07 12:39:47 PM PDT 24 32955421 ps
T1385 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4088088896 May 07 12:39:51 PM PDT 24 May 07 12:39:53 PM PDT 24 70180084 ps
T1386 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.358734613 May 07 12:39:14 PM PDT 24 May 07 12:39:19 PM PDT 24 254388738 ps
T257 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1474385327 May 07 12:39:18 PM PDT 24 May 07 12:39:22 PM PDT 24 99552858 ps
T239 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1296856599 May 07 12:39:39 PM PDT 24 May 07 12:39:43 PM PDT 24 147649856 ps
T244 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3112291789 May 07 12:39:33 PM PDT 24 May 07 12:39:34 PM PDT 24 72400979 ps
T211 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.346880066 May 07 12:39:21 PM PDT 24 May 07 12:39:25 PM PDT 24 169087741 ps
T240 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.446266743 May 07 12:39:34 PM PDT 24 May 07 12:39:38 PM PDT 24 115999528 ps
T238 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1447816440 May 07 12:39:36 PM PDT 24 May 07 12:39:40 PM PDT 24 195047201 ps
T258 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.409393923 May 07 12:39:18 PM PDT 24 May 07 12:39:23 PM PDT 24 155359136 ps
T277 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2607349828 May 07 12:39:55 PM PDT 24 May 07 12:39:59 PM PDT 24 59640906 ps
T287 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3610551065 May 07 12:39:29 PM PDT 24 May 07 12:39:35 PM PDT 24 756196111 ps
T241 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.253726153 May 07 12:39:31 PM PDT 24 May 07 12:39:35 PM PDT 24 110414649 ps
T259 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4268265190 May 07 12:39:32 PM PDT 24 May 07 12:39:34 PM PDT 24 45450988 ps
T242 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1178646260 May 07 12:39:19 PM PDT 24 May 07 12:39:23 PM PDT 24 119027082 ps
T295 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.995884597 May 07 12:39:40 PM PDT 24 May 07 12:39:44 PM PDT 24 352385942 ps
T246 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.4125070607 May 07 12:39:25 PM PDT 24 May 07 12:39:27 PM PDT 24 55783242 ps
T260 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2713712608 May 07 12:39:26 PM PDT 24 May 07 12:39:35 PM PDT 24 1141810240 ps
T1387 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.348339076 May 07 12:39:45 PM PDT 24 May 07 12:39:48 PM PDT 24 109883838 ps
T265 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1842647499 May 07 12:39:45 PM PDT 24 May 07 12:39:47 PM PDT 24 40883201 ps
T261 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.667002967 May 07 12:39:12 PM PDT 24 May 07 12:39:15 PM PDT 24 41460524 ps
T1388 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1269660675 May 07 12:39:48 PM PDT 24 May 07 12:39:50 PM PDT 24 41304611 ps
T245 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3258628005 May 07 12:39:33 PM PDT 24 May 07 12:39:36 PM PDT 24 47604197 ps
T1389 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3191631832 May 07 12:39:35 PM PDT 24 May 07 12:39:39 PM PDT 24 90304690 ps
T1390 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1483713251 May 07 12:39:37 PM PDT 24 May 07 12:39:40 PM PDT 24 97925229 ps
T1391 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2448019650 May 07 12:39:37 PM PDT 24 May 07 12:39:40 PM PDT 24 127994491 ps
T1392 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1470432540 May 07 12:39:30 PM PDT 24 May 07 12:39:36 PM PDT 24 476366879 ps
T1393 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2886511424 May 07 12:39:36 PM PDT 24 May 07 12:39:38 PM PDT 24 43701288 ps
T1394 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3842783594 May 07 12:39:46 PM PDT 24 May 07 12:39:53 PM PDT 24 988181495 ps
T278 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1796251536 May 07 12:39:50 PM PDT 24 May 07 12:39:52 PM PDT 24 37856087 ps
T281 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1647915932 May 07 12:39:49 PM PDT 24 May 07 12:39:51 PM PDT 24 30395252 ps
T279 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4221197753 May 07 12:39:56 PM PDT 24 May 07 12:39:59 PM PDT 24 27315446 ps
T267 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2296668534 May 07 12:39:47 PM PDT 24 May 07 12:39:51 PM PDT 24 352527517 ps
T1395 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4165636959 May 07 12:39:34 PM PDT 24 May 07 12:39:36 PM PDT 24 92179217 ps
T1396 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1388070025 May 07 12:39:41 PM PDT 24 May 07 12:39:44 PM PDT 24 68356223 ps
T1397 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1511445481 May 07 12:39:27 PM PDT 24 May 07 12:39:30 PM PDT 24 113000570 ps
T284 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1952756592 May 07 12:39:49 PM PDT 24 May 07 12:39:51 PM PDT 24 32233755 ps
T1398 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3881148484 May 07 12:39:36 PM PDT 24 May 07 12:39:40 PM PDT 24 364098734 ps
T1399 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3994051915 May 07 12:39:40 PM PDT 24 May 07 12:39:44 PM PDT 24 72442914 ps
T1400 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2630331879 May 07 12:39:53 PM PDT 24 May 07 12:39:55 PM PDT 24 33860558 ps
T1401 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3254797949 May 07 12:39:42 PM PDT 24 May 07 12:39:45 PM PDT 24 68288493 ps
T1402 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3600718634 May 07 12:39:40 PM PDT 24 May 07 12:39:43 PM PDT 24 93469094 ps
T1403 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1302059883 May 07 12:39:51 PM PDT 24 May 07 12:39:54 PM PDT 24 102940317 ps
T243 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2170501039 May 07 12:39:40 PM PDT 24 May 07 12:39:43 PM PDT 24 78231157 ps
T1404 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1570857793 May 07 12:39:37 PM PDT 24 May 07 12:39:40 PM PDT 24 63232841 ps
T1405 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2647656733 May 07 12:39:53 PM PDT 24 May 07 12:39:57 PM PDT 24 112352415 ps
T64 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1625101978 May 07 12:39:15 PM PDT 24 May 07 12:39:19 PM PDT 24 175791695 ps
T280 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.268736478 May 07 12:39:25 PM PDT 24 May 07 12:39:26 PM PDT 24 40830380 ps
T291 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.4148740399 May 07 12:39:46 PM PDT 24 May 07 12:39:50 PM PDT 24 396757457 ps
T285 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3031296219 May 07 12:39:54 PM PDT 24 May 07 12:39:58 PM PDT 24 20807967 ps
T1406 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2603496329 May 07 12:39:16 PM PDT 24 May 07 12:39:20 PM PDT 24 59898484 ps
T262 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.821764028 May 07 12:39:32 PM PDT 24 May 07 12:39:35 PM PDT 24 138765438 ps
T1407 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3889564065 May 07 12:39:36 PM PDT 24 May 07 12:39:40 PM PDT 24 114012942 ps
T290 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3384811340 May 07 12:39:44 PM PDT 24 May 07 12:39:50 PM PDT 24 948439654 ps
T1408 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.146202439 May 07 12:39:51 PM PDT 24 May 07 12:39:53 PM PDT 24 27863528 ps
T1409 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1259121678 May 07 12:39:34 PM PDT 24 May 07 12:39:37 PM PDT 24 31824197 ps
T1410 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.166864658 May 07 12:39:33 PM PDT 24 May 07 12:39:35 PM PDT 24 98844649 ps
T1411 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4065727982 May 07 12:39:39 PM PDT 24 May 07 12:39:43 PM PDT 24 176611046 ps
T1412 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.117262991 May 07 12:39:40 PM PDT 24 May 07 12:39:44 PM PDT 24 109511290 ps
T1413 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2115082360 May 07 12:39:51 PM PDT 24 May 07 12:39:54 PM PDT 24 45301324 ps
T1414 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.811301980 May 07 12:39:43 PM PDT 24 May 07 12:39:47 PM PDT 24 198319015 ps
T1415 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.44379654 May 07 12:39:49 PM PDT 24 May 07 12:39:51 PM PDT 24 30908718 ps
T1416 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1194702421 May 07 12:39:47 PM PDT 24 May 07 12:39:52 PM PDT 24 315675002 ps
T293 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2757375308 May 07 12:39:42 PM PDT 24 May 07 12:39:47 PM PDT 24 542599124 ps
T282 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3128688215 May 07 12:39:42 PM PDT 24 May 07 12:39:44 PM PDT 24 105372700 ps
T1417 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4227012230 May 07 12:39:34 PM PDT 24 May 07 12:39:37 PM PDT 24 140176501 ps
T1418 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2069472917 May 07 12:39:11 PM PDT 24 May 07 12:39:14 PM PDT 24 88930036 ps
T1419 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1018642128 May 07 12:39:11 PM PDT 24 May 07 12:39:14 PM PDT 24 142904789 ps
T1420 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3674650682 May 07 12:39:41 PM PDT 24 May 07 12:39:48 PM PDT 24 1188178564 ps
T1421 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4285405312 May 07 12:39:52 PM PDT 24 May 07 12:39:55 PM PDT 24 143283589 ps
T1422 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3906312235 May 07 12:39:53 PM PDT 24 May 07 12:39:56 PM PDT 24 69454681 ps
T294 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2460169991 May 07 12:39:48 PM PDT 24 May 07 12:39:52 PM PDT 24 511776368 ps
T1423 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2524036363 May 07 12:39:47 PM PDT 24 May 07 12:39:49 PM PDT 24 25121454 ps
T1424 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.515834091 May 07 12:39:26 PM PDT 24 May 07 12:39:28 PM PDT 24 30118214 ps
T288 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2406223003 May 07 12:39:42 PM PDT 24 May 07 12:39:48 PM PDT 24 566679094 ps
T283 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2528923546 May 07 12:39:32 PM PDT 24 May 07 12:39:34 PM PDT 24 25559516 ps
T1425 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2255691592 May 07 12:39:52 PM PDT 24 May 07 12:39:56 PM PDT 24 76706482 ps
T1426 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.4287468774 May 07 12:39:34 PM PDT 24 May 07 12:39:37 PM PDT 24 87183283 ps
T1427 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.292909391 May 07 12:39:43 PM PDT 24 May 07 12:39:45 PM PDT 24 34988634 ps
T1428 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.152529643 May 07 12:39:43 PM PDT 24 May 07 12:39:45 PM PDT 24 61470714 ps
T1429 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2935520908 May 07 12:39:41 PM PDT 24 May 07 12:39:44 PM PDT 24 51054611 ps
T1430 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1857765370 May 07 12:39:26 PM PDT 24 May 07 12:39:30 PM PDT 24 259400783 ps
T1431 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.271395350 May 07 12:39:35 PM PDT 24 May 07 12:39:38 PM PDT 24 85687432 ps
T1432 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.546109310 May 07 12:39:39 PM PDT 24 May 07 12:39:42 PM PDT 24 76452174 ps
T1433 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1572677830 May 07 12:39:39 PM PDT 24 May 07 12:39:42 PM PDT 24 70352372 ps
T1434 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.425804278 May 07 12:39:48 PM PDT 24 May 07 12:39:52 PM PDT 24 77107987 ps
T1435 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3206979665 May 07 12:39:36 PM PDT 24 May 07 12:39:46 PM PDT 24 1329497472 ps
T1436 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2112578873 May 07 12:39:52 PM PDT 24 May 07 12:39:57 PM PDT 24 89573135 ps
T292 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1265351524 May 07 12:39:15 PM PDT 24 May 07 12:39:20 PM PDT 24 281536376 ps
T1437 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1404409782 May 07 12:39:51 PM PDT 24 May 07 12:39:53 PM PDT 24 109530641 ps
T1438 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3383122008 May 07 12:39:28 PM PDT 24 May 07 12:39:32 PM PDT 24 96392076 ps
T1439 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1844165404 May 07 12:39:37 PM PDT 24 May 07 12:39:41 PM PDT 24 236093168 ps
T1440 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2243125009 May 07 12:39:36 PM PDT 24 May 07 12:39:38 PM PDT 24 30446159 ps
T1441 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3886481248 May 07 12:39:30 PM PDT 24 May 07 12:39:32 PM PDT 24 41912565 ps
T1442 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1497810731 May 07 12:39:49 PM PDT 24 May 07 12:39:52 PM PDT 24 162073770 ps
T1443 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.679115773 May 07 12:39:48 PM PDT 24 May 07 12:39:50 PM PDT 24 56877225 ps
T1444 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2836576673 May 07 12:39:50 PM PDT 24 May 07 12:39:53 PM PDT 24 30743080 ps
T1445 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.842280788 May 07 12:39:13 PM PDT 24 May 07 12:39:17 PM PDT 24 70417985 ps
T1446 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1738316082 May 07 12:39:54 PM PDT 24 May 07 12:39:57 PM PDT 24 38381439 ps
T1447 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2537581960 May 07 12:39:30 PM PDT 24 May 07 12:39:33 PM PDT 24 97164382 ps
T1448 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.984227436 May 07 12:39:45 PM PDT 24 May 07 12:39:47 PM PDT 24 69703108 ps
T1449 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2706363915 May 07 12:39:17 PM PDT 24 May 07 12:39:22 PM PDT 24 363680769 ps
T1450 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.62657935 May 07 12:39:31 PM PDT 24 May 07 12:39:35 PM PDT 24 71673025 ps
T1451 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.179861043 May 07 12:39:48 PM PDT 24 May 07 12:39:50 PM PDT 24 49104535 ps
T1452 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.392977049 May 07 12:39:48 PM PDT 24 May 07 12:39:50 PM PDT 24 59873496 ps
T1453 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3237803195 May 07 12:39:36 PM PDT 24 May 07 12:39:38 PM PDT 24 40311645 ps
T1454 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1731760870 May 07 12:39:48 PM PDT 24 May 07 12:39:51 PM PDT 24 25917550 ps
T1455 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.383035743 May 07 12:39:53 PM PDT 24 May 07 12:39:55 PM PDT 24 43164764 ps
T1456 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3190685366 May 07 12:39:20 PM PDT 24 May 07 12:39:23 PM PDT 24 60205518 ps
T1457 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2778128181 May 07 12:39:47 PM PDT 24 May 07 12:39:51 PM PDT 24 223616860 ps
T1458 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1285501391 May 07 12:39:49 PM PDT 24 May 07 12:39:52 PM PDT 24 117965401 ps
T1459 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2849414890 May 07 12:39:28 PM PDT 24 May 07 12:39:30 PM PDT 24 51576278 ps
T1460 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3495862591 May 07 12:39:40 PM PDT 24 May 07 12:39:43 PM PDT 24 43925624 ps
T1461 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2835617309 May 07 12:39:45 PM PDT 24 May 07 12:39:48 PM PDT 24 197504051 ps
T1462 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.442868571 May 07 12:39:12 PM PDT 24 May 07 12:39:16 PM PDT 24 190599808 ps
T1463 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.408462660 May 07 12:39:36 PM PDT 24 May 07 12:39:39 PM PDT 24 80668345 ps
T1464 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3730714447 May 07 12:39:09 PM PDT 24 May 07 12:39:11 PM PDT 24 58208223 ps
T1465 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1614092897 May 07 12:39:53 PM PDT 24 May 07 12:39:56 PM PDT 24 70366200 ps
T1466 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.189100423 May 07 12:39:51 PM PDT 24 May 07 12:39:53 PM PDT 24 27839003 ps
T1467 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2528564468 May 07 12:39:51 PM PDT 24 May 07 12:39:54 PM PDT 24 33330313 ps
T1468 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1825771741 May 07 12:39:45 PM PDT 24 May 07 12:39:49 PM PDT 24 193217239 ps
T289 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1699048361 May 07 12:39:47 PM PDT 24 May 07 12:39:51 PM PDT 24 470556698 ps
T69 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2219845689 May 07 12:39:30 PM PDT 24 May 07 12:39:32 PM PDT 24 98810534 ps
T1469 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3311479936 May 07 12:40:07 PM PDT 24 May 07 12:40:09 PM PDT 24 38881543 ps
T1470 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1161408360 May 07 12:39:44 PM PDT 24 May 07 12:39:46 PM PDT 24 44102751 ps
T1471 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3138217306 May 07 12:39:43 PM PDT 24 May 07 12:39:46 PM PDT 24 127007506 ps
T1472 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.939004652 May 07 12:39:52 PM PDT 24 May 07 12:39:54 PM PDT 24 52441734 ps
T1473 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.298230182 May 07 12:39:14 PM PDT 24 May 07 12:39:17 PM PDT 24 60481560 ps
T1474 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1118751063 May 07 12:39:46 PM PDT 24 May 07 12:39:48 PM PDT 24 54110731 ps
T1475 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.4089697829 May 07 12:39:45 PM PDT 24 May 07 12:39:49 PM PDT 24 85701524 ps
T1476 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3709033644 May 07 12:39:46 PM PDT 24 May 07 12:39:49 PM PDT 24 156815532 ps

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2201050616
Short name T10
Test name
Test status
Simulation time 15721020131 ps
CPU time 33.12 seconds
Started May 07 12:43:12 PM PDT 24
Finished May 07 12:43:47 PM PDT 24
Peak memory 204392 kb
Host smart-b51e2ab6-1e5f-4d9d-9a50-533f920b6445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22010
50616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2201050616
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.35356149
Short name T268
Test name
Test status
Simulation time 52510970 ps
CPU time 0.68 seconds
Started May 07 12:39:41 PM PDT 24
Finished May 07 12:39:43 PM PDT 24
Peak memory 203268 kb
Host smart-c812cdab-39e3-4fa1-bf9f-e79aaa781f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=35356149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.35356149
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/default/30.usbdev_enable.1606359372
Short name T89
Test name
Test status
Simulation time 8381538388 ps
CPU time 8.23 seconds
Started May 07 12:42:57 PM PDT 24
Finished May 07 12:43:08 PM PDT 24
Peak memory 204104 kb
Host smart-3c350816-eb00-48c3-b6bd-8ebc16fffb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16063
59372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1606359372
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1637900350
Short name T59
Test name
Test status
Simulation time 70329461 ps
CPU time 1.22 seconds
Started May 07 12:39:32 PM PDT 24
Finished May 07 12:39:34 PM PDT 24
Peak memory 212280 kb
Host smart-1c3ad92e-de43-4df0-af1f-77cb618ee2f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637900350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1637900350
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1821755396
Short name T3
Test name
Test status
Simulation time 8436679198 ps
CPU time 9.81 seconds
Started May 07 12:42:03 PM PDT 24
Finished May 07 12:42:14 PM PDT 24
Peak memory 204100 kb
Host smart-9e6d19ed-0072-471e-a414-6b65566327b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18217
55396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1821755396
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3087757378
Short name T216
Test name
Test status
Simulation time 214228883 ps
CPU time 1.82 seconds
Started May 07 12:41:32 PM PDT 24
Finished May 07 12:41:35 PM PDT 24
Peak memory 204232 kb
Host smart-55535dfe-c895-44e8-a724-00353d1e6989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30877
57378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3087757378
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3853128493
Short name T269
Test name
Test status
Simulation time 31060430 ps
CPU time 0.67 seconds
Started May 07 12:39:33 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 203208 kb
Host smart-076e2985-26bd-486c-a9c0-d1ca5031091e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3853128493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3853128493
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.4114945409
Short name T31
Test name
Test status
Simulation time 35750572 ps
CPU time 0.72 seconds
Started May 07 12:42:37 PM PDT 24
Finished May 07 12:42:40 PM PDT 24
Peak memory 203988 kb
Host smart-77c89c1d-841e-4b90-85e5-a42ee27b99b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41149
45409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.4114945409
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1710340447
Short name T210
Test name
Test status
Simulation time 2266180664 ps
CPU time 6.92 seconds
Started May 07 12:39:38 PM PDT 24
Finished May 07 12:39:46 PM PDT 24
Peak memory 204120 kb
Host smart-437e7f00-d607-49df-995f-12d8537b6ef4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1710340447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1710340447
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1516710093
Short name T163
Test name
Test status
Simulation time 8433165997 ps
CPU time 8.43 seconds
Started May 07 12:42:03 PM PDT 24
Finished May 07 12:42:13 PM PDT 24
Peak memory 204080 kb
Host smart-34ed4f6e-e006-4ff4-a766-e0270d56e1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15167
10093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1516710093
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3111494285
Short name T4
Test name
Test status
Simulation time 8365123050 ps
CPU time 8.12 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204132 kb
Host smart-48eb707f-3111-408f-97cd-86c6dcc5a146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31114
94285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3111494285
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3925806592
Short name T7
Test name
Test status
Simulation time 8364211572 ps
CPU time 8.84 seconds
Started May 07 12:43:43 PM PDT 24
Finished May 07 12:43:54 PM PDT 24
Peak memory 204124 kb
Host smart-f80e155e-9d6d-4bf0-a31d-247cca34dabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39258
06592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3925806592
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2621550077
Short name T130
Test name
Test status
Simulation time 8416857958 ps
CPU time 10.5 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:11 PM PDT 24
Peak memory 204104 kb
Host smart-6f6552c6-6647-4263-89d4-366b1da3d688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26215
50077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2621550077
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2607349828
Short name T277
Test name
Test status
Simulation time 59640906 ps
CPU time 0.68 seconds
Started May 07 12:39:55 PM PDT 24
Finished May 07 12:39:59 PM PDT 24
Peak memory 202960 kb
Host smart-706cdbd7-862e-498b-a3a9-40013bc0cbdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2607349828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2607349828
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2016995078
Short name T63
Test name
Test status
Simulation time 594833326 ps
CPU time 1.49 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:07 PM PDT 24
Peak memory 221420 kb
Host smart-911a12fe-6bcc-46fe-a639-19835980acc1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2016995078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2016995078
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1877814608
Short name T212
Test name
Test status
Simulation time 249757672 ps
CPU time 3.3 seconds
Started May 07 12:39:38 PM PDT 24
Finished May 07 12:39:43 PM PDT 24
Peak memory 204256 kb
Host smart-18cdf244-9313-482d-8e87-b750baa61464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1877814608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1877814608
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3435072670
Short name T67
Test name
Test status
Simulation time 981155736 ps
CPU time 8.25 seconds
Started May 07 12:39:28 PM PDT 24
Finished May 07 12:39:37 PM PDT 24
Peak memory 203944 kb
Host smart-d3e7d22c-6e7a-45e9-a6e6-94dc0594a1a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3435072670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3435072670
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2243125009
Short name T1440
Test name
Test status
Simulation time 30446159 ps
CPU time 0.63 seconds
Started May 07 12:39:36 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 203200 kb
Host smart-692ca461-4949-49af-869e-34191c024aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2243125009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2243125009
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2285145427
Short name T146
Test name
Test status
Simulation time 8434359474 ps
CPU time 8.2 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:09 PM PDT 24
Peak memory 204084 kb
Host smart-6d3f4ef4-33eb-4259-9b8a-549aec876ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22851
45427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2285145427
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3206056437
Short name T274
Test name
Test status
Simulation time 28116880 ps
CPU time 0.66 seconds
Started May 07 12:39:32 PM PDT 24
Finished May 07 12:39:34 PM PDT 24
Peak memory 203140 kb
Host smart-e7cf79ff-c38f-4faf-87d5-45c7ad2ecacd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3206056437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3206056437
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.966653190
Short name T228
Test name
Test status
Simulation time 22140590473 ps
CPU time 41.38 seconds
Started May 07 12:41:13 PM PDT 24
Finished May 07 12:41:56 PM PDT 24
Peak memory 204376 kb
Host smart-06e2567b-82c9-4987-916b-098f1340b7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96665
3190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.966653190
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3065624235
Short name T249
Test name
Test status
Simulation time 435910049 ps
CPU time 3.08 seconds
Started May 07 12:39:47 PM PDT 24
Finished May 07 12:39:51 PM PDT 24
Peak memory 204052 kb
Host smart-d5df9823-2062-4a6c-9279-82a8bf557a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3065624235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3065624235
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.268736478
Short name T280
Test name
Test status
Simulation time 40830380 ps
CPU time 0.66 seconds
Started May 07 12:39:25 PM PDT 24
Finished May 07 12:39:26 PM PDT 24
Peak memory 203132 kb
Host smart-5682145d-180d-41d2-aa23-0e2611d4704c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=268736478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.268736478
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3610551065
Short name T287
Test name
Test status
Simulation time 756196111 ps
CPU time 5.26 seconds
Started May 07 12:39:29 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 203944 kb
Host smart-73f10f01-a052-4921-a268-599438ba2628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3610551065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3610551065
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2765082350
Short name T106
Test name
Test status
Simulation time 5111347117 ps
CPU time 129.65 seconds
Started May 07 12:41:00 PM PDT 24
Finished May 07 12:43:12 PM PDT 24
Peak memory 204348 kb
Host smart-a5fa2882-dcc1-423e-8f37-521dc0b9c6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27650
82350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2765082350
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1625101978
Short name T64
Test name
Test status
Simulation time 175791695 ps
CPU time 0.99 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:39:19 PM PDT 24
Peak memory 203628 kb
Host smart-758f83ca-2962-4bdf-95f4-96a732ae2866
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1625101978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1625101978
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.618514071
Short name T68
Test name
Test status
Simulation time 101231928 ps
CPU time 1.61 seconds
Started May 07 12:39:30 PM PDT 24
Finished May 07 12:39:33 PM PDT 24
Peak memory 204016 kb
Host smart-63748fb7-9d17-4943-b454-c6934838d777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=618514071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.618514071
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2219845689
Short name T69
Test name
Test status
Simulation time 98810534 ps
CPU time 0.86 seconds
Started May 07 12:39:30 PM PDT 24
Finished May 07 12:39:32 PM PDT 24
Peak memory 203744 kb
Host smart-a527c206-db95-4e7c-a4d6-9dbb4df14bf8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2219845689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2219845689
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2126617941
Short name T161
Test name
Test status
Simulation time 8443138658 ps
CPU time 9.1 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:04 PM PDT 24
Peak memory 204088 kb
Host smart-83908ca2-5e20-4453-b30e-7355f0b90d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21266
17941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2126617941
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2460169991
Short name T294
Test name
Test status
Simulation time 511776368 ps
CPU time 2.86 seconds
Started May 07 12:39:48 PM PDT 24
Finished May 07 12:39:52 PM PDT 24
Peak memory 204036 kb
Host smart-34888210-5eb7-4ddd-a526-2f4892afc206
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2460169991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2460169991
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2448019650
Short name T1391
Test name
Test status
Simulation time 127994491 ps
CPU time 1.88 seconds
Started May 07 12:39:37 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 204256 kb
Host smart-b7e55452-cfbe-462a-8ccf-5f1af3ee7c33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2448019650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2448019650
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3544709110
Short name T726
Test name
Test status
Simulation time 49498256 ps
CPU time 0.67 seconds
Started May 07 12:43:26 PM PDT 24
Finished May 07 12:43:30 PM PDT 24
Peak memory 203988 kb
Host smart-53e9a388-556e-401b-931b-e0e10aa7c661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35447
09110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3544709110
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.442772379
Short name T29
Test name
Test status
Simulation time 8466534341 ps
CPU time 10.25 seconds
Started May 07 12:41:48 PM PDT 24
Finished May 07 12:42:00 PM PDT 24
Peak memory 204136 kb
Host smart-2f8c93c1-fe6d-4e48-9dd8-70201b535136
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=442772379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.442772379
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3053274764
Short name T561
Test name
Test status
Simulation time 8404751556 ps
CPU time 8.21 seconds
Started May 07 12:41:01 PM PDT 24
Finished May 07 12:41:13 PM PDT 24
Peak memory 204136 kb
Host smart-8886a468-ed09-49a6-8c4a-40af5265c3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30532
74764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3053274764
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1730499879
Short name T57
Test name
Test status
Simulation time 8381031208 ps
CPU time 7.56 seconds
Started May 07 12:41:49 PM PDT 24
Finished May 07 12:41:58 PM PDT 24
Peak memory 204144 kb
Host smart-6e1bba11-bbf9-4750-b3cd-c02028d204b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17304
99879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1730499879
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.4106179859
Short name T175
Test name
Test status
Simulation time 8427590920 ps
CPU time 8.18 seconds
Started May 07 12:42:02 PM PDT 24
Finished May 07 12:42:12 PM PDT 24
Peak memory 204108 kb
Host smart-5e99fa78-a1f4-4b60-84c3-15b7f052fe81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41061
79859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.4106179859
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.254012928
Short name T1369
Test name
Test status
Simulation time 8391048689 ps
CPU time 8.09 seconds
Started May 07 12:41:59 PM PDT 24
Finished May 07 12:42:09 PM PDT 24
Peak memory 204108 kb
Host smart-c5e63d36-fe28-4ecc-a7ca-e3e2c84b476f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25401
2928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.254012928
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.965647769
Short name T203
Test name
Test status
Simulation time 8398835580 ps
CPU time 9.98 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:06 PM PDT 24
Peak memory 204100 kb
Host smart-272b299f-f383-4482-872c-53d012869ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96564
7769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.965647769
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2299944435
Short name T179
Test name
Test status
Simulation time 8382276516 ps
CPU time 7.82 seconds
Started May 07 12:42:09 PM PDT 24
Finished May 07 12:42:18 PM PDT 24
Peak memory 203996 kb
Host smart-82266104-0015-498b-8965-968fe467a80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22999
44435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2299944435
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3076712039
Short name T1058
Test name
Test status
Simulation time 8417379383 ps
CPU time 8.4 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:43:00 PM PDT 24
Peak memory 204136 kb
Host smart-382bf5f0-0323-4c7e-adfd-cad98d146ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30767
12039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3076712039
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2267852278
Short name T168
Test name
Test status
Simulation time 8486642169 ps
CPU time 7.58 seconds
Started May 07 12:42:44 PM PDT 24
Finished May 07 12:42:53 PM PDT 24
Peak memory 204128 kb
Host smart-4a5765c9-532c-454a-b590-e48608a51eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22678
52278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2267852278
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.738266824
Short name T194
Test name
Test status
Simulation time 8411103855 ps
CPU time 7.93 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204116 kb
Host smart-4c6d1e7c-f308-4fb6-b154-98e6e216fa30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73826
6824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.738266824
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.88250842
Short name T13
Test name
Test status
Simulation time 8420875970 ps
CPU time 8.94 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:05 PM PDT 24
Peak memory 204100 kb
Host smart-455cb20f-bfb9-4a5f-ba8f-8f748e7ee6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88250
842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.88250842
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2438118243
Short name T232
Test name
Test status
Simulation time 29164703819 ps
CPU time 55.9 seconds
Started May 07 12:42:03 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204408 kb
Host smart-16fb3204-d1aa-4b1b-9d4a-b0a0f7b4ca62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24381
18243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2438118243
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1018642128
Short name T1419
Test name
Test status
Simulation time 142904789 ps
CPU time 1.93 seconds
Started May 07 12:39:11 PM PDT 24
Finished May 07 12:39:14 PM PDT 24
Peak memory 204052 kb
Host smart-87355120-7ea5-444a-b90c-06b63c483f0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1018642128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1018642128
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.465307035
Short name T1373
Test name
Test status
Simulation time 8428631745 ps
CPU time 9.36 seconds
Started May 07 12:40:58 PM PDT 24
Finished May 07 12:41:09 PM PDT 24
Peak memory 204072 kb
Host smart-2962623a-c018-4bf4-9b8b-b1a1719f2ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46530
7035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.465307035
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.616370638
Short name T23
Test name
Test status
Simulation time 8374822795 ps
CPU time 7.28 seconds
Started May 07 12:41:03 PM PDT 24
Finished May 07 12:41:13 PM PDT 24
Peak memory 204128 kb
Host smart-636c9e07-d7eb-40c7-9461-c558fe3be50d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61637
0638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.616370638
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.766457393
Short name T1140
Test name
Test status
Simulation time 8427006231 ps
CPU time 9.32 seconds
Started May 07 12:41:14 PM PDT 24
Finished May 07 12:41:24 PM PDT 24
Peak memory 204092 kb
Host smart-950f2c17-b538-4182-8dbb-70b263df27d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76645
7393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.766457393
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2859649746
Short name T758
Test name
Test status
Simulation time 8401705680 ps
CPU time 8.54 seconds
Started May 07 12:41:17 PM PDT 24
Finished May 07 12:41:27 PM PDT 24
Peak memory 204120 kb
Host smart-b39bbe4e-86f9-499d-ac49-2cb8b97fea48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28596
49746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2859649746
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.4248500041
Short name T1299
Test name
Test status
Simulation time 8364781478 ps
CPU time 8.27 seconds
Started May 07 12:41:04 PM PDT 24
Finished May 07 12:41:15 PM PDT 24
Peak memory 204132 kb
Host smart-ff118be7-00b7-4457-82b2-7edc1e4f4955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42485
00041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.4248500041
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3456139913
Short name T129
Test name
Test status
Simulation time 8414168765 ps
CPU time 9.04 seconds
Started May 07 12:41:14 PM PDT 24
Finished May 07 12:41:24 PM PDT 24
Peak memory 204116 kb
Host smart-d5bf5e64-e0a9-446f-b2d9-680806f6d679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34561
39913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3456139913
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.899673829
Short name T624
Test name
Test status
Simulation time 8481338498 ps
CPU time 7.38 seconds
Started May 07 12:41:48 PM PDT 24
Finished May 07 12:41:58 PM PDT 24
Peak memory 204124 kb
Host smart-fc8b93e0-06bd-4199-b037-77da3db8013c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89967
3829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.899673829
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1245534953
Short name T187
Test name
Test status
Simulation time 8370442068 ps
CPU time 8.16 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:06 PM PDT 24
Peak memory 204104 kb
Host smart-ac623df2-f055-4dcf-8813-a36bdb0c8bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12455
34953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1245534953
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2325627912
Short name T498
Test name
Test status
Simulation time 8456834543 ps
CPU time 8.11 seconds
Started May 07 12:41:52 PM PDT 24
Finished May 07 12:42:02 PM PDT 24
Peak memory 204032 kb
Host smart-7241f767-3f1f-4285-9c0d-2dfc5be73ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23256
27912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2325627912
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3965588383
Short name T115
Test name
Test status
Simulation time 8426959110 ps
CPU time 8.65 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:06 PM PDT 24
Peak memory 204056 kb
Host smart-df1028fd-c013-4b4c-a6cc-12ea3d2a8e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39655
88383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3965588383
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2961809211
Short name T505
Test name
Test status
Simulation time 8436462833 ps
CPU time 7.71 seconds
Started May 07 12:41:59 PM PDT 24
Finished May 07 12:42:10 PM PDT 24
Peak memory 204136 kb
Host smart-bd962d96-26ca-4b84-8c4b-0786739e3adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29618
09211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2961809211
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2038345356
Short name T1186
Test name
Test status
Simulation time 8392970979 ps
CPU time 7.76 seconds
Started May 07 12:41:46 PM PDT 24
Finished May 07 12:41:56 PM PDT 24
Peak memory 204028 kb
Host smart-bac440e8-9696-4507-a229-52e40a8e7d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20383
45356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2038345356
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.16393392
Short name T112
Test name
Test status
Simulation time 8435091572 ps
CPU time 7.82 seconds
Started May 07 12:42:06 PM PDT 24
Finished May 07 12:42:15 PM PDT 24
Peak memory 204100 kb
Host smart-de74e037-67c6-401f-86d9-0a184a8af163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16393
392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.16393392
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3592734864
Short name T104
Test name
Test status
Simulation time 8423043829 ps
CPU time 8.18 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204172 kb
Host smart-fbe85783-fe14-4940-b325-327639913abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35927
34864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3592734864
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2377962001
Short name T33
Test name
Test status
Simulation time 8387454869 ps
CPU time 7.89 seconds
Started May 07 12:42:25 PM PDT 24
Finished May 07 12:42:34 PM PDT 24
Peak memory 204112 kb
Host smart-56524832-0cf2-4466-bde1-4b71f552f9fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23779
62001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2377962001
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.19464778
Short name T1034
Test name
Test status
Simulation time 32226990631 ps
CPU time 65.47 seconds
Started May 07 12:42:09 PM PDT 24
Finished May 07 12:43:16 PM PDT 24
Peak memory 204404 kb
Host smart-ac0b91b7-6d1a-4503-b681-7f935b4eb29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19464
778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.19464778
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.69097546
Short name T1260
Test name
Test status
Simulation time 8402757101 ps
CPU time 8.34 seconds
Started May 07 12:41:19 PM PDT 24
Finished May 07 12:41:28 PM PDT 24
Peak memory 204112 kb
Host smart-f995511e-de1b-46b2-8860-da5401736381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69097
546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.69097546
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.289615097
Short name T126
Test name
Test status
Simulation time 8411441290 ps
CPU time 8.02 seconds
Started May 07 12:42:24 PM PDT 24
Finished May 07 12:42:34 PM PDT 24
Peak memory 204120 kb
Host smart-587d8bd0-7b84-4427-8c14-e5490f0c2212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28961
5097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.289615097
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3497284902
Short name T1148
Test name
Test status
Simulation time 8380414644 ps
CPU time 8.4 seconds
Started May 07 12:42:36 PM PDT 24
Finished May 07 12:42:47 PM PDT 24
Peak memory 204116 kb
Host smart-be6a0d33-e1cc-430d-95b1-aeb31fbdef75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34972
84902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3497284902
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3183183506
Short name T955
Test name
Test status
Simulation time 8460558358 ps
CPU time 8.11 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 204100 kb
Host smart-18d0ee57-9e07-4dde-95bd-82ee880d4fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31831
83506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3183183506
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3215738342
Short name T178
Test name
Test status
Simulation time 8377423141 ps
CPU time 7.69 seconds
Started May 07 12:42:41 PM PDT 24
Finished May 07 12:42:50 PM PDT 24
Peak memory 204136 kb
Host smart-13be4c99-bb9d-40fd-9345-33b6f7aea985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32157
38342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3215738342
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3414207597
Short name T22
Test name
Test status
Simulation time 8380665908 ps
CPU time 9.05 seconds
Started May 07 12:42:36 PM PDT 24
Finished May 07 12:42:47 PM PDT 24
Peak memory 204176 kb
Host smart-d766a182-285d-4ee2-91ae-1ba352f9a927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34142
07597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3414207597
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2572660100
Short name T1106
Test name
Test status
Simulation time 8415156520 ps
CPU time 7.63 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204104 kb
Host smart-cc6df908-3726-4fa3-a48d-9ee7c3832686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25726
60100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2572660100
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.574260059
Short name T27
Test name
Test status
Simulation time 8397721098 ps
CPU time 7.63 seconds
Started May 07 12:41:11 PM PDT 24
Finished May 07 12:41:20 PM PDT 24
Peak memory 204068 kb
Host smart-5323d04d-ae49-4c24-bc3e-da45f2b4db8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57426
0059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.574260059
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.442868571
Short name T1462
Test name
Test status
Simulation time 190599808 ps
CPU time 2.02 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 203884 kb
Host smart-9483e4fe-50bc-4dd4-ba3d-3ee80982cdaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=442868571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.442868571
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3383122008
Short name T1438
Test name
Test status
Simulation time 96392076 ps
CPU time 2.75 seconds
Started May 07 12:39:28 PM PDT 24
Finished May 07 12:39:32 PM PDT 24
Peak memory 212208 kb
Host smart-ce355f5e-13d7-4edd-98b7-6f3fddfbd158
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383122008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3383122008
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3190685366
Short name T1456
Test name
Test status
Simulation time 60205518 ps
CPU time 0.91 seconds
Started May 07 12:39:20 PM PDT 24
Finished May 07 12:39:23 PM PDT 24
Peak memory 203880 kb
Host smart-9f54e243-01f6-499b-957e-fa95a6c19495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3190685366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3190685366
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3730714447
Short name T1464
Test name
Test status
Simulation time 58208223 ps
CPU time 0.7 seconds
Started May 07 12:39:09 PM PDT 24
Finished May 07 12:39:11 PM PDT 24
Peak memory 203296 kb
Host smart-f205d8d5-f743-4465-92b6-89041f5f23c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3730714447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3730714447
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.821764028
Short name T262
Test name
Test status
Simulation time 138765438 ps
CPU time 1.5 seconds
Started May 07 12:39:32 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 204008 kb
Host smart-95fb1b13-e694-403e-b54f-58978fc02277
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=821764028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.821764028
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.358734613
Short name T1386
Test name
Test status
Simulation time 254388738 ps
CPU time 2.5 seconds
Started May 07 12:39:14 PM PDT 24
Finished May 07 12:39:19 PM PDT 24
Peak memory 203872 kb
Host smart-34987988-96e8-45cf-a9b7-bc308938a1db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=358734613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.358734613
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4165636959
Short name T1395
Test name
Test status
Simulation time 92179217 ps
CPU time 1.07 seconds
Started May 07 12:39:34 PM PDT 24
Finished May 07 12:39:36 PM PDT 24
Peak memory 203984 kb
Host smart-7ee333c6-be19-4567-904c-f9844140d525
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4165636959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.4165636959
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.966793273
Short name T1382
Test name
Test status
Simulation time 371378006 ps
CPU time 2.9 seconds
Started May 07 12:39:23 PM PDT 24
Finished May 07 12:39:28 PM PDT 24
Peak memory 204024 kb
Host smart-6703f533-10d3-46da-a5fa-c9e8d330ba40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=966793273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.966793273
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1599103600
Short name T100
Test name
Test status
Simulation time 72343801 ps
CPU time 1.84 seconds
Started May 07 12:39:23 PM PDT 24
Finished May 07 12:39:26 PM PDT 24
Peak memory 203904 kb
Host smart-a1fde9ce-62b6-4e24-916b-b50311bce273
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1599103600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1599103600
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.566086985
Short name T255
Test name
Test status
Simulation time 432395548 ps
CPU time 7.7 seconds
Started May 07 12:39:35 PM PDT 24
Finished May 07 12:39:44 PM PDT 24
Peak memory 203892 kb
Host smart-6c633c17-4d28-4439-9ff5-457d43799b98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=566086985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.566086985
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3112291789
Short name T244
Test name
Test status
Simulation time 72400979 ps
CPU time 0.79 seconds
Started May 07 12:39:33 PM PDT 24
Finished May 07 12:39:34 PM PDT 24
Peak memory 203744 kb
Host smart-1988a2f8-2016-4cab-bea5-264290087355
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3112291789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3112291789
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3138217306
Short name T1471
Test name
Test status
Simulation time 127007506 ps
CPU time 1.73 seconds
Started May 07 12:39:43 PM PDT 24
Finished May 07 12:39:46 PM PDT 24
Peak memory 214996 kb
Host smart-c3bb2ed2-f301-4c5d-b355-b9428021cf9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138217306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3138217306
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.842280788
Short name T1445
Test name
Test status
Simulation time 70417985 ps
CPU time 1.09 seconds
Started May 07 12:39:13 PM PDT 24
Finished May 07 12:39:17 PM PDT 24
Peak memory 204092 kb
Host smart-79d8703a-d696-4f2d-aa0c-0248b8f5b6ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=842280788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.842280788
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.515834091
Short name T1424
Test name
Test status
Simulation time 30118214 ps
CPU time 0.67 seconds
Started May 07 12:39:26 PM PDT 24
Finished May 07 12:39:28 PM PDT 24
Peak memory 203184 kb
Host smart-723f59aa-20bb-49e2-be7f-e6cc51e5d777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=515834091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.515834091
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1474385327
Short name T257
Test name
Test status
Simulation time 99552858 ps
CPU time 1.41 seconds
Started May 07 12:39:18 PM PDT 24
Finished May 07 12:39:22 PM PDT 24
Peak memory 212200 kb
Host smart-bb8ee7af-ac99-48ca-bb16-04ff3d3162ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1474385327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1474385327
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1470432540
Short name T1392
Test name
Test status
Simulation time 476366879 ps
CPU time 4.52 seconds
Started May 07 12:39:30 PM PDT 24
Finished May 07 12:39:36 PM PDT 24
Peak memory 203864 kb
Host smart-164e4082-ff88-4e19-ac15-64c5ee2db7d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1470432540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1470432540
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.298230182
Short name T1473
Test name
Test status
Simulation time 60481560 ps
CPU time 1.06 seconds
Started May 07 12:39:14 PM PDT 24
Finished May 07 12:39:17 PM PDT 24
Peak memory 203968 kb
Host smart-f507de81-234a-4089-8975-d345a9e3c174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=298230182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.298230182
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4254828745
Short name T236
Test name
Test status
Simulation time 69938186 ps
CPU time 2.14 seconds
Started May 07 12:39:16 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 204068 kb
Host smart-c0096c27-7228-44eb-b806-8a7d2c8326fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4254828745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.4254828745
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1265351524
Short name T292
Test name
Test status
Simulation time 281536376 ps
CPU time 2.34 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 204020 kb
Host smart-4b08a43a-ee42-466d-b50d-8679ce6942a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1265351524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1265351524
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4065727982
Short name T1411
Test name
Test status
Simulation time 176611046 ps
CPU time 2.05 seconds
Started May 07 12:39:39 PM PDT 24
Finished May 07 12:39:43 PM PDT 24
Peak memory 212268 kb
Host smart-e2ec4db5-0de9-4243-a761-0a60ed13e6d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065727982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.4065727982
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2886511424
Short name T1393
Test name
Test status
Simulation time 43701288 ps
CPU time 0.97 seconds
Started May 07 12:39:36 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 203908 kb
Host smart-bbb12f22-b6b8-4e26-90ca-155d760e8989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2886511424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2886511424
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.952752051
Short name T273
Test name
Test status
Simulation time 34038780 ps
CPU time 0.72 seconds
Started May 07 12:39:44 PM PDT 24
Finished May 07 12:39:51 PM PDT 24
Peak memory 203280 kb
Host smart-50d1baaf-4293-40e4-b868-2938df24035b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=952752051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.952752051
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1572677830
Short name T1433
Test name
Test status
Simulation time 70352372 ps
CPU time 1.4 seconds
Started May 07 12:39:39 PM PDT 24
Finished May 07 12:39:42 PM PDT 24
Peak memory 204044 kb
Host smart-fbdb1637-86d7-4c39-8c8c-5b6c69432a09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1572677830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1572677830
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.62657935
Short name T1450
Test name
Test status
Simulation time 71673025 ps
CPU time 2.08 seconds
Started May 07 12:39:31 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 204056 kb
Host smart-c7b8a489-64dd-473d-9a32-2beaa9c62128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=62657935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.62657935
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.995884597
Short name T295
Test name
Test status
Simulation time 352385942 ps
CPU time 2.69 seconds
Started May 07 12:39:40 PM PDT 24
Finished May 07 12:39:44 PM PDT 24
Peak memory 204004 kb
Host smart-d9bc9983-fb7b-4dd0-ba51-8c5c7dc59502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=995884597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.995884597
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1424196564
Short name T237
Test name
Test status
Simulation time 135848681 ps
CPU time 1.84 seconds
Started May 07 12:39:37 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 212112 kb
Host smart-4ac4908f-756c-4f2f-b6c5-1490e673ab85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424196564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1424196564
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1259121678
Short name T1409
Test name
Test status
Simulation time 31824197 ps
CPU time 0.73 seconds
Started May 07 12:39:34 PM PDT 24
Finished May 07 12:39:37 PM PDT 24
Peak memory 203768 kb
Host smart-3607591b-32c0-4e5a-86d5-83ff2de48685
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1259121678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1259121678
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3886481248
Short name T1441
Test name
Test status
Simulation time 41912565 ps
CPU time 0.65 seconds
Started May 07 12:39:30 PM PDT 24
Finished May 07 12:39:32 PM PDT 24
Peak memory 203184 kb
Host smart-0fe1f6c0-8b70-4036-ad16-70456af22f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3886481248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3886481248
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1570857793
Short name T1404
Test name
Test status
Simulation time 63232841 ps
CPU time 1.09 seconds
Started May 07 12:39:37 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 203952 kb
Host smart-3009d97a-1b7c-4806-9e57-2d692f5273f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1570857793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1570857793
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1483713251
Short name T1390
Test name
Test status
Simulation time 97925229 ps
CPU time 1.3 seconds
Started May 07 12:39:37 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 204028 kb
Host smart-370c2298-2355-4dbc-ad7d-9fa319b498d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1483713251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1483713251
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3842783594
Short name T1394
Test name
Test status
Simulation time 988181495 ps
CPU time 5.13 seconds
Started May 07 12:39:46 PM PDT 24
Finished May 07 12:39:53 PM PDT 24
Peak memory 203940 kb
Host smart-ba2eca3d-4c20-4eec-968f-9f877c1af78d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3842783594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3842783594
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1497810731
Short name T1442
Test name
Test status
Simulation time 162073770 ps
CPU time 1.72 seconds
Started May 07 12:39:49 PM PDT 24
Finished May 07 12:39:52 PM PDT 24
Peak memory 212092 kb
Host smart-b3f183b9-94b8-4b70-89e8-c394ffe02ac1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497810731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1497810731
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1842647499
Short name T265
Test name
Test status
Simulation time 40883201 ps
CPU time 0.77 seconds
Started May 07 12:39:45 PM PDT 24
Finished May 07 12:39:47 PM PDT 24
Peak memory 203700 kb
Host smart-72354ecd-7293-4bc6-b033-7f53c821b9fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1842647499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1842647499
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3237803195
Short name T1453
Test name
Test status
Simulation time 40311645 ps
CPU time 0.76 seconds
Started May 07 12:39:36 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 203200 kb
Host smart-8986c400-cd19-47f1-aaa6-598137eb3c23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3237803195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3237803195
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.4287468774
Short name T1426
Test name
Test status
Simulation time 87183283 ps
CPU time 1.2 seconds
Started May 07 12:39:34 PM PDT 24
Finished May 07 12:39:37 PM PDT 24
Peak memory 203960 kb
Host smart-a45e596d-9529-437d-9194-ecece7bd5238
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4287468774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.4287468774
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.4089697829
Short name T1475
Test name
Test status
Simulation time 85701524 ps
CPU time 2.04 seconds
Started May 07 12:39:45 PM PDT 24
Finished May 07 12:39:49 PM PDT 24
Peak memory 203572 kb
Host smart-bcf3a685-538a-4ccb-ad22-822db179ef37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4089697829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.4089697829
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3384811340
Short name T290
Test name
Test status
Simulation time 948439654 ps
CPU time 5.03 seconds
Started May 07 12:39:44 PM PDT 24
Finished May 07 12:39:50 PM PDT 24
Peak memory 203960 kb
Host smart-f7144a73-868a-4bce-b98d-0a81c5869ac0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3384811340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3384811340
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1388070025
Short name T1396
Test name
Test status
Simulation time 68356223 ps
CPU time 1.39 seconds
Started May 07 12:39:41 PM PDT 24
Finished May 07 12:39:44 PM PDT 24
Peak memory 213504 kb
Host smart-78e1d1a5-4de4-4397-b5bf-d828951561f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388070025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1388070025
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.152529643
Short name T1428
Test name
Test status
Simulation time 61470714 ps
CPU time 0.98 seconds
Started May 07 12:39:43 PM PDT 24
Finished May 07 12:39:45 PM PDT 24
Peak memory 203936 kb
Host smart-123d3efe-41e1-419a-a0ae-32b7c45f86a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=152529643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.152529643
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1844165404
Short name T1439
Test name
Test status
Simulation time 236093168 ps
CPU time 1.85 seconds
Started May 07 12:39:37 PM PDT 24
Finished May 07 12:39:41 PM PDT 24
Peak memory 204024 kb
Host smart-3f22ec68-45ad-4be4-bb8f-1b6df66eb91b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1844165404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1844165404
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3247065429
Short name T58
Test name
Test status
Simulation time 333764888 ps
CPU time 3.26 seconds
Started May 07 12:39:41 PM PDT 24
Finished May 07 12:39:45 PM PDT 24
Peak memory 204068 kb
Host smart-85c45de7-09a4-44c2-8e29-f9533e2cf507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3247065429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3247065429
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3709033644
Short name T1476
Test name
Test status
Simulation time 156815532 ps
CPU time 2.03 seconds
Started May 07 12:39:46 PM PDT 24
Finished May 07 12:39:49 PM PDT 24
Peak memory 212300 kb
Host smart-747a2f65-e0f8-4d0d-b437-493c4598f39d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709033644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3709033644
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2524036363
Short name T1423
Test name
Test status
Simulation time 25121454 ps
CPU time 0.78 seconds
Started May 07 12:39:47 PM PDT 24
Finished May 07 12:39:49 PM PDT 24
Peak memory 203664 kb
Host smart-9f56c185-c02a-4445-a1e0-0b4b5c45e191
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2524036363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2524036363
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.392977049
Short name T1452
Test name
Test status
Simulation time 59873496 ps
CPU time 0.7 seconds
Started May 07 12:39:48 PM PDT 24
Finished May 07 12:39:50 PM PDT 24
Peak memory 203248 kb
Host smart-b716ae17-408d-45ce-aebb-12e013236cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=392977049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.392977049
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2647656733
Short name T1405
Test name
Test status
Simulation time 112352415 ps
CPU time 1.43 seconds
Started May 07 12:39:53 PM PDT 24
Finished May 07 12:39:57 PM PDT 24
Peak memory 203980 kb
Host smart-9a8ac2f9-2860-4941-909d-55ec969b66e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2647656733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2647656733
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2778128181
Short name T1457
Test name
Test status
Simulation time 223616860 ps
CPU time 3.08 seconds
Started May 07 12:39:47 PM PDT 24
Finished May 07 12:39:51 PM PDT 24
Peak memory 203996 kb
Host smart-d5803a7e-d847-47d4-80ec-13f0f47c5b10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2778128181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2778128181
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.117262991
Short name T1412
Test name
Test status
Simulation time 109511290 ps
CPU time 1.88 seconds
Started May 07 12:39:40 PM PDT 24
Finished May 07 12:39:44 PM PDT 24
Peak memory 212156 kb
Host smart-24ab91bb-9059-477f-a7a1-4ec1ff1f1f3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117262991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.117262991
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1269660675
Short name T1388
Test name
Test status
Simulation time 41304611 ps
CPU time 0.82 seconds
Started May 07 12:39:48 PM PDT 24
Finished May 07 12:39:50 PM PDT 24
Peak memory 203768 kb
Host smart-fbb7217e-0887-4c6e-938b-a1e842bdd721
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1269660675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1269660675
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3128688215
Short name T282
Test name
Test status
Simulation time 105372700 ps
CPU time 0.72 seconds
Started May 07 12:39:42 PM PDT 24
Finished May 07 12:39:44 PM PDT 24
Peak memory 203260 kb
Host smart-4abcb91e-38d7-46aa-9156-9e0f3a6c7e74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3128688215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3128688215
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3994051915
Short name T1399
Test name
Test status
Simulation time 72442914 ps
CPU time 1.57 seconds
Started May 07 12:39:40 PM PDT 24
Finished May 07 12:39:44 PM PDT 24
Peak memory 203960 kb
Host smart-bae177ed-1273-4c10-aa4d-e15ff12811b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3994051915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3994051915
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2835617309
Short name T1461
Test name
Test status
Simulation time 197504051 ps
CPU time 2.16 seconds
Started May 07 12:39:45 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 203964 kb
Host smart-01a722f5-6ad9-40ba-bf5e-a9ffd7e5dada
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2835617309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2835617309
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.4148740399
Short name T291
Test name
Test status
Simulation time 396757457 ps
CPU time 3.1 seconds
Started May 07 12:39:46 PM PDT 24
Finished May 07 12:39:50 PM PDT 24
Peak memory 203960 kb
Host smart-ea99f8da-2fb3-4fdc-8a62-f63da4cf48d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4148740399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.4148740399
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.812554553
Short name T1384
Test name
Test status
Simulation time 152943473 ps
CPU time 1.85 seconds
Started May 07 12:39:51 PM PDT 24
Finished May 07 12:39:54 PM PDT 24
Peak memory 212260 kb
Host smart-9d414b83-0103-4f88-a77d-e02fce6d85ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812554553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.812554553
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2115082360
Short name T1413
Test name
Test status
Simulation time 45301324 ps
CPU time 0.78 seconds
Started May 07 12:39:51 PM PDT 24
Finished May 07 12:39:54 PM PDT 24
Peak memory 203772 kb
Host smart-7a221280-d13c-4e06-bd48-70f9faf93b0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2115082360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2115082360
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2935520908
Short name T1429
Test name
Test status
Simulation time 51054611 ps
CPU time 0.71 seconds
Started May 07 12:39:41 PM PDT 24
Finished May 07 12:39:44 PM PDT 24
Peak memory 203248 kb
Host smart-5d0097b0-4f92-4013-bd8d-35be755b8b52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2935520908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2935520908
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1302059883
Short name T1403
Test name
Test status
Simulation time 102940317 ps
CPU time 1.4 seconds
Started May 07 12:39:51 PM PDT 24
Finished May 07 12:39:54 PM PDT 24
Peak memory 204048 kb
Host smart-53efb09d-969a-4921-92b3-8b062abbcac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1302059883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1302059883
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.425804278
Short name T1434
Test name
Test status
Simulation time 77107987 ps
CPU time 2.04 seconds
Started May 07 12:39:48 PM PDT 24
Finished May 07 12:39:52 PM PDT 24
Peak memory 203956 kb
Host smart-93b29bef-1505-472b-9bab-e0f4694bcaf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=425804278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.425804278
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1699048361
Short name T289
Test name
Test status
Simulation time 470556698 ps
CPU time 2.9 seconds
Started May 07 12:39:47 PM PDT 24
Finished May 07 12:39:51 PM PDT 24
Peak memory 204012 kb
Host smart-52668453-ea73-478e-9901-cacb56999dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1699048361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1699048361
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.140037215
Short name T248
Test name
Test status
Simulation time 168066998 ps
CPU time 1.84 seconds
Started May 07 12:39:52 PM PDT 24
Finished May 07 12:39:55 PM PDT 24
Peak memory 212172 kb
Host smart-c19f4444-2207-4c85-adba-05d4abba5409
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140037215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.140037215
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2185014281
Short name T99
Test name
Test status
Simulation time 71356401 ps
CPU time 1.09 seconds
Started May 07 12:39:50 PM PDT 24
Finished May 07 12:39:53 PM PDT 24
Peak memory 203988 kb
Host smart-ab2a501d-ecd0-4447-941c-fd25f45f950e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2185014281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2185014281
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1404409782
Short name T1437
Test name
Test status
Simulation time 109530641 ps
CPU time 0.74 seconds
Started May 07 12:39:51 PM PDT 24
Finished May 07 12:39:53 PM PDT 24
Peak memory 203208 kb
Host smart-28d35905-7939-421c-b2ff-61c985e620cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1404409782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1404409782
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4285405312
Short name T1421
Test name
Test status
Simulation time 143283589 ps
CPU time 1.75 seconds
Started May 07 12:39:52 PM PDT 24
Finished May 07 12:39:55 PM PDT 24
Peak memory 203948 kb
Host smart-3aabb35a-7915-4e67-bdf7-b5e109ede57d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4285405312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.4285405312
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.348339076
Short name T1387
Test name
Test status
Simulation time 109883838 ps
CPU time 1.59 seconds
Started May 07 12:39:45 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 204056 kb
Host smart-c381cf84-9208-4300-b6ba-5e78408f4a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=348339076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.348339076
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2296668534
Short name T267
Test name
Test status
Simulation time 352527517 ps
CPU time 2.99 seconds
Started May 07 12:39:47 PM PDT 24
Finished May 07 12:39:51 PM PDT 24
Peak memory 203952 kb
Host smart-76b2a2ea-4fc9-4de3-9805-544dcd85b998
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2296668534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2296668534
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3596039273
Short name T213
Test name
Test status
Simulation time 133435365 ps
CPU time 1.92 seconds
Started May 07 12:39:45 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 215276 kb
Host smart-e26d4bfe-489d-4859-bcbf-2c362bfac26a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596039273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3596039273
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3254797949
Short name T1401
Test name
Test status
Simulation time 68288493 ps
CPU time 0.89 seconds
Started May 07 12:39:42 PM PDT 24
Finished May 07 12:39:45 PM PDT 24
Peak memory 203760 kb
Host smart-1d183a32-1ca2-4092-9e27-084e3113efc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3254797949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3254797949
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.679115773
Short name T1443
Test name
Test status
Simulation time 56877225 ps
CPU time 0.74 seconds
Started May 07 12:39:48 PM PDT 24
Finished May 07 12:39:50 PM PDT 24
Peak memory 203240 kb
Host smart-fa0339c2-db82-4829-8cec-4437ee86ec3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=679115773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.679115773
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2255691592
Short name T1425
Test name
Test status
Simulation time 76706482 ps
CPU time 1.62 seconds
Started May 07 12:39:52 PM PDT 24
Finished May 07 12:39:56 PM PDT 24
Peak memory 203948 kb
Host smart-2f6a7710-82de-4397-a92e-932577464bd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2255691592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2255691592
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2112578873
Short name T1436
Test name
Test status
Simulation time 89573135 ps
CPU time 2.51 seconds
Started May 07 12:39:52 PM PDT 24
Finished May 07 12:39:57 PM PDT 24
Peak memory 203972 kb
Host smart-01e607e2-30c2-4bce-8a25-9b637c315513
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2112578873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2112578873
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1194702421
Short name T1416
Test name
Test status
Simulation time 315675002 ps
CPU time 2.72 seconds
Started May 07 12:39:47 PM PDT 24
Finished May 07 12:39:52 PM PDT 24
Peak memory 203956 kb
Host smart-c2d03da5-21fd-4247-b14a-f62604c34a44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1194702421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1194702421
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2575095031
Short name T1383
Test name
Test status
Simulation time 164995092 ps
CPU time 1.96 seconds
Started May 07 12:39:49 PM PDT 24
Finished May 07 12:39:58 PM PDT 24
Peak memory 212180 kb
Host smart-c806076b-77ea-4557-a11c-27cdaffb6ac0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575095031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2575095031
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.939004652
Short name T1472
Test name
Test status
Simulation time 52441734 ps
CPU time 0.8 seconds
Started May 07 12:39:52 PM PDT 24
Finished May 07 12:39:54 PM PDT 24
Peak memory 203708 kb
Host smart-da4cfd7f-76da-439d-a4ff-b5847c66a4a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=939004652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.939004652
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.189100423
Short name T1466
Test name
Test status
Simulation time 27839003 ps
CPU time 0.69 seconds
Started May 07 12:39:51 PM PDT 24
Finished May 07 12:39:53 PM PDT 24
Peak memory 203460 kb
Host smart-97d3de80-b7a4-4207-b2a7-3cd85c3422e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=189100423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.189100423
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4261513315
Short name T101
Test name
Test status
Simulation time 102613272 ps
CPU time 1.14 seconds
Started May 07 12:39:52 PM PDT 24
Finished May 07 12:39:55 PM PDT 24
Peak memory 203980 kb
Host smart-43189d05-01ee-42d5-8466-f6617d6a17f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4261513315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.4261513315
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1285501391
Short name T1458
Test name
Test status
Simulation time 117965401 ps
CPU time 1.71 seconds
Started May 07 12:39:49 PM PDT 24
Finished May 07 12:39:52 PM PDT 24
Peak memory 204248 kb
Host smart-7e602838-e70c-4e22-88da-05f1bd6e08cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1285501391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1285501391
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.811301980
Short name T1414
Test name
Test status
Simulation time 198319015 ps
CPU time 2.27 seconds
Started May 07 12:39:43 PM PDT 24
Finished May 07 12:39:47 PM PDT 24
Peak memory 203880 kb
Host smart-60d5e4bc-f7df-4e48-8870-3c6ee5b0daba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=811301980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.811301980
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3681620076
Short name T1381
Test name
Test status
Simulation time 1218330107 ps
CPU time 9.92 seconds
Started May 07 12:39:29 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 203916 kb
Host smart-b746a52c-a34f-41ed-a140-f9ecd2f867ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3681620076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3681620076
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3258628005
Short name T245
Test name
Test status
Simulation time 47604197 ps
CPU time 0.89 seconds
Started May 07 12:39:33 PM PDT 24
Finished May 07 12:39:36 PM PDT 24
Peak memory 203744 kb
Host smart-5681910b-33f3-4db9-9a71-53c14977109d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3258628005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3258628005
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2998981602
Short name T60
Test name
Test status
Simulation time 73067671 ps
CPU time 2.01 seconds
Started May 07 12:39:22 PM PDT 24
Finished May 07 12:39:26 PM PDT 24
Peak memory 212216 kb
Host smart-946b2ab0-ca4c-4112-bf17-4208a9fe2aab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998981602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2998981602
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2603496329
Short name T1406
Test name
Test status
Simulation time 59898484 ps
CPU time 0.85 seconds
Started May 07 12:39:16 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 203628 kb
Host smart-7ab3c8cb-6ab7-4797-87de-bbda241aa1c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2603496329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2603496329
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2537581960
Short name T1447
Test name
Test status
Simulation time 97164382 ps
CPU time 1.39 seconds
Started May 07 12:39:30 PM PDT 24
Finished May 07 12:39:33 PM PDT 24
Peak memory 203988 kb
Host smart-41953512-dcd2-4710-b541-a52bc92c8da9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2537581960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2537581960
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3191631832
Short name T1389
Test name
Test status
Simulation time 90304690 ps
CPU time 2.33 seconds
Started May 07 12:39:35 PM PDT 24
Finished May 07 12:39:39 PM PDT 24
Peak memory 203940 kb
Host smart-2aa3c0d5-12a5-4aa9-8aa5-82a128e79439
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3191631832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3191631832
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2516720902
Short name T66
Test name
Test status
Simulation time 159173839 ps
CPU time 1.51 seconds
Started May 07 12:39:22 PM PDT 24
Finished May 07 12:39:25 PM PDT 24
Peak memory 203932 kb
Host smart-21e5042f-2279-4141-be67-e5121a83cd78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2516720902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2516720902
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.446266743
Short name T240
Test name
Test status
Simulation time 115999528 ps
CPU time 2.46 seconds
Started May 07 12:39:34 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 203996 kb
Host smart-8c3bd9cb-c2c3-4d53-9254-a8705047dcbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=446266743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.446266743
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1702294961
Short name T209
Test name
Test status
Simulation time 852748625 ps
CPU time 3.36 seconds
Started May 07 12:39:22 PM PDT 24
Finished May 07 12:39:27 PM PDT 24
Peak memory 203976 kb
Host smart-bb998d74-2b6b-48f3-bca3-fdb4297307e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1702294961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1702294961
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1731760870
Short name T1454
Test name
Test status
Simulation time 25917550 ps
CPU time 0.64 seconds
Started May 07 12:39:48 PM PDT 24
Finished May 07 12:39:51 PM PDT 24
Peak memory 203204 kb
Host smart-0515181b-93e3-4efb-a588-c1d47b6c26e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1731760870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1731760870
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1161408360
Short name T1470
Test name
Test status
Simulation time 44102751 ps
CPU time 0.74 seconds
Started May 07 12:39:44 PM PDT 24
Finished May 07 12:39:46 PM PDT 24
Peak memory 203304 kb
Host smart-0c9ba4ef-b211-4ed1-9b90-0ca583b49b4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1161408360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1161408360
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1796251536
Short name T278
Test name
Test status
Simulation time 37856087 ps
CPU time 0.64 seconds
Started May 07 12:39:50 PM PDT 24
Finished May 07 12:39:52 PM PDT 24
Peak memory 203236 kb
Host smart-478a6714-5f29-4fff-bb1d-35eb471a3838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1796251536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1796251536
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.179861043
Short name T1451
Test name
Test status
Simulation time 49104535 ps
CPU time 0.66 seconds
Started May 07 12:39:48 PM PDT 24
Finished May 07 12:39:50 PM PDT 24
Peak memory 203196 kb
Host smart-8b9dfc23-d939-4a78-9a8b-7f5e161150b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=179861043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.179861043
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.292909391
Short name T1427
Test name
Test status
Simulation time 34988634 ps
CPU time 0.66 seconds
Started May 07 12:39:43 PM PDT 24
Finished May 07 12:39:45 PM PDT 24
Peak memory 203200 kb
Host smart-00d9f14e-0356-4386-82d0-4b58b41fe279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=292909391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.292909391
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4221197753
Short name T279
Test name
Test status
Simulation time 27315446 ps
CPU time 0.63 seconds
Started May 07 12:39:56 PM PDT 24
Finished May 07 12:39:59 PM PDT 24
Peak memory 203020 kb
Host smart-69ee0b8d-752e-469c-bc15-96f37b55645c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4221197753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4221197753
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2673388111
Short name T73
Test name
Test status
Simulation time 37736783 ps
CPU time 0.62 seconds
Started May 07 12:39:53 PM PDT 24
Finished May 07 12:39:56 PM PDT 24
Peak memory 203188 kb
Host smart-8005ec8f-dd49-4c33-9f28-888d058982f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2673388111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2673388111
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4088088896
Short name T1385
Test name
Test status
Simulation time 70180084 ps
CPU time 0.65 seconds
Started May 07 12:39:51 PM PDT 24
Finished May 07 12:39:53 PM PDT 24
Peak memory 203108 kb
Host smart-f20bbe85-22ad-4b70-84bf-a88c91439b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4088088896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.4088088896
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1885152254
Short name T71
Test name
Test status
Simulation time 54054170 ps
CPU time 0.7 seconds
Started May 07 12:39:51 PM PDT 24
Finished May 07 12:39:53 PM PDT 24
Peak memory 203096 kb
Host smart-0ec081d2-5667-47d2-9fb6-59a5e2aa1fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1885152254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1885152254
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.383035743
Short name T1455
Test name
Test status
Simulation time 43164764 ps
CPU time 0.66 seconds
Started May 07 12:39:53 PM PDT 24
Finished May 07 12:39:55 PM PDT 24
Peak memory 203192 kb
Host smart-dff7f3bb-1740-4ccc-a01c-88a77628a3b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=383035743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.383035743
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3651863604
Short name T1380
Test name
Test status
Simulation time 159780625 ps
CPU time 2.18 seconds
Started May 07 12:39:28 PM PDT 24
Finished May 07 12:39:31 PM PDT 24
Peak memory 203892 kb
Host smart-c0d3249a-a879-4357-878f-ea8879e09099
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3651863604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3651863604
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2713712608
Short name T260
Test name
Test status
Simulation time 1141810240 ps
CPU time 7.77 seconds
Started May 07 12:39:26 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 203948 kb
Host smart-ac7316b8-0cf0-4e83-8862-c80afe4d28c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2713712608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2713712608
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1511445481
Short name T1397
Test name
Test status
Simulation time 113000570 ps
CPU time 1.43 seconds
Started May 07 12:39:27 PM PDT 24
Finished May 07 12:39:30 PM PDT 24
Peak memory 212184 kb
Host smart-5eea88bb-3983-4d8e-bbe9-0f7154c2370a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511445481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.1511445481
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.667002967
Short name T261
Test name
Test status
Simulation time 41460524 ps
CPU time 0.96 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 203988 kb
Host smart-e504554b-610d-4673-9b41-e2765f6649d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=667002967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.667002967
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1987024734
Short name T70
Test name
Test status
Simulation time 39387123 ps
CPU time 0.67 seconds
Started May 07 12:39:43 PM PDT 24
Finished May 07 12:39:45 PM PDT 24
Peak memory 203236 kb
Host smart-d4b0b1d5-28d8-40d9-ad89-889bea4c8a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1987024734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1987024734
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2849414890
Short name T1459
Test name
Test status
Simulation time 51576278 ps
CPU time 1.33 seconds
Started May 07 12:39:28 PM PDT 24
Finished May 07 12:39:30 PM PDT 24
Peak memory 212132 kb
Host smart-383a901b-4763-4230-9ebb-8bd408ed2c5a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2849414890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2849414890
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2706363915
Short name T1449
Test name
Test status
Simulation time 363680769 ps
CPU time 2.58 seconds
Started May 07 12:39:17 PM PDT 24
Finished May 07 12:39:22 PM PDT 24
Peak memory 203888 kb
Host smart-d294c542-40ad-45ab-85d6-9a800807bf07
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2706363915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2706363915
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.346880066
Short name T211
Test name
Test status
Simulation time 169087741 ps
CPU time 1.59 seconds
Started May 07 12:39:21 PM PDT 24
Finished May 07 12:39:25 PM PDT 24
Peak memory 203968 kb
Host smart-cf00a92d-6dee-4be4-a5d7-06de86825371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=346880066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.346880066
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1178646260
Short name T242
Test name
Test status
Simulation time 119027082 ps
CPU time 1.68 seconds
Started May 07 12:39:19 PM PDT 24
Finished May 07 12:39:23 PM PDT 24
Peak memory 204028 kb
Host smart-6c64020b-4928-4720-9a63-1a5d1d023dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1178646260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1178646260
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1895194053
Short name T102
Test name
Test status
Simulation time 659449836 ps
CPU time 2.86 seconds
Started May 07 12:39:35 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 204008 kb
Host smart-83abae76-1835-4e9e-b2d7-45580ac656e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1895194053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1895194053
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1100490272
Short name T276
Test name
Test status
Simulation time 32955421 ps
CPU time 0.69 seconds
Started May 07 12:39:45 PM PDT 24
Finished May 07 12:39:47 PM PDT 24
Peak memory 203204 kb
Host smart-c58e8f1f-fb48-4100-aed7-c72c3b9e2302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1100490272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1100490272
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2528564468
Short name T1467
Test name
Test status
Simulation time 33330313 ps
CPU time 0.67 seconds
Started May 07 12:39:51 PM PDT 24
Finished May 07 12:39:54 PM PDT 24
Peak memory 203212 kb
Host smart-92412775-6d6e-4c9d-91cf-a2e75ff4a23a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2528564468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2528564468
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3484052993
Short name T74
Test name
Test status
Simulation time 37011618 ps
CPU time 0.62 seconds
Started May 07 12:39:51 PM PDT 24
Finished May 07 12:39:53 PM PDT 24
Peak memory 203024 kb
Host smart-d6d0ff2c-4e38-4481-93cc-0d9a888509a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3484052993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3484052993
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1118751063
Short name T1474
Test name
Test status
Simulation time 54110731 ps
CPU time 0.7 seconds
Started May 07 12:39:46 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 203096 kb
Host smart-ecebfbac-691b-4e72-a142-fe85f5cddf45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1118751063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1118751063
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3668654261
Short name T76
Test name
Test status
Simulation time 40623871 ps
CPU time 0.67 seconds
Started May 07 12:39:44 PM PDT 24
Finished May 07 12:39:46 PM PDT 24
Peak memory 203192 kb
Host smart-cf92ea66-bccf-4100-add3-8a96d4cf192e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3668654261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3668654261
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1647915932
Short name T281
Test name
Test status
Simulation time 30395252 ps
CPU time 0.68 seconds
Started May 07 12:39:49 PM PDT 24
Finished May 07 12:39:51 PM PDT 24
Peak memory 203172 kb
Host smart-f4a6e4ea-0e5b-4f0c-90cd-8a21aa29797c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1647915932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1647915932
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.146202439
Short name T1408
Test name
Test status
Simulation time 27863528 ps
CPU time 0.63 seconds
Started May 07 12:39:51 PM PDT 24
Finished May 07 12:39:53 PM PDT 24
Peak memory 203276 kb
Host smart-f99a1b3b-517b-4a8c-af32-2d65df4824b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=146202439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.146202439
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2836576673
Short name T1444
Test name
Test status
Simulation time 30743080 ps
CPU time 0.64 seconds
Started May 07 12:39:50 PM PDT 24
Finished May 07 12:39:53 PM PDT 24
Peak memory 203176 kb
Host smart-7bcb3913-a502-4388-8b38-08e62fdff74e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2836576673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2836576673
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.44379654
Short name T1415
Test name
Test status
Simulation time 30908718 ps
CPU time 0.66 seconds
Started May 07 12:39:49 PM PDT 24
Finished May 07 12:39:51 PM PDT 24
Peak memory 203096 kb
Host smart-1aa5421d-0fc2-498e-9d92-4902ff54a796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=44379654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.44379654
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3906312235
Short name T1422
Test name
Test status
Simulation time 69454681 ps
CPU time 0.74 seconds
Started May 07 12:39:53 PM PDT 24
Finished May 07 12:39:56 PM PDT 24
Peak memory 203164 kb
Host smart-32cc0670-f9d5-4c37-a51e-6a0e851425f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3906312235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3906312235
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.593807302
Short name T256
Test name
Test status
Simulation time 110435705 ps
CPU time 3.23 seconds
Started May 07 12:39:35 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 203904 kb
Host smart-2f55aae7-e139-41b8-b4c6-f0bcd6ae95ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=593807302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.593807302
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3206979665
Short name T1435
Test name
Test status
Simulation time 1329497472 ps
CPU time 8.83 seconds
Started May 07 12:39:36 PM PDT 24
Finished May 07 12:39:46 PM PDT 24
Peak memory 203928 kb
Host smart-1f846c2a-aced-46f5-a779-cadea09b7afb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3206979665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3206979665
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.4125070607
Short name T246
Test name
Test status
Simulation time 55783242 ps
CPU time 0.83 seconds
Started May 07 12:39:25 PM PDT 24
Finished May 07 12:39:27 PM PDT 24
Peak memory 203712 kb
Host smart-a9d7c07e-172c-4bbb-afbb-2fa5dbbd9bc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4125070607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.4125070607
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.271395350
Short name T1431
Test name
Test status
Simulation time 85687432 ps
CPU time 1.2 seconds
Started May 07 12:39:35 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 213292 kb
Host smart-355b021b-181b-4b31-acde-cd3196a4c551
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271395350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.271395350
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2069472917
Short name T1418
Test name
Test status
Simulation time 88930036 ps
CPU time 0.81 seconds
Started May 07 12:39:11 PM PDT 24
Finished May 07 12:39:14 PM PDT 24
Peak memory 203716 kb
Host smart-8715c8e3-c72e-4b30-8045-d785478565fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2069472917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2069472917
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.409393923
Short name T258
Test name
Test status
Simulation time 155359136 ps
CPU time 2.42 seconds
Started May 07 12:39:18 PM PDT 24
Finished May 07 12:39:23 PM PDT 24
Peak memory 212172 kb
Host smart-bd9eee5c-3a2c-4b1a-80d8-11e1223422fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=409393923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.409393923
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1857765370
Short name T1430
Test name
Test status
Simulation time 259400783 ps
CPU time 2.51 seconds
Started May 07 12:39:26 PM PDT 24
Finished May 07 12:39:30 PM PDT 24
Peak memory 203860 kb
Host smart-aa58f0ee-1c49-4cfc-866d-81bab55a5fcd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1857765370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1857765370
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2258436976
Short name T263
Test name
Test status
Simulation time 124594158 ps
CPU time 1.16 seconds
Started May 07 12:39:38 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 203864 kb
Host smart-6bc23252-4154-47b5-aaf9-3e918ac454a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2258436976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2258436976
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1952756592
Short name T284
Test name
Test status
Simulation time 32233755 ps
CPU time 0.67 seconds
Started May 07 12:39:49 PM PDT 24
Finished May 07 12:39:51 PM PDT 24
Peak memory 203276 kb
Host smart-61c111d9-5c0e-461b-8c59-6231283dde04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1952756592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1952756592
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3441288951
Short name T270
Test name
Test status
Simulation time 31459559 ps
CPU time 0.65 seconds
Started May 07 12:39:54 PM PDT 24
Finished May 07 12:39:57 PM PDT 24
Peak memory 203028 kb
Host smart-606312e4-3c8d-4528-b178-7f70953b8e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3441288951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3441288951
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.982602537
Short name T272
Test name
Test status
Simulation time 25692741 ps
CPU time 0.68 seconds
Started May 07 12:39:57 PM PDT 24
Finished May 07 12:40:00 PM PDT 24
Peak memory 203092 kb
Host smart-1da781e5-b118-496a-a87f-9105343154d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=982602537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.982602537
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3311479936
Short name T1469
Test name
Test status
Simulation time 38881543 ps
CPU time 0.66 seconds
Started May 07 12:40:07 PM PDT 24
Finished May 07 12:40:09 PM PDT 24
Peak memory 203016 kb
Host smart-10c96413-6ad7-4ab8-8b06-3c5e33b7797c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3311479936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3311479936
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2630331879
Short name T1400
Test name
Test status
Simulation time 33860558 ps
CPU time 0.7 seconds
Started May 07 12:39:53 PM PDT 24
Finished May 07 12:39:55 PM PDT 24
Peak memory 203376 kb
Host smart-548316bc-63ed-43ae-8634-b3754798e0d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2630331879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2630331879
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1738316082
Short name T1446
Test name
Test status
Simulation time 38381439 ps
CPU time 0.65 seconds
Started May 07 12:39:54 PM PDT 24
Finished May 07 12:39:57 PM PDT 24
Peak memory 203064 kb
Host smart-26fec54f-dde4-4a12-9ed8-f7f303dd56dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1738316082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1738316082
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3031296219
Short name T285
Test name
Test status
Simulation time 20807967 ps
CPU time 0.67 seconds
Started May 07 12:39:54 PM PDT 24
Finished May 07 12:39:58 PM PDT 24
Peak memory 203200 kb
Host smart-5f82a9ff-ca42-4080-a565-8fba1864b189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3031296219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3031296219
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.469416499
Short name T72
Test name
Test status
Simulation time 45591475 ps
CPU time 0.66 seconds
Started May 07 12:39:55 PM PDT 24
Finished May 07 12:39:58 PM PDT 24
Peak memory 203208 kb
Host smart-a89d772d-3fc2-4062-b3e2-de8ed100998e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=469416499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.469416499
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1614092897
Short name T1465
Test name
Test status
Simulation time 70366200 ps
CPU time 0.71 seconds
Started May 07 12:39:53 PM PDT 24
Finished May 07 12:39:56 PM PDT 24
Peak memory 203272 kb
Host smart-8b1f9df1-da82-458e-9aa2-0e0d9a80f59f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1614092897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1614092897
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.546109310
Short name T1432
Test name
Test status
Simulation time 76452174 ps
CPU time 1.94 seconds
Started May 07 12:39:39 PM PDT 24
Finished May 07 12:39:42 PM PDT 24
Peak memory 212204 kb
Host smart-3c90e721-e873-4746-bf8d-1c99205cdf23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546109310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.546109310
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.408462660
Short name T1463
Test name
Test status
Simulation time 80668345 ps
CPU time 1.06 seconds
Started May 07 12:39:36 PM PDT 24
Finished May 07 12:39:39 PM PDT 24
Peak memory 203892 kb
Host smart-436a7b18-afde-475c-84dc-046449deefee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=408462660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.408462660
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2756773925
Short name T75
Test name
Test status
Simulation time 45623769 ps
CPU time 0.65 seconds
Started May 07 12:39:35 PM PDT 24
Finished May 07 12:39:37 PM PDT 24
Peak memory 203180 kb
Host smart-7d37ebf7-2541-42c7-a541-080aa60026f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2756773925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2756773925
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2138663017
Short name T264
Test name
Test status
Simulation time 182882865 ps
CPU time 1.73 seconds
Started May 07 12:39:38 PM PDT 24
Finished May 07 12:39:41 PM PDT 24
Peak memory 203944 kb
Host smart-82a5ccaf-b673-48b6-89ed-577069591e39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2138663017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2138663017
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1447816440
Short name T238
Test name
Test status
Simulation time 195047201 ps
CPU time 2.44 seconds
Started May 07 12:39:36 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 203972 kb
Host smart-b6df4d38-298f-4d62-86ae-8aede3daee67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1447816440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1447816440
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2640637730
Short name T286
Test name
Test status
Simulation time 231561337 ps
CPU time 2.38 seconds
Started May 07 12:39:30 PM PDT 24
Finished May 07 12:39:34 PM PDT 24
Peak memory 203952 kb
Host smart-0abe94f8-c4c7-49f9-b730-3862b6d4db36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2640637730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2640637730
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3889564065
Short name T1407
Test name
Test status
Simulation time 114012942 ps
CPU time 2.21 seconds
Started May 07 12:39:36 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 212200 kb
Host smart-324b06ed-3561-4d00-8b31-b3c203cdc74b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889564065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3889564065
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.166864658
Short name T1410
Test name
Test status
Simulation time 98844649 ps
CPU time 1.06 seconds
Started May 07 12:39:33 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 203928 kb
Host smart-75e8f6a9-387c-44f8-b4ee-53767e8627ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=166864658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.166864658
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3880924161
Short name T271
Test name
Test status
Simulation time 37640532 ps
CPU time 0.66 seconds
Started May 07 12:39:36 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 203244 kb
Host smart-c7aeca77-c4a7-4380-9517-d19813ee1fc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3880924161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3880924161
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.984227436
Short name T1448
Test name
Test status
Simulation time 69703108 ps
CPU time 1.07 seconds
Started May 07 12:39:45 PM PDT 24
Finished May 07 12:39:47 PM PDT 24
Peak memory 203956 kb
Host smart-3ec79243-692f-449c-ae8f-517e5b55ec82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=984227436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.984227436
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1825771741
Short name T1468
Test name
Test status
Simulation time 193217239 ps
CPU time 2.22 seconds
Started May 07 12:39:45 PM PDT 24
Finished May 07 12:39:49 PM PDT 24
Peak memory 203740 kb
Host smart-ab1a36db-7bea-44da-8132-82d61930f39b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1825771741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1825771741
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3674650682
Short name T1420
Test name
Test status
Simulation time 1188178564 ps
CPU time 4.98 seconds
Started May 07 12:39:41 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 204016 kb
Host smart-da7df479-d319-4def-8d25-a4c4a8d2645a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3674650682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3674650682
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1309186757
Short name T247
Test name
Test status
Simulation time 78072284 ps
CPU time 2.25 seconds
Started May 07 12:39:52 PM PDT 24
Finished May 07 12:39:56 PM PDT 24
Peak memory 212216 kb
Host smart-063de8ac-8b85-4207-be7f-9f85734746d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309186757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1309186757
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3495862591
Short name T1460
Test name
Test status
Simulation time 43925624 ps
CPU time 0.82 seconds
Started May 07 12:39:40 PM PDT 24
Finished May 07 12:39:43 PM PDT 24
Peak memory 203652 kb
Host smart-2abc5c63-2673-4f07-bee3-d3376e296116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3495862591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3495862591
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2170501039
Short name T243
Test name
Test status
Simulation time 78231157 ps
CPU time 1.94 seconds
Started May 07 12:39:40 PM PDT 24
Finished May 07 12:39:43 PM PDT 24
Peak memory 203972 kb
Host smart-b6898ce8-8bf9-406b-968c-d80cff898533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2170501039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2170501039
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3881148484
Short name T1398
Test name
Test status
Simulation time 364098734 ps
CPU time 2.72 seconds
Started May 07 12:39:36 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 203936 kb
Host smart-d83915ca-5077-4752-b8fa-869de9d6905b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3881148484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3881148484
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.47329570
Short name T65
Test name
Test status
Simulation time 74919843 ps
CPU time 0.98 seconds
Started May 07 12:39:35 PM PDT 24
Finished May 07 12:39:37 PM PDT 24
Peak memory 203892 kb
Host smart-83bcaebb-1de1-4d32-99ab-49701112f748
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=47329570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.47329570
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2528923546
Short name T283
Test name
Test status
Simulation time 25559516 ps
CPU time 0.64 seconds
Started May 07 12:39:32 PM PDT 24
Finished May 07 12:39:34 PM PDT 24
Peak memory 203264 kb
Host smart-1dbe0cdb-fd4f-4a14-8862-48f273cd3be6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2528923546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2528923546
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4227012230
Short name T1417
Test name
Test status
Simulation time 140176501 ps
CPU time 1.68 seconds
Started May 07 12:39:34 PM PDT 24
Finished May 07 12:39:37 PM PDT 24
Peak memory 203960 kb
Host smart-d7f3217d-f6e8-467c-9faf-21d67583b2af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4227012230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.4227012230
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.253726153
Short name T241
Test name
Test status
Simulation time 110414649 ps
CPU time 1.68 seconds
Started May 07 12:39:31 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 203992 kb
Host smart-2d57adb6-09e2-49f1-8bf3-911320347382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=253726153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.253726153
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2757375308
Short name T293
Test name
Test status
Simulation time 542599124 ps
CPU time 3.02 seconds
Started May 07 12:39:42 PM PDT 24
Finished May 07 12:39:47 PM PDT 24
Peak memory 204028 kb
Host smart-b061a0b5-2df0-4520-b1c9-72a15c68b184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2757375308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2757375308
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1296856599
Short name T239
Test name
Test status
Simulation time 147649856 ps
CPU time 1.91 seconds
Started May 07 12:39:39 PM PDT 24
Finished May 07 12:39:43 PM PDT 24
Peak memory 215884 kb
Host smart-5866dae9-274f-4a16-8dba-02861884525b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296856599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1296856599
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4268265190
Short name T259
Test name
Test status
Simulation time 45450988 ps
CPU time 0.95 seconds
Started May 07 12:39:32 PM PDT 24
Finished May 07 12:39:34 PM PDT 24
Peak memory 203980 kb
Host smart-f756a1be-7c3b-4821-8b45-f819312c3c32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4268265190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4268265190
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3600718634
Short name T1402
Test name
Test status
Simulation time 93469094 ps
CPU time 1.17 seconds
Started May 07 12:39:40 PM PDT 24
Finished May 07 12:39:43 PM PDT 24
Peak memory 203836 kb
Host smart-d4ffea3b-0299-41be-b634-9fddd18debcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3600718634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3600718634
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2406223003
Short name T288
Test name
Test status
Simulation time 566679094 ps
CPU time 4.38 seconds
Started May 07 12:39:42 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 204032 kb
Host smart-cfbfc8e2-5d91-41b3-aff3-551c41f11399
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2406223003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2406223003
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.810989152
Short name T454
Test name
Test status
Simulation time 8538652595 ps
CPU time 7.55 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:13 PM PDT 24
Peak memory 204120 kb
Host smart-ef394443-e8ff-471e-b381-96b4e9ac3c45
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=810989152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.810989152
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.863529009
Short name T319
Test name
Test status
Simulation time 8390490283 ps
CPU time 8.47 seconds
Started May 07 12:41:11 PM PDT 24
Finished May 07 12:41:21 PM PDT 24
Peak memory 204096 kb
Host smart-7625a06b-ab7e-4a2a-a174-716f3f433685
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=863529009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.863529009
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.2195402823
Short name T416
Test name
Test status
Simulation time 8519418121 ps
CPU time 8.43 seconds
Started May 07 12:41:08 PM PDT 24
Finished May 07 12:41:18 PM PDT 24
Peak memory 204080 kb
Host smart-d8675ea1-c6fc-40bf-9924-bc7bd8d1c9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21954
02823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.2195402823
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4141937272
Short name T884
Test name
Test status
Simulation time 8389180637 ps
CPU time 8.29 seconds
Started May 07 12:41:08 PM PDT 24
Finished May 07 12:41:18 PM PDT 24
Peak memory 204116 kb
Host smart-ae097e65-fd69-43c8-9dff-44aeb78ce818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41419
37272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4141937272
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.3125601591
Short name T934
Test name
Test status
Simulation time 8412888784 ps
CPU time 7.51 seconds
Started May 07 12:41:13 PM PDT 24
Finished May 07 12:41:22 PM PDT 24
Peak memory 204100 kb
Host smart-bc4d269a-0f30-4afd-8f75-b7e16ccd7852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31256
01591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3125601591
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.470800857
Short name T1105
Test name
Test status
Simulation time 254671946 ps
CPU time 1.81 seconds
Started May 07 12:41:01 PM PDT 24
Finished May 07 12:41:06 PM PDT 24
Peak memory 204224 kb
Host smart-1ce4e090-08df-40be-9832-a9e9b622b21f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47080
0857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.470800857
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.4294223648
Short name T1326
Test name
Test status
Simulation time 8403987028 ps
CPU time 8.7 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:14 PM PDT 24
Peak memory 204144 kb
Host smart-ec9df820-b5f3-4745-ab96-bfab84c64abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42942
23648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.4294223648
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1542476623
Short name T1277
Test name
Test status
Simulation time 8363648034 ps
CPU time 9.06 seconds
Started May 07 12:41:04 PM PDT 24
Finished May 07 12:41:16 PM PDT 24
Peak memory 204132 kb
Host smart-f4cebd4a-022e-4057-a564-47061ce90199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15424
76623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1542476623
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3529154374
Short name T1054
Test name
Test status
Simulation time 8444345243 ps
CPU time 8.54 seconds
Started May 07 12:41:08 PM PDT 24
Finished May 07 12:41:18 PM PDT 24
Peak memory 204128 kb
Host smart-77f3c535-5641-41fa-a15a-b14ce07362ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35291
54374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3529154374
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3349361225
Short name T90
Test name
Test status
Simulation time 8410999419 ps
CPU time 10.21 seconds
Started May 07 12:41:05 PM PDT 24
Finished May 07 12:41:18 PM PDT 24
Peak memory 204088 kb
Host smart-7c03b769-7764-4832-9bea-8e0c84421319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33493
61225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3349361225
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.550988968
Short name T1230
Test name
Test status
Simulation time 8375443781 ps
CPU time 9.06 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:15 PM PDT 24
Peak memory 203660 kb
Host smart-4ce83ceb-e96b-45f9-a92f-5e6b24facea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55098
8968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.550988968
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3284478895
Short name T98
Test name
Test status
Simulation time 8412388903 ps
CPU time 7.69 seconds
Started May 07 12:40:57 PM PDT 24
Finished May 07 12:41:06 PM PDT 24
Peak memory 204104 kb
Host smart-45d2202a-fc81-473f-bd1d-7cc82f869a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32844
78895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3284478895
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.638759810
Short name T809
Test name
Test status
Simulation time 8430671014 ps
CPU time 7.95 seconds
Started May 07 12:41:01 PM PDT 24
Finished May 07 12:41:13 PM PDT 24
Peak memory 204104 kb
Host smart-3fa5490f-f337-444d-96b1-b157672ab450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63875
9810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.638759810
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.854634552
Short name T649
Test name
Test status
Simulation time 8367139635 ps
CPU time 7.67 seconds
Started May 07 12:40:57 PM PDT 24
Finished May 07 12:41:06 PM PDT 24
Peak memory 204156 kb
Host smart-285733b6-e062-4bb5-a764-ae7ef3f40198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85463
4552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.854634552
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2500495047
Short name T39
Test name
Test status
Simulation time 43285363 ps
CPU time 0.67 seconds
Started May 07 12:41:10 PM PDT 24
Finished May 07 12:41:13 PM PDT 24
Peak memory 203960 kb
Host smart-1c9a31ee-0654-4b04-b99d-194d28eac876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25004
95047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2500495047
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1592232493
Short name T1197
Test name
Test status
Simulation time 8374875445 ps
CPU time 7.68 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:13 PM PDT 24
Peak memory 203996 kb
Host smart-5d9a37f8-d902-42bd-9bc2-311a8d36e9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15922
32493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1592232493
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2858390871
Short name T1052
Test name
Test status
Simulation time 8472627267 ps
CPU time 10.42 seconds
Started May 07 12:41:05 PM PDT 24
Finished May 07 12:41:18 PM PDT 24
Peak memory 204116 kb
Host smart-5f0a548b-3765-4d7b-aedf-26b243b7c680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28583
90871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2858390871
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.873212490
Short name T994
Test name
Test status
Simulation time 8430614036 ps
CPU time 7.98 seconds
Started May 07 12:41:17 PM PDT 24
Finished May 07 12:41:26 PM PDT 24
Peak memory 204140 kb
Host smart-6e015563-3efb-4a41-bcd5-7e0fde307271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87321
2490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.873212490
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.25058228
Short name T775
Test name
Test status
Simulation time 8370995260 ps
CPU time 8.69 seconds
Started May 07 12:41:09 PM PDT 24
Finished May 07 12:41:19 PM PDT 24
Peak memory 204124 kb
Host smart-196b665d-bb9b-4ee1-83c1-c5be7187fe0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25058
228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.25058228
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1650649835
Short name T917
Test name
Test status
Simulation time 8380577008 ps
CPU time 8.14 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:14 PM PDT 24
Peak memory 204092 kb
Host smart-899d2bef-e41c-45cd-9401-5d7dfc40da3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16506
49835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1650649835
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.981588852
Short name T413
Test name
Test status
Simulation time 8395910058 ps
CPU time 7.94 seconds
Started May 07 12:41:09 PM PDT 24
Finished May 07 12:41:18 PM PDT 24
Peak memory 204112 kb
Host smart-63f76d99-514a-4872-96ea-498ed5196e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98158
8852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.981588852
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.3587397890
Short name T1178
Test name
Test status
Simulation time 8484727827 ps
CPU time 8.61 seconds
Started May 07 12:41:13 PM PDT 24
Finished May 07 12:41:23 PM PDT 24
Peak memory 204104 kb
Host smart-0e2a3dfd-6d41-4350-a50f-118da9a78929
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3587397890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.3587397890
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.3738822636
Short name T301
Test name
Test status
Simulation time 8398493528 ps
CPU time 10.07 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:15 PM PDT 24
Peak memory 204136 kb
Host smart-d854cc5d-ee89-4bf1-bc12-f16f1c98e3ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3738822636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.3738822636
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.1729493828
Short name T374
Test name
Test status
Simulation time 8374609182 ps
CPU time 8.11 seconds
Started May 07 12:41:16 PM PDT 24
Finished May 07 12:41:25 PM PDT 24
Peak memory 204024 kb
Host smart-09386172-998d-426d-bd47-6f9197301206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17294
93828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.1729493828
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.510447594
Short name T798
Test name
Test status
Simulation time 8383118270 ps
CPU time 8.19 seconds
Started May 07 12:40:59 PM PDT 24
Finished May 07 12:41:09 PM PDT 24
Peak memory 204096 kb
Host smart-81698f06-e651-4b8a-a4ee-8260995ee531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51044
7594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.510447594
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.2314679350
Short name T981
Test name
Test status
Simulation time 8389446362 ps
CPU time 8.36 seconds
Started May 07 12:41:07 PM PDT 24
Finished May 07 12:41:17 PM PDT 24
Peak memory 204124 kb
Host smart-2290fb72-6fd7-408d-818c-c1bf7e32c65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23146
79350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2314679350
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2103645131
Short name T231
Test name
Test status
Simulation time 158523902 ps
CPU time 1.52 seconds
Started May 07 12:41:08 PM PDT 24
Finished May 07 12:41:11 PM PDT 24
Peak memory 204240 kb
Host smart-3839f52a-7e62-4e36-b1c3-afbf05992dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21036
45131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2103645131
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3410151324
Short name T1144
Test name
Test status
Simulation time 8387577206 ps
CPU time 9.65 seconds
Started May 07 12:41:07 PM PDT 24
Finished May 07 12:41:18 PM PDT 24
Peak memory 204120 kb
Host smart-6f6dd14c-3f01-43f6-9d55-5eeef36e42e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34101
51324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3410151324
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2198082774
Short name T818
Test name
Test status
Simulation time 8432772412 ps
CPU time 7.46 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:13 PM PDT 24
Peak memory 204144 kb
Host smart-56255f85-67bd-4e75-ab73-53ca388a6252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21980
82774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2198082774
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1404377251
Short name T1064
Test name
Test status
Simulation time 8369922357 ps
CPU time 8.97 seconds
Started May 07 12:41:09 PM PDT 24
Finished May 07 12:41:20 PM PDT 24
Peak memory 204140 kb
Host smart-435e8297-ffee-478d-bcef-d30b8cd7ada6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14043
77251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1404377251
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3807057826
Short name T961
Test name
Test status
Simulation time 8404091946 ps
CPU time 9.95 seconds
Started May 07 12:41:12 PM PDT 24
Finished May 07 12:41:24 PM PDT 24
Peak memory 204104 kb
Host smart-1441223b-ab5d-482a-a372-f5a7d9754e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38070
57826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3807057826
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.4237014536
Short name T483
Test name
Test status
Simulation time 8438953198 ps
CPU time 7.55 seconds
Started May 07 12:41:15 PM PDT 24
Finished May 07 12:41:24 PM PDT 24
Peak memory 204120 kb
Host smart-d0b5ab32-379e-4652-91a6-dae15c69876a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42370
14536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.4237014536
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3341053309
Short name T1271
Test name
Test status
Simulation time 8379689141 ps
CPU time 8.21 seconds
Started May 07 12:41:10 PM PDT 24
Finished May 07 12:41:22 PM PDT 24
Peak memory 204136 kb
Host smart-8861c04a-7537-4757-b273-3e47df543800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33410
53309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3341053309
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3334065179
Short name T868
Test name
Test status
Simulation time 8368820918 ps
CPU time 7.9 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:13 PM PDT 24
Peak memory 204152 kb
Host smart-8b874014-5e87-411b-87b2-ea798128fc0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33340
65179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3334065179
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3845994040
Short name T30
Test name
Test status
Simulation time 41648114 ps
CPU time 0.64 seconds
Started May 07 12:41:20 PM PDT 24
Finished May 07 12:41:22 PM PDT 24
Peak memory 203960 kb
Host smart-ff0a8744-26a5-4f37-b725-1c72ade45c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38459
94040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3845994040
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.640258139
Short name T1111
Test name
Test status
Simulation time 15249851552 ps
CPU time 27.94 seconds
Started May 07 12:41:15 PM PDT 24
Finished May 07 12:41:44 PM PDT 24
Peak memory 204404 kb
Host smart-685328da-5008-4d3e-a167-2dd94a15e502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64025
8139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.640258139
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.331147647
Short name T921
Test name
Test status
Simulation time 8383152614 ps
CPU time 7.81 seconds
Started May 07 12:41:11 PM PDT 24
Finished May 07 12:41:21 PM PDT 24
Peak memory 204084 kb
Host smart-62539828-ddd4-4409-a389-b57deb2a3a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33114
7647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.331147647
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.4155900805
Short name T1046
Test name
Test status
Simulation time 8468174339 ps
CPU time 9.16 seconds
Started May 07 12:41:12 PM PDT 24
Finished May 07 12:41:23 PM PDT 24
Peak memory 204104 kb
Host smart-84863f6a-76a2-49f9-a0cc-c787cf1efba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41559
00805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.4155900805
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1418695967
Short name T946
Test name
Test status
Simulation time 8398077229 ps
CPU time 7.67 seconds
Started May 07 12:41:10 PM PDT 24
Finished May 07 12:41:20 PM PDT 24
Peak memory 204032 kb
Host smart-3d719ee2-2099-43a6-9e8d-60c69e67a9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14186
95967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1418695967
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.41366437
Short name T61
Test name
Test status
Simulation time 452768917 ps
CPU time 1.39 seconds
Started May 07 12:41:13 PM PDT 24
Finished May 07 12:41:16 PM PDT 24
Peak memory 221432 kb
Host smart-bbcc2dc3-f111-450e-a996-1519941500dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=41366437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.41366437
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3359329557
Short name T1040
Test name
Test status
Simulation time 8372057203 ps
CPU time 7.73 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:13 PM PDT 24
Peak memory 204020 kb
Host smart-5273938e-a98b-4a9e-801d-45f413c639e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33593
29557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3359329557
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1729125273
Short name T1025
Test name
Test status
Simulation time 8367513746 ps
CPU time 8.97 seconds
Started May 07 12:41:20 PM PDT 24
Finished May 07 12:41:31 PM PDT 24
Peak memory 204144 kb
Host smart-2f431a24-095f-4232-80bd-4786c86cc341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17291
25273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1729125273
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3145194259
Short name T152
Test name
Test status
Simulation time 8478473397 ps
CPU time 9.91 seconds
Started May 07 12:41:08 PM PDT 24
Finished May 07 12:41:20 PM PDT 24
Peak memory 204136 kb
Host smart-179cf12c-2566-4bd9-8413-02965a30d738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31451
94259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3145194259
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1683787653
Short name T1041
Test name
Test status
Simulation time 8386788096 ps
CPU time 8.64 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:14 PM PDT 24
Peak memory 204132 kb
Host smart-4f6aad51-5d83-43b1-9879-c0b4ec27f2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16837
87653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1683787653
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3763570467
Short name T1128
Test name
Test status
Simulation time 8398235186 ps
CPU time 8.25 seconds
Started May 07 12:41:13 PM PDT 24
Finished May 07 12:41:23 PM PDT 24
Peak memory 203996 kb
Host smart-4c38087d-c6ef-49cd-bcc5-d64c0d562e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37635
70467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3763570467
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.1086995562
Short name T675
Test name
Test status
Simulation time 8382108936 ps
CPU time 7.51 seconds
Started May 07 12:41:51 PM PDT 24
Finished May 07 12:42:00 PM PDT 24
Peak memory 204128 kb
Host smart-aca5ce06-f19f-4c1a-a44b-d4ac91444090
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1086995562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.1086995562
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.137391797
Short name T763
Test name
Test status
Simulation time 8462545918 ps
CPU time 7.87 seconds
Started May 07 12:41:48 PM PDT 24
Finished May 07 12:41:58 PM PDT 24
Peak memory 204108 kb
Host smart-536d333e-6f32-4d86-8584-ee23be5826bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13739
1797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.137391797
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.621960878
Short name T744
Test name
Test status
Simulation time 8394973504 ps
CPU time 10.45 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:52 PM PDT 24
Peak memory 204096 kb
Host smart-a816a1a9-3dbf-420a-8591-573d7c0f4aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62196
0878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.621960878
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.1706239634
Short name T499
Test name
Test status
Simulation time 8403137435 ps
CPU time 7.9 seconds
Started May 07 12:41:46 PM PDT 24
Finished May 07 12:41:56 PM PDT 24
Peak memory 204176 kb
Host smart-912b6814-d9ee-455b-9141-fea303f89c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17062
39634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1706239634
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2596465435
Short name T429
Test name
Test status
Simulation time 106587745 ps
CPU time 1.27 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204008 kb
Host smart-1bc8b073-6dae-4b45-8d4d-b21c5f8f67c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25964
65435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2596465435
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1451374217
Short name T1212
Test name
Test status
Simulation time 8416364543 ps
CPU time 7.44 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:46 PM PDT 24
Peak memory 204124 kb
Host smart-4361126b-f246-422d-a6fb-3bac17def690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14513
74217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1451374217
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1283134563
Short name T1324
Test name
Test status
Simulation time 8461035938 ps
CPU time 9.83 seconds
Started May 07 12:42:09 PM PDT 24
Finished May 07 12:42:20 PM PDT 24
Peak memory 204080 kb
Host smart-dd1fdc14-0a31-4356-8ab1-832eda56d4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12831
34563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1283134563
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3215859463
Short name T792
Test name
Test status
Simulation time 8450941369 ps
CPU time 8.24 seconds
Started May 07 12:41:52 PM PDT 24
Finished May 07 12:42:02 PM PDT 24
Peak memory 204128 kb
Host smart-d00b0cb6-868a-4e4e-9e4c-d92baee2a65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32158
59463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3215859463
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1234598390
Short name T819
Test name
Test status
Simulation time 8416120981 ps
CPU time 8.49 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:04 PM PDT 24
Peak memory 204052 kb
Host smart-715ea2c5-beed-409d-ac0b-6779479b374d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12345
98390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1234598390
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.244157518
Short name T1238
Test name
Test status
Simulation time 8373990480 ps
CPU time 7.96 seconds
Started May 07 12:41:42 PM PDT 24
Finished May 07 12:41:52 PM PDT 24
Peak memory 204128 kb
Host smart-bb5eeffe-ebd3-4673-b4a7-9b7bcf5f8e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24415
7518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.244157518
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.885792465
Short name T1298
Test name
Test status
Simulation time 8464104218 ps
CPU time 7.55 seconds
Started May 07 12:43:17 PM PDT 24
Finished May 07 12:43:26 PM PDT 24
Peak memory 203936 kb
Host smart-a0d98a7e-4a15-4999-99be-175ba13bc13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88579
2465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.885792465
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.4142124216
Short name T356
Test name
Test status
Simulation time 8415340492 ps
CPU time 8.16 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:59 PM PDT 24
Peak memory 203048 kb
Host smart-58bcac15-f87b-460c-bc3a-d1dd925071f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41421
24216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.4142124216
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2504846572
Short name T573
Test name
Test status
Simulation time 8395358772 ps
CPU time 8.03 seconds
Started May 07 12:41:46 PM PDT 24
Finished May 07 12:41:56 PM PDT 24
Peak memory 204120 kb
Host smart-95a90098-12ce-4b4c-8f14-a638162f1a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25048
46572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2504846572
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2734034794
Short name T1123
Test name
Test status
Simulation time 8385317093 ps
CPU time 9.12 seconds
Started May 07 12:41:41 PM PDT 24
Finished May 07 12:41:52 PM PDT 24
Peak memory 204124 kb
Host smart-74c2c16c-66a8-449f-9de1-a60418012eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27340
34794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2734034794
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3580612737
Short name T636
Test name
Test status
Simulation time 8367936993 ps
CPU time 7.88 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:05 PM PDT 24
Peak memory 204128 kb
Host smart-6cfba38c-ff33-4985-a974-2a76d9f29816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35806
12737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3580612737
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.71681500
Short name T748
Test name
Test status
Simulation time 35243322 ps
CPU time 0.67 seconds
Started May 07 12:41:34 PM PDT 24
Finished May 07 12:41:36 PM PDT 24
Peak memory 203964 kb
Host smart-4afcb90a-ce11-417b-8ba8-ef760c895b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71681
500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.71681500
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.549083172
Short name T235
Test name
Test status
Simulation time 29944686495 ps
CPU time 65.68 seconds
Started May 07 12:42:02 PM PDT 24
Finished May 07 12:43:09 PM PDT 24
Peak memory 204416 kb
Host smart-ceb9f6d5-8c3f-422c-9ae6-235122a7b3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54908
3172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.549083172
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2216779340
Short name T82
Test name
Test status
Simulation time 8403414949 ps
CPU time 7.77 seconds
Started May 07 12:41:52 PM PDT 24
Finished May 07 12:42:02 PM PDT 24
Peak memory 204308 kb
Host smart-02465bab-8a18-4ec5-bc00-62739e5ce2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22167
79340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2216779340
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.2818167266
Short name T851
Test name
Test status
Simulation time 8414676668 ps
CPU time 8.38 seconds
Started May 07 12:41:53 PM PDT 24
Finished May 07 12:42:04 PM PDT 24
Peak memory 204068 kb
Host smart-c975561a-1da0-4daf-9217-1da78a1cd6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28181
67266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.2818167266
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.14917794
Short name T1168
Test name
Test status
Simulation time 8379378652 ps
CPU time 8.17 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:45 PM PDT 24
Peak memory 204040 kb
Host smart-dce1859f-7c9d-4083-91d5-78a5caee24b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14917
794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.14917794
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2612834487
Short name T674
Test name
Test status
Simulation time 8363463790 ps
CPU time 9.81 seconds
Started May 07 12:42:10 PM PDT 24
Finished May 07 12:42:22 PM PDT 24
Peak memory 204056 kb
Host smart-42e628b6-2428-49c9-a462-9dac8b722575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26128
34487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2612834487
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2573724119
Short name T1080
Test name
Test status
Simulation time 8415548557 ps
CPU time 8.33 seconds
Started May 07 12:41:43 PM PDT 24
Finished May 07 12:41:53 PM PDT 24
Peak memory 204136 kb
Host smart-ac206f65-b768-40fa-a70e-65b53ce521d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25737
24119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2573724119
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3587311999
Short name T848
Test name
Test status
Simulation time 8392183397 ps
CPU time 8.81 seconds
Started May 07 12:41:52 PM PDT 24
Finished May 07 12:42:02 PM PDT 24
Peak memory 204132 kb
Host smart-a18a5f5a-7d9d-4fae-9f93-cad22d777fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35873
11999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3587311999
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.4063347169
Short name T1033
Test name
Test status
Simulation time 8388849952 ps
CPU time 7.51 seconds
Started May 07 12:41:46 PM PDT 24
Finished May 07 12:41:55 PM PDT 24
Peak memory 204012 kb
Host smart-87c647b6-1ce2-4829-8271-1725b5af90fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40633
47169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.4063347169
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.1795876675
Short name T938
Test name
Test status
Simulation time 8467750595 ps
CPU time 9.71 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:11 PM PDT 24
Peak memory 204036 kb
Host smart-3aa50c7d-16ac-4d92-8ebd-c86896201be2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1795876675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.1795876675
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.2284431735
Short name T36
Test name
Test status
Simulation time 8382797888 ps
CPU time 8.14 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204104 kb
Host smart-8175f1da-9a2b-4216-b97d-44a8a2b7f640
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2284431735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.2284431735
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.2264030006
Short name T452
Test name
Test status
Simulation time 8405822287 ps
CPU time 8.05 seconds
Started May 07 12:41:59 PM PDT 24
Finished May 07 12:42:10 PM PDT 24
Peak memory 204120 kb
Host smart-bcc44192-8ab4-423e-94f3-73feb8fd575e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22640
30006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.2264030006
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2896813626
Short name T355
Test name
Test status
Simulation time 8380014165 ps
CPU time 7.54 seconds
Started May 07 12:41:46 PM PDT 24
Finished May 07 12:41:56 PM PDT 24
Peak memory 204092 kb
Host smart-100248c5-21ae-48be-8ffd-151ee0eb9af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28968
13626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2896813626
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.2305247331
Short name T627
Test name
Test status
Simulation time 8374376474 ps
CPU time 7.81 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:09 PM PDT 24
Peak memory 204124 kb
Host smart-97d12298-eb84-46cf-b07c-9b815851b90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23052
47331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2305247331
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.850358435
Short name T761
Test name
Test status
Simulation time 63819587 ps
CPU time 1.5 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:40 PM PDT 24
Peak memory 204136 kb
Host smart-bfc3fa40-718c-417a-8416-8fe7b64866cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85035
8435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.850358435
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.4271832
Short name T474
Test name
Test status
Simulation time 8445590340 ps
CPU time 9.26 seconds
Started May 07 12:41:48 PM PDT 24
Finished May 07 12:42:00 PM PDT 24
Peak memory 204108 kb
Host smart-c0f9d1ef-a3a7-47ef-b45d-3120bb80eb0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42718
32 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.4271832
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1238564260
Short name T336
Test name
Test status
Simulation time 8418130105 ps
CPU time 9.22 seconds
Started May 07 12:41:44 PM PDT 24
Finished May 07 12:41:56 PM PDT 24
Peak memory 204124 kb
Host smart-d6f04052-43b9-466e-8864-8e4b63f58e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385
64260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1238564260
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.596051828
Short name T1297
Test name
Test status
Simulation time 8373687357 ps
CPU time 8.11 seconds
Started May 07 12:43:09 PM PDT 24
Finished May 07 12:43:19 PM PDT 24
Peak memory 203940 kb
Host smart-7e3ac8ae-aa00-44fc-ac80-b9a48f9bd8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59605
1828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.596051828
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.81027299
Short name T662
Test name
Test status
Simulation time 8421717535 ps
CPU time 7.76 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:45 PM PDT 24
Peak memory 204120 kb
Host smart-c6b6503e-0515-44a1-b113-0f65fba59bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81027
299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.81027299
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.499024435
Short name T676
Test name
Test status
Simulation time 8395158744 ps
CPU time 8.45 seconds
Started May 07 12:42:05 PM PDT 24
Finished May 07 12:42:15 PM PDT 24
Peak memory 204028 kb
Host smart-b1238bd6-3e0c-4902-a74b-4c2f0e49fb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49902
4435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.499024435
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1437581809
Short name T1209
Test name
Test status
Simulation time 8377627802 ps
CPU time 8.39 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:09 PM PDT 24
Peak memory 204144 kb
Host smart-79b1f8c1-9e0d-4090-938b-ac21c6437bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14375
81809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1437581809
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3260887470
Short name T778
Test name
Test status
Simulation time 64965021 ps
CPU time 0.67 seconds
Started May 07 12:41:52 PM PDT 24
Finished May 07 12:41:54 PM PDT 24
Peak memory 203976 kb
Host smart-956cdb83-3cfe-4dbf-8709-4e511d6d1a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32608
87470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3260887470
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1875543954
Short name T1214
Test name
Test status
Simulation time 16837948794 ps
CPU time 27.18 seconds
Started May 07 12:43:06 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204220 kb
Host smart-b9636d53-b162-4094-82b4-1a2318cd367d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18755
43954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1875543954
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1086627486
Short name T1104
Test name
Test status
Simulation time 8401597458 ps
CPU time 7.36 seconds
Started May 07 12:41:48 PM PDT 24
Finished May 07 12:41:57 PM PDT 24
Peak memory 204028 kb
Host smart-f5fa52f1-807d-4aaa-8364-57e3dafc34a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10866
27486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1086627486
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1533711358
Short name T612
Test name
Test status
Simulation time 8425449345 ps
CPU time 7.96 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204100 kb
Host smart-f820ce23-65a1-443c-84bc-b23caf0ccf8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15337
11358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1533711358
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3958672401
Short name T1216
Test name
Test status
Simulation time 8374437838 ps
CPU time 7.79 seconds
Started May 07 12:41:48 PM PDT 24
Finished May 07 12:41:57 PM PDT 24
Peak memory 204140 kb
Host smart-535f0e02-d911-44b9-ad6d-f4cc69375b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39586
72401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3958672401
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3226511437
Short name T1364
Test name
Test status
Simulation time 8377396632 ps
CPU time 7.42 seconds
Started May 07 12:41:51 PM PDT 24
Finished May 07 12:42:00 PM PDT 24
Peak memory 204112 kb
Host smart-f51c884c-e908-4731-b686-9d5d15203f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32265
11437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3226511437
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2838592455
Short name T783
Test name
Test status
Simulation time 8372661432 ps
CPU time 8.23 seconds
Started May 07 12:42:06 PM PDT 24
Finished May 07 12:42:16 PM PDT 24
Peak memory 204132 kb
Host smart-6a05995e-87be-4ef1-8977-250442936c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28385
92455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2838592455
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1018557791
Short name T504
Test name
Test status
Simulation time 8461525011 ps
CPU time 9.79 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:33 PM PDT 24
Peak memory 203936 kb
Host smart-146e4a50-b05a-4668-99de-7486420f3e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10185
57791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1018557791
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2655156752
Short name T322
Test name
Test status
Simulation time 8392543401 ps
CPU time 8.41 seconds
Started May 07 12:41:59 PM PDT 24
Finished May 07 12:42:10 PM PDT 24
Peak memory 204116 kb
Host smart-0f67b78f-f4aa-4c72-aa70-e172b11efa4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26551
56752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2655156752
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.60287405
Short name T559
Test name
Test status
Simulation time 8413436957 ps
CPU time 8.9 seconds
Started May 07 12:41:38 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204088 kb
Host smart-2274c891-8368-4bb6-bd67-4104c6ae4845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60287
405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.60287405
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.614270678
Short name T776
Test name
Test status
Simulation time 8480558222 ps
CPU time 8.76 seconds
Started May 07 12:42:10 PM PDT 24
Finished May 07 12:42:21 PM PDT 24
Peak memory 204104 kb
Host smart-16ac918a-95e9-4763-9f45-e68b576aa3b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=614270678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.614270678
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.380390475
Short name T615
Test name
Test status
Simulation time 8399613452 ps
CPU time 8.84 seconds
Started May 07 12:41:51 PM PDT 24
Finished May 07 12:42:02 PM PDT 24
Peak memory 204100 kb
Host smart-74bb0047-b012-4d3b-85fe-ee718e397656
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=380390475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.380390475
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.2675410360
Short name T1377
Test name
Test status
Simulation time 8426854091 ps
CPU time 9.49 seconds
Started May 07 12:41:45 PM PDT 24
Finished May 07 12:41:57 PM PDT 24
Peak memory 204112 kb
Host smart-ff8a2d84-ab62-4a7f-8c78-1bde1c643680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26754
10360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.2675410360
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1474514329
Short name T846
Test name
Test status
Simulation time 8428365925 ps
CPU time 7.91 seconds
Started May 07 12:42:01 PM PDT 24
Finished May 07 12:42:11 PM PDT 24
Peak memory 204104 kb
Host smart-586a67f1-29ca-49d8-b1da-93ce26e40d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14745
14329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1474514329
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.2373280503
Short name T439
Test name
Test status
Simulation time 8374192304 ps
CPU time 8.07 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:05 PM PDT 24
Peak memory 204080 kb
Host smart-404a1c37-a2bf-4238-825f-79fcf02106c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23732
80503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2373280503
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1894727877
Short name T1157
Test name
Test status
Simulation time 182843057 ps
CPU time 1.91 seconds
Started May 07 12:41:47 PM PDT 24
Finished May 07 12:41:51 PM PDT 24
Peak memory 204200 kb
Host smart-1c4549a9-e554-471d-8310-1646c325ed75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18947
27877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1894727877
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1070320875
Short name T1089
Test name
Test status
Simulation time 8366604430 ps
CPU time 9.52 seconds
Started May 07 12:41:53 PM PDT 24
Finished May 07 12:42:05 PM PDT 24
Peak memory 204104 kb
Host smart-56917f38-60a1-4da1-b301-1bc047c1c1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10703
20875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1070320875
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2731709974
Short name T598
Test name
Test status
Simulation time 8423544159 ps
CPU time 8.24 seconds
Started May 07 12:42:08 PM PDT 24
Finished May 07 12:42:18 PM PDT 24
Peak memory 204144 kb
Host smart-0cec5ea4-4292-4524-bbf3-46b69b86ceb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27317
09974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2731709974
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.41929663
Short name T933
Test name
Test status
Simulation time 8422407179 ps
CPU time 8.04 seconds
Started May 07 12:42:01 PM PDT 24
Finished May 07 12:42:11 PM PDT 24
Peak memory 204136 kb
Host smart-9ca3e6c8-40d3-4dc9-b109-2407f2ec36ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41929
663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.41929663
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1014794619
Short name T444
Test name
Test status
Simulation time 8371586077 ps
CPU time 7.99 seconds
Started May 07 12:41:49 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 204148 kb
Host smart-53224399-37b5-42bc-8fcf-b014f1341378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10147
94619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1014794619
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2190674016
Short name T110
Test name
Test status
Simulation time 8426219135 ps
CPU time 7.65 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204116 kb
Host smart-2dd7960c-ba43-4c08-999f-311e7629a180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21906
74016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2190674016
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1261117846
Short name T546
Test name
Test status
Simulation time 8383378139 ps
CPU time 9.13 seconds
Started May 07 12:41:51 PM PDT 24
Finished May 07 12:42:02 PM PDT 24
Peak memory 204068 kb
Host smart-bc4733f7-0e88-4be0-a25a-7009c51a4b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12611
17846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1261117846
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2900619862
Short name T1248
Test name
Test status
Simulation time 8439201954 ps
CPU time 8.03 seconds
Started May 07 12:41:51 PM PDT 24
Finished May 07 12:42:01 PM PDT 24
Peak memory 204124 kb
Host smart-74380d3d-b539-4a17-ab4c-c86bdc4a13a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29006
19862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2900619862
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1861545662
Short name T974
Test name
Test status
Simulation time 8370299850 ps
CPU time 8.05 seconds
Started May 07 12:41:59 PM PDT 24
Finished May 07 12:42:14 PM PDT 24
Peak memory 204120 kb
Host smart-cc2468ed-dddd-4e2e-b66e-314a176b9cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18615
45662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1861545662
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3898963482
Short name T937
Test name
Test status
Simulation time 48671342 ps
CPU time 0.64 seconds
Started May 07 12:41:52 PM PDT 24
Finished May 07 12:41:55 PM PDT 24
Peak memory 203896 kb
Host smart-c8115d88-39bd-497d-81b8-4b74e6fb878e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38989
63482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3898963482
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1522258482
Short name T254
Test name
Test status
Simulation time 19589538039 ps
CPU time 37.51 seconds
Started May 07 12:41:53 PM PDT 24
Finished May 07 12:42:33 PM PDT 24
Peak memory 204456 kb
Host smart-33caeb0b-cb6b-490d-bd17-638542a5a2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15222
58482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1522258482
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3128363679
Short name T838
Test name
Test status
Simulation time 8399041505 ps
CPU time 7.64 seconds
Started May 07 12:41:49 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 204084 kb
Host smart-91d91e2f-0f43-46ea-afbe-5bf8921ca33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31283
63679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3128363679
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2070454537
Short name T672
Test name
Test status
Simulation time 8428947582 ps
CPU time 7.97 seconds
Started May 07 12:42:02 PM PDT 24
Finished May 07 12:42:12 PM PDT 24
Peak memory 204104 kb
Host smart-b9c4019c-9401-4fe8-9bff-394d1a172f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20704
54537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2070454537
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.3465996217
Short name T308
Test name
Test status
Simulation time 8413698509 ps
CPU time 7.48 seconds
Started May 07 12:41:50 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 204124 kb
Host smart-b286c8e1-aeb0-4079-bc91-a9620b009a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34659
96217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.3465996217
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.13499135
Short name T183
Test name
Test status
Simulation time 8375846275 ps
CPU time 9.43 seconds
Started May 07 12:41:59 PM PDT 24
Finished May 07 12:42:11 PM PDT 24
Peak memory 204096 kb
Host smart-53239a1b-65f5-4515-b078-850cde66dae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13499
135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.13499135
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3655491275
Short name T394
Test name
Test status
Simulation time 8398271542 ps
CPU time 8.11 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:06 PM PDT 24
Peak memory 204072 kb
Host smart-52a9a39b-b718-47c2-9494-7176b9994601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36554
91275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3655491275
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1822730379
Short name T831
Test name
Test status
Simulation time 8409391693 ps
CPU time 9.88 seconds
Started May 07 12:42:00 PM PDT 24
Finished May 07 12:42:12 PM PDT 24
Peak memory 204132 kb
Host smart-af2a26f5-b332-442e-9af2-a554034d3f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18227
30379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1822730379
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1546811000
Short name T771
Test name
Test status
Simulation time 8381653124 ps
CPU time 8.06 seconds
Started May 07 12:41:50 PM PDT 24
Finished May 07 12:42:00 PM PDT 24
Peak memory 204116 kb
Host smart-c3229abd-db04-4df4-ac3b-cb51d08ada07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15468
11000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1546811000
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.4255349197
Short name T423
Test name
Test status
Simulation time 8473498700 ps
CPU time 9.11 seconds
Started May 07 12:42:01 PM PDT 24
Finished May 07 12:42:12 PM PDT 24
Peak memory 204116 kb
Host smart-928f5bbc-aae9-4244-95e2-9f57740db18f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4255349197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.4255349197
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.64159571
Short name T468
Test name
Test status
Simulation time 8382758016 ps
CPU time 7.67 seconds
Started May 07 12:41:53 PM PDT 24
Finished May 07 12:42:03 PM PDT 24
Peak memory 204096 kb
Host smart-958de0a4-159b-4635-8337-6290a47eb861
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=64159571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.64159571
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.1247963920
Short name T653
Test name
Test status
Simulation time 8426676492 ps
CPU time 7.98 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:09 PM PDT 24
Peak memory 204072 kb
Host smart-55226a7d-65d9-43ea-b9d5-0d8206413f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12479
63920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.1247963920
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.629739600
Short name T1103
Test name
Test status
Simulation time 8378361437 ps
CPU time 8.01 seconds
Started May 07 12:42:02 PM PDT 24
Finished May 07 12:42:12 PM PDT 24
Peak memory 204124 kb
Host smart-7f411061-a20e-44e1-8e29-f2daaeefd57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62973
9600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.629739600
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.3237002766
Short name T218
Test name
Test status
Simulation time 8381296765 ps
CPU time 7.59 seconds
Started May 07 12:42:06 PM PDT 24
Finished May 07 12:42:15 PM PDT 24
Peak memory 204116 kb
Host smart-a7b895fb-e452-4e48-ab3d-e165c6c647d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32370
02766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3237002766
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3428156185
Short name T485
Test name
Test status
Simulation time 57655375 ps
CPU time 1.42 seconds
Started May 07 12:41:49 PM PDT 24
Finished May 07 12:41:52 PM PDT 24
Peak memory 204184 kb
Host smart-e24b9cb5-3125-475a-9c64-26a995245f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34281
56185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3428156185
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2028051428
Short name T1250
Test name
Test status
Simulation time 8420180709 ps
CPU time 7.99 seconds
Started May 07 12:41:47 PM PDT 24
Finished May 07 12:41:56 PM PDT 24
Peak memory 204092 kb
Host smart-d85c1d56-5c1d-4ec3-9cee-85efacaa5bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20280
51428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2028051428
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3406714907
Short name T206
Test name
Test status
Simulation time 8367604202 ps
CPU time 7.31 seconds
Started May 07 12:42:11 PM PDT 24
Finished May 07 12:42:20 PM PDT 24
Peak memory 204104 kb
Host smart-1a58ea10-c02f-4e2c-8404-63f7b5778ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34067
14907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3406714907
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1831196680
Short name T764
Test name
Test status
Simulation time 8458627148 ps
CPU time 7.95 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204304 kb
Host smart-978f483d-9123-4277-b7c3-c04567a56a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18311
96680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1831196680
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.4138200283
Short name T470
Test name
Test status
Simulation time 8421391485 ps
CPU time 8.41 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:05 PM PDT 24
Peak memory 203652 kb
Host smart-6fe94744-4e90-4ba5-82ac-cf96e48d059b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41382
00283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.4138200283
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.703436204
Short name T461
Test name
Test status
Simulation time 8377076596 ps
CPU time 7.99 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:05 PM PDT 24
Peak memory 204152 kb
Host smart-59e051c5-0027-4b01-9c80-4c8b4eb58d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70343
6204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.703436204
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1553200635
Short name T489
Test name
Test status
Simulation time 8420132419 ps
CPU time 8.2 seconds
Started May 07 12:41:59 PM PDT 24
Finished May 07 12:42:10 PM PDT 24
Peak memory 204108 kb
Host smart-50d3833b-6de8-4ed1-8c66-6644d3c5d986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15532
00635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1553200635
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3853431767
Short name T196
Test name
Test status
Simulation time 8397970769 ps
CPU time 7.71 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204132 kb
Host smart-b2bf77fd-4873-437a-b55c-1807d9bcfd3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38534
31767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3853431767
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.4058074938
Short name T701
Test name
Test status
Simulation time 8368724481 ps
CPU time 7.71 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:04 PM PDT 24
Peak memory 204124 kb
Host smart-f7ef0db5-8886-47f3-8de7-df194182dc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40580
74938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.4058074938
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1046511804
Short name T956
Test name
Test status
Simulation time 68700424 ps
CPU time 0.65 seconds
Started May 07 12:42:05 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 203980 kb
Host smart-97d057e1-25d6-4d83-b5c8-ff4d9588245f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10465
11804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1046511804
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1915208083
Short name T970
Test name
Test status
Simulation time 30556532272 ps
CPU time 55.94 seconds
Started May 07 12:41:59 PM PDT 24
Finished May 07 12:42:57 PM PDT 24
Peak memory 204404 kb
Host smart-4f73d29e-9f40-4a46-9987-2a0f1c428abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19152
08083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1915208083
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3144662342
Short name T524
Test name
Test status
Simulation time 8409261464 ps
CPU time 8.77 seconds
Started May 07 12:42:03 PM PDT 24
Finished May 07 12:42:14 PM PDT 24
Peak memory 204208 kb
Host smart-8006b51c-ed9a-4656-b073-9e79a5e28417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31446
62342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3144662342
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3262183694
Short name T1050
Test name
Test status
Simulation time 8458863538 ps
CPU time 7.76 seconds
Started May 07 12:42:03 PM PDT 24
Finished May 07 12:42:13 PM PDT 24
Peak memory 204132 kb
Host smart-4d6bc8c3-9e4d-434a-b95f-eb3640049f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32621
83694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3262183694
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.1343192018
Short name T1012
Test name
Test status
Simulation time 8388069003 ps
CPU time 7.61 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:05 PM PDT 24
Peak memory 204124 kb
Host smart-364358c9-29ee-48b9-a8b6-e75af0afb283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13431
92018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.1343192018
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.4236471170
Short name T1072
Test name
Test status
Simulation time 8391344346 ps
CPU time 8.87 seconds
Started May 07 12:43:07 PM PDT 24
Finished May 07 12:43:18 PM PDT 24
Peak memory 203928 kb
Host smart-91a10dd7-5b30-4bb5-9a03-b2a9054e195b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42364
71170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.4236471170
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3213343621
Short name T591
Test name
Test status
Simulation time 8389797212 ps
CPU time 7.8 seconds
Started May 07 12:41:53 PM PDT 24
Finished May 07 12:42:03 PM PDT 24
Peak memory 204116 kb
Host smart-e2792671-af88-4c12-aec4-065752e751c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32133
43621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3213343621
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1564923231
Short name T1308
Test name
Test status
Simulation time 8456036324 ps
CPU time 9.32 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 203648 kb
Host smart-a73f45ab-3e59-4464-9ba9-e127d49ce48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15649
23231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1564923231
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1419371720
Short name T623
Test name
Test status
Simulation time 8414237103 ps
CPU time 7.98 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:09 PM PDT 24
Peak memory 204048 kb
Host smart-e06db9d7-22a0-4cfa-8c67-dd2edba6678e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14193
71720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1419371720
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3096820189
Short name T800
Test name
Test status
Simulation time 8412769982 ps
CPU time 8.47 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204100 kb
Host smart-8de88f27-b404-4fee-95a1-14c65e8c30e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30968
20189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3096820189
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.263137067
Short name T1210
Test name
Test status
Simulation time 8461507381 ps
CPU time 8.7 seconds
Started May 07 12:42:11 PM PDT 24
Finished May 07 12:42:21 PM PDT 24
Peak memory 204136 kb
Host smart-76409235-11a8-419d-9464-289446d9aad5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=263137067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.263137067
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.2423777879
Short name T1340
Test name
Test status
Simulation time 8377567727 ps
CPU time 8.82 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204044 kb
Host smart-e2f452b4-2c80-4b7c-a984-b52cf01ff697
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2423777879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.2423777879
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.3696469086
Short name T904
Test name
Test status
Simulation time 8422594684 ps
CPU time 7.8 seconds
Started May 07 12:42:01 PM PDT 24
Finished May 07 12:42:11 PM PDT 24
Peak memory 204132 kb
Host smart-89178a09-e282-4299-a86e-89354d2de2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36964
69086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.3696469086
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.331211150
Short name T1081
Test name
Test status
Simulation time 8375762038 ps
CPU time 9.93 seconds
Started May 07 12:42:05 PM PDT 24
Finished May 07 12:42:16 PM PDT 24
Peak memory 204120 kb
Host smart-6591958b-ba1a-4baf-8260-bf2b86c4bd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33121
1150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.331211150
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.3972537467
Short name T351
Test name
Test status
Simulation time 8388243457 ps
CPU time 7.38 seconds
Started May 07 12:41:45 PM PDT 24
Finished May 07 12:41:55 PM PDT 24
Peak memory 204032 kb
Host smart-759a903e-d1f7-48df-9df4-15e1497fd54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725
37467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3972537467
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2592229173
Short name T1009
Test name
Test status
Simulation time 153349826 ps
CPU time 1.72 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:02 PM PDT 24
Peak memory 204212 kb
Host smart-db1c3171-3e59-40d2-9721-cbb1ef21ee21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25922
29173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2592229173
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1497890469
Short name T666
Test name
Test status
Simulation time 8365212805 ps
CPU time 7.31 seconds
Started May 07 12:42:01 PM PDT 24
Finished May 07 12:42:10 PM PDT 24
Peak memory 204096 kb
Host smart-a2bc9897-d85c-4187-957c-4c9c9b499f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14978
90469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1497890469
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3417429118
Short name T475
Test name
Test status
Simulation time 8482336380 ps
CPU time 8.46 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 203936 kb
Host smart-792e8649-a11d-405c-8d5e-5515a26192cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34174
29118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3417429118
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1875715037
Short name T931
Test name
Test status
Simulation time 8418428916 ps
CPU time 8.39 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204108 kb
Host smart-b6343098-d369-491f-94de-0129507d9d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18757
15037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1875715037
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2613712996
Short name T596
Test name
Test status
Simulation time 8437478600 ps
CPU time 8.78 seconds
Started May 07 12:41:52 PM PDT 24
Finished May 07 12:42:02 PM PDT 24
Peak memory 204120 kb
Host smart-20716c0b-6e19-4e2b-9e91-2b3ec6d413f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26137
12996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2613712996
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.458732205
Short name T1309
Test name
Test status
Simulation time 8394820044 ps
CPU time 8.22 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:06 PM PDT 24
Peak memory 204124 kb
Host smart-22e60785-9cdc-494d-9573-aa840f3cad30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45873
2205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.458732205
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.725175131
Short name T328
Test name
Test status
Simulation time 8394049898 ps
CPU time 8.38 seconds
Started May 07 12:43:28 PM PDT 24
Finished May 07 12:43:39 PM PDT 24
Peak memory 203932 kb
Host smart-6962172a-cdfb-455b-9d47-fae31b377e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72517
5131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.725175131
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3083112024
Short name T977
Test name
Test status
Simulation time 8375745309 ps
CPU time 10.18 seconds
Started May 07 12:42:03 PM PDT 24
Finished May 07 12:42:15 PM PDT 24
Peak memory 204104 kb
Host smart-3ab5c49f-7185-4173-8007-43fb74e579d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30831
12024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3083112024
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2925132338
Short name T1233
Test name
Test status
Simulation time 44268354 ps
CPU time 0.7 seconds
Started May 07 12:42:12 PM PDT 24
Finished May 07 12:42:15 PM PDT 24
Peak memory 203956 kb
Host smart-eb361cb8-380f-4c05-a513-063f35947fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29251
32338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2925132338
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.4131056794
Short name T252
Test name
Test status
Simulation time 24621883270 ps
CPU time 48.79 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:46 PM PDT 24
Peak memory 204360 kb
Host smart-b1291889-a078-42a2-bad8-a25d1fd3a5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41310
56794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.4131056794
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3029048977
Short name T1288
Test name
Test status
Simulation time 8383161107 ps
CPU time 8.82 seconds
Started May 07 12:42:07 PM PDT 24
Finished May 07 12:42:17 PM PDT 24
Peak memory 204104 kb
Host smart-adc74e22-dfa9-4973-a8dd-50e1c893930a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30290
48977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3029048977
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.2711240961
Short name T87
Test name
Test status
Simulation time 8394653585 ps
CPU time 9.86 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:06 PM PDT 24
Peak memory 203664 kb
Host smart-638cce0d-08a8-4287-8e84-46af919e570a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27112
40961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.2711240961
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2101200800
Short name T1082
Test name
Test status
Simulation time 8378161317 ps
CPU time 7.65 seconds
Started May 07 12:42:04 PM PDT 24
Finished May 07 12:42:13 PM PDT 24
Peak memory 204056 kb
Host smart-cd903df8-9527-42cb-9d02-dd896a5bcb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21012
00800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2101200800
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2743704511
Short name T878
Test name
Test status
Simulation time 8377397141 ps
CPU time 7.75 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204108 kb
Host smart-062fbaf6-5e66-4532-a5ad-48bdc8ccc444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27437
04511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2743704511
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.487541965
Short name T1329
Test name
Test status
Simulation time 8446504818 ps
CPU time 8.35 seconds
Started May 07 12:41:45 PM PDT 24
Finished May 07 12:41:55 PM PDT 24
Peak memory 204144 kb
Host smart-5b4096a9-7541-4021-b4f1-8213d4f2f8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48754
1965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.487541965
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2494359688
Short name T343
Test name
Test status
Simulation time 8389645199 ps
CPU time 7.97 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204084 kb
Host smart-208f528d-5175-4673-a620-e4fbcdc9e3e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24943
59688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2494359688
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.821715382
Short name T305
Test name
Test status
Simulation time 8382951903 ps
CPU time 8.52 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204072 kb
Host smart-431afd6e-5723-46bd-8cbd-b0b32a977ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82171
5382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.821715382
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.3254725265
Short name T574
Test name
Test status
Simulation time 8477492693 ps
CPU time 8.88 seconds
Started May 07 12:42:27 PM PDT 24
Finished May 07 12:42:37 PM PDT 24
Peak memory 204100 kb
Host smart-8bbc606e-c19f-4d50-a1db-2d4897c7f4e2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3254725265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.3254725265
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.3660281748
Short name T1145
Test name
Test status
Simulation time 8388663821 ps
CPU time 8.61 seconds
Started May 07 12:41:59 PM PDT 24
Finished May 07 12:42:10 PM PDT 24
Peak memory 204088 kb
Host smart-d70baba0-f13d-458d-843d-39cc1b088c08
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3660281748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.3660281748
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.1650367049
Short name T545
Test name
Test status
Simulation time 8412434373 ps
CPU time 7.73 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:13 PM PDT 24
Peak memory 204060 kb
Host smart-c15066da-1b22-4e7c-babb-1c2612f8653b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16503
67049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.1650367049
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3333345810
Short name T309
Test name
Test status
Simulation time 8379560251 ps
CPU time 9.62 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:11 PM PDT 24
Peak memory 204084 kb
Host smart-8a169169-f3b6-4665-8bd3-029d5621cf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33333
45810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3333345810
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.1579629840
Short name T1048
Test name
Test status
Simulation time 8374593280 ps
CPU time 7.85 seconds
Started May 07 12:42:15 PM PDT 24
Finished May 07 12:42:25 PM PDT 24
Peak memory 204088 kb
Host smart-25b490ec-5d4d-4745-8f9c-df00fa68de29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15796
29840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1579629840
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2898238908
Short name T1355
Test name
Test status
Simulation time 86180685 ps
CPU time 1.87 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 204172 kb
Host smart-ae382499-fe91-4be0-9f48-189307074dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28982
38908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2898238908
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1463910226
Short name T1234
Test name
Test status
Simulation time 8396397769 ps
CPU time 8.32 seconds
Started May 07 12:42:13 PM PDT 24
Finished May 07 12:42:24 PM PDT 24
Peak memory 204088 kb
Host smart-8d6ab24b-74b5-48d0-bbb0-f8fac3f8c66c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14639
10226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1463910226
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3788423914
Short name T1015
Test name
Test status
Simulation time 8369662656 ps
CPU time 7.54 seconds
Started May 07 12:41:53 PM PDT 24
Finished May 07 12:42:03 PM PDT 24
Peak memory 204080 kb
Host smart-d689344f-c28e-41cd-9c80-155d3dc9dfef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37884
23914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3788423914
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.4059539384
Short name T142
Test name
Test status
Simulation time 8433388920 ps
CPU time 7.81 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204084 kb
Host smart-71549a78-b474-47e9-a59a-c9dcf589eece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40595
39384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.4059539384
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3131087959
Short name T641
Test name
Test status
Simulation time 8441865298 ps
CPU time 8.36 seconds
Started May 07 12:42:13 PM PDT 24
Finished May 07 12:42:24 PM PDT 24
Peak memory 204120 kb
Host smart-843c40ed-ba85-422b-9c29-e79af2fa3eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31310
87959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3131087959
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3381912606
Short name T1154
Test name
Test status
Simulation time 8370722952 ps
CPU time 10.33 seconds
Started May 07 12:42:12 PM PDT 24
Finished May 07 12:42:25 PM PDT 24
Peak memory 204144 kb
Host smart-f3fcee18-0a41-4cf7-ad11-e4f13b929e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33819
12606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3381912606
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2291381131
Short name T1156
Test name
Test status
Simulation time 8407908824 ps
CPU time 7.43 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:06 PM PDT 24
Peak memory 204120 kb
Host smart-9ad9d674-76f3-4354-9b8e-f585743ac88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22913
81131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2291381131
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1877342814
Short name T720
Test name
Test status
Simulation time 8419535021 ps
CPU time 8.03 seconds
Started May 07 12:42:02 PM PDT 24
Finished May 07 12:42:12 PM PDT 24
Peak memory 204120 kb
Host smart-bb151ef4-0fac-4373-9e83-ca52a79150f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18773
42814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1877342814
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2937555482
Short name T1344
Test name
Test status
Simulation time 8367119080 ps
CPU time 7.91 seconds
Started May 07 12:42:14 PM PDT 24
Finished May 07 12:42:24 PM PDT 24
Peak memory 204312 kb
Host smart-7fccba9f-1784-4efe-b9bb-02cab818a1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29375
55482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2937555482
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3238777450
Short name T43
Test name
Test status
Simulation time 65344238 ps
CPU time 0.68 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:41:57 PM PDT 24
Peak memory 204008 kb
Host smart-077d124e-e4e5-473e-96b7-f111c98627b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32387
77450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3238777450
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1600909353
Short name T727
Test name
Test status
Simulation time 18840072199 ps
CPU time 34.36 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:34 PM PDT 24
Peak memory 204356 kb
Host smart-b35c1ee8-a812-41e6-bf51-54f61ab73b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16009
09353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1600909353
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1544394430
Short name T1301
Test name
Test status
Simulation time 8378238163 ps
CPU time 7.98 seconds
Started May 07 12:42:03 PM PDT 24
Finished May 07 12:42:12 PM PDT 24
Peak memory 204092 kb
Host smart-994e2959-e12e-4637-bf9e-5b3071f63790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15443
94430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1544394430
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1257782854
Short name T427
Test name
Test status
Simulation time 8446781715 ps
CPU time 7.45 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204132 kb
Host smart-1f99e67b-0a32-4e80-8079-f598776d6778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12577
82854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1257782854
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.2925343653
Short name T1244
Test name
Test status
Simulation time 8416943964 ps
CPU time 8.36 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204092 kb
Host smart-18ac8765-c078-45d2-8f31-bc388e6cacbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29253
43653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.2925343653
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1548487773
Short name T600
Test name
Test status
Simulation time 8371215421 ps
CPU time 8.14 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204208 kb
Host smart-7b330ace-2165-4d08-8421-797b22b461c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15484
87773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1548487773
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2488167106
Short name T1085
Test name
Test status
Simulation time 8435467121 ps
CPU time 7.74 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:06 PM PDT 24
Peak memory 204148 kb
Host smart-ec715a05-8f42-4393-9d37-5d8c86ad000d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24881
67106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2488167106
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1290598495
Short name T813
Test name
Test status
Simulation time 8375261140 ps
CPU time 9.03 seconds
Started May 07 12:42:04 PM PDT 24
Finished May 07 12:42:15 PM PDT 24
Peak memory 204108 kb
Host smart-334803f1-73f8-4581-a8a6-8cf2a03f6f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12905
98495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1290598495
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2106571908
Short name T954
Test name
Test status
Simulation time 8390615534 ps
CPU time 7.57 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:04 PM PDT 24
Peak memory 204020 kb
Host smart-735dc6a0-4ae5-493d-bfa4-7e42d92a6f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21065
71908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2106571908
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.769653222
Short name T1005
Test name
Test status
Simulation time 8496500698 ps
CPU time 8.8 seconds
Started May 07 12:42:02 PM PDT 24
Finished May 07 12:42:13 PM PDT 24
Peak memory 204132 kb
Host smart-87d3a113-70b1-43af-8b86-167eee556937
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=769653222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.769653222
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.1410820149
Short name T1319
Test name
Test status
Simulation time 8380431738 ps
CPU time 7.93 seconds
Started May 07 12:42:07 PM PDT 24
Finished May 07 12:42:16 PM PDT 24
Peak memory 204028 kb
Host smart-b5d7a389-2dac-4e50-a3cb-04a27bf388a9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1410820149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.1410820149
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.3626875852
Short name T984
Test name
Test status
Simulation time 8441858653 ps
CPU time 7.53 seconds
Started May 07 12:42:12 PM PDT 24
Finished May 07 12:42:21 PM PDT 24
Peak memory 204072 kb
Host smart-cb05618f-f786-4d6b-b2df-272248a367f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36268
75852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.3626875852
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2806968616
Short name T1
Test name
Test status
Simulation time 8377773026 ps
CPU time 8.08 seconds
Started May 07 12:42:03 PM PDT 24
Finished May 07 12:42:13 PM PDT 24
Peak memory 204080 kb
Host smart-a2b1728b-2189-4983-9572-3baadfa9d4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28069
68616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2806968616
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.2103647281
Short name T390
Test name
Test status
Simulation time 8392889805 ps
CPU time 9.69 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204096 kb
Host smart-671ffdc8-6f64-4ded-9bc9-0e06089c158c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21036
47281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2103647281
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3671467633
Short name T575
Test name
Test status
Simulation time 47805262 ps
CPU time 1.27 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:01 PM PDT 24
Peak memory 204268 kb
Host smart-a0cdd092-b9dc-4e7b-b69d-2bc527687a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36714
67633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3671467633
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.2270160859
Short name T935
Test name
Test status
Simulation time 8436032145 ps
CPU time 7.54 seconds
Started May 07 12:42:21 PM PDT 24
Finished May 07 12:42:29 PM PDT 24
Peak memory 204112 kb
Host smart-bb65b682-84f9-45b7-a8f7-ea12771736c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22701
60859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.2270160859
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1206152782
Short name T202
Test name
Test status
Simulation time 8405973126 ps
CPU time 8.26 seconds
Started May 07 12:42:14 PM PDT 24
Finished May 07 12:42:24 PM PDT 24
Peak memory 204084 kb
Host smart-41687d62-2c7e-4c88-8a08-1198f9e39949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12061
52782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1206152782
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4108258773
Short name T155
Test name
Test status
Simulation time 8389243021 ps
CPU time 7.92 seconds
Started May 07 12:42:04 PM PDT 24
Finished May 07 12:42:14 PM PDT 24
Peak memory 204120 kb
Host smart-54d59b6c-334a-4bc4-bc4e-454a461dea81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41082
58773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4108258773
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3757745246
Short name T303
Test name
Test status
Simulation time 8419076662 ps
CPU time 8.09 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:05 PM PDT 24
Peak memory 204120 kb
Host smart-9def5b90-c2f7-4ef4-9f3a-9914baac4e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37577
45246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3757745246
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1416483892
Short name T998
Test name
Test status
Simulation time 8374850574 ps
CPU time 7.68 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:05 PM PDT 24
Peak memory 204104 kb
Host smart-11e596a6-bd8c-4c5f-8421-d74c048e5d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14164
83892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1416483892
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3400464229
Short name T578
Test name
Test status
Simulation time 8393358262 ps
CPU time 8.68 seconds
Started May 07 12:42:09 PM PDT 24
Finished May 07 12:42:19 PM PDT 24
Peak memory 204112 kb
Host smart-dc0e52cc-1e1d-469e-93b6-2e5304a1c80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34004
64229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3400464229
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.4271289929
Short name T569
Test name
Test status
Simulation time 8387803089 ps
CPU time 7.91 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:09 PM PDT 24
Peak memory 204128 kb
Host smart-a6e123f8-1090-4680-baf9-250efd6a3c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42712
89929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.4271289929
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3938402642
Short name T1363
Test name
Test status
Simulation time 8412367065 ps
CPU time 7.42 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:04 PM PDT 24
Peak memory 204112 kb
Host smart-a07db032-1712-45c0-bb67-520cabccfa1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39384
02642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3938402642
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3928734085
Short name T665
Test name
Test status
Simulation time 8370454292 ps
CPU time 7.65 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204104 kb
Host smart-7ff759d9-9dc7-488f-9ac1-941e3d389fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39287
34085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3928734085
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.966183547
Short name T887
Test name
Test status
Simulation time 46961968 ps
CPU time 0.66 seconds
Started May 07 12:42:20 PM PDT 24
Finished May 07 12:42:21 PM PDT 24
Peak memory 203980 kb
Host smart-7db493af-e3be-4cdb-a1a8-06b402b42c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96618
3547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.966183547
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3703921062
Short name T847
Test name
Test status
Simulation time 8415478109 ps
CPU time 7.73 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:05 PM PDT 24
Peak memory 204124 kb
Host smart-445a8a15-2e18-41c1-a431-956c375f1700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37039
21062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3703921062
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.2784972114
Short name T1306
Test name
Test status
Simulation time 8414643310 ps
CPU time 7.6 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204160 kb
Host smart-8a09ebb5-d1c3-4569-9335-df9bbdcedc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27849
72114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.2784972114
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3674526515
Short name T2
Test name
Test status
Simulation time 8387370091 ps
CPU time 8.93 seconds
Started May 07 12:42:03 PM PDT 24
Finished May 07 12:42:13 PM PDT 24
Peak memory 204112 kb
Host smart-1f2a7e51-0ba6-49b9-9ff7-051b76c4841b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36745
26515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3674526515
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.4226889289
Short name T383
Test name
Test status
Simulation time 8403023923 ps
CPU time 7.66 seconds
Started May 07 12:42:07 PM PDT 24
Finished May 07 12:42:16 PM PDT 24
Peak memory 204100 kb
Host smart-146d6d82-c7e1-45ae-843d-aa28dcc27d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42268
89289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.4226889289
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.274850298
Short name T1314
Test name
Test status
Simulation time 8424230465 ps
CPU time 7.85 seconds
Started May 07 12:42:04 PM PDT 24
Finished May 07 12:42:14 PM PDT 24
Peak memory 204136 kb
Host smart-f7ecc1ae-78ff-484a-85bf-7e2254925bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27485
0298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.274850298
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1684489531
Short name T139
Test name
Test status
Simulation time 8429947504 ps
CPU time 7.5 seconds
Started May 07 12:42:12 PM PDT 24
Finished May 07 12:42:21 PM PDT 24
Peak memory 204096 kb
Host smart-c124aaa7-4a2f-4e2e-a62a-7ab5761670e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16844
89531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1684489531
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2289023083
Short name T312
Test name
Test status
Simulation time 8383162890 ps
CPU time 8.92 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:05 PM PDT 24
Peak memory 204100 kb
Host smart-ae372545-1c2e-450b-bff5-7695d86cc8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22890
23083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2289023083
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.1851851311
Short name T1232
Test name
Test status
Simulation time 8469395518 ps
CPU time 8.22 seconds
Started May 07 12:42:24 PM PDT 24
Finished May 07 12:42:34 PM PDT 24
Peak memory 204084 kb
Host smart-a9aeed0d-7fa2-4799-b6c9-02d58a1ab17c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1851851311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.1851851311
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.1619008509
Short name T1327
Test name
Test status
Simulation time 8383323897 ps
CPU time 8 seconds
Started May 07 12:42:22 PM PDT 24
Finished May 07 12:42:31 PM PDT 24
Peak memory 204092 kb
Host smart-d4143de9-4535-4d45-884e-84194296ad59
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1619008509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.1619008509
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.1754868693
Short name T330
Test name
Test status
Simulation time 8432234843 ps
CPU time 7.72 seconds
Started May 07 12:42:16 PM PDT 24
Finished May 07 12:42:25 PM PDT 24
Peak memory 204116 kb
Host smart-5f75d727-76c9-4656-95ab-c5df6045af60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17548
68693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.1754868693
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.834661573
Short name T910
Test name
Test status
Simulation time 8388495560 ps
CPU time 8.34 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204172 kb
Host smart-1a39d41d-2ef0-49c2-822f-4f86b7797976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83466
1573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.834661573
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.1420384547
Short name T654
Test name
Test status
Simulation time 8399492959 ps
CPU time 7.94 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 204108 kb
Host smart-c213dc26-eef5-4d01-8026-7a0ed8b2fc22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14203
84547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1420384547
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3449634974
Short name T986
Test name
Test status
Simulation time 55535644 ps
CPU time 1.01 seconds
Started May 07 12:42:15 PM PDT 24
Finished May 07 12:42:17 PM PDT 24
Peak memory 204248 kb
Host smart-76ac0a61-8f03-4287-8e8e-bbb6e9ca0104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34496
34974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3449634974
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.154046373
Short name T143
Test name
Test status
Simulation time 8384728068 ps
CPU time 8.44 seconds
Started May 07 12:42:17 PM PDT 24
Finished May 07 12:42:27 PM PDT 24
Peak memory 204120 kb
Host smart-2b731e09-1645-4ef6-b776-74553c6d2f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
6373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.154046373
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2054747901
Short name T565
Test name
Test status
Simulation time 8369497053 ps
CPU time 7.95 seconds
Started May 07 12:42:15 PM PDT 24
Finished May 07 12:42:25 PM PDT 24
Peak memory 204112 kb
Host smart-4b007f14-9751-4d86-a626-4f05d0ff3ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20547
47901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2054747901
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3251189061
Short name T856
Test name
Test status
Simulation time 8475107019 ps
CPU time 10.56 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:10 PM PDT 24
Peak memory 204128 kb
Host smart-612e2261-ce36-41f7-879c-da50dc1f22f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32511
89061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3251189061
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3461197434
Short name T1042
Test name
Test status
Simulation time 8413373264 ps
CPU time 7.86 seconds
Started May 07 12:42:21 PM PDT 24
Finished May 07 12:42:30 PM PDT 24
Peak memory 204104 kb
Host smart-c9038116-4f46-44da-a34e-945a52173dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34611
97434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3461197434
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.920149272
Short name T681
Test name
Test status
Simulation time 8369340001 ps
CPU time 7.92 seconds
Started May 07 12:42:13 PM PDT 24
Finished May 07 12:42:23 PM PDT 24
Peak memory 204144 kb
Host smart-9a551caa-f2b7-41cc-82ff-07b2e740b834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92014
9272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.920149272
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2434233560
Short name T116
Test name
Test status
Simulation time 8448639792 ps
CPU time 9.12 seconds
Started May 07 12:42:25 PM PDT 24
Finished May 07 12:42:36 PM PDT 24
Peak memory 204092 kb
Host smart-9c870cac-008b-43cc-a0da-dff836b6caee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24342
33560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2434233560
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1523786744
Short name T227
Test name
Test status
Simulation time 8388261040 ps
CPU time 8.2 seconds
Started May 07 12:42:14 PM PDT 24
Finished May 07 12:42:24 PM PDT 24
Peak memory 204084 kb
Host smart-f45daa8a-9732-449f-850e-01d31b435ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15237
86744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1523786744
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.864749376
Short name T827
Test name
Test status
Simulation time 8384029460 ps
CPU time 8.17 seconds
Started May 07 12:42:24 PM PDT 24
Finished May 07 12:42:33 PM PDT 24
Peak memory 204088 kb
Host smart-f982bfef-8cce-42c8-95bd-fb5d561be866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86474
9376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.864749376
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3677839148
Short name T56
Test name
Test status
Simulation time 8387807792 ps
CPU time 8.51 seconds
Started May 07 12:42:10 PM PDT 24
Finished May 07 12:42:20 PM PDT 24
Peak memory 204124 kb
Host smart-72c1ba2a-e19a-4b1f-b708-89651317ac04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36778
39148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3677839148
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.87473732
Short name T518
Test name
Test status
Simulation time 8374632647 ps
CPU time 10.07 seconds
Started May 07 12:42:26 PM PDT 24
Finished May 07 12:42:37 PM PDT 24
Peak memory 204120 kb
Host smart-bb37af15-284f-4d65-af9b-9f2891faa192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87473
732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.87473732
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3303160893
Short name T1090
Test name
Test status
Simulation time 35575722 ps
CPU time 0.63 seconds
Started May 07 12:42:14 PM PDT 24
Finished May 07 12:42:17 PM PDT 24
Peak memory 203980 kb
Host smart-87100b6b-356a-411f-adeb-cb79c622b4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33031
60893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3303160893
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.3285606209
Short name T443
Test name
Test status
Simulation time 8402092871 ps
CPU time 7.75 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:03 PM PDT 24
Peak memory 204076 kb
Host smart-4341ebbf-d08f-4557-9c11-5c1cb544afb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32856
06209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3285606209
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3764125488
Short name T959
Test name
Test status
Simulation time 8393799803 ps
CPU time 7.97 seconds
Started May 07 12:42:10 PM PDT 24
Finished May 07 12:42:19 PM PDT 24
Peak memory 204120 kb
Host smart-e3956292-0545-4082-b2ee-12c322c68f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37641
25488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3764125488
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.102816101
Short name T1211
Test name
Test status
Simulation time 8411151883 ps
CPU time 8.89 seconds
Started May 07 12:42:11 PM PDT 24
Finished May 07 12:42:22 PM PDT 24
Peak memory 204124 kb
Host smart-da651e29-4825-48e5-bc51-01bd018606b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10281
6101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.102816101
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.210437319
Short name T1163
Test name
Test status
Simulation time 8387631193 ps
CPU time 8.05 seconds
Started May 07 12:42:10 PM PDT 24
Finished May 07 12:42:19 PM PDT 24
Peak memory 204116 kb
Host smart-76dddb80-d1ed-49ef-8fab-6d413d879031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21043
7319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.210437319
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1646962475
Short name T1375
Test name
Test status
Simulation time 8378843170 ps
CPU time 9.86 seconds
Started May 07 12:42:11 PM PDT 24
Finished May 07 12:42:23 PM PDT 24
Peak memory 204092 kb
Host smart-73956ec8-af33-4925-93c6-934daec49a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16469
62475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1646962475
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3347646578
Short name T1379
Test name
Test status
Simulation time 8406297481 ps
CPU time 8.51 seconds
Started May 07 12:42:14 PM PDT 24
Finished May 07 12:42:25 PM PDT 24
Peak memory 204136 kb
Host smart-4b352bd7-cf7e-4052-90df-7ef021a32752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33476
46578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3347646578
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3735694379
Short name T1261
Test name
Test status
Simulation time 8423218219 ps
CPU time 8.12 seconds
Started May 07 12:41:57 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 204128 kb
Host smart-6356e276-5f02-4dd4-aa17-a2d91b66d2df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37356
94379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3735694379
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2779975005
Short name T1279
Test name
Test status
Simulation time 8395239731 ps
CPU time 9.97 seconds
Started May 07 12:42:10 PM PDT 24
Finished May 07 12:42:22 PM PDT 24
Peak memory 204100 kb
Host smart-10fe237f-cc98-4af7-ba5c-b12f1b5ad749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27799
75005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2779975005
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.2239031780
Short name T945
Test name
Test status
Simulation time 8527812945 ps
CPU time 9.24 seconds
Started May 07 12:42:21 PM PDT 24
Finished May 07 12:42:31 PM PDT 24
Peak memory 204068 kb
Host smart-717b1add-1bf4-4e91-954a-ed1989968a43
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2239031780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.2239031780
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.2454496516
Short name T1302
Test name
Test status
Simulation time 8374641380 ps
CPU time 8.59 seconds
Started May 07 12:42:23 PM PDT 24
Finished May 07 12:42:33 PM PDT 24
Peak memory 204128 kb
Host smart-21667418-7fe5-4b95-97d9-e15752aa43e0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2454496516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.2454496516
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.3353582271
Short name T1189
Test name
Test status
Simulation time 8419125558 ps
CPU time 8.36 seconds
Started May 07 12:42:12 PM PDT 24
Finished May 07 12:42:22 PM PDT 24
Peak memory 204108 kb
Host smart-b20b9c2a-251e-4be8-8aaf-c8ce9e7869f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33535
82271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.3353582271
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2082628688
Short name T329
Test name
Test status
Simulation time 8397435985 ps
CPU time 7.73 seconds
Started May 07 12:42:18 PM PDT 24
Finished May 07 12:42:27 PM PDT 24
Peak memory 204124 kb
Host smart-c6cb5821-c520-407c-9ca0-c61127c2be7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20826
28688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2082628688
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.3018737232
Short name T557
Test name
Test status
Simulation time 8374751671 ps
CPU time 9 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:09 PM PDT 24
Peak memory 204112 kb
Host smart-d2812c70-a09c-443d-8618-1dbc0037cac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30187
37232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3018737232
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3818779149
Short name T420
Test name
Test status
Simulation time 194882177 ps
CPU time 2.16 seconds
Started May 07 12:42:12 PM PDT 24
Finished May 07 12:42:17 PM PDT 24
Peak memory 204200 kb
Host smart-7b506400-e377-4c13-b181-f46459b33cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38187
79149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3818779149
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2834362330
Short name T991
Test name
Test status
Simulation time 8481664998 ps
CPU time 8.94 seconds
Started May 07 12:42:32 PM PDT 24
Finished May 07 12:42:44 PM PDT 24
Peak memory 204004 kb
Host smart-c758688b-74cf-463b-bee1-2647237fec3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28343
62330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2834362330
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.752010936
Short name T1039
Test name
Test status
Simulation time 8363944296 ps
CPU time 10.14 seconds
Started May 07 12:42:13 PM PDT 24
Finished May 07 12:42:25 PM PDT 24
Peak memory 204116 kb
Host smart-74f4a232-247a-4af7-ac68-0f890749401d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75201
0936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.752010936
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2919357109
Short name T396
Test name
Test status
Simulation time 8465249724 ps
CPU time 8.36 seconds
Started May 07 12:42:10 PM PDT 24
Finished May 07 12:42:19 PM PDT 24
Peak memory 204208 kb
Host smart-63c1368c-a26f-4b46-9caf-4d34a13e7142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29193
57109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2919357109
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3682178820
Short name T705
Test name
Test status
Simulation time 8431052998 ps
CPU time 8.15 seconds
Started May 07 12:42:30 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 204140 kb
Host smart-315076d3-10c9-4cd4-a4b7-03000b018df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36821
78820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3682178820
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.517073161
Short name T942
Test name
Test status
Simulation time 8383878630 ps
CPU time 8.37 seconds
Started May 07 12:42:14 PM PDT 24
Finished May 07 12:42:25 PM PDT 24
Peak memory 204156 kb
Host smart-8d43dd76-d51f-4b14-9b7b-e6ca88680917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51707
3161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.517073161
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2683716444
Short name T131
Test name
Test status
Simulation time 8428731231 ps
CPU time 7.32 seconds
Started May 07 12:42:10 PM PDT 24
Finished May 07 12:42:19 PM PDT 24
Peak memory 204084 kb
Host smart-b31712d6-2ab3-47ee-9a77-f462edd0e1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26837
16444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2683716444
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.4097023246
Short name T553
Test name
Test status
Simulation time 8383756417 ps
CPU time 8.05 seconds
Started May 07 12:42:10 PM PDT 24
Finished May 07 12:42:19 PM PDT 24
Peak memory 204116 kb
Host smart-b3230642-528c-4815-98a3-22cc5271eae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40970
23246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.4097023246
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3329495781
Short name T923
Test name
Test status
Simulation time 8399276141 ps
CPU time 7.41 seconds
Started May 07 12:42:23 PM PDT 24
Finished May 07 12:42:31 PM PDT 24
Peak memory 204084 kb
Host smart-133b978e-c587-4d14-9932-cd9c2309e998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33294
95781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3329495781
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2529672902
Short name T617
Test name
Test status
Simulation time 8410373602 ps
CPU time 10.33 seconds
Started May 07 12:42:23 PM PDT 24
Finished May 07 12:42:34 PM PDT 24
Peak memory 204084 kb
Host smart-dc4f1d37-43d3-4c62-8126-21f3c1cf630d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25296
72902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2529672902
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.2081562224
Short name T419
Test name
Test status
Simulation time 8374417254 ps
CPU time 8.3 seconds
Started May 07 12:42:20 PM PDT 24
Finished May 07 12:42:29 PM PDT 24
Peak memory 204100 kb
Host smart-6cacaeec-72ca-476c-9597-b9d5111b2598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20815
62224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.2081562224
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3328795664
Short name T1008
Test name
Test status
Simulation time 59956240 ps
CPU time 0.74 seconds
Started May 07 12:42:27 PM PDT 24
Finished May 07 12:42:29 PM PDT 24
Peak memory 203976 kb
Host smart-ce0d959b-9aeb-447b-a3a1-409284fc8d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33287
95664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3328795664
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2814378064
Short name T95
Test name
Test status
Simulation time 28247414783 ps
CPU time 56.24 seconds
Started May 07 12:42:18 PM PDT 24
Finished May 07 12:43:15 PM PDT 24
Peak memory 204400 kb
Host smart-fabe8989-f224-44b0-a45f-bd64b3d14f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28143
78064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2814378064
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1028251246
Short name T810
Test name
Test status
Simulation time 8370367584 ps
CPU time 7.88 seconds
Started May 07 12:42:13 PM PDT 24
Finished May 07 12:42:23 PM PDT 24
Peak memory 204116 kb
Host smart-5588bdc1-7fe2-47a4-ae88-7ef3f55234e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10282
51246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1028251246
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1066195467
Short name T622
Test name
Test status
Simulation time 8404132976 ps
CPU time 8.2 seconds
Started May 07 12:42:22 PM PDT 24
Finished May 07 12:42:31 PM PDT 24
Peak memory 204096 kb
Host smart-b8198ddf-f29d-41a2-8841-ee565375c502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10661
95467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1066195467
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.1452711143
Short name T347
Test name
Test status
Simulation time 8394143675 ps
CPU time 8.91 seconds
Started May 07 12:42:11 PM PDT 24
Finished May 07 12:42:22 PM PDT 24
Peak memory 204032 kb
Host smart-f6f50d78-ee1f-4cf5-b973-3eb2d2b0320e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14527
11143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.1452711143
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1716271017
Short name T46
Test name
Test status
Simulation time 8377943007 ps
CPU time 10.13 seconds
Started May 07 12:42:18 PM PDT 24
Finished May 07 12:42:30 PM PDT 24
Peak memory 203640 kb
Host smart-47ce7233-4908-43cd-a227-6659b00c2411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17162
71017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1716271017
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3754077069
Short name T1179
Test name
Test status
Simulation time 8368334986 ps
CPU time 7.95 seconds
Started May 07 12:42:10 PM PDT 24
Finished May 07 12:42:19 PM PDT 24
Peak memory 204092 kb
Host smart-b51cefe0-372f-4ae4-b4ba-e5b473c7e7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37540
77069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3754077069
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.586439153
Short name T92
Test name
Test status
Simulation time 8432099739 ps
CPU time 9.17 seconds
Started May 07 12:42:15 PM PDT 24
Finished May 07 12:42:26 PM PDT 24
Peak memory 204016 kb
Host smart-8cd5131b-3f68-447d-922c-1d49fcddbfcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58643
9153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.586439153
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2770628682
Short name T610
Test name
Test status
Simulation time 8456967948 ps
CPU time 8 seconds
Started May 07 12:42:17 PM PDT 24
Finished May 07 12:42:26 PM PDT 24
Peak memory 204140 kb
Host smart-d51ed6f8-8045-43be-b6a5-acc52cc4d6cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27706
28682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2770628682
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.441211551
Short name T903
Test name
Test status
Simulation time 8383569835 ps
CPU time 7.93 seconds
Started May 07 12:42:21 PM PDT 24
Finished May 07 12:42:31 PM PDT 24
Peak memory 204104 kb
Host smart-26cb2d8a-4e47-4057-8928-7ed97f2a4e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44121
1551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.441211551
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.2857342900
Short name T440
Test name
Test status
Simulation time 8465360084 ps
CPU time 9.43 seconds
Started May 07 12:42:26 PM PDT 24
Finished May 07 12:42:37 PM PDT 24
Peak memory 204028 kb
Host smart-40f6f5e6-5713-4919-988a-f64938a0d236
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2857342900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.2857342900
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.1565981819
Short name T157
Test name
Test status
Simulation time 8382503685 ps
CPU time 8.43 seconds
Started May 07 12:42:19 PM PDT 24
Finished May 07 12:42:29 PM PDT 24
Peak memory 204100 kb
Host smart-9383ddfb-aa7c-4783-a92e-e21856d7876f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1565981819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.1565981819
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.2564447810
Short name T730
Test name
Test status
Simulation time 8448647717 ps
CPU time 9.12 seconds
Started May 07 12:42:29 PM PDT 24
Finished May 07 12:42:39 PM PDT 24
Peak memory 204112 kb
Host smart-fa1f8c33-9455-42d8-987f-0d8975670e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25644
47810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.2564447810
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2413814645
Short name T519
Test name
Test status
Simulation time 8385462899 ps
CPU time 9.45 seconds
Started May 07 12:42:11 PM PDT 24
Finished May 07 12:42:23 PM PDT 24
Peak memory 204084 kb
Host smart-96b06716-39d4-41d5-b269-88a49c93b268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24138
14645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2413814645
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.2367289740
Short name T446
Test name
Test status
Simulation time 8374313130 ps
CPU time 7.72 seconds
Started May 07 12:42:28 PM PDT 24
Finished May 07 12:42:37 PM PDT 24
Peak memory 204024 kb
Host smart-27154c68-3b80-4158-8605-e5d927cd6b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23672
89740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2367289740
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.277322875
Short name T53
Test name
Test status
Simulation time 60075505 ps
CPU time 1.55 seconds
Started May 07 12:42:21 PM PDT 24
Finished May 07 12:42:24 PM PDT 24
Peak memory 204192 kb
Host smart-008a3b13-8e2f-4fbb-beea-d94da2c58377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27732
2875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.277322875
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2453164020
Short name T50
Test name
Test status
Simulation time 8486851363 ps
CPU time 8.31 seconds
Started May 07 12:42:25 PM PDT 24
Finished May 07 12:42:34 PM PDT 24
Peak memory 204112 kb
Host smart-b464e292-ce87-4ca4-8e8f-f637f08b5d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24531
64020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2453164020
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1003444926
Short name T1268
Test name
Test status
Simulation time 8385160330 ps
CPU time 8.47 seconds
Started May 07 12:42:32 PM PDT 24
Finished May 07 12:42:43 PM PDT 24
Peak memory 204012 kb
Host smart-734e64ec-025c-43e1-b5f1-65647826cc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10034
44926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1003444926
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.77257189
Short name T916
Test name
Test status
Simulation time 8458904692 ps
CPU time 10.47 seconds
Started May 07 12:42:15 PM PDT 24
Finished May 07 12:42:27 PM PDT 24
Peak memory 204084 kb
Host smart-fdeedc72-f3f7-426a-a430-ee0486e6f96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77257
189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.77257189
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1025091556
Short name T479
Test name
Test status
Simulation time 8441887268 ps
CPU time 7.94 seconds
Started May 07 12:42:26 PM PDT 24
Finished May 07 12:42:36 PM PDT 24
Peak memory 204124 kb
Host smart-03bf752d-c916-4c7e-9b00-5b7ec9797579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10250
91556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1025091556
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1949306611
Short name T608
Test name
Test status
Simulation time 8389536185 ps
CPU time 8.45 seconds
Started May 07 12:42:23 PM PDT 24
Finished May 07 12:42:33 PM PDT 24
Peak memory 204140 kb
Host smart-28d63407-e27c-4763-823e-28210dc81b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19493
06611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1949306611
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2075188778
Short name T893
Test name
Test status
Simulation time 8459257181 ps
CPU time 8.4 seconds
Started May 07 12:42:22 PM PDT 24
Finished May 07 12:42:31 PM PDT 24
Peak memory 204120 kb
Host smart-fa8da7ad-2228-4a6a-8390-11e9ab2197db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20751
88778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2075188778
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1611341288
Short name T14
Test name
Test status
Simulation time 8382168886 ps
CPU time 9.84 seconds
Started May 07 12:42:16 PM PDT 24
Finished May 07 12:42:27 PM PDT 24
Peak memory 204056 kb
Host smart-0234288d-4326-4226-9838-57dc948fe0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16113
41288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1611341288
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2216004237
Short name T634
Test name
Test status
Simulation time 8470667173 ps
CPU time 9.84 seconds
Started May 07 12:42:29 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 204128 kb
Host smart-dc73b2d7-003a-47c1-8f11-80e575968c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22160
04237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2216004237
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.122013421
Short name T1073
Test name
Test status
Simulation time 8472187514 ps
CPU time 10.16 seconds
Started May 07 12:42:12 PM PDT 24
Finished May 07 12:42:25 PM PDT 24
Peak memory 204100 kb
Host smart-cb431a10-dd1d-493e-9ffc-dd054889e250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12201
3421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.122013421
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3390439839
Short name T1173
Test name
Test status
Simulation time 8360794099 ps
CPU time 7.7 seconds
Started May 07 12:42:20 PM PDT 24
Finished May 07 12:42:28 PM PDT 24
Peak memory 204088 kb
Host smart-0bb99716-df42-4ff1-9937-a3353b1ba408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33904
39839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3390439839
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1782583144
Short name T1204
Test name
Test status
Simulation time 77025180 ps
CPU time 0.75 seconds
Started May 07 12:42:13 PM PDT 24
Finished May 07 12:42:16 PM PDT 24
Peak memory 203944 kb
Host smart-86926e0e-9a1e-4fae-a679-9501c062d4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17825
83144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1782583144
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1312029556
Short name T214
Test name
Test status
Simulation time 23980711023 ps
CPU time 43.43 seconds
Started May 07 12:42:25 PM PDT 24
Finished May 07 12:43:09 PM PDT 24
Peak memory 204420 kb
Host smart-85134940-9967-4faf-804d-adb5da7339b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13120
29556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1312029556
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.155201650
Short name T1317
Test name
Test status
Simulation time 8410571192 ps
CPU time 8.22 seconds
Started May 07 12:42:11 PM PDT 24
Finished May 07 12:42:21 PM PDT 24
Peak memory 204120 kb
Host smart-07016d42-3291-4d21-98a9-d90ef59f5d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15520
1650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.155201650
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1694045121
Short name T943
Test name
Test status
Simulation time 8446613702 ps
CPU time 8.99 seconds
Started May 07 12:42:13 PM PDT 24
Finished May 07 12:42:24 PM PDT 24
Peak memory 204096 kb
Host smart-b406e0a2-f625-4c67-bdb1-54f677d84811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16940
45121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1694045121
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.1449173358
Short name T473
Test name
Test status
Simulation time 8402209655 ps
CPU time 7.89 seconds
Started May 07 12:42:30 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 204136 kb
Host smart-993328f5-54f0-4640-88a4-6672f2e4389a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14491
73358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.1449173358
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2134293470
Short name T1316
Test name
Test status
Simulation time 8397024453 ps
CPU time 8.18 seconds
Started May 07 12:42:17 PM PDT 24
Finished May 07 12:42:26 PM PDT 24
Peak memory 204112 kb
Host smart-b7034b20-43ab-4e6a-9d17-66182abdf5ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21342
93470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2134293470
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2603355794
Short name T1330
Test name
Test status
Simulation time 8391665580 ps
CPU time 7.68 seconds
Started May 07 12:42:23 PM PDT 24
Finished May 07 12:42:32 PM PDT 24
Peak memory 204100 kb
Host smart-07a441a9-822a-4acd-aa83-3095b1bf3a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26033
55794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2603355794
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3295242650
Short name T1249
Test name
Test status
Simulation time 8445948225 ps
CPU time 8.61 seconds
Started May 07 12:42:24 PM PDT 24
Finished May 07 12:42:34 PM PDT 24
Peak memory 204124 kb
Host smart-bed65338-57cf-4b65-901c-d8665ba08d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32952
42650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3295242650
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.4247146620
Short name T297
Test name
Test status
Simulation time 8383599748 ps
CPU time 8.38 seconds
Started May 07 12:42:18 PM PDT 24
Finished May 07 12:42:28 PM PDT 24
Peak memory 204128 kb
Host smart-731037b2-a51a-4204-b100-1d579f3506cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42471
46620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.4247146620
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.312970351
Short name T824
Test name
Test status
Simulation time 8400920397 ps
CPU time 7.42 seconds
Started May 07 12:42:25 PM PDT 24
Finished May 07 12:42:33 PM PDT 24
Peak memory 204084 kb
Host smart-bd46b3d6-7856-4361-8c7a-b1923f20fef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31297
0351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.312970351
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.2231019846
Short name T1296
Test name
Test status
Simulation time 8469102445 ps
CPU time 9.89 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204132 kb
Host smart-fb42c308-b5d8-47e0-8451-29acfb03ad8e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2231019846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.2231019846
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.1771801819
Short name T597
Test name
Test status
Simulation time 8387112680 ps
CPU time 8.73 seconds
Started May 07 12:41:17 PM PDT 24
Finished May 07 12:41:27 PM PDT 24
Peak memory 204120 kb
Host smart-e77ec355-e96c-46f0-a24f-eb199127a724
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1771801819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.1771801819
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.2752698334
Short name T1321
Test name
Test status
Simulation time 8444709471 ps
CPU time 8.34 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204132 kb
Host smart-e5cd16b7-d863-4cff-b7e8-8e449ed77a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27526
98334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.2752698334
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.691459734
Short name T867
Test name
Test status
Simulation time 8374780430 ps
CPU time 8 seconds
Started May 07 12:41:23 PM PDT 24
Finished May 07 12:41:32 PM PDT 24
Peak memory 204080 kb
Host smart-346e83f9-a724-4757-8caa-9d4fce4503c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69145
9734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.691459734
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.1190981192
Short name T450
Test name
Test status
Simulation time 8378864669 ps
CPU time 8.26 seconds
Started May 07 12:41:11 PM PDT 24
Finished May 07 12:41:21 PM PDT 24
Peak memory 204084 kb
Host smart-8615d5ad-9407-4fc0-a065-e2ee62ee2035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11909
81192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1190981192
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2241951970
Short name T1350
Test name
Test status
Simulation time 204711885 ps
CPU time 2.2 seconds
Started May 07 12:41:21 PM PDT 24
Finished May 07 12:41:24 PM PDT 24
Peak memory 204164 kb
Host smart-cd7bcff4-b4ce-4704-bffb-684560c45644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22419
51970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2241951970
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.4017242120
Short name T1059
Test name
Test status
Simulation time 8420925136 ps
CPU time 9.72 seconds
Started May 07 12:41:21 PM PDT 24
Finished May 07 12:41:31 PM PDT 24
Peak memory 204172 kb
Host smart-ffcc8357-375c-4a16-b4d3-22d6413118db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40172
42120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.4017242120
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3398507728
Short name T204
Test name
Test status
Simulation time 8368735079 ps
CPU time 7.51 seconds
Started May 07 12:41:23 PM PDT 24
Finished May 07 12:41:32 PM PDT 24
Peak memory 204012 kb
Host smart-9b76ad92-2bc6-48af-9218-fb0e11c47e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33985
07728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3398507728
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2207559436
Short name T1205
Test name
Test status
Simulation time 8394138608 ps
CPU time 10.25 seconds
Started May 07 12:41:01 PM PDT 24
Finished May 07 12:41:15 PM PDT 24
Peak memory 204128 kb
Host smart-3e4afd06-0abf-44aa-91ba-4f56466d8d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22075
59436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2207559436
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2166104038
Short name T1055
Test name
Test status
Simulation time 8416548015 ps
CPU time 8.11 seconds
Started May 07 12:41:15 PM PDT 24
Finished May 07 12:41:24 PM PDT 24
Peak memory 204156 kb
Host smart-6c5e497a-70b7-42a7-99d2-556d68b3b4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21661
04038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2166104038
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.713759502
Short name T583
Test name
Test status
Simulation time 8371936233 ps
CPU time 7.58 seconds
Started May 07 12:41:21 PM PDT 24
Finished May 07 12:41:30 PM PDT 24
Peak memory 204156 kb
Host smart-e318732a-1cff-41b0-a90c-01cba16b615c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71375
9502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.713759502
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3845889330
Short name T371
Test name
Test status
Simulation time 8371355915 ps
CPU time 8.87 seconds
Started May 07 12:41:08 PM PDT 24
Finished May 07 12:41:19 PM PDT 24
Peak memory 204116 kb
Host smart-38669344-7c09-4550-8431-375929246b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38458
89330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3845889330
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2102999055
Short name T765
Test name
Test status
Simulation time 8394888634 ps
CPU time 8.12 seconds
Started May 07 12:41:03 PM PDT 24
Finished May 07 12:41:15 PM PDT 24
Peak memory 204076 kb
Host smart-d54fc17f-5011-4d46-bd35-7654be371316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21029
99055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2102999055
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2260618254
Short name T530
Test name
Test status
Simulation time 8400264996 ps
CPU time 9.97 seconds
Started May 07 12:41:23 PM PDT 24
Finished May 07 12:41:33 PM PDT 24
Peak memory 204080 kb
Host smart-848e7c18-2b90-4237-98c8-7327ab57303c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22606
18254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2260618254
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2781904303
Short name T1031
Test name
Test status
Simulation time 8368164260 ps
CPU time 9.62 seconds
Started May 07 12:41:30 PM PDT 24
Finished May 07 12:41:40 PM PDT 24
Peak memory 204164 kb
Host smart-cb8b0fd9-c912-42cb-8f95-44ae6bfdae87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27819
04303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2781904303
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3496040615
Short name T1022
Test name
Test status
Simulation time 39639160 ps
CPU time 0.69 seconds
Started May 07 12:41:30 PM PDT 24
Finished May 07 12:41:32 PM PDT 24
Peak memory 203992 kb
Host smart-6b33a1f4-50c9-4c5a-98bc-c29160529f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34960
40615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3496040615
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3449603397
Short name T1149
Test name
Test status
Simulation time 30283776928 ps
CPU time 55.54 seconds
Started May 07 12:41:03 PM PDT 24
Finished May 07 12:42:02 PM PDT 24
Peak memory 204308 kb
Host smart-e91c3db3-40a4-4600-b2c4-a0e78138bb41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34496
03397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3449603397
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3965138127
Short name T976
Test name
Test status
Simulation time 8416090488 ps
CPU time 8.77 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:15 PM PDT 24
Peak memory 204104 kb
Host smart-82a17753-0be0-407c-a898-c23b396d45b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39651
38127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3965138127
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1150372838
Short name T742
Test name
Test status
Simulation time 8427532383 ps
CPU time 8.77 seconds
Started May 07 12:41:01 PM PDT 24
Finished May 07 12:41:14 PM PDT 24
Peak memory 204140 kb
Host smart-346af99e-6c59-4018-bb29-e4fd8878c382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11503
72838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1150372838
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.1576393626
Short name T1240
Test name
Test status
Simulation time 8410666938 ps
CPU time 8.23 seconds
Started May 07 12:41:02 PM PDT 24
Finished May 07 12:41:14 PM PDT 24
Peak memory 204100 kb
Host smart-0ddb5fd8-187d-4a21-a8b0-9b647a2a68bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15763
93626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.1576393626
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1696110133
Short name T77
Test name
Test status
Simulation time 612427627 ps
CPU time 1.41 seconds
Started May 07 12:41:36 PM PDT 24
Finished May 07 12:41:40 PM PDT 24
Peak memory 220280 kb
Host smart-c0aa7a56-8ef8-4117-a311-4843e5940a59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1696110133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1696110133
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3078272443
Short name T453
Test name
Test status
Simulation time 8382711678 ps
CPU time 9.77 seconds
Started May 07 12:41:26 PM PDT 24
Finished May 07 12:41:36 PM PDT 24
Peak memory 204132 kb
Host smart-dbf30744-d00e-4397-b777-111960cddac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30782
72443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3078272443
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1751816955
Short name T1024
Test name
Test status
Simulation time 8375586208 ps
CPU time 9.55 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:48 PM PDT 24
Peak memory 204116 kb
Host smart-091ffedc-5bff-4439-b237-ddbd837e468b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17518
16955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1751816955
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1983801222
Short name T993
Test name
Test status
Simulation time 8416593628 ps
CPU time 8.13 seconds
Started May 07 12:41:01 PM PDT 24
Finished May 07 12:41:13 PM PDT 24
Peak memory 204088 kb
Host smart-9af09c25-a5d2-4950-9573-6fef8b23fbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19838
01222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1983801222
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1163062994
Short name T533
Test name
Test status
Simulation time 8415011748 ps
CPU time 8.05 seconds
Started May 07 12:41:23 PM PDT 24
Finished May 07 12:41:33 PM PDT 24
Peak memory 204004 kb
Host smart-90322116-3cc5-459a-aa5f-8c9798c316ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11630
62994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1163062994
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2306939033
Short name T80
Test name
Test status
Simulation time 8390210568 ps
CPU time 10.19 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:46 PM PDT 24
Peak memory 204088 kb
Host smart-6171adb4-0d44-4021-aebd-8995f75953ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23069
39033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2306939033
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.3683290053
Short name T437
Test name
Test status
Simulation time 8464696090 ps
CPU time 8.38 seconds
Started May 07 12:42:28 PM PDT 24
Finished May 07 12:42:37 PM PDT 24
Peak memory 204100 kb
Host smart-a277838f-e235-4d70-acfb-f66427756268
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3683290053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.3683290053
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.863830414
Short name T630
Test name
Test status
Simulation time 8429037208 ps
CPU time 8.58 seconds
Started May 07 12:42:37 PM PDT 24
Finished May 07 12:42:47 PM PDT 24
Peak memory 204128 kb
Host smart-d8091b72-c167-47f0-9b42-00eb07fff957
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=863830414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.863830414
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.1732009002
Short name T657
Test name
Test status
Simulation time 8378421182 ps
CPU time 8.11 seconds
Started May 07 12:42:26 PM PDT 24
Finished May 07 12:42:36 PM PDT 24
Peak memory 204108 kb
Host smart-ce0216fc-172a-4d9b-8436-b7eb7dc70a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17320
09002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.1732009002
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2092308939
Short name T1276
Test name
Test status
Simulation time 8453708643 ps
CPU time 7.87 seconds
Started May 07 12:42:17 PM PDT 24
Finished May 07 12:42:26 PM PDT 24
Peak memory 204120 kb
Host smart-9055db46-daec-4481-8da0-3203411df30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20923
08939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2092308939
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.2231472504
Short name T1331
Test name
Test status
Simulation time 8383676011 ps
CPU time 9.72 seconds
Started May 07 12:42:26 PM PDT 24
Finished May 07 12:42:36 PM PDT 24
Peak memory 204076 kb
Host smart-ab54a0a5-f6c1-48c7-882a-b96de4c486d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22314
72504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.2231472504
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.851754319
Short name T718
Test name
Test status
Simulation time 152302132 ps
CPU time 1.41 seconds
Started May 07 12:42:28 PM PDT 24
Finished May 07 12:42:30 PM PDT 24
Peak memory 204188 kb
Host smart-c646533a-e251-49af-8f4c-ef931b0e50b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85175
4319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.851754319
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2101382545
Short name T550
Test name
Test status
Simulation time 8433497874 ps
CPU time 9.15 seconds
Started May 07 12:42:29 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 204124 kb
Host smart-a3c9836e-106e-4170-aa7c-883b169c80e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21013
82545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2101382545
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3382859549
Short name T659
Test name
Test status
Simulation time 8370662435 ps
CPU time 9.26 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:42 PM PDT 24
Peak memory 204116 kb
Host smart-48df08c2-b320-466f-a314-24d80b2130f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33828
59549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3382859549
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2370996367
Short name T962
Test name
Test status
Simulation time 8395626881 ps
CPU time 8.98 seconds
Started May 07 12:42:24 PM PDT 24
Finished May 07 12:42:35 PM PDT 24
Peak memory 204120 kb
Host smart-f578418c-41b6-4664-8f82-3bccf7966aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23709
96367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2370996367
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1093211029
Short name T587
Test name
Test status
Simulation time 8464064027 ps
CPU time 9.15 seconds
Started May 07 12:42:24 PM PDT 24
Finished May 07 12:42:34 PM PDT 24
Peak memory 204128 kb
Host smart-69a8f657-9ae0-485e-94bb-90f5653f637b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10932
11029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1093211029
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3029948481
Short name T967
Test name
Test status
Simulation time 8371320743 ps
CPU time 10.24 seconds
Started May 07 12:42:22 PM PDT 24
Finished May 07 12:42:33 PM PDT 24
Peak memory 204140 kb
Host smart-75bdb0ab-6dd2-4b24-87dc-78bb58d36c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30299
48481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3029948481
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.809095753
Short name T495
Test name
Test status
Simulation time 8387984573 ps
CPU time 8.99 seconds
Started May 07 12:42:26 PM PDT 24
Finished May 07 12:42:36 PM PDT 24
Peak memory 204032 kb
Host smart-1ca96ec9-7db5-4837-847d-bb10eeb13bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80909
5753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.809095753
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3719973492
Short name T1336
Test name
Test status
Simulation time 8415228372 ps
CPU time 7.85 seconds
Started May 07 12:42:26 PM PDT 24
Finished May 07 12:42:34 PM PDT 24
Peak memory 204084 kb
Host smart-a9bdd956-5e62-4dcc-b75f-fa7a8159bc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37199
73492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3719973492
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1805817027
Short name T1126
Test name
Test status
Simulation time 8414332238 ps
CPU time 8.78 seconds
Started May 07 12:42:36 PM PDT 24
Finished May 07 12:42:47 PM PDT 24
Peak memory 204132 kb
Host smart-3e1ea6ec-c001-4457-8f4e-2b8d2f1600ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18058
17027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1805817027
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1935713988
Short name T1217
Test name
Test status
Simulation time 8369165516 ps
CPU time 8.01 seconds
Started May 07 12:42:43 PM PDT 24
Finished May 07 12:42:52 PM PDT 24
Peak memory 204128 kb
Host smart-44bbef10-1165-4046-991a-b1b633b2e0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19357
13988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1935713988
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.686276460
Short name T508
Test name
Test status
Simulation time 67399309 ps
CPU time 0.7 seconds
Started May 07 12:42:26 PM PDT 24
Finished May 07 12:42:28 PM PDT 24
Peak memory 204008 kb
Host smart-720dfd2e-1b14-47c7-a9ee-b7d06441dc9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68627
6460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.686276460
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.501815744
Short name T11
Test name
Test status
Simulation time 18965726664 ps
CPU time 38.85 seconds
Started May 07 12:42:29 PM PDT 24
Finished May 07 12:43:10 PM PDT 24
Peak memory 204392 kb
Host smart-a1174463-8db5-44ff-9237-8e3ceaeaa569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50181
5744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.501815744
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3695494928
Short name T1273
Test name
Test status
Simulation time 8385926348 ps
CPU time 7.71 seconds
Started May 07 12:42:16 PM PDT 24
Finished May 07 12:42:25 PM PDT 24
Peak memory 204072 kb
Host smart-081a499f-98a5-4f22-ba5c-29fc57366703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36954
94928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3695494928
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2705486622
Short name T150
Test name
Test status
Simulation time 8438613656 ps
CPU time 9.42 seconds
Started May 07 12:42:15 PM PDT 24
Finished May 07 12:42:26 PM PDT 24
Peak memory 204116 kb
Host smart-71cd7a0b-4341-4d7d-be73-0ffb67c50665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27054
86622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2705486622
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.2018603343
Short name T639
Test name
Test status
Simulation time 8383938723 ps
CPU time 7.97 seconds
Started May 07 12:42:27 PM PDT 24
Finished May 07 12:42:36 PM PDT 24
Peak memory 204160 kb
Host smart-d0ea62cf-1c5e-4974-af04-da2e751f4bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20186
03343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.2018603343
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1035983322
Short name T1313
Test name
Test status
Simulation time 8381911415 ps
CPU time 8.01 seconds
Started May 07 12:42:14 PM PDT 24
Finished May 07 12:42:24 PM PDT 24
Peak memory 204108 kb
Host smart-d8af293d-961e-47c2-9d9e-378a8af151d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10359
83322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1035983322
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3752048160
Short name T395
Test name
Test status
Simulation time 8371433881 ps
CPU time 9.26 seconds
Started May 07 12:42:35 PM PDT 24
Finished May 07 12:42:47 PM PDT 24
Peak memory 204092 kb
Host smart-12f99c78-3796-47fb-884f-ceb3f1a74166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37520
48160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3752048160
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.390124733
Short name T148
Test name
Test status
Simulation time 8468934263 ps
CPU time 7.83 seconds
Started May 07 12:42:21 PM PDT 24
Finished May 07 12:42:30 PM PDT 24
Peak memory 204144 kb
Host smart-caa884a8-405b-4c88-b756-e4eec0e65d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39012
4733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.390124733
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.222121705
Short name T728
Test name
Test status
Simulation time 8403762458 ps
CPU time 8.07 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 204012 kb
Host smart-5cf02092-b7a3-497f-a1c0-c2c25ef33a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22212
1705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.222121705
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3229955539
Short name T18
Test name
Test status
Simulation time 8407473896 ps
CPU time 10.14 seconds
Started May 07 12:42:23 PM PDT 24
Finished May 07 12:42:35 PM PDT 24
Peak memory 204072 kb
Host smart-f1f9e988-4e39-495e-85f6-760d5c54aa65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32299
55539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3229955539
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.836744078
Short name T754
Test name
Test status
Simulation time 8478871672 ps
CPU time 7.72 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 203648 kb
Host smart-f8513649-d3d6-429c-83b4-c0216561ca25
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=836744078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.836744078
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.1062616438
Short name T881
Test name
Test status
Simulation time 8437667607 ps
CPU time 7.48 seconds
Started May 07 12:42:45 PM PDT 24
Finished May 07 12:42:53 PM PDT 24
Peak memory 204116 kb
Host smart-5782c2bf-89b4-4cd7-a930-ffdbb4a9b18f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1062616438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.1062616438
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.182889233
Short name T1004
Test name
Test status
Simulation time 8466810352 ps
CPU time 9.71 seconds
Started May 07 12:42:39 PM PDT 24
Finished May 07 12:42:50 PM PDT 24
Peak memory 204132 kb
Host smart-c9d164d8-ce07-4b2b-8d4b-05a1705b7378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18288
9233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.182889233
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.482717472
Short name T91
Test name
Test status
Simulation time 8381084924 ps
CPU time 7.67 seconds
Started May 07 12:42:44 PM PDT 24
Finished May 07 12:42:53 PM PDT 24
Peak memory 204100 kb
Host smart-43b9a90b-f0a9-45b7-8b9d-9a8c905c0170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48271
7472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.482717472
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.941812722
Short name T531
Test name
Test status
Simulation time 8377431407 ps
CPU time 7.88 seconds
Started May 07 12:42:45 PM PDT 24
Finished May 07 12:42:55 PM PDT 24
Peak memory 204136 kb
Host smart-10fccc88-6a47-449f-8cee-4b7527efd535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94181
2722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.941812722
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2613461788
Short name T928
Test name
Test status
Simulation time 129072340 ps
CPU time 1.51 seconds
Started May 07 12:42:29 PM PDT 24
Finished May 07 12:42:31 PM PDT 24
Peak memory 204228 kb
Host smart-9f023dee-2c03-4eea-90c2-9d582adce4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26134
61788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2613461788
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2345525129
Short name T520
Test name
Test status
Simulation time 8454633876 ps
CPU time 9.18 seconds
Started May 07 12:42:30 PM PDT 24
Finished May 07 12:42:42 PM PDT 24
Peak memory 204112 kb
Host smart-d44730de-3d6c-41fb-aa50-f1353911557f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23455
25129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2345525129
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3631244845
Short name T1257
Test name
Test status
Simulation time 8386521521 ps
CPU time 7.9 seconds
Started May 07 12:42:34 PM PDT 24
Finished May 07 12:42:44 PM PDT 24
Peak memory 204116 kb
Host smart-dcb59a38-ff07-43df-9e64-65230660ca9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36312
44845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3631244845
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1891627328
Short name T459
Test name
Test status
Simulation time 8420693056 ps
CPU time 8.1 seconds
Started May 07 12:42:42 PM PDT 24
Finished May 07 12:42:51 PM PDT 24
Peak memory 204148 kb
Host smart-938411c5-bb83-46b1-bb32-9584e1c6f637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18916
27328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1891627328
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1245386571
Short name T16
Test name
Test status
Simulation time 8370274792 ps
CPU time 7.58 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 204148 kb
Host smart-f6a89aa7-c36e-401d-bba0-05678ff39450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12453
86571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1245386571
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2812054067
Short name T1122
Test name
Test status
Simulation time 8403454033 ps
CPU time 9.85 seconds
Started May 07 12:42:35 PM PDT 24
Finished May 07 12:42:48 PM PDT 24
Peak memory 204088 kb
Host smart-04854466-8856-4ced-85aa-5edfccedb0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28120
54067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2812054067
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1026449721
Short name T417
Test name
Test status
Simulation time 8409636750 ps
CPU time 9.25 seconds
Started May 07 12:42:29 PM PDT 24
Finished May 07 12:42:39 PM PDT 24
Peak memory 204112 kb
Host smart-3a38d122-ff87-4e86-95d0-a31cec268719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10264
49721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1026449721
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3919937530
Short name T266
Test name
Test status
Simulation time 17742140167 ps
CPU time 34.57 seconds
Started May 07 12:42:33 PM PDT 24
Finished May 07 12:43:10 PM PDT 24
Peak memory 204360 kb
Host smart-4360f91c-119b-43ee-ab05-1fed4f3e4278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39199
37530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3919937530
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.4162441456
Short name T732
Test name
Test status
Simulation time 8417505346 ps
CPU time 9.06 seconds
Started May 07 12:42:28 PM PDT 24
Finished May 07 12:42:38 PM PDT 24
Peak memory 204112 kb
Host smart-3a8cf92c-424d-4050-a229-9454e43f5dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41624
41456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.4162441456
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1552154045
Short name T668
Test name
Test status
Simulation time 8472776004 ps
CPU time 8 seconds
Started May 07 12:42:26 PM PDT 24
Finished May 07 12:42:42 PM PDT 24
Peak memory 204096 kb
Host smart-c440b841-6e30-4a93-9351-8173145a8942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15521
54045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1552154045
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.921719817
Short name T528
Test name
Test status
Simulation time 8400582055 ps
CPU time 7.92 seconds
Started May 07 12:42:29 PM PDT 24
Finished May 07 12:42:39 PM PDT 24
Peak memory 204120 kb
Host smart-a6f00b65-01f8-4874-9d8f-47a698526089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92171
9817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.921719817
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.3600315363
Short name T1014
Test name
Test status
Simulation time 8376434255 ps
CPU time 8.42 seconds
Started May 07 12:42:33 PM PDT 24
Finished May 07 12:42:44 PM PDT 24
Peak memory 204096 kb
Host smart-916da1b8-8ac5-4f07-9f55-2cfe8c52cee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36003
15363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3600315363
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.279684188
Short name T1099
Test name
Test status
Simulation time 8364377879 ps
CPU time 7.78 seconds
Started May 07 12:42:25 PM PDT 24
Finished May 07 12:42:34 PM PDT 24
Peak memory 204104 kb
Host smart-309c59da-846b-4257-afce-f876c172f63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27968
4188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.279684188
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3913528914
Short name T855
Test name
Test status
Simulation time 8464445406 ps
CPU time 8.78 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:43 PM PDT 24
Peak memory 204124 kb
Host smart-535b5035-d0d0-46d2-9ae9-bf0fb744fdef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39135
28914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3913528914
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1462403947
Short name T949
Test name
Test status
Simulation time 8414412206 ps
CPU time 9.51 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:43 PM PDT 24
Peak memory 204140 kb
Host smart-bcdd3191-26d8-426e-8ab2-a0cf1253069e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14624
03947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1462403947
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.4255637937
Short name T481
Test name
Test status
Simulation time 8392136294 ps
CPU time 9.08 seconds
Started May 07 12:42:27 PM PDT 24
Finished May 07 12:42:38 PM PDT 24
Peak memory 204104 kb
Host smart-86cec7e6-bb7f-4aa9-a968-dffb3693c021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42556
37937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.4255637937
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.3950925187
Short name T626
Test name
Test status
Simulation time 8470495796 ps
CPU time 10.61 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:06 PM PDT 24
Peak memory 204084 kb
Host smart-d22d5374-55dd-47a6-9fef-8f4aea338b3a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3950925187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.3950925187
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.2460896690
Short name T1218
Test name
Test status
Simulation time 8413148999 ps
CPU time 8.65 seconds
Started May 07 12:42:47 PM PDT 24
Finished May 07 12:42:58 PM PDT 24
Peak memory 204016 kb
Host smart-67200ff1-3cf2-40ca-9e08-f834fa65ef24
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2460896690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.2460896690
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.2946121183
Short name T1305
Test name
Test status
Simulation time 8416047864 ps
CPU time 9.63 seconds
Started May 07 12:42:32 PM PDT 24
Finished May 07 12:42:45 PM PDT 24
Peak memory 204068 kb
Host smart-312a41f9-0e3e-4bc8-b286-e1f94f63e45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29461
21183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.2946121183
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.4169010603
Short name T1231
Test name
Test status
Simulation time 8444778939 ps
CPU time 8.37 seconds
Started May 07 12:42:27 PM PDT 24
Finished May 07 12:42:37 PM PDT 24
Peak memory 204132 kb
Host smart-ad80416e-3968-4736-a32e-986f007cd668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41690
10603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4169010603
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.1071781478
Short name T373
Test name
Test status
Simulation time 8400988726 ps
CPU time 8.01 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:42 PM PDT 24
Peak memory 204136 kb
Host smart-0baa0d9e-402b-4a1b-bbde-7987b0f36713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10717
81478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1071781478
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.436174111
Short name T951
Test name
Test status
Simulation time 202770651 ps
CPU time 2.02 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:40 PM PDT 24
Peak memory 204192 kb
Host smart-8c0787da-0444-419e-8031-e33c7477ae08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43617
4111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.436174111
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3470278085
Short name T711
Test name
Test status
Simulation time 8480105937 ps
CPU time 8.32 seconds
Started May 07 12:42:26 PM PDT 24
Finished May 07 12:42:36 PM PDT 24
Peak memory 204088 kb
Host smart-d4e33407-8347-4643-ab5f-d561fba7c98b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34702
78085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3470278085
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.830537229
Short name T1325
Test name
Test status
Simulation time 8375813874 ps
CPU time 8.47 seconds
Started May 07 12:42:30 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 204124 kb
Host smart-6ecc0844-0e31-4247-9b13-d4056e74ad78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83053
7229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.830537229
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1782849676
Short name T1100
Test name
Test status
Simulation time 8451628100 ps
CPU time 7.66 seconds
Started May 07 12:42:27 PM PDT 24
Finished May 07 12:42:36 PM PDT 24
Peak memory 204104 kb
Host smart-a9dbceb0-3026-4b08-adc9-4edb3681fe78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17828
49676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1782849676
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3417496273
Short name T224
Test name
Test status
Simulation time 8414727268 ps
CPU time 8.4 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204104 kb
Host smart-1cec408a-a66f-4798-ac74-f4957003df7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34174
96273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3417496273
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2547721534
Short name T422
Test name
Test status
Simulation time 8368960044 ps
CPU time 7.95 seconds
Started May 07 12:42:28 PM PDT 24
Finished May 07 12:42:37 PM PDT 24
Peak memory 204080 kb
Host smart-2bfc1baa-2f51-4cb1-9c8d-503fad26e141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25477
21534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2547721534
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.8687978
Short name T1357
Test name
Test status
Simulation time 8406664971 ps
CPU time 7.83 seconds
Started May 07 12:42:46 PM PDT 24
Finished May 07 12:42:56 PM PDT 24
Peak memory 204076 kb
Host smart-e8fb6b7e-3fd0-4023-8443-4cb62ee1e374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86879
78 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.8687978
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1382282751
Short name T989
Test name
Test status
Simulation time 8410653868 ps
CPU time 7.81 seconds
Started May 07 12:42:45 PM PDT 24
Finished May 07 12:42:55 PM PDT 24
Peak memory 204120 kb
Host smart-1778a68c-b076-48c7-b502-2f6e379b7747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13822
82751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1382282751
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1203794554
Short name T1088
Test name
Test status
Simulation time 8401897159 ps
CPU time 7.89 seconds
Started May 07 12:42:37 PM PDT 24
Finished May 07 12:42:47 PM PDT 24
Peak memory 204128 kb
Host smart-498a497f-3984-441e-a968-5ffd3a91f67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12037
94554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1203794554
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.153584686
Short name T1119
Test name
Test status
Simulation time 8464274215 ps
CPU time 9.35 seconds
Started May 07 12:42:40 PM PDT 24
Finished May 07 12:42:50 PM PDT 24
Peak memory 204100 kb
Host smart-e66f4362-b314-4530-bdbf-6e5072344f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15358
4686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.153584686
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.587211354
Short name T1198
Test name
Test status
Simulation time 8368459799 ps
CPU time 10.24 seconds
Started May 07 12:42:29 PM PDT 24
Finished May 07 12:42:40 PM PDT 24
Peak memory 204140 kb
Host smart-d03e97f5-98c6-48f6-90b6-4d8abe38ece7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58721
1354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.587211354
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3815099738
Short name T891
Test name
Test status
Simulation time 63945375 ps
CPU time 0.66 seconds
Started May 07 12:42:44 PM PDT 24
Finished May 07 12:42:45 PM PDT 24
Peak memory 203968 kb
Host smart-b38b218b-298b-483e-b75c-fb1b9acb2475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38150
99738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3815099738
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3439976682
Short name T1222
Test name
Test status
Simulation time 29759256019 ps
CPU time 63.48 seconds
Started May 07 12:42:32 PM PDT 24
Finished May 07 12:43:39 PM PDT 24
Peak memory 204492 kb
Host smart-a9d3ac5a-b7d0-48dc-a5eb-fc73a94932bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34399
76682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3439976682
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.743286926
Short name T1200
Test name
Test status
Simulation time 8408367047 ps
CPU time 8.86 seconds
Started May 07 12:42:33 PM PDT 24
Finished May 07 12:42:44 PM PDT 24
Peak memory 204132 kb
Host smart-e10ec3f1-ffb6-4db2-a4af-ccd34c054c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74328
6926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.743286926
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3326685458
Short name T1184
Test name
Test status
Simulation time 8391939607 ps
CPU time 8.46 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:04 PM PDT 24
Peak memory 204116 kb
Host smart-9bf65021-91d7-467e-b970-801811d5f4ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33266
85458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3326685458
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2263867270
Short name T400
Test name
Test status
Simulation time 8413570973 ps
CPU time 8.23 seconds
Started May 07 12:42:34 PM PDT 24
Finished May 07 12:42:44 PM PDT 24
Peak memory 204152 kb
Host smart-3ef6c5fd-aa19-4d4c-8a14-35931f73729e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22638
67270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2263867270
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2322806455
Short name T664
Test name
Test status
Simulation time 8368877461 ps
CPU time 7.75 seconds
Started May 07 12:42:28 PM PDT 24
Finished May 07 12:42:37 PM PDT 24
Peak memory 204080 kb
Host smart-96d1a870-e840-4858-9868-67e7fec0bf76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23228
06455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2322806455
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1341772919
Short name T1347
Test name
Test status
Simulation time 8401592976 ps
CPU time 9.87 seconds
Started May 07 12:42:30 PM PDT 24
Finished May 07 12:42:45 PM PDT 24
Peak memory 204092 kb
Host smart-72af9b8d-a27f-472a-924b-423e667d2ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13417
72919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1341772919
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3168482120
Short name T147
Test name
Test status
Simulation time 8479173566 ps
CPU time 9.15 seconds
Started May 07 12:42:32 PM PDT 24
Finished May 07 12:42:43 PM PDT 24
Peak memory 204124 kb
Host smart-19f6da38-15aa-4265-b5b3-3d21c4f8a714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31684
82120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3168482120
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2949516810
Short name T340
Test name
Test status
Simulation time 8405159345 ps
CPU time 8.35 seconds
Started May 07 12:42:33 PM PDT 24
Finished May 07 12:42:44 PM PDT 24
Peak memory 204144 kb
Host smart-08ed2bc2-9ae7-4cc7-9944-a01c1043e068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29495
16810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2949516810
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2260088940
Short name T594
Test name
Test status
Simulation time 8421033475 ps
CPU time 8.18 seconds
Started May 07 12:42:40 PM PDT 24
Finished May 07 12:42:49 PM PDT 24
Peak memory 204112 kb
Host smart-30241b4e-8f05-4c64-99fc-cb224709c1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22600
88940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2260088940
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.1783891177
Short name T1000
Test name
Test status
Simulation time 8522582130 ps
CPU time 8.83 seconds
Started May 07 12:42:41 PM PDT 24
Finished May 07 12:42:51 PM PDT 24
Peak memory 204120 kb
Host smart-d9fa1ede-0010-4b5a-9a6b-d16cbf7d6b29
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1783891177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.1783891177
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.34271264
Short name T1339
Test name
Test status
Simulation time 8378035022 ps
CPU time 7.21 seconds
Started May 07 12:42:40 PM PDT 24
Finished May 07 12:42:48 PM PDT 24
Peak memory 204120 kb
Host smart-63744190-583c-4cf2-acee-68ca568d318f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=34271264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.34271264
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.1181538476
Short name T406
Test name
Test status
Simulation time 8451297231 ps
CPU time 7.97 seconds
Started May 07 12:43:33 PM PDT 24
Finished May 07 12:43:43 PM PDT 24
Peak memory 203936 kb
Host smart-fa24e5c5-1963-422c-8898-c984347e65de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11815
38476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.1181538476
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3178266369
Short name T1310
Test name
Test status
Simulation time 8381258701 ps
CPU time 7.49 seconds
Started May 07 12:42:30 PM PDT 24
Finished May 07 12:42:40 PM PDT 24
Peak memory 204056 kb
Host smart-ffd6d6b8-c8cf-4f65-90e8-6f8338c0cc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31782
66369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3178266369
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.3751668062
Short name T865
Test name
Test status
Simulation time 8406577717 ps
CPU time 9.53 seconds
Started May 07 12:42:35 PM PDT 24
Finished May 07 12:42:47 PM PDT 24
Peak memory 204120 kb
Host smart-e2608e37-4d98-41b6-b658-749dbd5d5da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37516
68062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3751668062
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1597387148
Short name T438
Test name
Test status
Simulation time 146002232 ps
CPU time 1.4 seconds
Started May 07 12:42:28 PM PDT 24
Finished May 07 12:42:30 PM PDT 24
Peak memory 204176 kb
Host smart-964ff193-e0bd-4202-8701-4662281312db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15973
87148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1597387148
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.4091747025
Short name T460
Test name
Test status
Simulation time 8417227532 ps
CPU time 8.64 seconds
Started May 07 12:42:27 PM PDT 24
Finished May 07 12:42:37 PM PDT 24
Peak memory 204120 kb
Host smart-2ed22485-91b1-4e51-8ca0-9242cbd8d0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40917
47025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.4091747025
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1248239837
Short name T207
Test name
Test status
Simulation time 8398443112 ps
CPU time 7.59 seconds
Started May 07 12:42:36 PM PDT 24
Finished May 07 12:42:46 PM PDT 24
Peak memory 204004 kb
Host smart-6626bf30-3c7f-4e38-a33b-5c7f85276ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12482
39837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1248239837
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3767745792
Short name T1017
Test name
Test status
Simulation time 8449400470 ps
CPU time 7.58 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204116 kb
Host smart-5dd8675c-c899-4efd-bab2-35aaa1cd3a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37677
45792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3767745792
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3853694045
Short name T632
Test name
Test status
Simulation time 8416759460 ps
CPU time 7.6 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 204036 kb
Host smart-cfd0f905-890b-48dc-a73a-cb94db8a16d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
94045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3853694045
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1475867608
Short name T389
Test name
Test status
Simulation time 8417993505 ps
CPU time 7.48 seconds
Started May 07 12:42:28 PM PDT 24
Finished May 07 12:42:37 PM PDT 24
Peak memory 204124 kb
Host smart-395dc5fb-91b5-416f-81ad-c5cb00a11be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14758
67608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1475867608
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2265948110
Short name T119
Test name
Test status
Simulation time 8461360634 ps
CPU time 10.43 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:04 PM PDT 24
Peak memory 204084 kb
Host smart-1d75647f-eb8b-4588-b86d-4a4570ad1010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22659
48110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2265948110
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2678382060
Short name T1263
Test name
Test status
Simulation time 8414528451 ps
CPU time 8.46 seconds
Started May 07 12:42:45 PM PDT 24
Finished May 07 12:42:56 PM PDT 24
Peak memory 204092 kb
Host smart-61fff0f4-6e83-43d6-8e7b-a0a6796f65d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26783
82060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2678382060
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3689670214
Short name T1280
Test name
Test status
Simulation time 8482058763 ps
CPU time 8.54 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204068 kb
Host smart-8e25fae6-4dc5-4c78-a7a7-c122d68859ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36896
70214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3689670214
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.787321204
Short name T902
Test name
Test status
Simulation time 8404852461 ps
CPU time 8.24 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:42 PM PDT 24
Peak memory 204100 kb
Host smart-ec2a5758-202d-46a6-8493-60e558b19e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78732
1204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.787321204
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.4281871347
Short name T777
Test name
Test status
Simulation time 8373247057 ps
CPU time 9.56 seconds
Started May 07 12:42:42 PM PDT 24
Finished May 07 12:42:53 PM PDT 24
Peak memory 204128 kb
Host smart-48f1e982-2770-49b6-8522-4dbcb835a842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42818
71347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.4281871347
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.205205014
Short name T513
Test name
Test status
Simulation time 44911646 ps
CPU time 0.63 seconds
Started May 07 12:42:32 PM PDT 24
Finished May 07 12:42:35 PM PDT 24
Peak memory 203960 kb
Host smart-150b078c-fccb-4f51-a6e5-45b186eb19c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20520
5014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.205205014
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2336515147
Short name T980
Test name
Test status
Simulation time 16547925760 ps
CPU time 28.64 seconds
Started May 07 12:42:32 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204304 kb
Host smart-3837bcb7-c405-4e12-b04f-8dea6e8dc514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23365
15147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2336515147
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.507512944
Short name T911
Test name
Test status
Simulation time 8394680068 ps
CPU time 7.57 seconds
Started May 07 12:42:41 PM PDT 24
Finished May 07 12:42:50 PM PDT 24
Peak memory 204124 kb
Host smart-1b9998be-d246-4c49-a26c-4ab65a4baeba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50751
2944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.507512944
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3792293691
Short name T774
Test name
Test status
Simulation time 8422671402 ps
CPU time 8.38 seconds
Started May 07 12:42:30 PM PDT 24
Finished May 07 12:42:41 PM PDT 24
Peak memory 204096 kb
Host smart-dff8f738-75fc-4c82-b058-0b2de7c2ac29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37922
93691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3792293691
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.1022081834
Short name T782
Test name
Test status
Simulation time 8406182936 ps
CPU time 7.39 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:58 PM PDT 24
Peak memory 204148 kb
Host smart-3ed4f15c-bedd-4dd2-aef8-275b04722007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10220
81834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.1022081834
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1817574841
Short name T912
Test name
Test status
Simulation time 8379538145 ps
CPU time 7.52 seconds
Started May 07 12:42:42 PM PDT 24
Finished May 07 12:42:51 PM PDT 24
Peak memory 204084 kb
Host smart-7276e619-306d-4c8f-b3d6-c61e29ee0171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18175
74841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1817574841
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.604793071
Short name T793
Test name
Test status
Simulation time 8372175796 ps
CPU time 8.02 seconds
Started May 07 12:43:26 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 203932 kb
Host smart-de4f5363-ad98-479e-b1d7-0db5c1dd0df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60479
3071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.604793071
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1023460778
Short name T905
Test name
Test status
Simulation time 8448035917 ps
CPU time 7.85 seconds
Started May 07 12:42:46 PM PDT 24
Finished May 07 12:42:56 PM PDT 24
Peak memory 204132 kb
Host smart-35e6d472-85d0-4489-9b19-7a06252cc985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10234
60778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1023460778
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.747817275
Short name T377
Test name
Test status
Simulation time 8406231160 ps
CPU time 7.47 seconds
Started May 07 12:42:42 PM PDT 24
Finished May 07 12:42:51 PM PDT 24
Peak memory 204124 kb
Host smart-4288aa4b-77b1-430a-873b-783263168327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74781
7275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.747817275
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1684799439
Short name T741
Test name
Test status
Simulation time 8391502182 ps
CPU time 9.43 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:43:00 PM PDT 24
Peak memory 204060 kb
Host smart-25ad368a-9bf5-4ea4-8941-12f42cce02f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16847
99439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1684799439
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.4143284892
Short name T709
Test name
Test status
Simulation time 8469457104 ps
CPU time 7.83 seconds
Started May 07 12:42:44 PM PDT 24
Finished May 07 12:42:53 PM PDT 24
Peak memory 204096 kb
Host smart-c4ff83e7-762c-4d20-ba4e-b9331fd5ce9d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4143284892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.4143284892
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.1726505102
Short name T1187
Test name
Test status
Simulation time 8391677980 ps
CPU time 7.87 seconds
Started May 07 12:42:40 PM PDT 24
Finished May 07 12:42:49 PM PDT 24
Peak memory 204104 kb
Host smart-db20a113-feab-4ac7-ad48-5dd84ca8cad9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1726505102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.1726505102
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.2737599248
Short name T688
Test name
Test status
Simulation time 8435655564 ps
CPU time 10.18 seconds
Started May 07 12:43:05 PM PDT 24
Finished May 07 12:43:17 PM PDT 24
Peak memory 204108 kb
Host smart-25800996-7a60-424f-badf-c199f66a3d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27375
99248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.2737599248
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1636338340
Short name T1159
Test name
Test status
Simulation time 8375264690 ps
CPU time 8.35 seconds
Started May 07 12:42:36 PM PDT 24
Finished May 07 12:42:46 PM PDT 24
Peak memory 204108 kb
Host smart-b3c7408c-c7d6-4d9f-bef6-2a9d64875ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16363
38340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1636338340
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.3699484575
Short name T554
Test name
Test status
Simulation time 8371236516 ps
CPU time 7.79 seconds
Started May 07 12:42:30 PM PDT 24
Finished May 07 12:42:40 PM PDT 24
Peak memory 204132 kb
Host smart-aa0bb402-b211-453a-aff6-adb90f201e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36994
84575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3699484575
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2352295448
Short name T694
Test name
Test status
Simulation time 122209858 ps
CPU time 1.45 seconds
Started May 07 12:42:53 PM PDT 24
Finished May 07 12:42:58 PM PDT 24
Peak memory 204228 kb
Host smart-5e32a1db-74ee-4f79-94ca-5ff9ca4ad514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23522
95448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2352295448
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.4173281680
Short name T769
Test name
Test status
Simulation time 8496744265 ps
CPU time 8.36 seconds
Started May 07 12:42:59 PM PDT 24
Finished May 07 12:43:10 PM PDT 24
Peak memory 204112 kb
Host smart-c012d9b2-21b1-4734-a239-77336cf543f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41732
81680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.4173281680
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2995867954
Short name T1062
Test name
Test status
Simulation time 8370374041 ps
CPU time 7.95 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204128 kb
Host smart-c1f2f4f4-054e-49cf-a393-0348c4599822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29958
67954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2995867954
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.155590004
Short name T145
Test name
Test status
Simulation time 8446790332 ps
CPU time 7.75 seconds
Started May 07 12:42:29 PM PDT 24
Finished May 07 12:42:37 PM PDT 24
Peak memory 204128 kb
Host smart-5eb091c6-1af4-4c36-9366-184ff9d257d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15559
0004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.155590004
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2403069538
Short name T729
Test name
Test status
Simulation time 8464452842 ps
CPU time 8.15 seconds
Started May 07 12:42:56 PM PDT 24
Finished May 07 12:43:07 PM PDT 24
Peak memory 204104 kb
Host smart-8dfe0e70-c04b-4434-ac5e-c1aed0b908bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24030
69538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2403069538
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3445126100
Short name T381
Test name
Test status
Simulation time 8378957783 ps
CPU time 8.23 seconds
Started May 07 12:42:46 PM PDT 24
Finished May 07 12:42:56 PM PDT 24
Peak memory 204128 kb
Host smart-e0e810c8-9286-438e-af49-81d82314761d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34451
26100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3445126100
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3871071572
Short name T1199
Test name
Test status
Simulation time 8407058936 ps
CPU time 8.83 seconds
Started May 07 12:42:45 PM PDT 24
Finished May 07 12:42:55 PM PDT 24
Peak memory 204108 kb
Host smart-28f4339c-c6fc-4190-8d66-080a41a77720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38710
71572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3871071572
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.981157590
Short name T350
Test name
Test status
Simulation time 8403948034 ps
CPU time 10.24 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204080 kb
Host smart-8d14167f-572b-4def-9740-6a68400583d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98115
7590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.981157590
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3701165634
Short name T385
Test name
Test status
Simulation time 8430581878 ps
CPU time 7.61 seconds
Started May 07 12:42:46 PM PDT 24
Finished May 07 12:42:56 PM PDT 24
Peak memory 204116 kb
Host smart-3784678e-20f7-4dab-97c4-c303f57392df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37011
65634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3701165634
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.553163099
Short name T1131
Test name
Test status
Simulation time 8370776948 ps
CPU time 9.38 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:43:00 PM PDT 24
Peak memory 204120 kb
Host smart-02daac4a-97b2-4340-87f6-7b69f18bf54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55316
3099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.553163099
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.597185049
Short name T15
Test name
Test status
Simulation time 42855483 ps
CPU time 0.67 seconds
Started May 07 12:42:31 PM PDT 24
Finished May 07 12:42:35 PM PDT 24
Peak memory 203948 kb
Host smart-e605ce60-a3df-4da5-b2ec-013299f8e01d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59718
5049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.597185049
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.70135106
Short name T12
Test name
Test status
Simulation time 29527286799 ps
CPU time 56.95 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:43:48 PM PDT 24
Peak memory 204416 kb
Host smart-226f2666-410c-4c7c-880a-56a0df13593c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70135
106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.70135106
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1873157387
Short name T628
Test name
Test status
Simulation time 8403267731 ps
CPU time 7.92 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204108 kb
Host smart-94426779-cdd6-4bbb-8855-b7c72cc99bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18731
57387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1873157387
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2767528387
Short name T609
Test name
Test status
Simulation time 8472287670 ps
CPU time 8.51 seconds
Started May 07 12:42:36 PM PDT 24
Finished May 07 12:42:47 PM PDT 24
Peak memory 204120 kb
Host smart-f34e4218-d531-4077-89c5-4ad39ed4b7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27675
28387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2767528387
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.1871734423
Short name T1201
Test name
Test status
Simulation time 8420272533 ps
CPU time 7.72 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204124 kb
Host smart-ed97c25b-d4a5-4673-b472-4702d7b00dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18717
34423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.1871734423
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2404013997
Short name T171
Test name
Test status
Simulation time 8376631046 ps
CPU time 7.73 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:58 PM PDT 24
Peak memory 204204 kb
Host smart-b11242c3-3038-40f6-bae2-e6dda9f01933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24040
13997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2404013997
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.4067403997
Short name T1292
Test name
Test status
Simulation time 8373425980 ps
CPU time 8.91 seconds
Started May 07 12:42:53 PM PDT 24
Finished May 07 12:43:06 PM PDT 24
Peak memory 204100 kb
Host smart-dbdca27c-c46c-4b0a-9466-3afa6ff9d11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40674
03997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.4067403997
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1672025446
Short name T760
Test name
Test status
Simulation time 8406515608 ps
CPU time 7.83 seconds
Started May 07 12:42:44 PM PDT 24
Finished May 07 12:42:53 PM PDT 24
Peak memory 204112 kb
Host smart-9602b18d-4d2f-454d-9d2c-f357157573f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16720
25446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1672025446
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1141623571
Short name T418
Test name
Test status
Simulation time 8410392747 ps
CPU time 7.44 seconds
Started May 07 12:42:45 PM PDT 24
Finished May 07 12:42:54 PM PDT 24
Peak memory 204084 kb
Host smart-d9227af8-9e74-42fd-95c6-abd9b169ddc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11416
23571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1141623571
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.1593740364
Short name T45
Test name
Test status
Simulation time 8520039053 ps
CPU time 9.32 seconds
Started May 07 12:42:43 PM PDT 24
Finished May 07 12:42:54 PM PDT 24
Peak memory 204096 kb
Host smart-29de8ce6-94f8-4009-a64a-0c2d811c3bdc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1593740364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.1593740364
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.122498815
Short name T770
Test name
Test status
Simulation time 8413943040 ps
CPU time 9.35 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204136 kb
Host smart-0d07d270-e0d2-4a6b-9d36-9bdd30fb479c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=122498815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.122498815
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.2934099915
Short name T296
Test name
Test status
Simulation time 8387727117 ps
CPU time 8.53 seconds
Started May 07 12:42:41 PM PDT 24
Finished May 07 12:42:51 PM PDT 24
Peak memory 204120 kb
Host smart-6a8f4bb7-f750-47ad-b8df-b64e39715e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29340
99915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.2934099915
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1833346168
Short name T864
Test name
Test status
Simulation time 8377358830 ps
CPU time 8.24 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:00 PM PDT 24
Peak memory 204092 kb
Host smart-fc95e700-7be6-436d-b8b6-d448dc996feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18333
46168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1833346168
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.3268818178
Short name T909
Test name
Test status
Simulation time 8373534345 ps
CPU time 7.92 seconds
Started May 07 12:42:36 PM PDT 24
Finished May 07 12:42:47 PM PDT 24
Peak memory 204048 kb
Host smart-1bac07b4-d4a9-405d-9de3-f66db249d2a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32688
18178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3268818178
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1187863641
Short name T1282
Test name
Test status
Simulation time 72458522 ps
CPU time 0.95 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:42:54 PM PDT 24
Peak memory 204112 kb
Host smart-bb888656-b5c3-4754-b2c6-fde8093ec49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11878
63641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1187863641
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.640400600
Short name T1112
Test name
Test status
Simulation time 8439825926 ps
CPU time 9.09 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:59 PM PDT 24
Peak memory 204096 kb
Host smart-7b7763b8-0f5a-4da2-8557-900cca3301fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64040
0600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.640400600
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.996276193
Short name T6
Test name
Test status
Simulation time 8364669706 ps
CPU time 9.04 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204120 kb
Host smart-ff0cdc21-d1cf-4525-9c57-cdb0f855d419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99627
6193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.996276193
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.880085127
Short name T1115
Test name
Test status
Simulation time 8407183070 ps
CPU time 8.34 seconds
Started May 07 12:42:47 PM PDT 24
Finished May 07 12:42:58 PM PDT 24
Peak memory 204300 kb
Host smart-b5dc1876-1bea-424a-914e-6234005e1fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88008
5127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.880085127
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3900652978
Short name T405
Test name
Test status
Simulation time 8417279756 ps
CPU time 8.75 seconds
Started May 07 12:42:53 PM PDT 24
Finished May 07 12:43:05 PM PDT 24
Peak memory 204108 kb
Host smart-a3caeb7f-f363-4a9d-abee-a2828bb85feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39006
52978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3900652978
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1857946288
Short name T1029
Test name
Test status
Simulation time 8369597706 ps
CPU time 7.97 seconds
Started May 07 12:43:01 PM PDT 24
Finished May 07 12:43:11 PM PDT 24
Peak memory 204100 kb
Host smart-4149861c-b8e7-4bdd-b339-c33ce14a0ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18579
46288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1857946288
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1807301822
Short name T1093
Test name
Test status
Simulation time 8391463321 ps
CPU time 7.8 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204132 kb
Host smart-7624bf85-ea7e-44c7-93bd-4d6023555c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18073
01822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1807301822
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2783021261
Short name T671
Test name
Test status
Simulation time 8400723713 ps
CPU time 7.94 seconds
Started May 07 12:42:47 PM PDT 24
Finished May 07 12:42:57 PM PDT 24
Peak memory 204100 kb
Host smart-fe2ed869-38b1-4374-991c-0c69384363e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27830
21261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2783021261
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3929639224
Short name T376
Test name
Test status
Simulation time 8417731231 ps
CPU time 8.77 seconds
Started May 07 12:42:54 PM PDT 24
Finished May 07 12:43:06 PM PDT 24
Peak memory 204120 kb
Host smart-470d64d5-078e-4113-b7f5-669b9ddc61cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39296
39224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3929639224
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1903440462
Short name T1053
Test name
Test status
Simulation time 8417104856 ps
CPU time 8.3 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:00 PM PDT 24
Peak memory 204104 kb
Host smart-cd58f581-74f7-4b04-801b-8f3f0a71cfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19034
40462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1903440462
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.873121523
Short name T571
Test name
Test status
Simulation time 8371647197 ps
CPU time 7.24 seconds
Started May 07 12:42:43 PM PDT 24
Finished May 07 12:42:52 PM PDT 24
Peak memory 204128 kb
Host smart-7c8afee4-b9cf-4503-aa2e-91c17767d24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87312
1523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.873121523
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2663474531
Short name T42
Test name
Test status
Simulation time 83803151 ps
CPU time 0.69 seconds
Started May 07 12:42:38 PM PDT 24
Finished May 07 12:42:40 PM PDT 24
Peak memory 203984 kb
Host smart-fafb2ec7-44ae-4ae0-a103-488885a81d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26634
74531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2663474531
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.325590713
Short name T811
Test name
Test status
Simulation time 27870572214 ps
CPU time 51.43 seconds
Started May 07 12:42:47 PM PDT 24
Finished May 07 12:43:40 PM PDT 24
Peak memory 204328 kb
Host smart-d3920697-dad7-4d7c-ae76-e4f443884b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32559
0713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.325590713
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.939441553
Short name T736
Test name
Test status
Simulation time 8423391632 ps
CPU time 8.39 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:06 PM PDT 24
Peak memory 204116 kb
Host smart-30ca47a0-a085-426c-8860-007513429279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93944
1553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.939441553
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1148103337
Short name T862
Test name
Test status
Simulation time 8418638823 ps
CPU time 8.69 seconds
Started May 07 12:43:09 PM PDT 24
Finished May 07 12:43:20 PM PDT 24
Peak memory 204100 kb
Host smart-31997800-ef53-459d-a037-d6c19f5b20d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11481
03337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1148103337
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.1020421074
Short name T844
Test name
Test status
Simulation time 8421589146 ps
CPU time 7.69 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204152 kb
Host smart-f1ce307d-8dd4-43cf-abe4-5b704533fabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10204
21074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.1020421074
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1115726728
Short name T180
Test name
Test status
Simulation time 8376355679 ps
CPU time 7.73 seconds
Started May 07 12:42:45 PM PDT 24
Finished May 07 12:42:54 PM PDT 24
Peak memory 204108 kb
Host smart-c1ec915f-620d-4b4d-9342-e049ac36a074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11157
26728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1115726728
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3785430654
Short name T467
Test name
Test status
Simulation time 8371678098 ps
CPU time 8.32 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:58 PM PDT 24
Peak memory 204112 kb
Host smart-3eae34ba-f22b-4212-a4c7-dec29b3fd5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37854
30654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3785430654
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3471111611
Short name T170
Test name
Test status
Simulation time 8410870777 ps
CPU time 7.71 seconds
Started May 07 12:42:45 PM PDT 24
Finished May 07 12:42:54 PM PDT 24
Peak memory 204036 kb
Host smart-814de92a-3183-4548-b6f9-28f2854be6b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34711
11611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3471111611
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3278254327
Short name T1252
Test name
Test status
Simulation time 8419599421 ps
CPU time 8.13 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204124 kb
Host smart-d1e900d3-74fd-4707-8b3b-22c82f3709f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32782
54327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3278254327
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.131459627
Short name T1160
Test name
Test status
Simulation time 8400960291 ps
CPU time 7.49 seconds
Started May 07 12:42:37 PM PDT 24
Finished May 07 12:42:46 PM PDT 24
Peak memory 204056 kb
Host smart-bba3fbb2-5633-4e59-9cc7-b8973e54ac8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13145
9627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.131459627
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.3255608896
Short name T987
Test name
Test status
Simulation time 8479871748 ps
CPU time 8.02 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204108 kb
Host smart-56c185d8-c741-4e50-95bf-ce663cb67783
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3255608896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.3255608896
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.2127222975
Short name T755
Test name
Test status
Simulation time 8378929565 ps
CPU time 8.12 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204128 kb
Host smart-875bfd03-882f-4e55-9def-581bcfc6a5f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2127222975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.2127222975
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.120610933
Short name T908
Test name
Test status
Simulation time 8472357062 ps
CPU time 8.38 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204092 kb
Host smart-922dbfaa-57f5-4ad3-847e-2ebbd702fdc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12061
0933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.120610933
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2573959208
Short name T1084
Test name
Test status
Simulation time 8389064857 ps
CPU time 7.96 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204120 kb
Host smart-aeccc7fe-ed0d-44f3-9ec8-4d2937194260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25739
59208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2573959208
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.1188861682
Short name T83
Test name
Test status
Simulation time 8375704078 ps
CPU time 7.63 seconds
Started May 07 12:43:01 PM PDT 24
Finished May 07 12:43:11 PM PDT 24
Peak memory 204124 kb
Host smart-f5e13b28-e493-4fbc-a8d3-5876bbadcb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11888
61682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1188861682
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2151310930
Short name T1293
Test name
Test status
Simulation time 244828294 ps
CPU time 1.89 seconds
Started May 07 12:42:43 PM PDT 24
Finished May 07 12:42:46 PM PDT 24
Peak memory 204252 kb
Host smart-8219aec2-adb3-4fa9-a647-a25c2b9b9782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21513
10930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2151310930
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1682730416
Short name T1091
Test name
Test status
Simulation time 8435758314 ps
CPU time 8.12 seconds
Started May 07 12:42:57 PM PDT 24
Finished May 07 12:43:07 PM PDT 24
Peak memory 204020 kb
Host smart-ba5b2b8c-5ee8-42ad-89e1-2708f0a445e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16827
30416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1682730416
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2603597667
Short name T1125
Test name
Test status
Simulation time 8379966510 ps
CPU time 9.33 seconds
Started May 07 12:43:05 PM PDT 24
Finished May 07 12:43:16 PM PDT 24
Peak memory 204120 kb
Host smart-3e66266b-0edd-4600-9828-ecd29d1dd142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26035
97667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2603597667
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2424357919
Short name T743
Test name
Test status
Simulation time 8468210239 ps
CPU time 9.29 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204124 kb
Host smart-9b5c8022-8942-4748-9caa-cc4d91d7c26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243
57919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2424357919
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3741512652
Short name T88
Test name
Test status
Simulation time 8429886603 ps
CPU time 7.84 seconds
Started May 07 12:42:46 PM PDT 24
Finished May 07 12:42:56 PM PDT 24
Peak memory 204124 kb
Host smart-3f9a09b5-d2b2-425a-b9f9-3b20252af490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37415
12652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3741512652
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3145844781
Short name T38
Test name
Test status
Simulation time 8369780094 ps
CPU time 7.77 seconds
Started May 07 12:42:46 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204128 kb
Host smart-bcf54d02-e4c8-4a07-a82e-3f61508d1c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31458
44781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3145844781
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2731385098
Short name T124
Test name
Test status
Simulation time 8427858181 ps
CPU time 10.07 seconds
Started May 07 12:42:57 PM PDT 24
Finished May 07 12:43:09 PM PDT 24
Peak memory 204112 kb
Host smart-783a07f1-7459-494b-b2ca-621bba9a0456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27313
85098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2731385098
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1960987975
Short name T749
Test name
Test status
Simulation time 8469500469 ps
CPU time 8.36 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204116 kb
Host smart-cc28c8cf-65b9-470d-a65f-bb448d496db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19609
87975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1960987975
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3171015200
Short name T476
Test name
Test status
Simulation time 8383672825 ps
CPU time 8.03 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204112 kb
Host smart-acdcae01-dc2d-4033-8579-c596ee6491b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31710
15200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3171015200
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3356299155
Short name T174
Test name
Test status
Simulation time 8396625293 ps
CPU time 8.05 seconds
Started May 07 12:43:00 PM PDT 24
Finished May 07 12:43:10 PM PDT 24
Peak memory 204116 kb
Host smart-a82fe45d-43ec-4fd8-b427-1b061584c300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33562
99155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3356299155
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1742445935
Short name T399
Test name
Test status
Simulation time 8369652685 ps
CPU time 10.05 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204136 kb
Host smart-ee9da78b-e5f8-4049-859b-6e7b350d63a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17424
45935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1742445935
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3276226501
Short name T40
Test name
Test status
Simulation time 72988232 ps
CPU time 0.71 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:51 PM PDT 24
Peak memory 203968 kb
Host smart-d289b6dc-f3f5-403e-bf0a-ef92e17df4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32762
26501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3276226501
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2319136765
Short name T250
Test name
Test status
Simulation time 25203668266 ps
CPU time 48.01 seconds
Started May 07 12:42:55 PM PDT 24
Finished May 07 12:43:46 PM PDT 24
Peak memory 204396 kb
Host smart-c59f5547-b67c-4877-8627-b28439e04893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23191
36765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2319136765
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.132083678
Short name T925
Test name
Test status
Simulation time 8412236303 ps
CPU time 8.44 seconds
Started May 07 12:42:54 PM PDT 24
Finished May 07 12:43:05 PM PDT 24
Peak memory 204116 kb
Host smart-f7b2ea64-95cd-445c-88d7-68eeac7127ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13208
3678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.132083678
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3701573416
Short name T323
Test name
Test status
Simulation time 8411069146 ps
CPU time 8.38 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204120 kb
Host smart-f3ae3931-4c91-4014-9995-4bab77d14761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37015
73416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3701573416
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.3848382647
Short name T1096
Test name
Test status
Simulation time 8400082037 ps
CPU time 7.85 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204100 kb
Host smart-07ed80ed-40f0-4714-8ef9-fb62f4e292e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38483
82647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.3848382647
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3743429360
Short name T762
Test name
Test status
Simulation time 8374688697 ps
CPU time 7.49 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:57 PM PDT 24
Peak memory 204080 kb
Host smart-f7bbf7bb-0f58-493c-a265-94c978077947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37434
29360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3743429360
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.774005816
Short name T517
Test name
Test status
Simulation time 8376247383 ps
CPU time 7.44 seconds
Started May 07 12:42:47 PM PDT 24
Finished May 07 12:42:57 PM PDT 24
Peak memory 204132 kb
Host smart-3cf5d41e-61ab-4558-8a8b-357a61035fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77400
5816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.774005816
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2624229802
Short name T901
Test name
Test status
Simulation time 8428788888 ps
CPU time 8.04 seconds
Started May 07 12:43:04 PM PDT 24
Finished May 07 12:43:14 PM PDT 24
Peak memory 204136 kb
Host smart-f4f23a44-41ca-408f-b14a-2fc2995e2c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26242
29802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2624229802
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1086984185
Short name T1365
Test name
Test status
Simulation time 8381071900 ps
CPU time 8.35 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:59 PM PDT 24
Peak memory 204108 kb
Host smart-f558f0bc-2920-4efb-a53c-254e20a1bf67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10869
84185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1086984185
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.3219117167
Short name T1311
Test name
Test status
Simulation time 8442685577 ps
CPU time 7.88 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:59 PM PDT 24
Peak memory 204116 kb
Host smart-8057d27b-08ca-40ec-8971-192c41e4daba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32191
17167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3219117167
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.4266447231
Short name T463
Test name
Test status
Simulation time 8468234315 ps
CPU time 8.54 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204036 kb
Host smart-4ed83320-0f81-4003-ba8f-4c6704017fca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4266447231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.4266447231
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.2740683405
Short name T1258
Test name
Test status
Simulation time 8382086799 ps
CPU time 8.62 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204128 kb
Host smart-6f52ef8f-52c2-48b6-a570-4a48b0ac709d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2740683405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.2740683405
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.2455678099
Short name T358
Test name
Test status
Simulation time 8391279643 ps
CPU time 7.95 seconds
Started May 07 12:43:06 PM PDT 24
Finished May 07 12:43:16 PM PDT 24
Peak memory 204108 kb
Host smart-16992a95-9d8f-489b-b0f7-4d12751b6040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24556
78099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.2455678099
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2111357338
Short name T611
Test name
Test status
Simulation time 8389139717 ps
CPU time 7.41 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:00 PM PDT 24
Peak memory 204172 kb
Host smart-ce3e2df4-e90a-4b7f-9afe-9540a58efaa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21113
57338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2111357338
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.2134709360
Short name T975
Test name
Test status
Simulation time 8398018820 ps
CPU time 8.09 seconds
Started May 07 12:42:55 PM PDT 24
Finished May 07 12:43:07 PM PDT 24
Peak memory 204108 kb
Host smart-e0150c30-51ab-4eb4-b905-aa3235fb4179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21347
09360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2134709360
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2008615987
Short name T1307
Test name
Test status
Simulation time 277740326 ps
CPU time 2.19 seconds
Started May 07 12:42:59 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204140 kb
Host smart-7d885bd9-8ca1-43e7-aef3-0957c8092b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20086
15987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2008615987
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2100062078
Short name T560
Test name
Test status
Simulation time 8431394106 ps
CPU time 7.66 seconds
Started May 07 12:42:55 PM PDT 24
Finished May 07 12:43:06 PM PDT 24
Peak memory 204088 kb
Host smart-52e036af-cfd2-465f-a156-70c18d8a26a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21000
62078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2100062078
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1099153744
Short name T1318
Test name
Test status
Simulation time 8391722615 ps
CPU time 7.54 seconds
Started May 07 12:42:45 PM PDT 24
Finished May 07 12:42:54 PM PDT 24
Peak memory 204124 kb
Host smart-d4b83b59-d170-4cef-a87d-14f027425fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10991
53744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1099153744
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3031829714
Short name T375
Test name
Test status
Simulation time 8446230001 ps
CPU time 9.4 seconds
Started May 07 12:43:23 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204120 kb
Host smart-6c8bfa2e-bb43-4031-a333-826d45239f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30318
29714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3031829714
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.4144782906
Short name T1274
Test name
Test status
Simulation time 8419055403 ps
CPU time 9.17 seconds
Started May 07 12:42:55 PM PDT 24
Finished May 07 12:43:07 PM PDT 24
Peak memory 204116 kb
Host smart-152a5c71-df1b-4895-af09-913950faaacf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41447
82906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.4144782906
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2890160996
Short name T392
Test name
Test status
Simulation time 8364925620 ps
CPU time 8.64 seconds
Started May 07 12:42:52 PM PDT 24
Finished May 07 12:43:05 PM PDT 24
Peak memory 204124 kb
Host smart-87961367-df19-46d9-87a0-8851dd38cebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901
60996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2890160996
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2284564652
Short name T1378
Test name
Test status
Simulation time 8409656908 ps
CPU time 7.98 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:31 PM PDT 24
Peak memory 204108 kb
Host smart-e7b0f616-c656-486b-b939-8110c7a69d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22845
64652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2284564652
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3477820830
Short name T370
Test name
Test status
Simulation time 8431084383 ps
CPU time 8.19 seconds
Started May 07 12:43:00 PM PDT 24
Finished May 07 12:43:10 PM PDT 24
Peak memory 204128 kb
Host smart-159c7c62-37e3-4de2-8abb-19fe2ffa52f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34778
20830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3477820830
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.68071724
Short name T804
Test name
Test status
Simulation time 8409447421 ps
CPU time 10.08 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204112 kb
Host smart-7106261f-1a88-4c68-962a-84040040edce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68071
724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.68071724
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3546619359
Short name T1247
Test name
Test status
Simulation time 8385557739 ps
CPU time 7.69 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:06 PM PDT 24
Peak memory 204052 kb
Host smart-693c6e0b-4fe0-4810-9677-f1a73f8f3476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35466
19359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3546619359
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.110895534
Short name T940
Test name
Test status
Simulation time 159128727 ps
CPU time 0.77 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:42:53 PM PDT 24
Peak memory 203900 kb
Host smart-a02843e6-b64f-4586-98b2-1bd9e7a1d5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11089
5534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.110895534
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1475189299
Short name T94
Test name
Test status
Simulation time 16083447381 ps
CPU time 30.18 seconds
Started May 07 12:42:56 PM PDT 24
Finished May 07 12:43:29 PM PDT 24
Peak memory 204284 kb
Host smart-6acff792-b1b9-4a2f-8cf0-0d26d10d8e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14751
89299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1475189299
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3679179105
Short name T1283
Test name
Test status
Simulation time 8400172201 ps
CPU time 8.23 seconds
Started May 07 12:43:19 PM PDT 24
Finished May 07 12:43:29 PM PDT 24
Peak memory 204088 kb
Host smart-8215dee9-a80f-4432-8989-5c91b53ba78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36791
79105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3679179105
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.4015739666
Short name T692
Test name
Test status
Simulation time 8454975844 ps
CPU time 8.02 seconds
Started May 07 12:42:46 PM PDT 24
Finished May 07 12:42:56 PM PDT 24
Peak memory 204104 kb
Host smart-b81c2bd4-0719-4d7a-869f-ca132e7dfa29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40157
39666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.4015739666
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.2089634302
Short name T1304
Test name
Test status
Simulation time 8408365712 ps
CPU time 9.14 seconds
Started May 07 12:42:54 PM PDT 24
Finished May 07 12:43:06 PM PDT 24
Peak memory 204160 kb
Host smart-110655b9-56dc-4d92-909b-ecdabf4142ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20896
34302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.2089634302
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3913815905
Short name T836
Test name
Test status
Simulation time 8414623462 ps
CPU time 8.4 seconds
Started May 07 12:42:47 PM PDT 24
Finished May 07 12:42:57 PM PDT 24
Peak memory 204128 kb
Host smart-5007fc45-f422-41a2-b39f-c490e2d8d5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39138
15905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3913815905
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.4115598209
Short name T1164
Test name
Test status
Simulation time 8375966941 ps
CPU time 7.95 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204084 kb
Host smart-8323289e-a2aa-4395-8047-5f819db4179a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41155
98209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.4115598209
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1320810758
Short name T1213
Test name
Test status
Simulation time 8410192477 ps
CPU time 8.37 seconds
Started May 07 12:42:41 PM PDT 24
Finished May 07 12:42:51 PM PDT 24
Peak memory 204128 kb
Host smart-6cc35560-9a5d-441b-b557-5b230b133151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13208
10758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1320810758
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1431746287
Short name T137
Test name
Test status
Simulation time 8381604074 ps
CPU time 7.68 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 203648 kb
Host smart-f70d6370-8c9f-4626-ac91-39799a8ed52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14317
46287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1431746287
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.833260780
Short name T1037
Test name
Test status
Simulation time 8411843951 ps
CPU time 7.74 seconds
Started May 07 12:42:53 PM PDT 24
Finished May 07 12:43:05 PM PDT 24
Peak memory 204084 kb
Host smart-00ca0058-a657-4698-9857-f184eb1795e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83326
0780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.833260780
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.3645721889
Short name T982
Test name
Test status
Simulation time 8467826830 ps
CPU time 10.14 seconds
Started May 07 12:42:53 PM PDT 24
Finished May 07 12:43:07 PM PDT 24
Peak memory 204140 kb
Host smart-f19e322f-52d8-42ea-aada-8a3424235a3d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3645721889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.3645721889
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.1140777421
Short name T1021
Test name
Test status
Simulation time 8446000651 ps
CPU time 7.59 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:58 PM PDT 24
Peak memory 204080 kb
Host smart-b2549931-aa5e-4321-8086-d89b8c7b8ebf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1140777421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.1140777421
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.3946552599
Short name T689
Test name
Test status
Simulation time 8466107837 ps
CPU time 9.55 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204000 kb
Host smart-28e5cede-5244-41eb-9562-042725a8cd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39465
52599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.3946552599
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3719982634
Short name T1291
Test name
Test status
Simulation time 8372188047 ps
CPU time 7.92 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:00 PM PDT 24
Peak memory 204084 kb
Host smart-e21defef-e54e-4260-8873-c55a492561b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37199
82634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3719982634
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.2501292329
Short name T1063
Test name
Test status
Simulation time 8400843169 ps
CPU time 8.47 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204116 kb
Host smart-038f65b5-abaf-4cfc-806c-1bd86a2cab03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25012
92329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2501292329
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.152551952
Short name T451
Test name
Test status
Simulation time 120683571 ps
CPU time 1.41 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:53 PM PDT 24
Peak memory 204156 kb
Host smart-1fa041a6-9003-4b21-9ce5-3e9a6b0940bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15255
1952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.152551952
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1690819323
Short name T791
Test name
Test status
Simulation time 8461215066 ps
CPU time 8.78 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:43:00 PM PDT 24
Peak memory 204096 kb
Host smart-51c8e021-848f-4c2e-bd20-3a4bd504a11b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16908
19323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1690819323
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.855224459
Short name T724
Test name
Test status
Simulation time 8384612955 ps
CPU time 7.67 seconds
Started May 07 12:42:54 PM PDT 24
Finished May 07 12:43:05 PM PDT 24
Peak memory 204008 kb
Host smart-f24256af-736b-4792-9936-b3627438b37d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85522
4459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.855224459
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3970574283
Short name T866
Test name
Test status
Simulation time 8388242676 ps
CPU time 7.95 seconds
Started May 07 12:42:46 PM PDT 24
Finished May 07 12:42:57 PM PDT 24
Peak memory 204116 kb
Host smart-e9aaa30a-bda0-45a5-98c6-f2b43ce4bdce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39705
74283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3970574283
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3251944509
Short name T618
Test name
Test status
Simulation time 8418499968 ps
CPU time 9.08 seconds
Started May 07 12:42:45 PM PDT 24
Finished May 07 12:42:56 PM PDT 24
Peak memory 204128 kb
Host smart-b82b8138-10a8-47b3-95f8-19f8739f7806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32519
44509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3251944509
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1080105711
Short name T1155
Test name
Test status
Simulation time 8372583456 ps
CPU time 7.61 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204120 kb
Host smart-e2aea5a4-41b5-4e8a-902b-efb3f2508e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10801
05711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1080105711
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.4092037768
Short name T1051
Test name
Test status
Simulation time 8436200721 ps
CPU time 7.7 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204088 kb
Host smart-57cbeb7e-0d9e-4bb9-9f75-ca6b95731069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40920
37768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.4092037768
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3187385673
Short name T941
Test name
Test status
Simulation time 8382625773 ps
CPU time 7.38 seconds
Started May 07 12:42:45 PM PDT 24
Finished May 07 12:42:54 PM PDT 24
Peak memory 204108 kb
Host smart-6eb5b57c-86e1-4af5-b44a-5298a29cb318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31873
85673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3187385673
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1301662651
Short name T1003
Test name
Test status
Simulation time 8412455266 ps
CPU time 7.68 seconds
Started May 07 12:42:58 PM PDT 24
Finished May 07 12:43:08 PM PDT 24
Peak memory 204128 kb
Host smart-a0087a16-35d7-4827-9dbb-179131552adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13016
62651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1301662651
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1977873251
Short name T1152
Test name
Test status
Simulation time 8420714734 ps
CPU time 7.74 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204120 kb
Host smart-ac8f6c4c-113d-4cf9-84b1-ba3c3008b54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19778
73251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1977873251
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2860126320
Short name T873
Test name
Test status
Simulation time 8374324716 ps
CPU time 8.15 seconds
Started May 07 12:42:44 PM PDT 24
Finished May 07 12:42:54 PM PDT 24
Peak memory 204044 kb
Host smart-1dd62b36-c464-41dc-b571-ea7e5893a513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28601
26320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2860126320
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.648197455
Short name T478
Test name
Test status
Simulation time 79800716 ps
CPU time 0.7 seconds
Started May 07 12:43:08 PM PDT 24
Finished May 07 12:43:11 PM PDT 24
Peak memory 203992 kb
Host smart-f4a4be34-652c-4557-bce8-5be56758d788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64819
7455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.648197455
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3563060225
Short name T1172
Test name
Test status
Simulation time 19702891442 ps
CPU time 34.88 seconds
Started May 07 12:43:01 PM PDT 24
Finished May 07 12:43:38 PM PDT 24
Peak memory 204396 kb
Host smart-38794eac-f682-49ea-a44f-0fe36d518dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35630
60225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3563060225
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2669652223
Short name T795
Test name
Test status
Simulation time 8403068023 ps
CPU time 7.89 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:42:59 PM PDT 24
Peak memory 204104 kb
Host smart-fe73263d-7685-4a93-aaff-6f1e17ee04e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26696
52223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2669652223
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2552898330
Short name T806
Test name
Test status
Simulation time 8449158964 ps
CPU time 9.4 seconds
Started May 07 12:43:01 PM PDT 24
Finished May 07 12:43:13 PM PDT 24
Peak memory 204104 kb
Host smart-90fa1a12-7054-4593-be1f-9e586095fe33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25528
98330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2552898330
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.251930873
Short name T563
Test name
Test status
Simulation time 8405475037 ps
CPU time 7.66 seconds
Started May 07 12:42:41 PM PDT 24
Finished May 07 12:42:50 PM PDT 24
Peak memory 204052 kb
Host smart-01f7f85c-35ef-44d8-9448-695461638c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25193
0873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.251930873
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3642790650
Short name T757
Test name
Test status
Simulation time 8378824792 ps
CPU time 8.88 seconds
Started May 07 12:42:44 PM PDT 24
Finished May 07 12:42:54 PM PDT 24
Peak memory 204112 kb
Host smart-bbec2a85-6ca5-41a0-8ae2-32d9a83f6f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36427
90650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3642790650
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2345415404
Short name T1255
Test name
Test status
Simulation time 8374109046 ps
CPU time 9.74 seconds
Started May 07 12:42:54 PM PDT 24
Finished May 07 12:43:08 PM PDT 24
Peak memory 204128 kb
Host smart-be2379ab-24e7-443d-9e7a-a592f28a8f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23454
15404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2345415404
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3338454500
Short name T151
Test name
Test status
Simulation time 8445773705 ps
CPU time 7.61 seconds
Started May 07 12:42:56 PM PDT 24
Finished May 07 12:43:06 PM PDT 24
Peak memory 204124 kb
Host smart-988c6784-aaa6-43f4-8d56-05d918af6396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33384
54500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3338454500
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1782529381
Short name T409
Test name
Test status
Simulation time 8406611779 ps
CPU time 8.16 seconds
Started May 07 12:43:14 PM PDT 24
Finished May 07 12:43:24 PM PDT 24
Peak memory 204032 kb
Host smart-5924bf2f-264a-479e-b601-1886cb48d5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17825
29381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1782529381
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.705074595
Short name T398
Test name
Test status
Simulation time 8383472078 ps
CPU time 8.16 seconds
Started May 07 12:42:46 PM PDT 24
Finished May 07 12:42:56 PM PDT 24
Peak memory 204120 kb
Host smart-eeebbe55-97db-49dd-aca4-d011c820f587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70507
4595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.705074595
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.803061766
Short name T44
Test name
Test status
Simulation time 8464220036 ps
CPU time 8.43 seconds
Started May 07 12:43:27 PM PDT 24
Finished May 07 12:43:38 PM PDT 24
Peak memory 204088 kb
Host smart-9102ac67-07d8-4bf7-9312-3e404ba7bce9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=803061766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.803061766
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.4046189796
Short name T1026
Test name
Test status
Simulation time 8381478061 ps
CPU time 8.54 seconds
Started May 07 12:43:09 PM PDT 24
Finished May 07 12:43:19 PM PDT 24
Peak memory 204100 kb
Host smart-0eb9dde6-3f09-41cd-842a-a1dfdd4eae26
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4046189796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.4046189796
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.3369780189
Short name T570
Test name
Test status
Simulation time 8394309831 ps
CPU time 7.77 seconds
Started May 07 12:43:03 PM PDT 24
Finished May 07 12:43:13 PM PDT 24
Peak memory 204104 kb
Host smart-4082d940-ad2c-4ed3-91b8-338eedd5745b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33697
80189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.3369780189
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.978488090
Short name T1161
Test name
Test status
Simulation time 8418255296 ps
CPU time 10.15 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204100 kb
Host smart-dfa8b16c-ae6c-49ac-8c9c-e88e47977b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97848
8090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.978488090
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.2872809231
Short name T324
Test name
Test status
Simulation time 8376817219 ps
CPU time 10.11 seconds
Started May 07 12:42:52 PM PDT 24
Finished May 07 12:43:06 PM PDT 24
Peak memory 204120 kb
Host smart-0a1fc89a-2f92-4143-a846-d32c958167f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28728
09231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2872809231
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1777254478
Short name T871
Test name
Test status
Simulation time 276029029 ps
CPU time 2.13 seconds
Started May 07 12:42:53 PM PDT 24
Finished May 07 12:42:59 PM PDT 24
Peak memory 204228 kb
Host smart-c4bbbb91-78ca-4956-a92c-feab523b5446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17772
54478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1777254478
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2448183856
Short name T859
Test name
Test status
Simulation time 8464492219 ps
CPU time 9.83 seconds
Started May 07 12:43:02 PM PDT 24
Finished May 07 12:43:14 PM PDT 24
Peak memory 204124 kb
Host smart-09727ab7-770e-4ea2-a4e9-a8e664e7211a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24481
83856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2448183856
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.693169710
Short name T1343
Test name
Test status
Simulation time 8364245711 ps
CPU time 8.6 seconds
Started May 07 12:43:10 PM PDT 24
Finished May 07 12:43:21 PM PDT 24
Peak memory 204108 kb
Host smart-f8acc16e-4e13-45c5-b39d-23f1ceeb35ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69316
9710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.693169710
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2312306557
Short name T1171
Test name
Test status
Simulation time 8408244528 ps
CPU time 8.37 seconds
Started May 07 12:42:57 PM PDT 24
Finished May 07 12:43:08 PM PDT 24
Peak memory 204112 kb
Host smart-fc6cf9a8-7a43-46bc-b206-9a84b140339c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23123
06557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2312306557
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1327297458
Short name T1351
Test name
Test status
Simulation time 8423943374 ps
CPU time 8.52 seconds
Started May 07 12:43:05 PM PDT 24
Finished May 07 12:43:16 PM PDT 24
Peak memory 204136 kb
Host smart-333e27c3-4a7e-4291-94cc-631d3f275c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13272
97458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1327297458
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3940349269
Short name T899
Test name
Test status
Simulation time 8367631285 ps
CPU time 10.06 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204084 kb
Host smart-49fa46dc-2665-4a1e-bb2f-fe90c5112668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39403
49269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3940349269
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2775161511
Short name T114
Test name
Test status
Simulation time 8400612194 ps
CPU time 7.57 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204172 kb
Host smart-fdec8bf0-5a46-4054-8403-ad7574440ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27751
61511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2775161511
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2307380752
Short name T462
Test name
Test status
Simulation time 8407830387 ps
CPU time 8.09 seconds
Started May 07 12:43:14 PM PDT 24
Finished May 07 12:43:23 PM PDT 24
Peak memory 204120 kb
Host smart-404e939f-c4df-433d-b1aa-fa1ba62ab0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23073
80752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2307380752
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2142663125
Short name T225
Test name
Test status
Simulation time 8437048723 ps
CPU time 8.66 seconds
Started May 07 12:42:58 PM PDT 24
Finished May 07 12:43:09 PM PDT 24
Peak memory 204120 kb
Host smart-6b94af92-fcc5-45f3-9e44-72a151012154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21426
63125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2142663125
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3145559126
Short name T190
Test name
Test status
Simulation time 8469377535 ps
CPU time 8.58 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:04 PM PDT 24
Peak memory 204072 kb
Host smart-d2c193eb-e62f-499d-86d6-f4fdfd1f5f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31455
59126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3145559126
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1870620414
Short name T679
Test name
Test status
Simulation time 8369414335 ps
CPU time 7.57 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:00 PM PDT 24
Peak memory 204128 kb
Host smart-90ebb454-40bc-4e5f-8339-e9269daa4a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18706
20414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1870620414
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2931986204
Short name T581
Test name
Test status
Simulation time 57943076 ps
CPU time 0.66 seconds
Started May 07 12:42:53 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 203968 kb
Host smart-d15c6da3-9ac0-4401-872d-67e8b2ba9aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29319
86204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2931986204
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3537751355
Short name T233
Test name
Test status
Simulation time 30768527768 ps
CPU time 64.54 seconds
Started May 07 12:42:49 PM PDT 24
Finished May 07 12:43:56 PM PDT 24
Peak memory 204404 kb
Host smart-82169363-f567-45f1-94fe-8a6c09c3c842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35377
51355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3537751355
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2638902596
Short name T830
Test name
Test status
Simulation time 8408301759 ps
CPU time 7.99 seconds
Started May 07 12:43:02 PM PDT 24
Finished May 07 12:43:12 PM PDT 24
Peak memory 204092 kb
Host smart-a45231c9-f74a-49b8-afb5-049c25d4247a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26389
02596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2638902596
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.4155077950
Short name T497
Test name
Test status
Simulation time 8426922055 ps
CPU time 8.08 seconds
Started May 07 12:43:04 PM PDT 24
Finished May 07 12:43:14 PM PDT 24
Peak memory 204144 kb
Host smart-d2874221-20d1-4c1b-a0a8-d58eb818fdce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41550
77950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.4155077950
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.1965006797
Short name T880
Test name
Test status
Simulation time 8377407506 ps
CPU time 7.88 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204148 kb
Host smart-d2303126-2a4d-4add-85e3-ad19f527b6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19650
06797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.1965006797
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.1532877612
Short name T182
Test name
Test status
Simulation time 8373071574 ps
CPU time 8.86 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:29 PM PDT 24
Peak memory 204084 kb
Host smart-902a0087-5da5-4961-a116-00cb5d30cc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15328
77612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1532877612
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2095622698
Short name T25
Test name
Test status
Simulation time 8370488679 ps
CPU time 8.03 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204116 kb
Host smart-dfe1c745-86b8-40ec-9a14-6cdc12d651ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20956
22698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2095622698
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1560690
Short name T1006
Test name
Test status
Simulation time 8415155134 ps
CPU time 8.08 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 204120 kb
Host smart-7c1ae223-afeb-4a78-85c9-53c23ff00ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15606
90 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1560690
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.148938877
Short name T932
Test name
Test status
Simulation time 8433559556 ps
CPU time 8.75 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:03 PM PDT 24
Peak memory 204116 kb
Host smart-df5d6e25-add5-4961-9b1b-de074c040b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14893
8877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.148938877
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1625642219
Short name T410
Test name
Test status
Simulation time 8375083083 ps
CPU time 8.87 seconds
Started May 07 12:43:13 PM PDT 24
Finished May 07 12:43:23 PM PDT 24
Peak memory 204108 kb
Host smart-fc10a9c0-a96a-45eb-9c08-aa22234a1bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16256
42219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1625642219
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.505089410
Short name T445
Test name
Test status
Simulation time 8531859943 ps
CPU time 7.7 seconds
Started May 07 12:41:26 PM PDT 24
Finished May 07 12:41:35 PM PDT 24
Peak memory 204108 kb
Host smart-405bf1ae-b6ec-444c-aa07-ac75b3452647
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=505089410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.505089410
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.2012964632
Short name T521
Test name
Test status
Simulation time 8382270647 ps
CPU time 7.68 seconds
Started May 07 12:41:32 PM PDT 24
Finished May 07 12:41:44 PM PDT 24
Peak memory 204124 kb
Host smart-ba3faec4-5438-4310-ad6e-cbdbdeb3ac84
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2012964632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.2012964632
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.2793822927
Short name T153
Test name
Test status
Simulation time 8412858498 ps
CPU time 7.4 seconds
Started May 07 12:41:21 PM PDT 24
Finished May 07 12:41:30 PM PDT 24
Peak memory 204120 kb
Host smart-df32701f-6662-4850-b8cb-a1a392907e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27938
22927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.2793822927
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.574550709
Short name T885
Test name
Test status
Simulation time 8382296327 ps
CPU time 8.29 seconds
Started May 07 12:41:41 PM PDT 24
Finished May 07 12:41:51 PM PDT 24
Peak memory 204096 kb
Host smart-9a9bdc81-51fe-4865-9596-87c4864a7087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57455
0709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.574550709
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.2988526271
Short name T750
Test name
Test status
Simulation time 8405241281 ps
CPU time 7.77 seconds
Started May 07 12:41:22 PM PDT 24
Finished May 07 12:41:31 PM PDT 24
Peak memory 204128 kb
Host smart-48039e14-b98a-4e7d-a845-598e143d1455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29885
26271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2988526271
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3361061045
Short name T469
Test name
Test status
Simulation time 203274073 ps
CPU time 1.6 seconds
Started May 07 12:41:16 PM PDT 24
Finished May 07 12:41:19 PM PDT 24
Peak memory 204208 kb
Host smart-54feba04-4043-40f8-9acb-e07c112743d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33610
61045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3361061045
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3019597314
Short name T81
Test name
Test status
Simulation time 8421187110 ps
CPU time 7.62 seconds
Started May 07 12:41:07 PM PDT 24
Finished May 07 12:41:16 PM PDT 24
Peak memory 204132 kb
Host smart-4b0b769a-b557-45d6-b5ec-4814be1f89d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30195
97314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3019597314
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3116060903
Short name T972
Test name
Test status
Simulation time 8365035014 ps
CPU time 7.62 seconds
Started May 07 12:41:24 PM PDT 24
Finished May 07 12:41:33 PM PDT 24
Peak memory 204100 kb
Host smart-54a3676f-be6e-4854-a368-babde9163d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31160
60903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3116060903
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.251776094
Short name T950
Test name
Test status
Simulation time 8392271729 ps
CPU time 8.67 seconds
Started May 07 12:41:29 PM PDT 24
Finished May 07 12:41:38 PM PDT 24
Peak memory 204084 kb
Host smart-71daea4f-df65-4fe6-bb67-393db4e668de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25177
6094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.251776094
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3785418389
Short name T1056
Test name
Test status
Simulation time 8465360285 ps
CPU time 8.04 seconds
Started May 07 12:41:20 PM PDT 24
Finished May 07 12:41:28 PM PDT 24
Peak memory 204124 kb
Host smart-81f611c9-2296-4a5b-a201-1c38311b33fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37854
18389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3785418389
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3535594661
Short name T707
Test name
Test status
Simulation time 8368340993 ps
CPU time 7.47 seconds
Started May 07 12:41:24 PM PDT 24
Finished May 07 12:41:33 PM PDT 24
Peak memory 204144 kb
Host smart-cfc5ba56-be63-4fa5-8cc5-d85aa8a09547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35355
94661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3535594661
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.792859596
Short name T1181
Test name
Test status
Simulation time 8406073781 ps
CPU time 8.03 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204100 kb
Host smart-4b4a0585-7f4f-43f3-b122-04bdfa92879e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79285
9596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.792859596
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3656668470
Short name T363
Test name
Test status
Simulation time 8388559592 ps
CPU time 9.66 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204132 kb
Host smart-9a3089c5-2cfd-41ea-abd7-a41d0643240f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36566
68470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3656668470
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1178376836
Short name T199
Test name
Test status
Simulation time 8383042594 ps
CPU time 7.54 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:44 PM PDT 24
Peak memory 204140 kb
Host smart-60797423-185b-4599-b5d6-2e24c303c7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11783
76836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1178376836
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3499052975
Short name T1176
Test name
Test status
Simulation time 8376736913 ps
CPU time 8.65 seconds
Started May 07 12:41:31 PM PDT 24
Finished May 07 12:41:41 PM PDT 24
Peak memory 204128 kb
Host smart-07f380a3-1b10-46e6-ab56-35cf654dbb56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34990
52975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3499052975
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2046419430
Short name T717
Test name
Test status
Simulation time 34221286 ps
CPU time 0.65 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:37 PM PDT 24
Peak memory 203972 kb
Host smart-00d7db74-0235-418a-a37a-4dce4db6b6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20464
19430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2046419430
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.42608697
Short name T1215
Test name
Test status
Simulation time 16035513058 ps
CPU time 30.06 seconds
Started May 07 12:41:10 PM PDT 24
Finished May 07 12:41:42 PM PDT 24
Peak memory 204416 kb
Host smart-7da73e70-fd49-4938-969b-e76ecb469d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42608
697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.42608697
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3481835888
Short name T788
Test name
Test status
Simulation time 8462533800 ps
CPU time 8.61 seconds
Started May 07 12:41:30 PM PDT 24
Finished May 07 12:41:40 PM PDT 24
Peak memory 204132 kb
Host smart-a1a1a939-81fc-4bdf-a764-6cfc3d81eceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34818
35888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3481835888
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2738041669
Short name T913
Test name
Test status
Simulation time 8464031820 ps
CPU time 9.16 seconds
Started May 07 12:41:23 PM PDT 24
Finished May 07 12:41:34 PM PDT 24
Peak memory 204096 kb
Host smart-7a4540dd-4294-4e18-af4b-57df4ea0def0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27380
41669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2738041669
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.1134678025
Short name T746
Test name
Test status
Simulation time 8407956597 ps
CPU time 8.21 seconds
Started May 07 12:41:21 PM PDT 24
Finished May 07 12:41:30 PM PDT 24
Peak memory 204124 kb
Host smart-5ab49c2d-fef5-4b90-8cd0-7675db9becca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11346
78025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.1134678025
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2845748291
Short name T78
Test name
Test status
Simulation time 198257386 ps
CPU time 1.03 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:35 PM PDT 24
Peak memory 220296 kb
Host smart-bb1c6852-97cd-4fb9-8677-f541e745826e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2845748291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2845748291
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1750727706
Short name T496
Test name
Test status
Simulation time 8376851074 ps
CPU time 7.88 seconds
Started May 07 12:41:36 PM PDT 24
Finished May 07 12:41:45 PM PDT 24
Peak memory 204100 kb
Host smart-4beb46a4-6eb0-4cff-ad2f-69016b0b25bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17507
27706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1750727706
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2906583965
Short name T734
Test name
Test status
Simulation time 8361180999 ps
CPU time 8.12 seconds
Started May 07 12:41:31 PM PDT 24
Finished May 07 12:41:41 PM PDT 24
Peak memory 204100 kb
Host smart-a467d173-a0e6-40f6-8280-11f880e6bb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29065
83965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2906583965
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2191476290
Short name T159
Test name
Test status
Simulation time 8400915611 ps
CPU time 7.83 seconds
Started May 07 12:41:38 PM PDT 24
Finished May 07 12:41:48 PM PDT 24
Peak memory 204124 kb
Host smart-ccfef5ef-a095-46e0-b811-e5aefac6d8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21914
76290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2191476290
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3181499591
Short name T693
Test name
Test status
Simulation time 8428229552 ps
CPU time 7.79 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204088 kb
Host smart-fb0bd70c-0dea-4d7f-92a6-c7ce9c3c7cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31814
99591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3181499591
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3102990915
Short name T1169
Test name
Test status
Simulation time 8401711815 ps
CPU time 10.25 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204132 kb
Host smart-cc7f0371-eb3f-4e07-bd5d-b7f299c1e7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31029
90915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3102990915
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.2659926868
Short name T677
Test name
Test status
Simulation time 8461815578 ps
CPU time 7.93 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204128 kb
Host smart-263b79d3-bb6f-415f-96e9-ed489fc07c02
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2659926868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.2659926868
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.3174986091
Short name T349
Test name
Test status
Simulation time 8377506179 ps
CPU time 9.05 seconds
Started May 07 12:43:03 PM PDT 24
Finished May 07 12:43:14 PM PDT 24
Peak memory 204308 kb
Host smart-4e4a220e-c18b-4ea5-9fe8-5f03d27509d5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3174986091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.3174986091
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.3886231847
Short name T1018
Test name
Test status
Simulation time 8491874046 ps
CPU time 7.54 seconds
Started May 07 12:43:00 PM PDT 24
Finished May 07 12:43:10 PM PDT 24
Peak memory 204308 kb
Host smart-5ac1dbbb-a2fe-472b-b8f1-fc7c76678b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38862
31847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.3886231847
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.639432914
Short name T1057
Test name
Test status
Simulation time 8420164933 ps
CPU time 7.79 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:02 PM PDT 24
Peak memory 203632 kb
Host smart-67a14300-edfb-40b3-9483-c0e59513490c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63943
2914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.639432914
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3665914408
Short name T217
Test name
Test status
Simulation time 104596433 ps
CPU time 1.29 seconds
Started May 07 12:42:54 PM PDT 24
Finished May 07 12:42:59 PM PDT 24
Peak memory 204280 kb
Host smart-63e4125c-b4f7-4e7a-9eb6-8274fa86adf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36659
14408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3665914408
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.2532019402
Short name T1207
Test name
Test status
Simulation time 8423217459 ps
CPU time 8.55 seconds
Started May 07 12:43:20 PM PDT 24
Finished May 07 12:43:30 PM PDT 24
Peak memory 204032 kb
Host smart-f912b7fd-fb40-4956-ad52-a7d5d0d69512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25320
19402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2532019402
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3768135993
Short name T1116
Test name
Test status
Simulation time 8364469580 ps
CPU time 7.75 seconds
Started May 07 12:43:13 PM PDT 24
Finished May 07 12:43:23 PM PDT 24
Peak memory 204040 kb
Host smart-4a4afecc-8b75-4502-b4b6-9d8cb22e49b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37681
35993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3768135993
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.556423219
Short name T1352
Test name
Test status
Simulation time 8421802072 ps
CPU time 7.95 seconds
Started May 07 12:42:56 PM PDT 24
Finished May 07 12:43:07 PM PDT 24
Peak memory 204128 kb
Host smart-df68c0ca-2187-46bc-80d3-3965ea81ea78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55642
3219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.556423219
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.4219632649
Short name T331
Test name
Test status
Simulation time 8416792481 ps
CPU time 7.97 seconds
Started May 07 12:43:16 PM PDT 24
Finished May 07 12:43:24 PM PDT 24
Peak memory 204120 kb
Host smart-2524c262-7ab9-4bff-ae17-dd4a41b7e999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42196
32649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.4219632649
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.615109641
Short name T1079
Test name
Test status
Simulation time 8369763559 ps
CPU time 8.14 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:31 PM PDT 24
Peak memory 204156 kb
Host smart-d0721ba7-68b9-42ea-82f9-1c5d161ce75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61510
9641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.615109641
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.4022803832
Short name T133
Test name
Test status
Simulation time 8440467707 ps
CPU time 8.12 seconds
Started May 07 12:43:14 PM PDT 24
Finished May 07 12:43:23 PM PDT 24
Peak memory 204104 kb
Host smart-10ca0409-30b0-4c89-8a30-9381adaef0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40228
03832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.4022803832
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.897337485
Short name T823
Test name
Test status
Simulation time 8389175860 ps
CPU time 8.28 seconds
Started May 07 12:43:07 PM PDT 24
Finished May 07 12:43:17 PM PDT 24
Peak memory 204144 kb
Host smart-b2aa4310-32b5-4077-b3e5-2229a2f87741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89733
7485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.897337485
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.63630948
Short name T333
Test name
Test status
Simulation time 8398550283 ps
CPU time 7.89 seconds
Started May 07 12:42:48 PM PDT 24
Finished May 07 12:42:59 PM PDT 24
Peak memory 204120 kb
Host smart-6f844a07-ce2d-489b-a70b-e12e351b61e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63630
948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.63630948
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.514000533
Short name T169
Test name
Test status
Simulation time 8448720441 ps
CPU time 9.34 seconds
Started May 07 12:43:10 PM PDT 24
Finished May 07 12:43:22 PM PDT 24
Peak memory 204024 kb
Host smart-9c73b359-1b89-4c8f-8bf7-0f83b40bb3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51400
0533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.514000533
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3958184446
Short name T1203
Test name
Test status
Simulation time 8370457411 ps
CPU time 7.52 seconds
Started May 07 12:43:05 PM PDT 24
Finished May 07 12:43:14 PM PDT 24
Peak memory 204136 kb
Host smart-3e41b159-5f42-41e4-811f-09a36a26266b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39581
84446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3958184446
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3978737648
Short name T1360
Test name
Test status
Simulation time 44588242 ps
CPU time 0.65 seconds
Started May 07 12:42:57 PM PDT 24
Finished May 07 12:43:00 PM PDT 24
Peak memory 203968 kb
Host smart-093eab45-2a5c-4b17-a3b3-47d348a149f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39787
37648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3978737648
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2405452399
Short name T879
Test name
Test status
Simulation time 23775992810 ps
CPU time 49.86 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:44 PM PDT 24
Peak memory 204356 kb
Host smart-9f053835-f6a6-47f7-baed-7a7ee7a6e4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24054
52399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2405452399
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.4207712510
Short name T1109
Test name
Test status
Simulation time 8417483321 ps
CPU time 10.07 seconds
Started May 07 12:43:08 PM PDT 24
Finished May 07 12:43:20 PM PDT 24
Peak memory 204092 kb
Host smart-918d7d66-1736-4a2e-9933-5e1ed8623749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42077
12510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.4207712510
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1883487673
Short name T1120
Test name
Test status
Simulation time 8412488648 ps
CPU time 9.25 seconds
Started May 07 12:42:51 PM PDT 24
Finished May 07 12:43:04 PM PDT 24
Peak memory 204124 kb
Host smart-854d7ca4-5f19-4d4c-8ddd-a21a9de81db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18834
87673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1883487673
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.2776737042
Short name T1045
Test name
Test status
Simulation time 8387499761 ps
CPU time 8.71 seconds
Started May 07 12:43:12 PM PDT 24
Finished May 07 12:43:22 PM PDT 24
Peak memory 204140 kb
Host smart-06000d6f-a719-4c1a-aaed-f3c3d45de6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27767
37042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.2776737042
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1524175733
Short name T616
Test name
Test status
Simulation time 8377448874 ps
CPU time 7.6 seconds
Started May 07 12:42:59 PM PDT 24
Finished May 07 12:43:09 PM PDT 24
Peak memory 204300 kb
Host smart-b5cd35f5-9dcc-4bb2-809f-a5f102bc30d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15241
75733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1524175733
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1422424325
Short name T1070
Test name
Test status
Simulation time 8368407275 ps
CPU time 9.28 seconds
Started May 07 12:43:15 PM PDT 24
Finished May 07 12:43:25 PM PDT 24
Peak memory 204072 kb
Host smart-d836ff20-8394-4af1-b7b2-0890f72117b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14224
24325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1422424325
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3764149768
Short name T567
Test name
Test status
Simulation time 8436813404 ps
CPU time 8.31 seconds
Started May 07 12:43:10 PM PDT 24
Finished May 07 12:43:21 PM PDT 24
Peak memory 204136 kb
Host smart-78290fd6-00fb-4690-bf60-3383c5e14509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37641
49768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3764149768
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1082394556
Short name T722
Test name
Test status
Simulation time 8396056675 ps
CPU time 7.95 seconds
Started May 07 12:42:56 PM PDT 24
Finished May 07 12:43:07 PM PDT 24
Peak memory 204128 kb
Host smart-f7851d80-f419-472a-b937-03b31b563d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10823
94556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1082394556
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3576744726
Short name T1177
Test name
Test status
Simulation time 8377947469 ps
CPU time 7.98 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204116 kb
Host smart-7ce1a452-a19c-4f55-9735-945e0a6ebc74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767
44726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3576744726
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.3742591894
Short name T566
Test name
Test status
Simulation time 8476817574 ps
CPU time 9.69 seconds
Started May 07 12:43:15 PM PDT 24
Finished May 07 12:43:25 PM PDT 24
Peak memory 204124 kb
Host smart-e7f9353f-62b0-4c99-84c4-877a8e8fe4ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3742591894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.3742591894
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.2548347758
Short name T870
Test name
Test status
Simulation time 8388097257 ps
CPU time 9.46 seconds
Started May 07 12:43:07 PM PDT 24
Finished May 07 12:43:19 PM PDT 24
Peak memory 204100 kb
Host smart-0a84e58b-a382-4034-9680-73efd9136eef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2548347758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.2548347758
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.3621922287
Short name T832
Test name
Test status
Simulation time 8410072421 ps
CPU time 8.63 seconds
Started May 07 12:43:30 PM PDT 24
Finished May 07 12:43:41 PM PDT 24
Peak memory 204092 kb
Host smart-8d698e06-3338-4d84-867a-b3983c7daf37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36219
22287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.3621922287
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3900048712
Short name T1049
Test name
Test status
Simulation time 8374616066 ps
CPU time 7.54 seconds
Started May 07 12:43:07 PM PDT 24
Finished May 07 12:43:17 PM PDT 24
Peak memory 204092 kb
Host smart-804c494a-1f31-4ccd-a38d-c471574f258d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39000
48712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3900048712
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.781778770
Short name T651
Test name
Test status
Simulation time 8370760395 ps
CPU time 7.67 seconds
Started May 07 12:43:01 PM PDT 24
Finished May 07 12:43:11 PM PDT 24
Peak memory 204112 kb
Host smart-2a3aaf99-fc16-44ae-8676-86f1aacd6f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78177
8770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.781778770
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3192601334
Short name T55
Test name
Test status
Simulation time 69003121 ps
CPU time 1.69 seconds
Started May 07 12:43:16 PM PDT 24
Finished May 07 12:43:20 PM PDT 24
Peak memory 204184 kb
Host smart-4d03b587-c259-4c7c-9b7e-791eae8ccf52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31926
01334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3192601334
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1016950649
Short name T815
Test name
Test status
Simulation time 8457533278 ps
CPU time 8.25 seconds
Started May 07 12:43:03 PM PDT 24
Finished May 07 12:43:13 PM PDT 24
Peak memory 204092 kb
Host smart-740d407c-ae74-4f88-b965-163d6a38b44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10169
50649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1016950649
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.949020784
Short name T1185
Test name
Test status
Simulation time 8362385194 ps
CPU time 8.1 seconds
Started May 07 12:43:08 PM PDT 24
Finished May 07 12:43:19 PM PDT 24
Peak memory 203628 kb
Host smart-119287a0-309a-4721-9c3d-40925d613529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94902
0784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.949020784
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2953476290
Short name T843
Test name
Test status
Simulation time 8432910968 ps
CPU time 8.55 seconds
Started May 07 12:43:06 PM PDT 24
Finished May 07 12:43:17 PM PDT 24
Peak memory 204068 kb
Host smart-fff3c17a-9833-4662-97b6-6a2ceefe412c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29534
76290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2953476290
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2385126656
Short name T889
Test name
Test status
Simulation time 8421187057 ps
CPU time 9.17 seconds
Started May 07 12:43:17 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204136 kb
Host smart-080f4330-d751-45fd-83dd-06b33f8f6109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23851
26656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2385126656
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.175683056
Short name T1134
Test name
Test status
Simulation time 8384920948 ps
CPU time 9.64 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:33 PM PDT 24
Peak memory 204124 kb
Host smart-180408ef-d82c-4226-aeee-e387c12dfd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17568
3056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.175683056
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2510783292
Short name T135
Test name
Test status
Simulation time 8457790189 ps
CPU time 8.38 seconds
Started May 07 12:43:02 PM PDT 24
Finished May 07 12:43:13 PM PDT 24
Peak memory 204028 kb
Host smart-5dd918df-6b80-4987-9e31-879cd06f5070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25107
83292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2510783292
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1320194206
Short name T1251
Test name
Test status
Simulation time 8408657257 ps
CPU time 8.95 seconds
Started May 07 12:43:16 PM PDT 24
Finished May 07 12:43:26 PM PDT 24
Peak memory 204120 kb
Host smart-c02f6690-fa6c-4a4e-a9d2-3f435ab68a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13201
94206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1320194206
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2823797152
Short name T997
Test name
Test status
Simulation time 8385271400 ps
CPU time 9.82 seconds
Started May 07 12:43:02 PM PDT 24
Finished May 07 12:43:14 PM PDT 24
Peak memory 204120 kb
Host smart-55d04d53-8ca3-46cd-a524-65d10312ffc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28237
97152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2823797152
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3056861851
Short name T189
Test name
Test status
Simulation time 8421925211 ps
CPU time 7.49 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204176 kb
Host smart-d8c40b61-2455-47d7-9b1b-b429a2d9bb60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30568
61851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3056861851
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3299135606
Short name T1118
Test name
Test status
Simulation time 8370157088 ps
CPU time 8.12 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:31 PM PDT 24
Peak memory 204100 kb
Host smart-55d14553-6654-40ec-aa61-127f0e4d20d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32991
35606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3299135606
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.837340675
Short name T713
Test name
Test status
Simulation time 49618947 ps
CPU time 0.66 seconds
Started May 07 12:42:57 PM PDT 24
Finished May 07 12:43:00 PM PDT 24
Peak memory 203968 kb
Host smart-5b682952-4166-4fb2-adcb-c882f2f116a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83734
0675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.837340675
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3273415817
Short name T234
Test name
Test status
Simulation time 16025041365 ps
CPU time 26.94 seconds
Started May 07 12:42:52 PM PDT 24
Finished May 07 12:43:23 PM PDT 24
Peak memory 204388 kb
Host smart-14998b07-fafe-4c5c-a1c6-1f5c18512151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32734
15817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3273415817
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.4201381176
Short name T897
Test name
Test status
Simulation time 8376633952 ps
CPU time 7.3 seconds
Started May 07 12:43:07 PM PDT 24
Finished May 07 12:43:16 PM PDT 24
Peak memory 204120 kb
Host smart-e0671202-7e7c-438c-bb85-1146c029ccea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42013
81176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.4201381176
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1729029351
Short name T156
Test name
Test status
Simulation time 8407390898 ps
CPU time 8.78 seconds
Started May 07 12:42:56 PM PDT 24
Finished May 07 12:43:08 PM PDT 24
Peak memory 204132 kb
Host smart-c96a8581-0eb9-4ecf-9221-840bf96cd4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17290
29351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1729029351
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.3231748947
Short name T621
Test name
Test status
Simulation time 8394744678 ps
CPU time 7.64 seconds
Started May 07 12:43:07 PM PDT 24
Finished May 07 12:43:17 PM PDT 24
Peak memory 204148 kb
Host smart-6536f5e0-8587-4b1d-bff5-f81c932dd447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32317
48947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.3231748947
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2377335727
Short name T1270
Test name
Test status
Simulation time 8465757349 ps
CPU time 7.51 seconds
Started May 07 12:42:50 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 204116 kb
Host smart-b71ab810-e633-49de-a7c6-dc0ba24cf32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23773
35727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2377335727
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1631440379
Short name T1028
Test name
Test status
Simulation time 8372823339 ps
CPU time 7.79 seconds
Started May 07 12:43:04 PM PDT 24
Finished May 07 12:43:14 PM PDT 24
Peak memory 204040 kb
Host smart-4dcc9f9f-a5a4-4195-aaf5-442d2bcec04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16314
40379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1631440379
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2213921082
Short name T342
Test name
Test status
Simulation time 8373594888 ps
CPU time 8.83 seconds
Started May 07 12:43:06 PM PDT 24
Finished May 07 12:43:17 PM PDT 24
Peak memory 204092 kb
Host smart-a712164b-836d-4639-94a8-c24c66a405a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22139
21082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2213921082
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1496655390
Short name T368
Test name
Test status
Simulation time 8400145100 ps
CPU time 7.74 seconds
Started May 07 12:43:15 PM PDT 24
Finished May 07 12:43:23 PM PDT 24
Peak memory 204128 kb
Host smart-8ade4f68-5d47-461c-974c-1a6330cdefae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14966
55390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1496655390
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.3983530040
Short name T507
Test name
Test status
Simulation time 8371956252 ps
CPU time 10.15 seconds
Started May 07 12:43:11 PM PDT 24
Finished May 07 12:43:23 PM PDT 24
Peak memory 204104 kb
Host smart-3e95a17a-d5e8-4340-b929-6028f4fe3fb6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3983530040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.3983530040
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.4226386792
Short name T759
Test name
Test status
Simulation time 8390527031 ps
CPU time 9.99 seconds
Started May 07 12:43:06 PM PDT 24
Finished May 07 12:43:18 PM PDT 24
Peak memory 204028 kb
Host smart-107a57a7-6977-489e-a3ea-0e603d862cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42263
86792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.4226386792
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1714748679
Short name T794
Test name
Test status
Simulation time 8390292312 ps
CPU time 8.02 seconds
Started May 07 12:42:57 PM PDT 24
Finished May 07 12:43:08 PM PDT 24
Peak memory 204132 kb
Host smart-f4d709c6-90ba-4732-886b-2e8d5b9d8fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17147
48679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1714748679
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.1620153514
Short name T1224
Test name
Test status
Simulation time 8380755447 ps
CPU time 10.27 seconds
Started May 07 12:43:19 PM PDT 24
Finished May 07 12:43:31 PM PDT 24
Peak memory 204112 kb
Host smart-31272971-791f-462d-9dd6-bf85a451de2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16201
53514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1620153514
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3863147740
Short name T708
Test name
Test status
Simulation time 219177023 ps
CPU time 1.78 seconds
Started May 07 12:43:11 PM PDT 24
Finished May 07 12:43:15 PM PDT 24
Peak memory 204160 kb
Host smart-5b3ace0c-8773-47e5-b994-acd82cb50be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38631
47740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3863147740
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.3327588480
Short name T549
Test name
Test status
Simulation time 8444969244 ps
CPU time 7.94 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:34 PM PDT 24
Peak memory 204092 kb
Host smart-19af55d6-085d-419f-ae2f-847e5a6c8bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33275
88480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3327588480
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1928931813
Short name T536
Test name
Test status
Simulation time 8379086835 ps
CPU time 7.64 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:31 PM PDT 24
Peak memory 204104 kb
Host smart-5eee048c-ffa2-459c-bf98-1fcc2790b9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19289
31813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1928931813
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.934900808
Short name T1136
Test name
Test status
Simulation time 8498442177 ps
CPU time 10.82 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204140 kb
Host smart-9959660b-95b4-48fe-94c5-43867a344c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93490
0808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.934900808
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1116177022
Short name T537
Test name
Test status
Simulation time 8446082333 ps
CPU time 8.52 seconds
Started May 07 12:43:26 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 204144 kb
Host smart-1e415ec8-22ba-42c0-9b14-ded27232d32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11161
77022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1116177022
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3366389753
Short name T387
Test name
Test status
Simulation time 8381043128 ps
CPU time 9.41 seconds
Started May 07 12:43:10 PM PDT 24
Finished May 07 12:43:22 PM PDT 24
Peak memory 204136 kb
Host smart-a834549a-77c3-448c-a650-c1ef32d67b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33663
89753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3366389753
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2104186160
Short name T1361
Test name
Test status
Simulation time 8464285416 ps
CPU time 8.31 seconds
Started May 07 12:43:19 PM PDT 24
Finished May 07 12:43:29 PM PDT 24
Peak memory 204120 kb
Host smart-67dce9d3-6b8b-4545-935a-fde72b2d1042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21041
86160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2104186160
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.2983189436
Short name T625
Test name
Test status
Simulation time 8433475708 ps
CPU time 8.83 seconds
Started May 07 12:43:06 PM PDT 24
Finished May 07 12:43:17 PM PDT 24
Peak memory 204108 kb
Host smart-7e9c61d8-171a-4d70-9354-7cd2ee4b3e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29831
89436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2983189436
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2359876630
Short name T712
Test name
Test status
Simulation time 8402249410 ps
CPU time 8.45 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204084 kb
Host smart-b6a852a4-9a70-43ed-8858-bd0a1ef187bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23598
76630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2359876630
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1576515461
Short name T738
Test name
Test status
Simulation time 8380778269 ps
CPU time 7.72 seconds
Started May 07 12:43:12 PM PDT 24
Finished May 07 12:43:21 PM PDT 24
Peak memory 204148 kb
Host smart-e4ba4415-4737-45a3-a7bc-9239a41b7f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15765
15461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1576515461
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.354606945
Short name T8
Test name
Test status
Simulation time 8445516966 ps
CPU time 8.07 seconds
Started May 07 12:43:08 PM PDT 24
Finished May 07 12:43:18 PM PDT 24
Peak memory 204120 kb
Host smart-8e463012-5f64-45a5-a7c3-2ef090c0578a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35460
6945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.354606945
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2489324762
Short name T698
Test name
Test status
Simulation time 89724407 ps
CPU time 0.73 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 203976 kb
Host smart-143a62f1-13ac-4fcd-b6a1-7c0f69ad7a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24893
24762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2489324762
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.884862864
Short name T637
Test name
Test status
Simulation time 18780273071 ps
CPU time 33.26 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:44:00 PM PDT 24
Peak memory 204308 kb
Host smart-2dc53a13-0485-40c6-bce8-cd6b486decc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88486
2864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.884862864
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3191657416
Short name T723
Test name
Test status
Simulation time 8386432729 ps
CPU time 10.2 seconds
Started May 07 12:43:17 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204112 kb
Host smart-c97d6972-dc96-404c-ad3b-bb8b3ac1da57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31916
57416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3191657416
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.4046373605
Short name T803
Test name
Test status
Simulation time 8384491673 ps
CPU time 10.62 seconds
Started May 07 12:43:17 PM PDT 24
Finished May 07 12:43:29 PM PDT 24
Peak memory 204116 kb
Host smart-0370b057-21cb-4e30-8289-761e997d9c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40463
73605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.4046373605
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.2979013885
Short name T1066
Test name
Test status
Simulation time 8414321086 ps
CPU time 7.87 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:27 PM PDT 24
Peak memory 204136 kb
Host smart-8121883c-c7d8-413d-a142-27ddad4cbd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29790
13885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.2979013885
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3399620664
Short name T604
Test name
Test status
Simulation time 8375169497 ps
CPU time 8.32 seconds
Started May 07 12:43:10 PM PDT 24
Finished May 07 12:43:20 PM PDT 24
Peak memory 204064 kb
Host smart-65780896-9f6e-49ea-ab6a-976fc5858f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33996
20664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3399620664
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1177584478
Short name T863
Test name
Test status
Simulation time 8361597899 ps
CPU time 8.64 seconds
Started May 07 12:43:20 PM PDT 24
Finished May 07 12:43:30 PM PDT 24
Peak memory 204072 kb
Host smart-64fcd46f-81be-4b03-b7d5-2139f6fe746b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11775
84478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1177584478
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2410235123
Short name T606
Test name
Test status
Simulation time 8429740986 ps
CPU time 7.7 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204176 kb
Host smart-7993ffbd-6a3f-467d-b718-33647b624cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24102
35123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2410235123
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1344645084
Short name T1348
Test name
Test status
Simulation time 8393889069 ps
CPU time 9.66 seconds
Started May 07 12:43:08 PM PDT 24
Finished May 07 12:43:20 PM PDT 24
Peak memory 204132 kb
Host smart-e3032a63-6e3f-4e82-82f7-cfbf793a5d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13446
45084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1344645084
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2594454464
Short name T971
Test name
Test status
Simulation time 8394918377 ps
CPU time 8.84 seconds
Started May 07 12:43:11 PM PDT 24
Finished May 07 12:43:22 PM PDT 24
Peak memory 204124 kb
Host smart-87dcaa41-67d1-4ca2-8709-85385146964f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25944
54464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2594454464
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.3995839113
Short name T490
Test name
Test status
Simulation time 8525650158 ps
CPU time 8.66 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204124 kb
Host smart-f8ac17ab-af5d-4f71-a438-a725193a7000
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3995839113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.3995839113
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.3958760373
Short name T1354
Test name
Test status
Simulation time 8379269741 ps
CPU time 9.67 seconds
Started May 07 12:43:13 PM PDT 24
Finished May 07 12:43:24 PM PDT 24
Peak memory 204092 kb
Host smart-da7c2cc2-f237-4e32-8674-2c9ce51a6382
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3958760373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.3958760373
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.1397666671
Short name T34
Test name
Test status
Simulation time 8388679166 ps
CPU time 7.73 seconds
Started May 07 12:43:30 PM PDT 24
Finished May 07 12:43:40 PM PDT 24
Peak memory 204076 kb
Host smart-cecf0969-0d32-45ea-92e9-1335981a835e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13976
66671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.1397666671
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2611713594
Short name T725
Test name
Test status
Simulation time 8370241760 ps
CPU time 8.33 seconds
Started May 07 12:43:20 PM PDT 24
Finished May 07 12:43:31 PM PDT 24
Peak memory 204128 kb
Host smart-4fceb883-2cbd-4a15-b910-1bcff221151f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26117
13594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2611713594
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.1971419834
Short name T768
Test name
Test status
Simulation time 8383288155 ps
CPU time 7.65 seconds
Started May 07 12:43:20 PM PDT 24
Finished May 07 12:43:29 PM PDT 24
Peak memory 204116 kb
Host smart-1f00e8c7-7d2d-4173-b0b4-026aafffc787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19714
19834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1971419834
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3714564542
Short name T367
Test name
Test status
Simulation time 91141115 ps
CPU time 2.36 seconds
Started May 07 12:43:12 PM PDT 24
Finished May 07 12:43:16 PM PDT 24
Peak memory 204116 kb
Host smart-e79a7617-ab79-472a-a5b0-387669384dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37145
64542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3714564542
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2258890723
Short name T948
Test name
Test status
Simulation time 8471406662 ps
CPU time 8 seconds
Started May 07 12:43:20 PM PDT 24
Finished May 07 12:43:30 PM PDT 24
Peak memory 204108 kb
Host smart-3eefde63-09a0-44e7-9ae1-1998281c632e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22588
90723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2258890723
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3457602748
Short name T1192
Test name
Test status
Simulation time 8364173729 ps
CPU time 8.68 seconds
Started May 07 12:43:08 PM PDT 24
Finished May 07 12:43:19 PM PDT 24
Peak memory 204144 kb
Host smart-5e738dcb-3bdc-4310-8fb5-e2463a92039a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34576
02748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3457602748
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.4117946500
Short name T683
Test name
Test status
Simulation time 8453597118 ps
CPU time 7.67 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:27 PM PDT 24
Peak memory 204104 kb
Host smart-29f0f60a-3c85-4dda-b909-75780c96bcc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41179
46500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.4117946500
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1032691058
Short name T486
Test name
Test status
Simulation time 8434576011 ps
CPU time 8.19 seconds
Started May 07 12:43:10 PM PDT 24
Finished May 07 12:43:20 PM PDT 24
Peak memory 204120 kb
Host smart-204a5765-5146-4cca-9f1d-abacf0d95eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10326
91058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1032691058
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1684049830
Short name T509
Test name
Test status
Simulation time 8380875375 ps
CPU time 7.72 seconds
Started May 07 12:43:08 PM PDT 24
Finished May 07 12:43:18 PM PDT 24
Peak memory 204052 kb
Host smart-a712af39-d15c-4c13-b86c-93a2bfb439f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16840
49830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1684049830
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.4062906600
Short name T128
Test name
Test status
Simulation time 8483914557 ps
CPU time 7.7 seconds
Started May 07 12:43:06 PM PDT 24
Finished May 07 12:43:16 PM PDT 24
Peak memory 204120 kb
Host smart-6835a7e0-5d21-4113-bf2f-ca4374c88d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40629
06600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.4062906600
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1064530535
Short name T1228
Test name
Test status
Simulation time 8409610641 ps
CPU time 7.78 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204124 kb
Host smart-186b6db0-fe99-4093-b51a-ee021d85d563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10645
30535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1064530535
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.924491350
Short name T535
Test name
Test status
Simulation time 8389531519 ps
CPU time 7.56 seconds
Started May 07 12:43:17 PM PDT 24
Finished May 07 12:43:26 PM PDT 24
Peak memory 204120 kb
Host smart-2c4db79f-7f62-48e6-828d-717eb2bfcbc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92449
1350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.924491350
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2760058267
Short name T184
Test name
Test status
Simulation time 8371359231 ps
CPU time 8.41 seconds
Started May 07 12:43:20 PM PDT 24
Finished May 07 12:43:30 PM PDT 24
Peak memory 204120 kb
Host smart-2904abda-8b52-4043-996e-57372ceeaa98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27600
58267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2760058267
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.304718582
Short name T706
Test name
Test status
Simulation time 8412078673 ps
CPU time 7.4 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:27 PM PDT 24
Peak memory 204108 kb
Host smart-c1d8d2e9-cb94-45f9-a268-a40078cf4216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30471
8582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.304718582
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.754997000
Short name T703
Test name
Test status
Simulation time 75091605 ps
CPU time 0.66 seconds
Started May 07 12:43:20 PM PDT 24
Finished May 07 12:43:22 PM PDT 24
Peak memory 203988 kb
Host smart-5b7b519c-bd0b-421d-b9b2-4463684be0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75499
7000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.754997000
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2612591178
Short name T833
Test name
Test status
Simulation time 8392141425 ps
CPU time 8.04 seconds
Started May 07 12:43:19 PM PDT 24
Finished May 07 12:43:29 PM PDT 24
Peak memory 204020 kb
Host smart-16979e55-6b2b-45d5-8e4a-052b5fc3ed25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26125
91178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2612591178
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2679432686
Short name T965
Test name
Test status
Simulation time 8483786510 ps
CPU time 7.73 seconds
Started May 07 12:43:19 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204116 kb
Host smart-7ebf797d-a5b7-4b5f-8384-79299957180b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26794
32686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2679432686
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.2767915461
Short name T480
Test name
Test status
Simulation time 8415676337 ps
CPU time 7.86 seconds
Started May 07 12:43:17 PM PDT 24
Finished May 07 12:43:26 PM PDT 24
Peak memory 204052 kb
Host smart-127342df-85b4-40be-aa93-b1c59299833a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27679
15461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.2767915461
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2741308559
Short name T165
Test name
Test status
Simulation time 8376099200 ps
CPU time 7.97 seconds
Started May 07 12:43:29 PM PDT 24
Finished May 07 12:43:40 PM PDT 24
Peak memory 204072 kb
Host smart-55817e80-aff9-428c-a603-10c0b9d4dfc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27413
08559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2741308559
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.350909902
Short name T635
Test name
Test status
Simulation time 8372551948 ps
CPU time 7.9 seconds
Started May 07 12:43:19 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204140 kb
Host smart-f56ef130-04b9-4cc5-8d8f-1a7df3c60f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35090
9902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.350909902
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1241451563
Short name T353
Test name
Test status
Simulation time 8421212593 ps
CPU time 8.24 seconds
Started May 07 12:43:02 PM PDT 24
Finished May 07 12:43:12 PM PDT 24
Peak memory 204124 kb
Host smart-1db1f112-e9a6-44f3-9d36-afbf9f91dd72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12414
51563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1241451563
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2301634042
Short name T402
Test name
Test status
Simulation time 8402748466 ps
CPU time 10.2 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:30 PM PDT 24
Peak memory 204104 kb
Host smart-ae87af7e-584b-4167-b0e4-92ee9ab7059e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23016
34042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2301634042
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3238251427
Short name T895
Test name
Test status
Simulation time 8410301847 ps
CPU time 7.48 seconds
Started May 07 12:43:15 PM PDT 24
Finished May 07 12:43:24 PM PDT 24
Peak memory 204040 kb
Host smart-517bd0b5-b81e-4b6e-813f-a7c2fffad639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32382
51427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3238251427
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.2338393037
Short name T503
Test name
Test status
Simulation time 8473584936 ps
CPU time 8.45 seconds
Started May 07 12:43:16 PM PDT 24
Finished May 07 12:43:25 PM PDT 24
Peak memory 204128 kb
Host smart-a58f1784-42d4-47ea-9234-815919a76c33
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2338393037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.2338393037
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.2366975462
Short name T407
Test name
Test status
Simulation time 8373561285 ps
CPU time 8.2 seconds
Started May 07 12:43:13 PM PDT 24
Finished May 07 12:43:23 PM PDT 24
Peak memory 204036 kb
Host smart-f1f797a9-adab-4f7a-aa6c-0150dc282849
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2366975462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.2366975462
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.3408598705
Short name T802
Test name
Test status
Simulation time 8457203010 ps
CPU time 7.94 seconds
Started May 07 12:43:19 PM PDT 24
Finished May 07 12:43:29 PM PDT 24
Peak memory 204116 kb
Host smart-9740001c-202e-4b8a-ae35-adc4557cdc97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34085
98705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.3408598705
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1692561045
Short name T1092
Test name
Test status
Simulation time 8405333261 ps
CPU time 7.56 seconds
Started May 07 12:43:08 PM PDT 24
Finished May 07 12:43:18 PM PDT 24
Peak memory 204072 kb
Host smart-df6c8422-6297-4d7e-986b-c4d3335f9f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16925
61045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1692561045
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.3958970428
Short name T316
Test name
Test status
Simulation time 8376419862 ps
CPU time 8.1 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:31 PM PDT 24
Peak memory 204076 kb
Host smart-305d3811-c4a6-4461-8f37-20528441e1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39589
70428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3958970428
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.741567750
Short name T640
Test name
Test status
Simulation time 144147241 ps
CPU time 1.57 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:25 PM PDT 24
Peak memory 204208 kb
Host smart-e730adac-1176-4086-8468-d59cf4b4a3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74156
7750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.741567750
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3051734031
Short name T704
Test name
Test status
Simulation time 8394227259 ps
CPU time 7.85 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:32 PM PDT 24
Peak memory 203788 kb
Host smart-4a93027f-9c33-49de-8078-ded28a68bda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30517
34031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3051734031
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2186126405
Short name T200
Test name
Test status
Simulation time 8387773119 ps
CPU time 8.72 seconds
Started May 07 12:43:16 PM PDT 24
Finished May 07 12:43:26 PM PDT 24
Peak memory 204132 kb
Host smart-cde4bd58-4a25-4f1b-a543-0c4c69bf576a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21861
26405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2186126405
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.793885402
Short name T360
Test name
Test status
Simulation time 8419981646 ps
CPU time 8.23 seconds
Started May 07 12:43:23 PM PDT 24
Finished May 07 12:43:33 PM PDT 24
Peak memory 204124 kb
Host smart-863a4a98-e545-434f-83f1-a26a42317a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79388
5402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.793885402
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3994869667
Short name T789
Test name
Test status
Simulation time 8417419105 ps
CPU time 7.77 seconds
Started May 07 12:43:08 PM PDT 24
Finished May 07 12:43:18 PM PDT 24
Peak memory 204136 kb
Host smart-5d8aad57-4a56-4cc8-8209-59b91349d055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39948
69667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3994869667
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3805069515
Short name T1342
Test name
Test status
Simulation time 8369915592 ps
CPU time 7.22 seconds
Started May 07 12:43:37 PM PDT 24
Finished May 07 12:43:47 PM PDT 24
Peak memory 204092 kb
Host smart-51a67bca-4cb0-448d-947d-4f161b23f986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38050
69515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3805069515
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1335105974
Short name T109
Test name
Test status
Simulation time 8452221477 ps
CPU time 7.78 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:27 PM PDT 24
Peak memory 204140 kb
Host smart-0d6bc3d4-d8a4-4a97-9568-e3cab9fccfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13351
05974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1335105974
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3341385594
Short name T678
Test name
Test status
Simulation time 8407868285 ps
CPU time 9.79 seconds
Started May 07 12:43:28 PM PDT 24
Finished May 07 12:43:40 PM PDT 24
Peak memory 204120 kb
Host smart-11a2bb7a-4629-4fb9-960b-4c8149f3550c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33413
85594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3341385594
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1490187036
Short name T540
Test name
Test status
Simulation time 8421402272 ps
CPU time 9.84 seconds
Started May 07 12:43:16 PM PDT 24
Finished May 07 12:43:27 PM PDT 24
Peak memory 204000 kb
Host smart-27e9213f-45fb-45f7-8bde-6b0dbe5cf9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14901
87036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1490187036
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2855297621
Short name T185
Test name
Test status
Simulation time 8396783515 ps
CPU time 8.2 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204124 kb
Host smart-71563730-3f2e-4403-9ef2-0bedb28b93ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28552
97621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2855297621
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.681097113
Short name T1220
Test name
Test status
Simulation time 8387435646 ps
CPU time 9.97 seconds
Started May 07 12:43:26 PM PDT 24
Finished May 07 12:43:38 PM PDT 24
Peak memory 204112 kb
Host smart-a050c13f-9aa7-49fe-8f09-5b4bf2f816db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68109
7113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.681097113
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1636649772
Short name T401
Test name
Test status
Simulation time 66380258 ps
CPU time 0.68 seconds
Started May 07 12:43:16 PM PDT 24
Finished May 07 12:43:17 PM PDT 24
Peak memory 203956 kb
Host smart-b62ffc78-5d93-4223-ac89-740982d0f9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16366
49772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1636649772
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3339958306
Short name T494
Test name
Test status
Simulation time 14604992626 ps
CPU time 24.29 seconds
Started May 07 12:43:09 PM PDT 24
Finished May 07 12:43:36 PM PDT 24
Peak memory 204392 kb
Host smart-bbf7691c-eeaf-4193-81e7-3dbe7af7cf80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33399
58306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3339958306
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2635827567
Short name T1356
Test name
Test status
Simulation time 8400262238 ps
CPU time 8.04 seconds
Started May 07 12:43:16 PM PDT 24
Finished May 07 12:43:25 PM PDT 24
Peak memory 204084 kb
Host smart-b7160426-359f-44b9-b197-02f45fc0a7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26358
27567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2635827567
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.885553663
Short name T927
Test name
Test status
Simulation time 8433405504 ps
CPU time 7.93 seconds
Started May 07 12:43:12 PM PDT 24
Finished May 07 12:43:22 PM PDT 24
Peak memory 204092 kb
Host smart-a8f26df4-81fd-458d-8cff-4802449deb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88555
3663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.885553663
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.1804530120
Short name T816
Test name
Test status
Simulation time 8414049412 ps
CPU time 9.73 seconds
Started May 07 12:43:20 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 204116 kb
Host smart-3d35605e-ef2a-4341-ac6b-5cb6c2ee5df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18045
30120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.1804530120
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.479343655
Short name T589
Test name
Test status
Simulation time 8380251105 ps
CPU time 8.22 seconds
Started May 07 12:43:19 PM PDT 24
Finished May 07 12:43:29 PM PDT 24
Peak memory 204116 kb
Host smart-92117298-33b4-4704-be6e-d20686255067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47934
3655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.479343655
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3606396453
Short name T1068
Test name
Test status
Simulation time 8369323514 ps
CPU time 7.92 seconds
Started May 07 12:43:28 PM PDT 24
Finished May 07 12:43:38 PM PDT 24
Peak memory 204116 kb
Host smart-2bcc97d1-dad4-4303-afd7-15769f948f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36063
96453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3606396453
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1569238271
Short name T595
Test name
Test status
Simulation time 8441507088 ps
CPU time 9.25 seconds
Started May 07 12:43:10 PM PDT 24
Finished May 07 12:43:21 PM PDT 24
Peak memory 204108 kb
Host smart-0c01fc21-fb8b-46e5-a815-f22fa892214e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15692
38271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1569238271
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1339861780
Short name T466
Test name
Test status
Simulation time 8395937865 ps
CPU time 8 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:34 PM PDT 24
Peak memory 204144 kb
Host smart-b62ccd18-e34a-401e-884f-6c332830cfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13398
61780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1339861780
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1603978936
Short name T19
Test name
Test status
Simulation time 8421858855 ps
CPU time 7.31 seconds
Started May 07 12:43:31 PM PDT 24
Finished May 07 12:43:41 PM PDT 24
Peak memory 204072 kb
Host smart-0129946c-5e73-424c-818b-5659a8f981bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16039
78936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1603978936
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.1493551107
Short name T341
Test name
Test status
Simulation time 8477815885 ps
CPU time 7.68 seconds
Started May 07 12:43:33 PM PDT 24
Finished May 07 12:43:43 PM PDT 24
Peak memory 204096 kb
Host smart-ec69eb79-4cd7-4914-9afe-92c0d9b767c9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1493551107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.1493551107
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.225538716
Short name T352
Test name
Test status
Simulation time 8375465027 ps
CPU time 9.91 seconds
Started May 07 12:43:19 PM PDT 24
Finished May 07 12:43:31 PM PDT 24
Peak memory 204144 kb
Host smart-01ca7b8a-170d-4ed3-8c67-0139a1718787
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=225538716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.225538716
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.2373285073
Short name T1287
Test name
Test status
Simulation time 8473004260 ps
CPU time 8.35 seconds
Started May 07 12:43:36 PM PDT 24
Finished May 07 12:43:46 PM PDT 24
Peak memory 204088 kb
Host smart-7cff6cb2-9452-43e7-9add-0e1d9338208c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23732
85073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.2373285073
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.11336161
Short name T906
Test name
Test status
Simulation time 8395652551 ps
CPU time 8.27 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204076 kb
Host smart-d4702785-07f4-4eb1-a797-ba681148e5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11336
161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.11336161
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.3418404946
Short name T753
Test name
Test status
Simulation time 8377565261 ps
CPU time 7.57 seconds
Started May 07 12:43:12 PM PDT 24
Finished May 07 12:43:21 PM PDT 24
Peak memory 204104 kb
Host smart-34d19e78-4bb2-4edb-9329-51bdabe21f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34184
04946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3418404946
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1654915696
Short name T1366
Test name
Test status
Simulation time 178326973 ps
CPU time 1.93 seconds
Started May 07 12:43:17 PM PDT 24
Finished May 07 12:43:21 PM PDT 24
Peak memory 204264 kb
Host smart-6b039e67-da00-43f9-bcc4-fa5fd090a923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16549
15696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1654915696
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2946491810
Short name T1358
Test name
Test status
Simulation time 8451380766 ps
CPU time 8.14 seconds
Started May 07 12:43:22 PM PDT 24
Finished May 07 12:43:32 PM PDT 24
Peak memory 204120 kb
Host smart-50ec5888-f616-445a-b011-e34002b0c31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29464
91810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2946491810
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1866162469
Short name T197
Test name
Test status
Simulation time 8371743454 ps
CPU time 10.17 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:38 PM PDT 24
Peak memory 204100 kb
Host smart-98e4ea49-90da-4d16-b1e9-852062fd419f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18661
62469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1866162469
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.565379843
Short name T968
Test name
Test status
Simulation time 8421074573 ps
CPU time 7.94 seconds
Started May 07 12:43:23 PM PDT 24
Finished May 07 12:43:33 PM PDT 24
Peak memory 204116 kb
Host smart-522683d3-bf18-4e51-b9f3-682afddbabf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56537
9843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.565379843
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1628034891
Short name T592
Test name
Test status
Simulation time 8436507936 ps
CPU time 8.52 seconds
Started May 07 12:43:23 PM PDT 24
Finished May 07 12:43:34 PM PDT 24
Peak memory 204112 kb
Host smart-a23d229a-84f3-4b95-bc4a-7f93a9210502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16280
34891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1628034891
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3399098060
Short name T1303
Test name
Test status
Simulation time 8369715258 ps
CPU time 8.73 seconds
Started May 07 12:43:11 PM PDT 24
Finished May 07 12:43:22 PM PDT 24
Peak memory 204116 kb
Host smart-5fe247dd-7503-4ddd-bcd0-084469ac76d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33990
98060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3399098060
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3890595929
Short name T134
Test name
Test status
Simulation time 8420150559 ps
CPU time 8.43 seconds
Started May 07 12:43:20 PM PDT 24
Finished May 07 12:43:31 PM PDT 24
Peak memory 204116 kb
Host smart-8eec7e94-2d06-4173-a0ad-ee3d902c1dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38905
95929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3890595929
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3102052189
Short name T1102
Test name
Test status
Simulation time 8405536846 ps
CPU time 8.15 seconds
Started May 07 12:43:12 PM PDT 24
Finished May 07 12:43:22 PM PDT 24
Peak memory 204092 kb
Host smart-60f4ec62-13f0-456e-9175-7dfff4565d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31020
52189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3102052189
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.15751469
Short name T646
Test name
Test status
Simulation time 8381826797 ps
CPU time 8.35 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:32 PM PDT 24
Peak memory 204116 kb
Host smart-50c4a941-1424-482c-a1cf-184d3e404e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15751
469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.15751469
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2543480373
Short name T812
Test name
Test status
Simulation time 8394331182 ps
CPU time 7.49 seconds
Started May 07 12:43:33 PM PDT 24
Finished May 07 12:43:42 PM PDT 24
Peak memory 204076 kb
Host smart-7254cb21-9f7c-4705-a4e3-b6b7b37bf06c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25434
80373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2543480373
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1206555259
Short name T366
Test name
Test status
Simulation time 8371552993 ps
CPU time 9.79 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 204088 kb
Host smart-7fdc7c82-7916-4fca-a7a1-57efcc740df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12065
55259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1206555259
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.127213239
Short name T1180
Test name
Test status
Simulation time 83852214 ps
CPU time 0.7 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:27 PM PDT 24
Peak memory 203988 kb
Host smart-f14291ad-8209-4812-b387-d382b88eda73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12721
3239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.127213239
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1391980825
Short name T251
Test name
Test status
Simulation time 28692589512 ps
CPU time 59.23 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 204368 kb
Host smart-7d00b5aa-d6e2-4f0c-b472-43c33c5fc1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13919
80825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1391980825
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1353965290
Short name T822
Test name
Test status
Simulation time 8415237975 ps
CPU time 8.08 seconds
Started May 07 12:43:33 PM PDT 24
Finished May 07 12:43:43 PM PDT 24
Peak memory 204060 kb
Host smart-b177466c-2590-4a00-b4e9-1c8130adc193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13539
65290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1353965290
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1626109710
Short name T601
Test name
Test status
Simulation time 8387475211 ps
CPU time 8.05 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204100 kb
Host smart-eec42b18-1aa8-4c12-af83-ce0db73ab1e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16261
09710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1626109710
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.1400834348
Short name T369
Test name
Test status
Simulation time 8394485485 ps
CPU time 7.73 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204140 kb
Host smart-042c1965-0201-4656-a83e-1bc08e68acc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14008
34348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.1400834348
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.929101364
Short name T436
Test name
Test status
Simulation time 8385833662 ps
CPU time 8.11 seconds
Started May 07 12:43:28 PM PDT 24
Finished May 07 12:43:38 PM PDT 24
Peak memory 204104 kb
Host smart-d5608870-da00-4c51-a479-593f69896539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92910
1364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.929101364
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3910673132
Short name T361
Test name
Test status
Simulation time 8370206662 ps
CPU time 8.41 seconds
Started May 07 12:43:36 PM PDT 24
Finished May 07 12:43:46 PM PDT 24
Peak memory 204084 kb
Host smart-9197a153-8480-4aca-8fa8-d482cba51e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39106
73132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3910673132
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.4270751793
Short name T534
Test name
Test status
Simulation time 8453859795 ps
CPU time 10.28 seconds
Started May 07 12:43:17 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204132 kb
Host smart-eca05aa7-f59a-4c5a-a204-cc7e0806d763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42707
51793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.4270751793
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.833920791
Short name T1196
Test name
Test status
Simulation time 8382498990 ps
CPU time 7.61 seconds
Started May 07 12:43:15 PM PDT 24
Finished May 07 12:43:23 PM PDT 24
Peak memory 204116 kb
Host smart-8a9472bf-a3dd-466e-91f5-7192ae051161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83392
0791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.833920791
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3969338347
Short name T576
Test name
Test status
Simulation time 8409089235 ps
CPU time 8.23 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:34 PM PDT 24
Peak memory 204084 kb
Host smart-922fe995-baa7-4c1e-a616-1c14e69d5dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39693
38347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3969338347
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.3952706233
Short name T796
Test name
Test status
Simulation time 8494052751 ps
CPU time 8.68 seconds
Started May 07 12:43:38 PM PDT 24
Finished May 07 12:43:49 PM PDT 24
Peak memory 204080 kb
Host smart-311ff890-4a93-42ad-b8ef-79a5f2015c71
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3952706233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.3952706233
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.2091139685
Short name T620
Test name
Test status
Simulation time 8381732008 ps
CPU time 7.97 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204120 kb
Host smart-4e8a535d-0db5-41df-8a28-f529bbad1df5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2091139685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.2091139685
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.1997711181
Short name T801
Test name
Test status
Simulation time 8385480878 ps
CPU time 7.8 seconds
Started May 07 12:43:26 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 204108 kb
Host smart-7bab273b-58a0-44f1-870d-1ea6ea26f873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19977
11181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.1997711181
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.23790134
Short name T542
Test name
Test status
Simulation time 8430131650 ps
CPU time 8.2 seconds
Started May 07 12:43:20 PM PDT 24
Finished May 07 12:43:30 PM PDT 24
Peak memory 204140 kb
Host smart-c98885d6-eb84-41c6-a9e2-8af5b82d7930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790
134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.23790134
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.522037505
Short name T1117
Test name
Test status
Simulation time 8378749611 ps
CPU time 7.4 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:33 PM PDT 24
Peak memory 204104 kb
Host smart-5c7b290a-058b-4046-9b8a-1da29c5c98c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52203
7505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.522037505
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1319757187
Short name T888
Test name
Test status
Simulation time 164238813 ps
CPU time 1.76 seconds
Started May 07 12:43:19 PM PDT 24
Finished May 07 12:43:22 PM PDT 24
Peak memory 204224 kb
Host smart-33a0a011-ff69-4238-bfc3-d7dbf8cd8032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13197
57187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1319757187
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3610151563
Short name T1285
Test name
Test status
Simulation time 8446850849 ps
CPU time 10.17 seconds
Started May 07 12:43:36 PM PDT 24
Finished May 07 12:43:48 PM PDT 24
Peak memory 204112 kb
Host smart-bf979575-9056-4e23-a605-72fbee8f12e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36101
51563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3610151563
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2602004439
Short name T1195
Test name
Test status
Simulation time 8402189656 ps
CPU time 8.3 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:34 PM PDT 24
Peak memory 204132 kb
Host smart-4a6b71cd-4833-4331-be9f-45014d944f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26020
04439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2602004439
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.598775702
Short name T144
Test name
Test status
Simulation time 8402237793 ps
CPU time 8.63 seconds
Started May 07 12:43:22 PM PDT 24
Finished May 07 12:43:33 PM PDT 24
Peak memory 204128 kb
Host smart-21a91ed8-3c53-45d6-8654-b034da6ab22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59877
5702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.598775702
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.241675352
Short name T327
Test name
Test status
Simulation time 8437842224 ps
CPU time 10.56 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:38 PM PDT 24
Peak memory 204140 kb
Host smart-99f53b49-d609-475a-8cb1-8c74570492b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24167
5352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.241675352
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3599167603
Short name T857
Test name
Test status
Simulation time 8377664604 ps
CPU time 7.9 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:31 PM PDT 24
Peak memory 204076 kb
Host smart-14c37e6f-a683-4091-b78f-81cb87202f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35991
67603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3599167603
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2147787959
Short name T988
Test name
Test status
Simulation time 8439933221 ps
CPU time 7.61 seconds
Started May 07 12:43:18 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204088 kb
Host smart-53b6ca78-67fe-47f2-bc65-db3133efc029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21477
87959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2147787959
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1074701584
Short name T875
Test name
Test status
Simulation time 8412882586 ps
CPU time 8.48 seconds
Started May 07 12:43:26 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 204132 kb
Host smart-b0c2232e-d763-4f1b-8937-b66a01a80525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10747
01584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1074701584
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.601419992
Short name T766
Test name
Test status
Simulation time 8501948488 ps
CPU time 7.92 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204116 kb
Host smart-f7d0e4ee-52b0-4d5d-9362-d0f5a76344c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60141
9992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.601419992
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1150469803
Short name T1245
Test name
Test status
Simulation time 8436635043 ps
CPU time 8.76 seconds
Started May 07 12:43:34 PM PDT 24
Finished May 07 12:43:45 PM PDT 24
Peak memory 204036 kb
Host smart-22df2ec0-ff4a-4700-9516-dd2be61aeaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11504
69803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1150469803
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2674377569
Short name T1269
Test name
Test status
Simulation time 8394218745 ps
CPU time 8.4 seconds
Started May 07 12:43:34 PM PDT 24
Finished May 07 12:43:45 PM PDT 24
Peak memory 204108 kb
Host smart-896bafda-d95b-47da-a1b5-336a490d10e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26743
77569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2674377569
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.946440822
Short name T1227
Test name
Test status
Simulation time 52917952 ps
CPU time 0.7 seconds
Started May 07 12:43:33 PM PDT 24
Finished May 07 12:43:36 PM PDT 24
Peak memory 204004 kb
Host smart-632d8b5a-7c95-411d-b078-92fa82e28a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94644
0822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.946440822
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3542428821
Short name T1127
Test name
Test status
Simulation time 29826923522 ps
CPU time 55.8 seconds
Started May 07 12:43:20 PM PDT 24
Finished May 07 12:44:18 PM PDT 24
Peak memory 204396 kb
Host smart-30b75d43-ff1c-4809-ab64-815ff0ef90a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35424
28821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3542428821
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3432958793
Short name T506
Test name
Test status
Simulation time 8380499192 ps
CPU time 7.83 seconds
Started May 07 12:43:28 PM PDT 24
Finished May 07 12:43:39 PM PDT 24
Peak memory 204116 kb
Host smart-0039c94a-e840-437c-b485-667506caf7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34329
58793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3432958793
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.4212466731
Short name T35
Test name
Test status
Simulation time 8388276810 ps
CPU time 8.28 seconds
Started May 07 12:43:16 PM PDT 24
Finished May 07 12:43:25 PM PDT 24
Peak memory 204208 kb
Host smart-92ba9d0c-6207-416d-b4fc-331c7e8ea174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42124
66731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.4212466731
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.2072110841
Short name T784
Test name
Test status
Simulation time 8391789242 ps
CPU time 8.56 seconds
Started May 07 12:43:37 PM PDT 24
Finished May 07 12:43:48 PM PDT 24
Peak memory 204100 kb
Host smart-1b15ea88-af6e-49d0-a9d7-5c55a566f8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20721
10841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.2072110841
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.398364047
Short name T1139
Test name
Test status
Simulation time 8370612799 ps
CPU time 9.38 seconds
Started May 07 12:43:35 PM PDT 24
Finished May 07 12:43:47 PM PDT 24
Peak memory 204072 kb
Host smart-ec2d04b9-0afd-48e4-8628-c579b4c07bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39836
4047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.398364047
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3116793235
Short name T433
Test name
Test status
Simulation time 8371875756 ps
CPU time 8.38 seconds
Started May 07 12:43:30 PM PDT 24
Finished May 07 12:43:40 PM PDT 24
Peak memory 204028 kb
Host smart-bab38d1d-85be-41bc-aea6-b358fd301244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31167
93235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3116793235
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3265732071
Short name T874
Test name
Test status
Simulation time 8445177554 ps
CPU time 8.23 seconds
Started May 07 12:43:22 PM PDT 24
Finished May 07 12:43:33 PM PDT 24
Peak memory 204016 kb
Host smart-d7cf281c-57f8-4149-a4b1-e2c77807135e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32657
32071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3265732071
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3608274837
Short name T555
Test name
Test status
Simulation time 8381560271 ps
CPU time 7.95 seconds
Started May 07 12:43:29 PM PDT 24
Finished May 07 12:43:39 PM PDT 24
Peak memory 204012 kb
Host smart-6e7fbbab-7647-4a0e-b0ff-4d8698904a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36082
74837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3608274837
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2222021396
Short name T1150
Test name
Test status
Simulation time 8387749867 ps
CPU time 7.64 seconds
Started May 07 12:43:22 PM PDT 24
Finished May 07 12:43:32 PM PDT 24
Peak memory 204088 kb
Host smart-f0c26a51-9876-4788-a939-e6954fa02c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22220
21396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2222021396
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.819720964
Short name T745
Test name
Test status
Simulation time 8534513279 ps
CPU time 8.37 seconds
Started May 07 12:43:40 PM PDT 24
Finished May 07 12:43:50 PM PDT 24
Peak memory 204144 kb
Host smart-0e0c8d6c-7d31-43e0-95ed-033547f472f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=819720964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.819720964
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.4192842033
Short name T492
Test name
Test status
Simulation time 8438072539 ps
CPU time 10.2 seconds
Started May 07 12:43:22 PM PDT 24
Finished May 07 12:43:34 PM PDT 24
Peak memory 204120 kb
Host smart-98b921bb-d014-482a-b6aa-12e109c4d209
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4192842033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.4192842033
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.2109292247
Short name T1334
Test name
Test status
Simulation time 8429892564 ps
CPU time 10.11 seconds
Started May 07 12:43:43 PM PDT 24
Finished May 07 12:43:56 PM PDT 24
Peak memory 204120 kb
Host smart-dbbb0f59-90fd-43cb-9507-1630fbcb41fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21092
92247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.2109292247
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1233392828
Short name T335
Test name
Test status
Simulation time 8398270905 ps
CPU time 7.71 seconds
Started May 07 12:43:32 PM PDT 24
Finished May 07 12:43:41 PM PDT 24
Peak memory 204072 kb
Host smart-ff0d7e29-b3d9-4fa7-84d2-aa1ebcb04206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12333
92828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1233392828
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.652974333
Short name T825
Test name
Test status
Simulation time 8371851804 ps
CPU time 8.78 seconds
Started May 07 12:43:35 PM PDT 24
Finished May 07 12:43:46 PM PDT 24
Peak memory 204036 kb
Host smart-1a06b288-739b-44c5-b278-a96238f1036f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65297
4333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.652974333
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1506309323
Short name T54
Test name
Test status
Simulation time 114971720 ps
CPU time 1.1 seconds
Started May 07 12:43:23 PM PDT 24
Finished May 07 12:43:26 PM PDT 24
Peak memory 204248 kb
Host smart-a12e1e23-e63c-4d90-bfc8-d1d298e65534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15063
09323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1506309323
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.294980696
Short name T51
Test name
Test status
Simulation time 8431189944 ps
CPU time 7.66 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204148 kb
Host smart-55ab0969-b234-4b0e-ba2c-f3cc87025b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29498
0696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.294980696
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1641476548
Short name T186
Test name
Test status
Simulation time 8368460968 ps
CPU time 8.39 seconds
Started May 07 12:43:32 PM PDT 24
Finished May 07 12:43:42 PM PDT 24
Peak memory 204132 kb
Host smart-270d3cbd-9f35-4a34-bdb1-03b6bad56494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16414
76548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1641476548
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3947464966
Short name T1190
Test name
Test status
Simulation time 8410307167 ps
CPU time 7.49 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204112 kb
Host smart-b7782eb8-4134-4808-8755-abc4bb88c2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39474
64966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3947464966
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1828448471
Short name T1147
Test name
Test status
Simulation time 8421800229 ps
CPU time 7.6 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:33 PM PDT 24
Peak memory 204136 kb
Host smart-6e61967d-98a4-4b7f-9c5d-cca84bb55424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284
48471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1828448471
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2446453860
Short name T1143
Test name
Test status
Simulation time 8371918493 ps
CPU time 7.56 seconds
Started May 07 12:43:23 PM PDT 24
Finished May 07 12:43:33 PM PDT 24
Peak memory 204100 kb
Host smart-2c5141d0-1cc1-4b8e-9f3c-82b4620a7451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24464
53860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2446453860
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2821755433
Short name T111
Test name
Test status
Simulation time 8466018858 ps
CPU time 8.68 seconds
Started May 07 12:43:34 PM PDT 24
Finished May 07 12:43:45 PM PDT 24
Peak memory 204128 kb
Host smart-205cc556-c30e-402c-a062-4ac13de2c299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28217
55433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2821755433
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.614314931
Short name T222
Test name
Test status
Simulation time 8414518092 ps
CPU time 7.74 seconds
Started May 07 12:43:26 PM PDT 24
Finished May 07 12:43:36 PM PDT 24
Peak memory 204112 kb
Host smart-2445e39e-771e-48ea-b488-af0a836ff5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61431
4931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.614314931
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2797674051
Short name T1328
Test name
Test status
Simulation time 8411777725 ps
CPU time 9.83 seconds
Started May 07 12:43:33 PM PDT 24
Finished May 07 12:43:45 PM PDT 24
Peak memory 204116 kb
Host smart-26d5ee00-22b6-4a50-9a82-d8a09b15c3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27976
74051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2797674051
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2882016934
Short name T579
Test name
Test status
Simulation time 8369536493 ps
CPU time 10.11 seconds
Started May 07 12:43:28 PM PDT 24
Finished May 07 12:43:41 PM PDT 24
Peak memory 204116 kb
Host smart-148feeee-69d4-48c0-82f7-8359f549a39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28820
16934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2882016934
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1069765495
Short name T958
Test name
Test status
Simulation time 24398909520 ps
CPU time 50.98 seconds
Started May 07 12:43:35 PM PDT 24
Finished May 07 12:44:28 PM PDT 24
Peak memory 204456 kb
Host smart-0ace6a3f-2c84-449d-98df-c6c2f3c833fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10697
65495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1069765495
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3264003338
Short name T1141
Test name
Test status
Simulation time 8396749585 ps
CPU time 8.41 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:32 PM PDT 24
Peak memory 204108 kb
Host smart-05834636-5fe7-4124-801a-b940ba398a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32640
03338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3264003338
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3205395525
Short name T141
Test name
Test status
Simulation time 8392872258 ps
CPU time 7.65 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:33 PM PDT 24
Peak memory 204096 kb
Host smart-519da6e2-f97d-4cf1-ba44-0d9c0e26139f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32053
95525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3205395525
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.324494483
Short name T516
Test name
Test status
Simulation time 8399423169 ps
CPU time 8.19 seconds
Started May 07 12:43:33 PM PDT 24
Finished May 07 12:43:43 PM PDT 24
Peak memory 204148 kb
Host smart-9485a07a-da4b-4c73-924d-94c24bb0f7b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32449
4483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.324494483
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.894171494
Short name T1333
Test name
Test status
Simulation time 8382805880 ps
CPU time 7.53 seconds
Started May 07 12:43:35 PM PDT 24
Finished May 07 12:43:44 PM PDT 24
Peak memory 204108 kb
Host smart-bfe7775d-8bab-404a-8316-ec002119c0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89417
1494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.894171494
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.746347948
Short name T391
Test name
Test status
Simulation time 8366567043 ps
CPU time 7.75 seconds
Started May 07 12:43:22 PM PDT 24
Finished May 07 12:43:32 PM PDT 24
Peak memory 204120 kb
Host smart-ea6430a7-1af8-4388-954f-f5d4fcf0dd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74634
7948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.746347948
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2674590569
Short name T162
Test name
Test status
Simulation time 8411103217 ps
CPU time 10.28 seconds
Started May 07 12:43:36 PM PDT 24
Finished May 07 12:43:49 PM PDT 24
Peak memory 204088 kb
Host smart-2d5fe882-c908-410f-a12f-2ff6998e0a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26745
90569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2674590569
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2083736065
Short name T527
Test name
Test status
Simulation time 8434796365 ps
CPU time 7.54 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:31 PM PDT 24
Peak memory 204116 kb
Host smart-518f73fb-0b47-47be-b183-efd57808ff9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20837
36065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2083736065
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.4226642024
Short name T695
Test name
Test status
Simulation time 8413945954 ps
CPU time 8.39 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:52 PM PDT 24
Peak memory 204084 kb
Host smart-ab82cf14-28da-44fd-a5fb-ec74f85e79be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42266
42024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.4226642024
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.3387565678
Short name T922
Test name
Test status
Simulation time 8460577665 ps
CPU time 7.99 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:34 PM PDT 24
Peak memory 204116 kb
Host smart-2bc91c3a-272c-449f-9a1e-b7a6b0acf435
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3387565678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.3387565678
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.1467629823
Short name T338
Test name
Test status
Simulation time 8396939021 ps
CPU time 7.53 seconds
Started May 07 12:45:06 PM PDT 24
Finished May 07 12:45:15 PM PDT 24
Peak memory 203848 kb
Host smart-8d7be87d-3ca7-4fc9-bc41-a081a0d150c7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1467629823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.1467629823
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.3057952144
Short name T995
Test name
Test status
Simulation time 8467438628 ps
CPU time 8.26 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 204060 kb
Host smart-b493e2fb-e329-4721-8ec6-c565d2820bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30579
52144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.3057952144
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.49775083
Short name T501
Test name
Test status
Simulation time 8392182956 ps
CPU time 8.26 seconds
Started May 07 12:43:33 PM PDT 24
Finished May 07 12:43:43 PM PDT 24
Peak memory 204120 kb
Host smart-0240aa50-bc3b-4b9b-b0fe-a6705f833955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49775
083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.49775083
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.1080622924
Short name T696
Test name
Test status
Simulation time 8380146921 ps
CPU time 8.65 seconds
Started May 07 12:43:27 PM PDT 24
Finished May 07 12:43:38 PM PDT 24
Peak memory 204108 kb
Host smart-78685d62-1877-4b88-96aa-5547fc12e9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10806
22924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1080622924
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.830138762
Short name T772
Test name
Test status
Simulation time 81000666 ps
CPU time 1.13 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:29 PM PDT 24
Peak memory 204216 kb
Host smart-837f5f27-a909-4878-b9ed-b1b0494a9a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83013
8762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.830138762
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2575102701
Short name T787
Test name
Test status
Simulation time 8403821130 ps
CPU time 8.02 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:20 PM PDT 24
Peak memory 203876 kb
Host smart-659a3d35-b5fc-4a00-81cd-af8f18509170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25751
02701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2575102701
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2099060093
Short name T425
Test name
Test status
Simulation time 8450972268 ps
CPU time 7.71 seconds
Started May 07 12:43:30 PM PDT 24
Finished May 07 12:43:41 PM PDT 24
Peak memory 204104 kb
Host smart-25813074-024d-4189-91d1-95f2378d3277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20990
60093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2099060093
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.943463451
Short name T584
Test name
Test status
Simulation time 8420679987 ps
CPU time 8.8 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 204104 kb
Host smart-50e418ed-190c-48ef-963f-1f8cef320a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94346
3451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.943463451
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2598539791
Short name T643
Test name
Test status
Simulation time 8374600931 ps
CPU time 10.38 seconds
Started May 07 12:43:26 PM PDT 24
Finished May 07 12:43:39 PM PDT 24
Peak memory 204128 kb
Host smart-5f0e8f0f-a330-4a81-8727-05fff4dc6064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25985
39791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2598539791
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3224999764
Short name T108
Test name
Test status
Simulation time 8399978170 ps
CPU time 8.1 seconds
Started May 07 12:43:40 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 204112 kb
Host smart-11026c9a-38dc-4b42-9b6c-b60683434a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32249
99764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3224999764
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3112549792
Short name T1225
Test name
Test status
Simulation time 8400502737 ps
CPU time 7.68 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:33 PM PDT 24
Peak memory 204108 kb
Host smart-bda4c116-6dcb-4443-b888-0d2aaeabc1b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31125
49792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3112549792
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2838289173
Short name T529
Test name
Test status
Simulation time 8447556527 ps
CPU time 7.77 seconds
Started May 07 12:43:39 PM PDT 24
Finished May 07 12:43:48 PM PDT 24
Peak memory 204092 kb
Host smart-f02b7b42-a5da-4b5e-99e3-506d94caf22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28382
89173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2838289173
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1323994027
Short name T195
Test name
Test status
Simulation time 8395963267 ps
CPU time 8.17 seconds
Started May 07 12:43:27 PM PDT 24
Finished May 07 12:43:38 PM PDT 24
Peak memory 204104 kb
Host smart-6e1ab9aa-93bc-43cf-951b-3de2b2b42c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13239
94027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1323994027
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3687954986
Short name T379
Test name
Test status
Simulation time 8368979933 ps
CPU time 9.38 seconds
Started May 07 12:43:31 PM PDT 24
Finished May 07 12:43:43 PM PDT 24
Peak memory 204148 kb
Host smart-6d392cff-2722-4c58-995f-7f08245adca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36879
54986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3687954986
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1181314366
Short name T1284
Test name
Test status
Simulation time 55447683 ps
CPU time 0.67 seconds
Started May 07 12:43:37 PM PDT 24
Finished May 07 12:43:40 PM PDT 24
Peak memory 203988 kb
Host smart-1da51b2d-ece2-49bc-b9af-5eeb946c797b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11813
14366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1181314366
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2107325102
Short name T685
Test name
Test status
Simulation time 25962481916 ps
CPU time 51.78 seconds
Started May 07 12:43:28 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 204384 kb
Host smart-4aad56e0-233a-4c35-a5a0-5414b252adfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21073
25102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2107325102
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2241746319
Short name T944
Test name
Test status
Simulation time 8388799845 ps
CPU time 8.41 seconds
Started May 07 12:43:30 PM PDT 24
Finished May 07 12:43:41 PM PDT 24
Peak memory 204108 kb
Host smart-cb558f10-b32b-4a85-935d-eb21c1b761a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22417
46319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2241746319
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1513127157
Short name T799
Test name
Test status
Simulation time 8452640700 ps
CPU time 8.8 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:47 PM PDT 24
Peak memory 202476 kb
Host smart-af1f4ea9-2044-465c-8b2d-90e7c3689fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15131
27157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1513127157
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.2930013363
Short name T307
Test name
Test status
Simulation time 8420161076 ps
CPU time 7.57 seconds
Started May 07 12:43:40 PM PDT 24
Finished May 07 12:43:49 PM PDT 24
Peak memory 204092 kb
Host smart-b4c9f952-cb82-4a45-87a8-22ad37895420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29300
13363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.2930013363
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.192770393
Short name T858
Test name
Test status
Simulation time 8372074515 ps
CPU time 8.4 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:41 PM PDT 24
Peak memory 204088 kb
Host smart-9b3559a8-3b3e-40fa-a571-63214522a265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19277
0393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.192770393
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2139822343
Short name T345
Test name
Test status
Simulation time 8373241839 ps
CPU time 8.2 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:15 PM PDT 24
Peak memory 203872 kb
Host smart-92daf08d-117f-4201-8e4a-5ef388810f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21398
22343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2139822343
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3159469149
Short name T1097
Test name
Test status
Simulation time 8469451978 ps
CPU time 8.03 seconds
Started May 07 12:43:21 PM PDT 24
Finished May 07 12:43:32 PM PDT 24
Peak memory 204136 kb
Host smart-905d13ff-865c-4669-8bc2-8846098f5ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31594
69149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3159469149
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1940444412
Short name T890
Test name
Test status
Simulation time 8390822225 ps
CPU time 7.73 seconds
Started May 07 12:45:11 PM PDT 24
Finished May 07 12:45:21 PM PDT 24
Peak memory 203876 kb
Host smart-0ec41235-c15e-4781-a34a-075c61cfcd91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19404
44412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1940444412
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.180851650
Short name T1368
Test name
Test status
Simulation time 8400339281 ps
CPU time 8.04 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:34 PM PDT 24
Peak memory 204120 kb
Host smart-6361d640-f332-4a43-8960-41a305b4fcdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18085
1650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.180851650
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.1109922186
Short name T1158
Test name
Test status
Simulation time 8469579064 ps
CPU time 8.73 seconds
Started May 07 12:43:39 PM PDT 24
Finished May 07 12:43:50 PM PDT 24
Peak memory 204116 kb
Host smart-92af3a46-0037-44e7-9ff0-d28ea4c9f053
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1109922186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.1109922186
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.2418398756
Short name T619
Test name
Test status
Simulation time 8380484807 ps
CPU time 9.4 seconds
Started May 07 12:43:50 PM PDT 24
Finished May 07 12:44:02 PM PDT 24
Peak memory 204100 kb
Host smart-394d2d80-c4d0-4f8c-b8e4-748212c3a09b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2418398756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.2418398756
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.3031636051
Short name T690
Test name
Test status
Simulation time 8407528721 ps
CPU time 8.7 seconds
Started May 07 12:43:26 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 204108 kb
Host smart-0a170198-cc5a-41d9-bab1-6673781cf849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30316
36051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.3031636051
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2278967359
Short name T966
Test name
Test status
Simulation time 8432994372 ps
CPU time 7.8 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 204060 kb
Host smart-973871f8-ea31-40aa-b6a3-95f200d40cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22789
67359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2278967359
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.826719562
Short name T785
Test name
Test status
Simulation time 8385343900 ps
CPU time 8.6 seconds
Started May 07 12:45:06 PM PDT 24
Finished May 07 12:45:17 PM PDT 24
Peak memory 203880 kb
Host smart-ec4b6b14-39be-4353-9107-7183d46294ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82671
9562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.826719562
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1547632365
Short name T415
Test name
Test status
Simulation time 66468836 ps
CPU time 1.69 seconds
Started May 07 12:43:24 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 204112 kb
Host smart-d5722d38-9af3-43c7-8602-e2ab78628648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15476
32365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1547632365
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.847780972
Short name T985
Test name
Test status
Simulation time 8453590398 ps
CPU time 9.57 seconds
Started May 07 12:43:26 PM PDT 24
Finished May 07 12:43:38 PM PDT 24
Peak memory 204096 kb
Host smart-e61d252a-74a9-4320-b7c8-a1e399a66d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84778
0972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.847780972
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1699474763
Short name T629
Test name
Test status
Simulation time 8390855788 ps
CPU time 8.5 seconds
Started May 07 12:43:34 PM PDT 24
Finished May 07 12:43:44 PM PDT 24
Peak memory 204096 kb
Host smart-0cb1189e-084c-4563-9834-2c05f5d57816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16994
74763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1699474763
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.4095448669
Short name T860
Test name
Test status
Simulation time 8425801149 ps
CPU time 7.79 seconds
Started May 07 12:43:28 PM PDT 24
Finished May 07 12:43:39 PM PDT 24
Peak memory 204100 kb
Host smart-25974035-c829-4768-a0a3-fd74a20d0d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40954
48669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.4095448669
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.410890393
Short name T298
Test name
Test status
Simulation time 8424020378 ps
CPU time 9.29 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 204156 kb
Host smart-450d5189-101d-486f-a174-e17338415628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41089
0393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.410890393
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1037208583
Short name T1275
Test name
Test status
Simulation time 8371269453 ps
CPU time 7.6 seconds
Started May 07 12:43:39 PM PDT 24
Finished May 07 12:43:49 PM PDT 24
Peak memory 204124 kb
Host smart-70676bdd-3622-42fb-8a7c-145ce874d1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10372
08583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1037208583
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3565077311
Short name T123
Test name
Test status
Simulation time 8434818450 ps
CPU time 7.59 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204124 kb
Host smart-863efcf8-3ff0-4d5a-8c22-92c8ab8173dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35650
77311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3565077311
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.443348939
Short name T805
Test name
Test status
Simulation time 8421932381 ps
CPU time 7.74 seconds
Started May 07 12:43:26 PM PDT 24
Finished May 07 12:43:36 PM PDT 24
Peak memory 204096 kb
Host smart-24e29abe-55ef-48b5-a597-7b694f16a073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44334
8939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.443348939
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1573875288
Short name T716
Test name
Test status
Simulation time 8397803859 ps
CPU time 9.2 seconds
Started May 07 12:45:01 PM PDT 24
Finished May 07 12:45:11 PM PDT 24
Peak memory 203876 kb
Host smart-ea58776a-6b88-4b13-ada6-c3e18228917a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15738
75288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1573875288
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2771623141
Short name T514
Test name
Test status
Simulation time 8377433913 ps
CPU time 7.91 seconds
Started May 07 12:45:04 PM PDT 24
Finished May 07 12:45:13 PM PDT 24
Peak memory 203876 kb
Host smart-c0ddd450-9e17-4d4d-a440-153029a40c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27716
23141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2771623141
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1152204132
Short name T983
Test name
Test status
Simulation time 8376051231 ps
CPU time 7.62 seconds
Started May 07 12:45:09 PM PDT 24
Finished May 07 12:45:19 PM PDT 24
Peak memory 203884 kb
Host smart-d1f13b0c-2154-4895-9174-0ad65191f0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11522
04132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1152204132
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.16706495
Short name T841
Test name
Test status
Simulation time 47485517 ps
CPU time 0.63 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 203964 kb
Host smart-b2e64ca3-5a7c-4397-915b-199612589be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16706
495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.16706495
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.4290575483
Short name T1349
Test name
Test status
Simulation time 24551232207 ps
CPU time 43.53 seconds
Started May 07 12:45:05 PM PDT 24
Finished May 07 12:45:50 PM PDT 24
Peak memory 204164 kb
Host smart-0d1a057f-8929-488c-9da8-0790a4bb2535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42905
75483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.4290575483
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1297817735
Short name T900
Test name
Test status
Simulation time 8401312929 ps
CPU time 7.53 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:35 PM PDT 24
Peak memory 204088 kb
Host smart-03219386-fa8b-43fb-ade3-829e33c0dd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12978
17735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1297817735
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2706461847
Short name T1020
Test name
Test status
Simulation time 8423634111 ps
CPU time 8.16 seconds
Started May 07 12:43:39 PM PDT 24
Finished May 07 12:43:49 PM PDT 24
Peak memory 204072 kb
Host smart-dd09b774-cf87-47e6-891e-3a90612dd2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27064
61847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2706461847
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.2429355239
Short name T1337
Test name
Test status
Simulation time 8396756200 ps
CPU time 8.27 seconds
Started May 07 12:43:30 PM PDT 24
Finished May 07 12:43:45 PM PDT 24
Peak memory 204052 kb
Host smart-24d10133-9edf-40ef-8e06-58c6546d5e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24293
55239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.2429355239
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.791531168
Short name T580
Test name
Test status
Simulation time 8370855064 ps
CPU time 9.33 seconds
Started May 07 12:43:25 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 204108 kb
Host smart-128014f5-34f9-4c84-b415-b39ec72f62e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79153
1168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.791531168
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3629328422
Short name T431
Test name
Test status
Simulation time 8416711542 ps
CPU time 7.52 seconds
Started May 07 12:43:27 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 204084 kb
Host smart-2bb5922f-f89c-4f3f-8264-f49a4b808b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36293
28422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3629328422
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.941114764
Short name T1202
Test name
Test status
Simulation time 8456141418 ps
CPU time 8.79 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:58 PM PDT 24
Peak memory 204092 kb
Host smart-e47f2b67-7bc3-4eda-ba6b-6314eb206a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94111
4764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.941114764
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3771540588
Short name T1359
Test name
Test status
Simulation time 8382627818 ps
CPU time 8.87 seconds
Started May 07 12:44:34 PM PDT 24
Finished May 07 12:44:47 PM PDT 24
Peak memory 202456 kb
Host smart-7dd56850-32ee-47a4-b0b9-b61ae23e058f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37715
40588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3771540588
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3293821375
Short name T482
Test name
Test status
Simulation time 8468910266 ps
CPU time 7.66 seconds
Started May 07 12:43:46 PM PDT 24
Finished May 07 12:43:56 PM PDT 24
Peak memory 204072 kb
Host smart-2bf25759-0f65-4cdd-ab75-7152ce9e6160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32938
21375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3293821375
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.1714984690
Short name T850
Test name
Test status
Simulation time 8474304447 ps
CPU time 8.63 seconds
Started May 07 12:41:23 PM PDT 24
Finished May 07 12:41:33 PM PDT 24
Peak memory 204012 kb
Host smart-ad3992fa-203b-4de7-af8d-abd21ce83663
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1714984690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.1714984690
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.1737299651
Short name T1286
Test name
Test status
Simulation time 8381546672 ps
CPU time 7.75 seconds
Started May 07 12:41:16 PM PDT 24
Finished May 07 12:41:25 PM PDT 24
Peak memory 204100 kb
Host smart-94cc044d-ecaf-4ab9-8fbc-b5d634bdca27
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1737299651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.1737299651
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.2085334000
Short name T936
Test name
Test status
Simulation time 8520726009 ps
CPU time 7.95 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204212 kb
Host smart-6a09cbe7-9de8-43af-ba73-65f3c6dff1bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20853
34000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.2085334000
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1132206810
Short name T411
Test name
Test status
Simulation time 8398714902 ps
CPU time 8.53 seconds
Started May 07 12:41:29 PM PDT 24
Finished May 07 12:41:38 PM PDT 24
Peak memory 204132 kb
Host smart-892160ce-5f53-4ec7-a285-922fb11d3d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11322
06810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1132206810
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.283705084
Short name T590
Test name
Test status
Simulation time 8375222112 ps
CPU time 8.01 seconds
Started May 07 12:41:16 PM PDT 24
Finished May 07 12:41:25 PM PDT 24
Peak memory 204124 kb
Host smart-899c292e-d61f-42d3-b460-70f0eb97c089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28370
5084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.283705084
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.487316236
Short name T502
Test name
Test status
Simulation time 187612331 ps
CPU time 1.98 seconds
Started May 07 12:41:27 PM PDT 24
Finished May 07 12:41:30 PM PDT 24
Peak memory 204180 kb
Host smart-9a52ff90-72c0-415f-bc76-656ab3fbb037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48731
6236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.487316236
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3353623322
Short name T1183
Test name
Test status
Simulation time 8433549678 ps
CPU time 8.45 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:43 PM PDT 24
Peak memory 204016 kb
Host smart-953d0162-637a-4a34-b646-8884622ec89a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33536
23322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3353623322
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.4042455705
Short name T1370
Test name
Test status
Simulation time 8375980192 ps
CPU time 8.25 seconds
Started May 07 12:41:14 PM PDT 24
Finished May 07 12:41:24 PM PDT 24
Peak memory 204080 kb
Host smart-f65f2c44-6659-44aa-b828-1ad0ff7babbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40424
55705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.4042455705
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2215879697
Short name T1132
Test name
Test status
Simulation time 8414922476 ps
CPU time 7.52 seconds
Started May 07 12:41:29 PM PDT 24
Finished May 07 12:41:38 PM PDT 24
Peak memory 204144 kb
Host smart-08212d65-93b1-4b6e-9a5c-f7379d659387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22158
79697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2215879697
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2834834289
Short name T1266
Test name
Test status
Simulation time 8425359325 ps
CPU time 8.52 seconds
Started May 07 12:41:22 PM PDT 24
Finished May 07 12:41:32 PM PDT 24
Peak memory 204144 kb
Host smart-b106e2cc-9599-4903-be03-7312aa0a35f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28348
34289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2834834289
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1832941018
Short name T219
Test name
Test status
Simulation time 8373195975 ps
CPU time 8.76 seconds
Started May 07 12:41:23 PM PDT 24
Finished May 07 12:41:33 PM PDT 24
Peak memory 204156 kb
Host smart-0f55bfb3-7375-46c3-b848-b53ceef9590e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18329
41018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1832941018
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3592346514
Short name T1138
Test name
Test status
Simulation time 8430449373 ps
CPU time 9 seconds
Started May 07 12:41:21 PM PDT 24
Finished May 07 12:41:31 PM PDT 24
Peak memory 204124 kb
Host smart-68e250fc-15e1-4dc5-86d5-bd6231b2c030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35923
46514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3592346514
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3538157806
Short name T378
Test name
Test status
Simulation time 8390514021 ps
CPU time 7.59 seconds
Started May 07 12:41:30 PM PDT 24
Finished May 07 12:41:39 PM PDT 24
Peak memory 204056 kb
Host smart-ff96228c-ec35-46fe-864a-f3169e6e4bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35381
57806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3538157806
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.4198401181
Short name T388
Test name
Test status
Simulation time 8397375852 ps
CPU time 7.6 seconds
Started May 07 12:41:31 PM PDT 24
Finished May 07 12:41:40 PM PDT 24
Peak memory 204100 kb
Host smart-82ef806b-ea95-4412-b821-1e1487240080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41984
01181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.4198401181
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1566493489
Short name T177
Test name
Test status
Simulation time 8393397766 ps
CPU time 7.74 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:43 PM PDT 24
Peak memory 204128 kb
Host smart-8056524d-7650-4b03-9c41-3b4f8330cfad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15664
93489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1566493489
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.240766077
Short name T877
Test name
Test status
Simulation time 68293099 ps
CPU time 0.68 seconds
Started May 07 12:41:36 PM PDT 24
Finished May 07 12:41:38 PM PDT 24
Peak memory 203972 kb
Host smart-625ad3b5-b75c-4063-b23d-1b6c57d14a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24076
6077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.240766077
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3797753228
Short name T1170
Test name
Test status
Simulation time 14523237037 ps
CPU time 24.31 seconds
Started May 07 12:41:31 PM PDT 24
Finished May 07 12:42:02 PM PDT 24
Peak memory 204408 kb
Host smart-db26edea-4ead-4064-a51d-a4ed6423b48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37977
53228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3797753228
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3733314215
Short name T275
Test name
Test status
Simulation time 8391485690 ps
CPU time 7.98 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:45 PM PDT 24
Peak memory 204092 kb
Host smart-b57fff34-10e7-46f1-924e-8a022605f7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37333
14215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3733314215
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2283062880
Short name T710
Test name
Test status
Simulation time 8459845405 ps
CPU time 9.87 seconds
Started May 07 12:41:25 PM PDT 24
Finished May 07 12:41:36 PM PDT 24
Peak memory 204120 kb
Host smart-e279d991-b701-4647-aa61-d67d84a8528b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22830
62880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2283062880
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.3410053197
Short name T424
Test name
Test status
Simulation time 8405000044 ps
CPU time 8.8 seconds
Started May 07 12:41:38 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204144 kb
Host smart-cc1b6ce1-dbc1-42f1-8692-ad8578b8cff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34100
53197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.3410053197
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1493929789
Short name T62
Test name
Test status
Simulation time 148899312 ps
CPU time 1 seconds
Started May 07 12:41:21 PM PDT 24
Finished May 07 12:41:23 PM PDT 24
Peak memory 220248 kb
Host smart-d1f962b5-9df5-4a71-9fed-a6c99c45b7a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1493929789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1493929789
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1071064273
Short name T603
Test name
Test status
Simulation time 8370696407 ps
CPU time 8.25 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:09 PM PDT 24
Peak memory 204068 kb
Host smart-a47fd4dc-b1bc-4b79-9abf-298e3c320023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10710
64273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1071064273
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2344630213
Short name T1223
Test name
Test status
Simulation time 8368698124 ps
CPU time 8.77 seconds
Started May 07 12:41:22 PM PDT 24
Finished May 07 12:41:32 PM PDT 24
Peak memory 204104 kb
Host smart-429630fe-12bf-46a9-ad56-aea12621c0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23446
30213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2344630213
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1706801049
Short name T773
Test name
Test status
Simulation time 8464936832 ps
CPU time 8.57 seconds
Started May 07 12:41:25 PM PDT 24
Finished May 07 12:41:34 PM PDT 24
Peak memory 204108 kb
Host smart-79a1ddc2-70d1-464f-9c78-8017e1ad15bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17068
01049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1706801049
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1413376864
Short name T1044
Test name
Test status
Simulation time 8383785113 ps
CPU time 10.24 seconds
Started May 07 12:41:32 PM PDT 24
Finished May 07 12:41:44 PM PDT 24
Peak memory 204120 kb
Host smart-63bb267d-651d-4269-95da-dec23d6ce8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14133
76864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1413376864
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.991396588
Short name T465
Test name
Test status
Simulation time 8403005090 ps
CPU time 7.46 seconds
Started May 07 12:41:38 PM PDT 24
Finished May 07 12:41:48 PM PDT 24
Peak memory 204128 kb
Host smart-4babab87-0654-437a-8ba7-a17d54bfb8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99139
6588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.991396588
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.3153411916
Short name T1272
Test name
Test status
Simulation time 8462268053 ps
CPU time 8.42 seconds
Started May 07 12:43:30 PM PDT 24
Finished May 07 12:43:41 PM PDT 24
Peak memory 204116 kb
Host smart-7ba7161f-c6fd-43f1-95ab-680394ca24dd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3153411916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.3153411916
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.3115012971
Short name T500
Test name
Test status
Simulation time 8378733528 ps
CPU time 8.08 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 204140 kb
Host smart-05cffca1-340d-4465-a0fb-8bf245377cc3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3115012971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.3115012971
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.1219176032
Short name T837
Test name
Test status
Simulation time 8393234884 ps
CPU time 9.48 seconds
Started May 07 12:43:36 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204092 kb
Host smart-47640291-5f4e-4998-8dd2-09d4a9ff7aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12191
76032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.1219176032
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1663396602
Short name T1278
Test name
Test status
Simulation time 8378159682 ps
CPU time 7.41 seconds
Started May 07 12:43:40 PM PDT 24
Finished May 07 12:43:49 PM PDT 24
Peak memory 204104 kb
Host smart-19b59671-deca-4abf-b751-20af43076a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16633
96602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1663396602
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.604111876
Short name T996
Test name
Test status
Simulation time 8375584199 ps
CPU time 10.38 seconds
Started May 07 12:43:37 PM PDT 24
Finished May 07 12:43:49 PM PDT 24
Peak memory 204128 kb
Host smart-7a842391-0a68-4909-a3bc-4e2da4c114dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60411
1876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.604111876
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3308722125
Short name T1036
Test name
Test status
Simulation time 73830198 ps
CPU time 1.92 seconds
Started May 07 12:43:47 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 204336 kb
Host smart-944edb87-4368-4f6a-b8c0-6049331bcb84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33087
22125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3308722125
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.2355858762
Short name T49
Test name
Test status
Simulation time 8438288513 ps
CPU time 7.98 seconds
Started May 07 12:43:38 PM PDT 24
Finished May 07 12:43:48 PM PDT 24
Peak memory 204116 kb
Host smart-f20b9208-bc4c-4ec7-b486-f9b69472b94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23558
58762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2355858762
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3889272016
Short name T188
Test name
Test status
Simulation time 8363265325 ps
CPU time 10.15 seconds
Started May 07 12:43:47 PM PDT 24
Finished May 07 12:43:59 PM PDT 24
Peak memory 204120 kb
Host smart-00f5c725-af01-4583-a366-63acd81f0fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38892
72016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3889272016
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3935850556
Short name T1182
Test name
Test status
Simulation time 8400580154 ps
CPU time 9.66 seconds
Started May 07 12:43:38 PM PDT 24
Finished May 07 12:43:49 PM PDT 24
Peak memory 204116 kb
Host smart-4bbfaf0a-af8d-448c-be5d-821fbf738fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39358
50556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3935850556
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2278285387
Short name T992
Test name
Test status
Simulation time 8414318564 ps
CPU time 7.43 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 204164 kb
Host smart-7a7bfa21-fdfa-4afc-909c-ca8eada1032b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22782
85387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2278285387
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1243632504
Short name T1124
Test name
Test status
Simulation time 8441189941 ps
CPU time 7.69 seconds
Started May 07 12:43:46 PM PDT 24
Finished May 07 12:43:55 PM PDT 24
Peak memory 204148 kb
Host smart-1788d3af-2b92-408d-8840-2ec6d2161561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12436
32504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1243632504
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3414205314
Short name T125
Test name
Test status
Simulation time 8465588315 ps
CPU time 9.04 seconds
Started May 07 12:43:27 PM PDT 24
Finished May 07 12:43:39 PM PDT 24
Peak memory 204108 kb
Host smart-30734dba-5825-4192-afb4-5b8b9196db85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34142
05314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3414205314
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2037336047
Short name T1371
Test name
Test status
Simulation time 8414397664 ps
CPU time 7.92 seconds
Started May 07 12:43:37 PM PDT 24
Finished May 07 12:43:47 PM PDT 24
Peak memory 204136 kb
Host smart-788c3f1e-f9f0-414f-b988-0f4fd6563060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20373
36047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2037336047
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3634130488
Short name T1074
Test name
Test status
Simulation time 8389974769 ps
CPU time 8.92 seconds
Started May 07 12:43:29 PM PDT 24
Finished May 07 12:43:40 PM PDT 24
Peak memory 204108 kb
Host smart-c987f12a-3cea-47bf-bf7e-245542a68cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36341
30488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3634130488
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1319560260
Short name T1239
Test name
Test status
Simulation time 8409148804 ps
CPU time 7.81 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:52 PM PDT 24
Peak memory 204116 kb
Host smart-59a7257f-bc3e-40ee-8896-e6093a20adc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13195
60260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1319560260
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1879997082
Short name T882
Test name
Test status
Simulation time 8361274679 ps
CPU time 8.14 seconds
Started May 07 12:43:48 PM PDT 24
Finished May 07 12:43:58 PM PDT 24
Peak memory 204100 kb
Host smart-cf1f473b-4841-4914-b9f0-0d931a91e9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18799
97082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1879997082
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.767699850
Short name T790
Test name
Test status
Simulation time 72667026 ps
CPU time 0.67 seconds
Started May 07 12:43:54 PM PDT 24
Finished May 07 12:43:56 PM PDT 24
Peak memory 203984 kb
Host smart-4bd839b4-8392-4896-b0a0-98314c9ddd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76769
9850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.767699850
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3450359070
Short name T817
Test name
Test status
Simulation time 15782329265 ps
CPU time 29.65 seconds
Started May 07 12:43:49 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 204380 kb
Host smart-f1ce09e6-94f4-4b94-8791-6dfdb0b429fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34503
59070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3450359070
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.4050685536
Short name T572
Test name
Test status
Simulation time 8409324404 ps
CPU time 8.35 seconds
Started May 07 12:43:38 PM PDT 24
Finished May 07 12:43:49 PM PDT 24
Peak memory 204116 kb
Host smart-e3dcbfb9-0d39-480a-8970-ef8c62fa075b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40506
85536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.4050685536
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1750774693
Short name T808
Test name
Test status
Simulation time 8422821384 ps
CPU time 8.01 seconds
Started May 07 12:43:43 PM PDT 24
Finished May 07 12:43:54 PM PDT 24
Peak memory 204124 kb
Host smart-8f41d4b5-f44d-4aff-a449-2f4030858448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17507
74693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1750774693
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.3690767200
Short name T304
Test name
Test status
Simulation time 8399834466 ps
CPU time 7.53 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:52 PM PDT 24
Peak memory 204052 kb
Host smart-fc98db72-70c5-4d0f-8fd7-a734a11af8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36907
67200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.3690767200
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2762705986
Short name T1320
Test name
Test status
Simulation time 8407713914 ps
CPU time 7.94 seconds
Started May 07 12:43:43 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204064 kb
Host smart-91b87064-bab8-4aa7-b591-19dbb92c97ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27627
05986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2762705986
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3025844714
Short name T348
Test name
Test status
Simulation time 8370333020 ps
CPU time 7.83 seconds
Started May 07 12:43:29 PM PDT 24
Finished May 07 12:43:39 PM PDT 24
Peak memory 204108 kb
Host smart-0a120737-75e7-4b3e-a828-de7c88d2ad76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30258
44714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3025844714
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2603536810
Short name T1094
Test name
Test status
Simulation time 8457955294 ps
CPU time 7.75 seconds
Started May 07 12:43:29 PM PDT 24
Finished May 07 12:43:39 PM PDT 24
Peak memory 204016 kb
Host smart-94e9ef7d-3051-4dca-8813-42d01fe1ee68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26035
36810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2603536810
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2529325029
Short name T1264
Test name
Test status
Simulation time 8382548373 ps
CPU time 7.78 seconds
Started May 07 12:43:46 PM PDT 24
Finished May 07 12:43:55 PM PDT 24
Peak memory 203652 kb
Host smart-3f0ae96d-799c-4122-a313-2b562c4cc00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25293
25029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2529325029
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2650130482
Short name T302
Test name
Test status
Simulation time 8372469855 ps
CPU time 8.1 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:52 PM PDT 24
Peak memory 203640 kb
Host smart-d82dc364-1dd4-4a96-a4bc-7b5cf9ef51cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26501
30482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2650130482
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.1810127171
Short name T1219
Test name
Test status
Simulation time 8536508267 ps
CPU time 8.75 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204092 kb
Host smart-bc6bbd69-a639-441d-9012-ff40dc7be52d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1810127171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.1810127171
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.71973908
Short name T365
Test name
Test status
Simulation time 8387714559 ps
CPU time 8.89 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204120 kb
Host smart-23b27eae-b599-45d1-b171-03c173f008e8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=71973908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.71973908
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.1217646429
Short name T1065
Test name
Test status
Simulation time 8486415430 ps
CPU time 7.95 seconds
Started May 07 12:43:40 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 204112 kb
Host smart-8cd31e59-ac0d-48d6-8c35-d6cb1d8b4d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12176
46429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.1217646429
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3464174202
Short name T669
Test name
Test status
Simulation time 8375274004 ps
CPU time 8.74 seconds
Started May 07 12:43:40 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 204104 kb
Host smart-53d521c0-7e59-4d89-b2c5-13294119b14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34641
74202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3464174202
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.390392657
Short name T1086
Test name
Test status
Simulation time 8375165074 ps
CPU time 10.41 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:54 PM PDT 24
Peak memory 204132 kb
Host smart-6f954c0c-ca3a-4f0e-a573-4b02c94ab27c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39039
2657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.390392657
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2782592785
Short name T359
Test name
Test status
Simulation time 126700853 ps
CPU time 1.52 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:46 PM PDT 24
Peak memory 204196 kb
Host smart-32034a83-7663-48f8-9b9e-81e758da226a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27825
92785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2782592785
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.59278541
Short name T1367
Test name
Test status
Simulation time 8431083120 ps
CPU time 10.31 seconds
Started May 07 12:43:47 PM PDT 24
Finished May 07 12:43:59 PM PDT 24
Peak memory 204108 kb
Host smart-76499aba-1168-4b9e-9a01-cd6c49273132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59278
541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.59278541
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2322397390
Short name T568
Test name
Test status
Simulation time 8369229587 ps
CPU time 7.76 seconds
Started May 07 12:43:52 PM PDT 24
Finished May 07 12:44:02 PM PDT 24
Peak memory 204116 kb
Host smart-bec6a647-2bf8-4163-b737-9927d3daa3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23223
97390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2322397390
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3028800024
Short name T488
Test name
Test status
Simulation time 8459159690 ps
CPU time 8.32 seconds
Started May 07 12:43:37 PM PDT 24
Finished May 07 12:43:48 PM PDT 24
Peak memory 204144 kb
Host smart-aca87b87-2a33-4861-8c54-0ef6494913d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30288
00024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3028800024
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.870907341
Short name T1153
Test name
Test status
Simulation time 8413705088 ps
CPU time 7.89 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204156 kb
Host smart-75b3d7f1-1282-4e46-b5fb-2c79d06b1ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87090
7341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.870907341
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3644678291
Short name T607
Test name
Test status
Simulation time 8371519981 ps
CPU time 9.14 seconds
Started May 07 12:43:36 PM PDT 24
Finished May 07 12:43:47 PM PDT 24
Peak memory 204032 kb
Host smart-6760ab5b-8b81-4c83-b52d-e13d0cb97b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36446
78291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3644678291
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2420572613
Short name T127
Test name
Test status
Simulation time 8460788625 ps
CPU time 8.2 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204092 kb
Host smart-2709b575-c294-4a9e-8e43-817ee064ce0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24205
72613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2420572613
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2793526829
Short name T853
Test name
Test status
Simulation time 8371610802 ps
CPU time 7.31 seconds
Started May 07 12:43:43 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204084 kb
Host smart-8d0b8cfe-86e3-47ba-8e39-5d27e410299f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27935
26829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2793526829
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1470846515
Short name T321
Test name
Test status
Simulation time 8383902464 ps
CPU time 7.52 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 204068 kb
Host smart-d17868d9-c08f-4e46-9b3e-280d4733f6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14708
46515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1470846515
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3083158009
Short name T208
Test name
Test status
Simulation time 8416271460 ps
CPU time 7.36 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:52 PM PDT 24
Peak memory 204128 kb
Host smart-237620bf-4f57-4037-bb0b-1db2290a8dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30831
58009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3083158009
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.4043050949
Short name T9
Test name
Test status
Simulation time 8369981258 ps
CPU time 7.99 seconds
Started May 07 12:43:45 PM PDT 24
Finished May 07 12:43:55 PM PDT 24
Peak memory 204100 kb
Host smart-c3f5c18b-09ae-4332-a8d7-3e3bd5aa86b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40430
50949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.4043050949
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.1872043010
Short name T84
Test name
Test status
Simulation time 71214042 ps
CPU time 0.68 seconds
Started May 07 12:43:45 PM PDT 24
Finished May 07 12:43:48 PM PDT 24
Peak memory 203916 kb
Host smart-b49e8911-091e-4761-ae25-34d6b3de6023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18720
43010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.1872043010
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.610229462
Short name T660
Test name
Test status
Simulation time 27964365485 ps
CPU time 51.21 seconds
Started May 07 12:43:51 PM PDT 24
Finished May 07 12:44:45 PM PDT 24
Peak memory 204380 kb
Host smart-23c74dae-016a-424f-a866-af256857e3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61022
9462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.610229462
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.199042159
Short name T320
Test name
Test status
Simulation time 8485528304 ps
CPU time 8.5 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204112 kb
Host smart-44dfd87d-5c91-4fda-a54e-c9a8b552b053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19904
2159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.199042159
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2413907708
Short name T1206
Test name
Test status
Simulation time 8445950540 ps
CPU time 9.88 seconds
Started May 07 12:43:38 PM PDT 24
Finished May 07 12:43:50 PM PDT 24
Peak memory 204124 kb
Host smart-12ef3cdb-0404-4520-8970-6ec47f5c06f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24139
07708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2413907708
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2703653184
Short name T448
Test name
Test status
Simulation time 8405397353 ps
CPU time 7.38 seconds
Started May 07 12:43:44 PM PDT 24
Finished May 07 12:43:54 PM PDT 24
Peak memory 204116 kb
Host smart-ef90e1cb-2cf5-42c5-88d0-2e301e171932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27036
53184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2703653184
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2629819760
Short name T1281
Test name
Test status
Simulation time 8377835545 ps
CPU time 9.58 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204084 kb
Host smart-6170d2b2-2252-4e2c-9f9c-48b4b52990cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26298
19760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2629819760
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.4230655260
Short name T362
Test name
Test status
Simulation time 8367781831 ps
CPU time 8.29 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:52 PM PDT 24
Peak memory 204120 kb
Host smart-09b23838-4231-411c-886c-8b4f69e80106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42306
55260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.4230655260
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1245263483
Short name T93
Test name
Test status
Simulation time 8440761386 ps
CPU time 8.23 seconds
Started May 07 12:43:52 PM PDT 24
Finished May 07 12:44:03 PM PDT 24
Peak memory 204108 kb
Host smart-35546d99-23ac-4cf8-b628-e97182a1c4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12452
63483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1245263483
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3688864786
Short name T697
Test name
Test status
Simulation time 8414733310 ps
CPU time 8.16 seconds
Started May 07 12:43:44 PM PDT 24
Finished May 07 12:43:54 PM PDT 24
Peak memory 204128 kb
Host smart-809ff33f-ca28-4611-87a2-1168e3180427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36888
64786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3688864786
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3237647077
Short name T767
Test name
Test status
Simulation time 8401401378 ps
CPU time 7.87 seconds
Started May 07 12:43:59 PM PDT 24
Finished May 07 12:44:08 PM PDT 24
Peak memory 204088 kb
Host smart-a8811f2b-0fc0-43c4-8d4b-6ee324d56426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32376
47077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3237647077
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.950739789
Short name T472
Test name
Test status
Simulation time 8474158999 ps
CPU time 7.7 seconds
Started May 07 12:44:05 PM PDT 24
Finished May 07 12:44:15 PM PDT 24
Peak memory 204108 kb
Host smart-423c1861-7636-486a-bcee-19fd8db3acb9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=950739789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.950739789
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.3141603434
Short name T963
Test name
Test status
Simulation time 8379765067 ps
CPU time 7.52 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204140 kb
Host smart-b26df4e9-c5e5-4ed4-8f51-9220cb21e139
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3141603434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.3141603434
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.2300323867
Short name T32
Test name
Test status
Simulation time 8440817027 ps
CPU time 9.13 seconds
Started May 07 12:43:43 PM PDT 24
Finished May 07 12:43:54 PM PDT 24
Peak memory 204028 kb
Host smart-55d73ece-7163-4457-96a4-530164a5bebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23003
23867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.2300323867
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1737899684
Short name T1345
Test name
Test status
Simulation time 8399533575 ps
CPU time 8.29 seconds
Started May 07 12:43:47 PM PDT 24
Finished May 07 12:43:57 PM PDT 24
Peak memory 204112 kb
Host smart-a0ca6a5b-c892-4a32-804c-4c979774d746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17378
99684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1737899684
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.3236835978
Short name T326
Test name
Test status
Simulation time 8412047480 ps
CPU time 7.54 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 204136 kb
Host smart-e195ba3d-9cf5-49f8-9975-126fc1b87bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32368
35978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3236835978
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3177645473
Short name T820
Test name
Test status
Simulation time 217691648 ps
CPU time 1.79 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:45 PM PDT 24
Peak memory 204272 kb
Host smart-1e6964f3-7f7a-4fa6-9ce7-4c2cca8aeb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31776
45473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3177645473
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.2921699301
Short name T325
Test name
Test status
Simulation time 8434532342 ps
CPU time 8.36 seconds
Started May 07 12:44:05 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 204124 kb
Host smart-76e74abd-624a-4657-9737-10c40ddb62c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29216
99301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.2921699301
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2919888724
Short name T1110
Test name
Test status
Simulation time 8362466764 ps
CPU time 10.64 seconds
Started May 07 12:43:54 PM PDT 24
Finished May 07 12:44:06 PM PDT 24
Peak memory 204100 kb
Host smart-d157afaf-649a-42aa-b958-063492b8c10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29198
88724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2919888724
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.3895710052
Short name T547
Test name
Test status
Simulation time 8467160227 ps
CPU time 8.2 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204104 kb
Host smart-a7772b3d-da36-4717-9ada-67935a121159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38957
10052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3895710052
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3529242298
Short name T1253
Test name
Test status
Simulation time 8419491606 ps
CPU time 9.65 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:54 PM PDT 24
Peak memory 204144 kb
Host smart-fc3eacdf-efc4-4196-8faa-87eb3a3eec38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35292
42298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3529242298
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.656893378
Short name T306
Test name
Test status
Simulation time 8367994854 ps
CPU time 7.92 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204136 kb
Host smart-290d879e-d31a-4921-9999-11d07174228d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65689
3378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.656893378
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3881248940
Short name T1259
Test name
Test status
Simulation time 8462512336 ps
CPU time 7.59 seconds
Started May 07 12:43:43 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204092 kb
Host smart-ee89074a-d2c8-4be9-b87e-925f36c3f9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38812
48940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3881248940
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1119620667
Short name T1229
Test name
Test status
Simulation time 8411373309 ps
CPU time 7.83 seconds
Started May 07 12:44:05 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 204092 kb
Host smart-12e07db1-fe49-4751-b6fb-d8c042b58c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11196
20667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1119620667
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1472517163
Short name T826
Test name
Test status
Simulation time 8462230660 ps
CPU time 8.9 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204108 kb
Host smart-79286078-1d62-4ef9-a151-be5d5e1094b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14725
17163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1472517163
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3939412298
Short name T586
Test name
Test status
Simulation time 8417086907 ps
CPU time 7.62 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:52 PM PDT 24
Peak memory 204124 kb
Host smart-d63823ed-1904-4255-a076-8dcebbe48ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39394
12298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3939412298
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.94369418
Short name T861
Test name
Test status
Simulation time 8372970796 ps
CPU time 7.74 seconds
Started May 07 12:43:46 PM PDT 24
Finished May 07 12:43:56 PM PDT 24
Peak memory 204124 kb
Host smart-97a95e52-1e9d-47c1-a7be-a36a95774987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94369
418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.94369418
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2387778418
Short name T1130
Test name
Test status
Simulation time 118080083 ps
CPU time 0.73 seconds
Started May 07 12:44:00 PM PDT 24
Finished May 07 12:44:03 PM PDT 24
Peak memory 203988 kb
Host smart-b288ef4e-2ed5-46b2-8f90-6013981a317f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23877
78418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2387778418
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3225802358
Short name T457
Test name
Test status
Simulation time 17672551214 ps
CPU time 33.5 seconds
Started May 07 12:43:50 PM PDT 24
Finished May 07 12:44:26 PM PDT 24
Peak memory 204376 kb
Host smart-d904ddff-3ce8-48cd-aac5-41e83e077c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32258
02358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3225802358
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2197461678
Short name T334
Test name
Test status
Simulation time 8413440852 ps
CPU time 7.84 seconds
Started May 07 12:43:35 PM PDT 24
Finished May 07 12:43:44 PM PDT 24
Peak memory 204128 kb
Host smart-78a4f188-5e4d-4ad9-87f8-cd8937848a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21974
61678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2197461678
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.455229206
Short name T140
Test name
Test status
Simulation time 8441549497 ps
CPU time 8.67 seconds
Started May 07 12:43:40 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 204116 kb
Host smart-f75334bc-018a-4397-9d5b-b48ee751d0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45522
9206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.455229206
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.713714702
Short name T512
Test name
Test status
Simulation time 8399375588 ps
CPU time 7.73 seconds
Started May 07 12:43:48 PM PDT 24
Finished May 07 12:43:58 PM PDT 24
Peak memory 204124 kb
Host smart-ebcedbbd-4c12-4d2d-b72a-785872628b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71371
4702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.713714702
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.174978904
Short name T173
Test name
Test status
Simulation time 8380193125 ps
CPU time 7.51 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:52 PM PDT 24
Peak memory 204120 kb
Host smart-4531b8e0-9cc7-434b-9cb1-8be41b35e4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17497
8904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.174978904
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1780135668
Short name T926
Test name
Test status
Simulation time 8415017323 ps
CPU time 9.04 seconds
Started May 07 12:43:50 PM PDT 24
Finished May 07 12:44:01 PM PDT 24
Peak memory 204092 kb
Host smart-2ba22478-64ac-49c1-a89d-7eaf81ed15b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17801
35668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1780135668
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.577919760
Short name T1077
Test name
Test status
Simulation time 8469182839 ps
CPU time 8.24 seconds
Started May 07 12:43:45 PM PDT 24
Finished May 07 12:43:55 PM PDT 24
Peak memory 204100 kb
Host smart-fa26a0b7-c0c7-4b94-b6eb-c55b274a576e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57791
9760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.577919760
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.4261368462
Short name T393
Test name
Test status
Simulation time 8406796189 ps
CPU time 7.51 seconds
Started May 07 12:43:52 PM PDT 24
Finished May 07 12:44:01 PM PDT 24
Peak memory 204104 kb
Host smart-335d2622-1a8b-4d55-ac2c-50b9a0d3a3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42613
68462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.4261368462
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.1307207636
Short name T1010
Test name
Test status
Simulation time 8402081965 ps
CPU time 7.84 seconds
Started May 07 12:43:53 PM PDT 24
Finished May 07 12:44:03 PM PDT 24
Peak memory 204088 kb
Host smart-031e86c7-cf34-4fa8-a9b7-7a1426eb1018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13072
07636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.1307207636
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.2599823102
Short name T1013
Test name
Test status
Simulation time 8485766136 ps
CPU time 7.93 seconds
Started May 07 12:43:48 PM PDT 24
Finished May 07 12:43:58 PM PDT 24
Peak memory 204108 kb
Host smart-8a63439c-d452-4d9c-aa1b-9bda57aade77
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2599823102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.2599823102
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.3024531414
Short name T226
Test name
Test status
Simulation time 8380981820 ps
CPU time 8.01 seconds
Started May 07 12:43:45 PM PDT 24
Finished May 07 12:43:55 PM PDT 24
Peak memory 204128 kb
Host smart-7cb4994f-d4a2-4719-94b3-e3dd697c1c6b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3024531414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.3024531414
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.2869732147
Short name T1107
Test name
Test status
Simulation time 8400635966 ps
CPU time 9.59 seconds
Started May 07 12:43:49 PM PDT 24
Finished May 07 12:44:00 PM PDT 24
Peak memory 204028 kb
Host smart-2fd894e2-6b5b-4efb-bfdd-1a0707847078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28697
32147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.2869732147
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1939701935
Short name T414
Test name
Test status
Simulation time 8383520103 ps
CPU time 8.21 seconds
Started May 07 12:43:43 PM PDT 24
Finished May 07 12:43:54 PM PDT 24
Peak memory 204112 kb
Host smart-59b3d974-86d1-4dcb-8ebe-5943845eda5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19397
01935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1939701935
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.778231930
Short name T37
Test name
Test status
Simulation time 8395094188 ps
CPU time 8.75 seconds
Started May 07 12:43:44 PM PDT 24
Finished May 07 12:43:55 PM PDT 24
Peak memory 204108 kb
Host smart-bdf3edaa-ba3e-4df4-a0d0-851ac7ca9c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77823
1930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.778231930
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3171017414
Short name T526
Test name
Test status
Simulation time 63079304 ps
CPU time 1.61 seconds
Started May 07 12:44:06 PM PDT 24
Finished May 07 12:44:10 PM PDT 24
Peak memory 204084 kb
Host smart-77aefd3e-1409-4e3c-b0c9-74b112bb215d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31710
17414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3171017414
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.942826613
Short name T638
Test name
Test status
Simulation time 8424560444 ps
CPU time 10.06 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204084 kb
Host smart-61222ef9-825c-4e29-ba20-46f7d51e731b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94282
6613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.942826613
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2229022818
Short name T487
Test name
Test status
Simulation time 8377704303 ps
CPU time 8.67 seconds
Started May 07 12:44:06 PM PDT 24
Finished May 07 12:44:17 PM PDT 24
Peak memory 204132 kb
Host smart-4708aa5f-c0db-40be-8a42-3a2c5934de19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22290
22818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2229022818
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1460329972
Short name T714
Test name
Test status
Simulation time 8400650109 ps
CPU time 8.26 seconds
Started May 07 12:43:47 PM PDT 24
Finished May 07 12:43:57 PM PDT 24
Peak memory 204100 kb
Host smart-744e956b-055f-4940-8619-c70878b528cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14603
29972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1460329972
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.425422767
Short name T739
Test name
Test status
Simulation time 8419786194 ps
CPU time 7.74 seconds
Started May 07 12:43:47 PM PDT 24
Finished May 07 12:43:57 PM PDT 24
Peak memory 204156 kb
Host smart-69f994c0-ca00-42bc-a829-653ec4d21c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42542
2767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.425422767
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2689415582
Short name T964
Test name
Test status
Simulation time 8377833814 ps
CPU time 8.26 seconds
Started May 07 12:43:50 PM PDT 24
Finished May 07 12:44:00 PM PDT 24
Peak memory 204108 kb
Host smart-82ccc341-93f0-4ad1-b6f8-ff10b8bfd3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26894
15582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2689415582
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3324636752
Short name T113
Test name
Test status
Simulation time 8482883828 ps
CPU time 7.96 seconds
Started May 07 12:43:39 PM PDT 24
Finished May 07 12:43:49 PM PDT 24
Peak memory 204132 kb
Host smart-5b2affa2-8290-4aad-a228-f2eae0f23bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33246
36752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3324636752
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1585759493
Short name T354
Test name
Test status
Simulation time 8392717417 ps
CPU time 8 seconds
Started May 07 12:44:06 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 204104 kb
Host smart-60b63391-f3f0-42b3-83dc-9d1dc49c5e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15857
59493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1585759493
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.505156171
Short name T511
Test name
Test status
Simulation time 8387331533 ps
CPU time 7.61 seconds
Started May 07 12:43:53 PM PDT 24
Finished May 07 12:44:02 PM PDT 24
Peak memory 204092 kb
Host smart-dd5e2d94-d595-4907-a099-e4cbfccb378d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50515
6171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.505156171
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2252065584
Short name T523
Test name
Test status
Simulation time 8395006379 ps
CPU time 9.2 seconds
Started May 07 12:43:53 PM PDT 24
Finished May 07 12:44:04 PM PDT 24
Peak memory 204132 kb
Host smart-e2bf3a5c-ab45-4f2b-befd-10d4b7966197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22520
65584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2252065584
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.371522198
Short name T1101
Test name
Test status
Simulation time 46440780 ps
CPU time 0.67 seconds
Started May 07 12:43:43 PM PDT 24
Finished May 07 12:43:46 PM PDT 24
Peak memory 203876 kb
Host smart-8a7364a3-25de-4472-baf2-951befa2a295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37152
2198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.371522198
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.23552102
Short name T1030
Test name
Test status
Simulation time 20866097553 ps
CPU time 36.86 seconds
Started May 07 12:43:55 PM PDT 24
Finished May 07 12:44:38 PM PDT 24
Peak memory 204420 kb
Host smart-400c3704-338a-43ca-b8b5-4f4f1f4df0b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23552
102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.23552102
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2261747767
Short name T229
Test name
Test status
Simulation time 8369109511 ps
CPU time 9.14 seconds
Started May 07 12:43:51 PM PDT 24
Finished May 07 12:44:02 PM PDT 24
Peak memory 204120 kb
Host smart-d28e765e-6627-459b-b3dc-70660b178fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22617
47767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2261747767
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.552986999
Short name T1254
Test name
Test status
Simulation time 8443066628 ps
CPU time 7.54 seconds
Started May 07 12:43:55 PM PDT 24
Finished May 07 12:44:04 PM PDT 24
Peak memory 204116 kb
Host smart-37ee4e85-d44f-460f-a3d1-ae145fa49638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55298
6999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.552986999
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.2773261993
Short name T300
Test name
Test status
Simulation time 8384939138 ps
CPU time 7.5 seconds
Started May 07 12:43:54 PM PDT 24
Finished May 07 12:44:03 PM PDT 24
Peak memory 204104 kb
Host smart-8c090a43-e40c-4e63-a079-b03fe0439313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27732
61993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.2773261993
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.4222798184
Short name T947
Test name
Test status
Simulation time 8371518641 ps
CPU time 8.56 seconds
Started May 07 12:43:51 PM PDT 24
Finished May 07 12:44:02 PM PDT 24
Peak memory 204104 kb
Host smart-674d091a-0b70-4bf2-9b9a-2eceb0a19353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42227
98184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.4222798184
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.4269362777
Short name T364
Test name
Test status
Simulation time 8386165391 ps
CPU time 8.06 seconds
Started May 07 12:43:42 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204040 kb
Host smart-6c52f61b-46d9-41b7-94a8-7e3a6446cda1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42693
62777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.4269362777
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2436197590
Short name T1095
Test name
Test status
Simulation time 8505520949 ps
CPU time 8.73 seconds
Started May 07 12:43:43 PM PDT 24
Finished May 07 12:43:54 PM PDT 24
Peak memory 204084 kb
Host smart-bd25297b-fbda-4c06-bb1a-5a9f5d34bbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24361
97590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2436197590
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1562766269
Short name T564
Test name
Test status
Simulation time 8373512996 ps
CPU time 7.77 seconds
Started May 07 12:44:04 PM PDT 24
Finished May 07 12:44:14 PM PDT 24
Peak memory 204132 kb
Host smart-0af0086a-92fe-4e2e-94a6-8caadb2e1474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15627
66269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1562766269
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.4246267748
Short name T1241
Test name
Test status
Simulation time 8404297509 ps
CPU time 9.02 seconds
Started May 07 12:43:43 PM PDT 24
Finished May 07 12:43:55 PM PDT 24
Peak memory 204096 kb
Host smart-6a6cc508-8a83-4404-b086-ee27da8617c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42462
67748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.4246267748
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.3096960409
Short name T332
Test name
Test status
Simulation time 8466799579 ps
CPU time 10.04 seconds
Started May 07 12:43:48 PM PDT 24
Finished May 07 12:44:00 PM PDT 24
Peak memory 204124 kb
Host smart-25768b3e-9ab9-4280-a727-70e7a8434e95
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3096960409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.3096960409
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.93022672
Short name T605
Test name
Test status
Simulation time 8376884725 ps
CPU time 8.45 seconds
Started May 07 12:43:54 PM PDT 24
Finished May 07 12:44:04 PM PDT 24
Peak memory 204096 kb
Host smart-ccdb8974-a647-49bd-8d44-4892819eec90
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=93022672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.93022672
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.2305801925
Short name T1290
Test name
Test status
Simulation time 8461256153 ps
CPU time 7.8 seconds
Started May 07 12:43:52 PM PDT 24
Finished May 07 12:44:02 PM PDT 24
Peak memory 204088 kb
Host smart-48beac2e-e473-4fd0-bc47-4aff572d1b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23058
01925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.2305801925
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.735780357
Short name T644
Test name
Test status
Simulation time 8391492580 ps
CPU time 8.79 seconds
Started May 07 12:43:52 PM PDT 24
Finished May 07 12:44:03 PM PDT 24
Peak memory 204208 kb
Host smart-07f681b7-583e-46f2-a3c1-4e72c601f787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73578
0357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.735780357
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.1840079155
Short name T1162
Test name
Test status
Simulation time 8393784677 ps
CPU time 10.07 seconds
Started May 07 12:43:40 PM PDT 24
Finished May 07 12:43:53 PM PDT 24
Peak memory 204120 kb
Host smart-37f19bdc-5393-4dfc-a4de-22cce6ec5e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18400
79155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1840079155
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.4111620916
Short name T538
Test name
Test status
Simulation time 183045554 ps
CPU time 1.87 seconds
Started May 07 12:43:41 PM PDT 24
Finished May 07 12:43:45 PM PDT 24
Peak memory 204064 kb
Host smart-f4b9dd9e-05a1-4c07-b1a3-bb21853cc54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41116
20916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.4111620916
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2075590621
Short name T1341
Test name
Test status
Simulation time 8441756266 ps
CPU time 8.59 seconds
Started May 07 12:43:46 PM PDT 24
Finished May 07 12:43:57 PM PDT 24
Peak memory 204116 kb
Host smart-388c57a7-fd85-4875-acd6-0ef823ebeef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20755
90621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2075590621
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1524732201
Short name T780
Test name
Test status
Simulation time 8365845099 ps
CPU time 7.52 seconds
Started May 07 12:44:26 PM PDT 24
Finished May 07 12:44:35 PM PDT 24
Peak memory 204144 kb
Host smart-5d46b773-fdf1-4fd5-a04f-2453a12e830e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15247
32201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1524732201
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3684001149
Short name T160
Test name
Test status
Simulation time 8427432872 ps
CPU time 7.92 seconds
Started May 07 12:43:48 PM PDT 24
Finished May 07 12:43:58 PM PDT 24
Peak memory 204124 kb
Host smart-fda00537-7654-4e30-a19d-0a5f91881cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36840
01149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3684001149
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.830745453
Short name T682
Test name
Test status
Simulation time 8416369719 ps
CPU time 9.23 seconds
Started May 07 12:43:49 PM PDT 24
Finished May 07 12:44:00 PM PDT 24
Peak memory 204140 kb
Host smart-d2db875c-3e9f-4c6e-8e6e-610fba02c544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83074
5453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.830745453
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.240222474
Short name T314
Test name
Test status
Simulation time 8391077437 ps
CPU time 8.28 seconds
Started May 07 12:43:50 PM PDT 24
Finished May 07 12:44:00 PM PDT 24
Peak memory 204120 kb
Host smart-5fae1221-349e-4590-b889-10da869ca0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24022
2474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.240222474
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1766570839
Short name T117
Test name
Test status
Simulation time 8414477817 ps
CPU time 7.7 seconds
Started May 07 12:43:53 PM PDT 24
Finished May 07 12:44:03 PM PDT 24
Peak memory 204092 kb
Host smart-76a591c1-5bf3-47e8-b7ae-d744102381f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17665
70839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1766570839
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2320477099
Short name T562
Test name
Test status
Simulation time 8478736704 ps
CPU time 7.94 seconds
Started May 07 12:44:07 PM PDT 24
Finished May 07 12:44:17 PM PDT 24
Peak memory 204128 kb
Host smart-c889b334-f171-41ca-8217-268b0f4a4f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23204
77099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2320477099
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1384988819
Short name T551
Test name
Test status
Simulation time 8414805408 ps
CPU time 7.64 seconds
Started May 07 12:43:54 PM PDT 24
Finished May 07 12:44:04 PM PDT 24
Peak memory 204120 kb
Host smart-f68335a2-f40a-4e47-a9d7-aa761aea6d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13849
88819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1384988819
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.852939513
Short name T733
Test name
Test status
Simulation time 8378276867 ps
CPU time 7.88 seconds
Started May 07 12:43:47 PM PDT 24
Finished May 07 12:43:57 PM PDT 24
Peak memory 204128 kb
Host smart-5fe93b4e-d00c-49ce-a431-1e7e07ca0fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85293
9513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.852939513
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1977591194
Short name T477
Test name
Test status
Simulation time 8382503795 ps
CPU time 7.9 seconds
Started May 07 12:43:45 PM PDT 24
Finished May 07 12:43:55 PM PDT 24
Peak memory 204036 kb
Host smart-817b7a7e-1772-4af0-a6ba-429f588576f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19775
91194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1977591194
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.431956975
Short name T1146
Test name
Test status
Simulation time 58051081 ps
CPU time 0.68 seconds
Started May 07 12:43:48 PM PDT 24
Finished May 07 12:43:51 PM PDT 24
Peak memory 203988 kb
Host smart-f37a09ee-001c-462d-a2b7-306767220d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43195
6975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.431956975
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2902162764
Short name T253
Test name
Test status
Simulation time 25824185906 ps
CPU time 52.15 seconds
Started May 07 12:43:48 PM PDT 24
Finished May 07 12:44:42 PM PDT 24
Peak memory 204392 kb
Host smart-a3b8a645-050a-4279-b3d6-49c3dfcebd01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29021
62764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2902162764
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.136540203
Short name T869
Test name
Test status
Simulation time 8429651344 ps
CPU time 8.72 seconds
Started May 07 12:43:55 PM PDT 24
Finished May 07 12:44:05 PM PDT 24
Peak memory 204088 kb
Host smart-adf0027b-517a-4a66-8a5d-6537d3af972f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13654
0203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.136540203
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1808542968
Short name T435
Test name
Test status
Simulation time 8439999696 ps
CPU time 8.11 seconds
Started May 07 12:44:01 PM PDT 24
Finished May 07 12:44:11 PM PDT 24
Peak memory 204032 kb
Host smart-fe99b432-4c1a-4cb9-92e5-0466156ab505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18085
42968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1808542968
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.1093010137
Short name T1135
Test name
Test status
Simulation time 8424661208 ps
CPU time 7.43 seconds
Started May 07 12:44:01 PM PDT 24
Finished May 07 12:44:11 PM PDT 24
Peak memory 204124 kb
Host smart-a017b504-ae0f-4cd0-903d-6572dda090e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10930
10137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.1093010137
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.891861043
Short name T167
Test name
Test status
Simulation time 8399558585 ps
CPU time 7.99 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:26 PM PDT 24
Peak memory 204116 kb
Host smart-56bb15fe-e1f5-42ad-84ed-e32b88d28d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89186
1043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.891861043
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3284629643
Short name T631
Test name
Test status
Simulation time 8366614528 ps
CPU time 7.95 seconds
Started May 07 12:43:53 PM PDT 24
Finished May 07 12:44:03 PM PDT 24
Peak memory 204116 kb
Host smart-b5ac864f-f9ed-4647-b935-bdf21f27925d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32846
29643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3284629643
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.100207734
Short name T48
Test name
Test status
Simulation time 8465699524 ps
CPU time 9.03 seconds
Started May 07 12:43:57 PM PDT 24
Finished May 07 12:44:07 PM PDT 24
Peak memory 204076 kb
Host smart-674addd7-ed58-4580-afd6-d1b179117fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10020
7734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.100207734
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2713226627
Short name T138
Test name
Test status
Simulation time 8418780457 ps
CPU time 9.16 seconds
Started May 07 12:43:40 PM PDT 24
Finished May 07 12:43:52 PM PDT 24
Peak memory 204128 kb
Host smart-9f1b49b5-7c5f-4439-8cdb-73bb3b9048b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27132
26627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2713226627
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2112684801
Short name T648
Test name
Test status
Simulation time 8401304124 ps
CPU time 9.55 seconds
Started May 07 12:43:44 PM PDT 24
Finished May 07 12:43:56 PM PDT 24
Peak memory 204168 kb
Host smart-8f6ca62e-714b-42aa-8357-442c61b84a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21126
84801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2112684801
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.4065723437
Short name T1019
Test name
Test status
Simulation time 8380177333 ps
CPU time 8.84 seconds
Started May 07 12:43:56 PM PDT 24
Finished May 07 12:44:07 PM PDT 24
Peak memory 204076 kb
Host smart-084b5810-e6ec-4724-afc1-9be2916cda68
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4065723437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.4065723437
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1016200160
Short name T421
Test name
Test status
Simulation time 8373680413 ps
CPU time 8.89 seconds
Started May 07 12:43:56 PM PDT 24
Finished May 07 12:44:06 PM PDT 24
Peak memory 204092 kb
Host smart-893daced-02a3-4c70-9992-4f8c96c4a742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10162
00160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1016200160
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.3296209314
Short name T1372
Test name
Test status
Simulation time 8386779039 ps
CPU time 8.15 seconds
Started May 07 12:43:59 PM PDT 24
Finished May 07 12:44:09 PM PDT 24
Peak memory 204136 kb
Host smart-fb2aa883-4382-46fd-9495-770cca82611c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32962
09314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3296209314
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3550589526
Short name T346
Test name
Test status
Simulation time 188921583 ps
CPU time 1.96 seconds
Started May 07 12:44:26 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 204172 kb
Host smart-fe7ebb73-fac2-4485-b989-69ae483926eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35505
89526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3550589526
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3758904729
Short name T1133
Test name
Test status
Simulation time 8406491171 ps
CPU time 7.52 seconds
Started May 07 12:43:53 PM PDT 24
Finished May 07 12:44:02 PM PDT 24
Peak memory 204084 kb
Host smart-c6656fb8-a3c4-4abc-8228-dace6577d513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37589
04729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3758904729
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.4161792192
Short name T201
Test name
Test status
Simulation time 8363181136 ps
CPU time 9.01 seconds
Started May 07 12:44:06 PM PDT 24
Finished May 07 12:44:17 PM PDT 24
Peak memory 204140 kb
Host smart-3fc80f27-dcad-407d-8071-1926b7727408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41617
92192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.4161792192
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.4033626147
Short name T886
Test name
Test status
Simulation time 8397953801 ps
CPU time 9.51 seconds
Started May 07 12:44:12 PM PDT 24
Finished May 07 12:44:24 PM PDT 24
Peak memory 204044 kb
Host smart-82388067-5e8c-43aa-bcf5-407779afb74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40336
26147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.4033626147
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1505871839
Short name T434
Test name
Test status
Simulation time 8411946262 ps
CPU time 7.68 seconds
Started May 07 12:43:53 PM PDT 24
Finished May 07 12:44:03 PM PDT 24
Peak memory 204120 kb
Host smart-96c80d81-ec9a-4be3-b5f3-f9a6f1d42402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15058
71839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1505871839
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3176224113
Short name T311
Test name
Test status
Simulation time 8370843200 ps
CPU time 7.7 seconds
Started May 07 12:43:46 PM PDT 24
Finished May 07 12:43:56 PM PDT 24
Peak memory 204212 kb
Host smart-4bac42f4-fe35-489b-96ba-9b634a5a9752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31762
24113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3176224113
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2697776360
Short name T105
Test name
Test status
Simulation time 8417263254 ps
CPU time 8.47 seconds
Started May 07 12:43:52 PM PDT 24
Finished May 07 12:44:02 PM PDT 24
Peak memory 204084 kb
Host smart-4decb868-9c2e-4f2f-9d5a-7078df598daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26977
76360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2697776360
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2299901699
Short name T548
Test name
Test status
Simulation time 8405286127 ps
CPU time 8.69 seconds
Started May 07 12:43:56 PM PDT 24
Finished May 07 12:44:06 PM PDT 24
Peak memory 204084 kb
Host smart-5bafd203-e085-48ae-b96c-2bc7ea56d206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22999
01699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2299901699
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2232849092
Short name T28
Test name
Test status
Simulation time 8420822149 ps
CPU time 8.61 seconds
Started May 07 12:43:51 PM PDT 24
Finished May 07 12:44:01 PM PDT 24
Peak memory 204104 kb
Host smart-968de8bf-13e5-480f-b5ea-ff9c8d342129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22328
49092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2232849092
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.3031847258
Short name T198
Test name
Test status
Simulation time 8423196743 ps
CPU time 9.47 seconds
Started May 07 12:43:57 PM PDT 24
Finished May 07 12:44:08 PM PDT 24
Peak memory 204136 kb
Host smart-f6abfa19-cdb4-4e7a-a2b8-be8e9dd3fb47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30318
47258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.3031847258
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.926611702
Short name T786
Test name
Test status
Simulation time 81196371 ps
CPU time 0.73 seconds
Started May 07 12:44:03 PM PDT 24
Finished May 07 12:44:06 PM PDT 24
Peak memory 204180 kb
Host smart-68e49ec7-f853-4ed5-85c0-c700fabc1251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92661
1702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.926611702
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2661638256
Short name T1246
Test name
Test status
Simulation time 19518006570 ps
CPU time 38.1 seconds
Started May 07 12:43:48 PM PDT 24
Finished May 07 12:44:28 PM PDT 24
Peak memory 204284 kb
Host smart-194348fe-87c5-4977-acda-0d00b887324d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26616
38256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2661638256
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.143534029
Short name T658
Test name
Test status
Simulation time 8432347850 ps
CPU time 7.62 seconds
Started May 07 12:43:50 PM PDT 24
Finished May 07 12:43:59 PM PDT 24
Peak memory 204000 kb
Host smart-7d3e5457-0091-4139-9324-ce256fc099a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
4029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.143534029
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.322975392
Short name T522
Test name
Test status
Simulation time 8419174649 ps
CPU time 7.96 seconds
Started May 07 12:43:56 PM PDT 24
Finished May 07 12:44:05 PM PDT 24
Peak memory 204168 kb
Host smart-c753fb92-c874-402e-9273-b8480644cb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32297
5392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.322975392
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.2007941615
Short name T1001
Test name
Test status
Simulation time 8424519483 ps
CPU time 7.8 seconds
Started May 07 12:43:48 PM PDT 24
Finished May 07 12:43:58 PM PDT 24
Peak memory 204136 kb
Host smart-b748e7bc-105f-42dc-84f1-f02e3b650bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20079
41615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.2007941615
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1334437903
Short name T924
Test name
Test status
Simulation time 8377991738 ps
CPU time 10.08 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:28 PM PDT 24
Peak memory 204168 kb
Host smart-ff625d7e-0c49-4a20-a938-2bc617d01197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13344
37903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1334437903
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.4029267722
Short name T883
Test name
Test status
Simulation time 8367736599 ps
CPU time 8.19 seconds
Started May 07 12:44:06 PM PDT 24
Finished May 07 12:44:17 PM PDT 24
Peak memory 204108 kb
Host smart-14eaf19f-3241-434a-ae8e-19989650b132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40292
67722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.4029267722
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1958189474
Short name T1023
Test name
Test status
Simulation time 8433623473 ps
CPU time 10.6 seconds
Started May 07 12:43:59 PM PDT 24
Finished May 07 12:44:11 PM PDT 24
Peak memory 204044 kb
Host smart-c43745d7-f7ef-4f6f-b88b-c69f8464554c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19581
89474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1958189474
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1899216255
Short name T1226
Test name
Test status
Simulation time 8374501794 ps
CPU time 7.75 seconds
Started May 07 12:44:05 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 204132 kb
Host smart-00511815-dd35-4e3d-bba4-e162e940e44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18992
16255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1899216255
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1519150676
Short name T525
Test name
Test status
Simulation time 8383117852 ps
CPU time 7.91 seconds
Started May 07 12:43:58 PM PDT 24
Finished May 07 12:44:07 PM PDT 24
Peak memory 204088 kb
Host smart-7af40edd-6944-4a2b-8eec-933ec06a6e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15191
50676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1519150676
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.3410172341
Short name T699
Test name
Test status
Simulation time 8461638024 ps
CPU time 8.86 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:27 PM PDT 24
Peak memory 204076 kb
Host smart-9d618a7d-664c-430c-b997-98b843947991
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3410172341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.3410172341
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.874676266
Short name T510
Test name
Test status
Simulation time 8442466096 ps
CPU time 10.7 seconds
Started May 07 12:44:07 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 203652 kb
Host smart-8a1f0b9f-47c8-428f-8576-0b08eecc15fa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=874676266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.874676266
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.2536061176
Short name T1191
Test name
Test status
Simulation time 8467641666 ps
CPU time 8.2 seconds
Started May 07 12:44:03 PM PDT 24
Finished May 07 12:44:13 PM PDT 24
Peak memory 204068 kb
Host smart-99f36ebc-aa63-487a-847b-6b1a964f00a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25360
61176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.2536061176
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.804511364
Short name T318
Test name
Test status
Simulation time 8377930161 ps
CPU time 8.18 seconds
Started May 07 12:44:13 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 204172 kb
Host smart-e4373686-10c6-4a52-b3c2-c20c4ff725c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80451
1364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.804511364
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.3478027944
Short name T1113
Test name
Test status
Simulation time 8378332277 ps
CPU time 8.67 seconds
Started May 07 12:43:56 PM PDT 24
Finished May 07 12:44:06 PM PDT 24
Peak memory 204112 kb
Host smart-24d5b11a-781a-4b06-b770-ccd55b349cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34780
27944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3478027944
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3739602298
Short name T814
Test name
Test status
Simulation time 64953301 ps
CPU time 1.39 seconds
Started May 07 12:44:08 PM PDT 24
Finished May 07 12:44:11 PM PDT 24
Peak memory 204204 kb
Host smart-d5777edf-af88-4d35-86e6-7126af686ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37396
02298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3739602298
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3253748373
Short name T835
Test name
Test status
Simulation time 8397640397 ps
CPU time 8.81 seconds
Started May 07 12:44:02 PM PDT 24
Finished May 07 12:44:13 PM PDT 24
Peak memory 204084 kb
Host smart-7001f871-e11b-4635-9427-c2bc87d2fe08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32537
48373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3253748373
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.813442049
Short name T205
Test name
Test status
Simulation time 8395106481 ps
CPU time 8.81 seconds
Started May 07 12:44:02 PM PDT 24
Finished May 07 12:44:13 PM PDT 24
Peak memory 204076 kb
Host smart-34a318b9-4ffa-4ba9-b738-bbe1df1cb2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81344
2049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.813442049
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1908350327
Short name T1011
Test name
Test status
Simulation time 8456197024 ps
CPU time 7.87 seconds
Started May 07 12:44:00 PM PDT 24
Finished May 07 12:44:10 PM PDT 24
Peak memory 204120 kb
Host smart-6775337e-2af4-414c-9f8e-f6a88e26d1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19083
50327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1908350327
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2850407427
Short name T978
Test name
Test status
Simulation time 8414321313 ps
CPU time 9.58 seconds
Started May 07 12:44:07 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 204100 kb
Host smart-f90b3407-a067-4ec9-a56d-bb7c2f0e3b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28504
07427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2850407427
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3361655883
Short name T655
Test name
Test status
Simulation time 8410922928 ps
CPU time 8.32 seconds
Started May 07 12:43:59 PM PDT 24
Finished May 07 12:44:09 PM PDT 24
Peak memory 204124 kb
Host smart-a6674a94-0a01-4e38-bea9-e7040248c730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33616
55883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3361655883
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3447539718
Short name T118
Test name
Test status
Simulation time 8437999519 ps
CPU time 8.43 seconds
Started May 07 12:43:56 PM PDT 24
Finished May 07 12:44:06 PM PDT 24
Peak memory 204068 kb
Host smart-602a3dd3-e369-40d3-a2f9-ddf4ce6d7ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34475
39718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3447539718
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.21898323
Short name T1166
Test name
Test status
Simulation time 8408059260 ps
CPU time 8.9 seconds
Started May 07 12:43:53 PM PDT 24
Finished May 07 12:44:04 PM PDT 24
Peak memory 204300 kb
Host smart-9b6ecfbe-7e29-4a0e-9c84-f8768022b9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21898
323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.21898323
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.198662855
Short name T1071
Test name
Test status
Simulation time 8401883284 ps
CPU time 7.6 seconds
Started May 07 12:44:04 PM PDT 24
Finished May 07 12:44:14 PM PDT 24
Peak memory 204104 kb
Host smart-1625c148-5108-426d-b798-dc6494524f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19866
2855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.198662855
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.628522650
Short name T192
Test name
Test status
Simulation time 8390779634 ps
CPU time 8.9 seconds
Started May 07 12:44:05 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 204092 kb
Host smart-b6bc9aa3-ca97-401b-97d8-a5b7ffaf38c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62852
2650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.628522650
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3466396707
Short name T740
Test name
Test status
Simulation time 8425585555 ps
CPU time 9.68 seconds
Started May 07 12:44:06 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 204140 kb
Host smart-0ee2347f-b854-4e6f-9881-30cfd3110162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34663
96707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3466396707
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2375221619
Short name T719
Test name
Test status
Simulation time 40863005 ps
CPU time 0.63 seconds
Started May 07 12:43:57 PM PDT 24
Finished May 07 12:43:59 PM PDT 24
Peak memory 203964 kb
Host smart-11935f6d-49bc-446f-9b6e-2ab42d865bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23752
21619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2375221619
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.794033616
Short name T1083
Test name
Test status
Simulation time 29193135212 ps
CPU time 65.09 seconds
Started May 07 12:43:51 PM PDT 24
Finished May 07 12:44:58 PM PDT 24
Peak memory 204376 kb
Host smart-ae496926-e20a-4baf-bf9f-0e27a02fba88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79403
3616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.794033616
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1308885617
Short name T1221
Test name
Test status
Simulation time 8378872859 ps
CPU time 8.57 seconds
Started May 07 12:43:53 PM PDT 24
Finished May 07 12:44:03 PM PDT 24
Peak memory 203640 kb
Host smart-ae409b34-cb07-4ee3-b26e-68758f60b02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13088
85617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1308885617
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.433653487
Short name T661
Test name
Test status
Simulation time 8445888676 ps
CPU time 10.17 seconds
Started May 07 12:44:00 PM PDT 24
Finished May 07 12:44:12 PM PDT 24
Peak memory 204128 kb
Host smart-5343876c-112b-439b-95d1-8aa4ee984699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43365
3487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.433653487
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.2739165532
Short name T337
Test name
Test status
Simulation time 8403671833 ps
CPU time 9.44 seconds
Started May 07 12:44:05 PM PDT 24
Finished May 07 12:44:17 PM PDT 24
Peak memory 204148 kb
Host smart-56eee536-8229-4e95-96f0-6be759e8b5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27391
65532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.2739165532
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2321104112
Short name T220
Test name
Test status
Simulation time 8396385879 ps
CPU time 7.76 seconds
Started May 07 12:44:00 PM PDT 24
Finished May 07 12:44:09 PM PDT 24
Peak memory 204100 kb
Host smart-25c630b3-fbb8-42ad-82a3-3f8d73a6037c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23211
04112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2321104112
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3416404463
Short name T614
Test name
Test status
Simulation time 8366870960 ps
CPU time 8.71 seconds
Started May 07 12:44:07 PM PDT 24
Finished May 07 12:44:18 PM PDT 24
Peak memory 204116 kb
Host smart-1545655e-ba56-4a15-8558-18556ba5023a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34164
04463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3416404463
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.396566531
Short name T166
Test name
Test status
Simulation time 8419125083 ps
CPU time 7.67 seconds
Started May 07 12:44:04 PM PDT 24
Finished May 07 12:44:14 PM PDT 24
Peak memory 204124 kb
Host smart-c1cda040-b401-48ab-8191-eceb1c4e7318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39656
6531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.396566531
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.1326785678
Short name T797
Test name
Test status
Simulation time 8384396310 ps
CPU time 7.19 seconds
Started May 07 12:44:12 PM PDT 24
Finished May 07 12:44:22 PM PDT 24
Peak memory 204128 kb
Host smart-7d413830-db4f-44cc-b28a-8ca8c471ce5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13267
85678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1326785678
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2792945265
Short name T593
Test name
Test status
Simulation time 8408334116 ps
CPU time 9.4 seconds
Started May 07 12:44:05 PM PDT 24
Finished May 07 12:44:17 PM PDT 24
Peak memory 204116 kb
Host smart-fa589234-f778-4299-9bbc-aefcacda41b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27929
45265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2792945265
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.1475083332
Short name T1108
Test name
Test status
Simulation time 8465216464 ps
CPU time 9.42 seconds
Started May 07 12:44:04 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 204096 kb
Host smart-1ffd9c1c-d3e5-41e9-b78f-d816f589b41c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1475083332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.1475083332
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.2035911426
Short name T1256
Test name
Test status
Simulation time 8381190958 ps
CPU time 8.62 seconds
Started May 07 12:44:11 PM PDT 24
Finished May 07 12:44:22 PM PDT 24
Peak memory 203648 kb
Host smart-bb5cb164-2bc3-43c5-828c-2098bb2d273f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2035911426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.2035911426
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.3820130671
Short name T432
Test name
Test status
Simulation time 8410729905 ps
CPU time 8.86 seconds
Started May 07 12:44:10 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 204116 kb
Host smart-e1e63e5d-5da3-433e-bbdf-6a72f873c888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38201
30671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.3820130671
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1913178847
Short name T310
Test name
Test status
Simulation time 8413351419 ps
CPU time 7.49 seconds
Started May 07 12:44:02 PM PDT 24
Finished May 07 12:44:12 PM PDT 24
Peak memory 204092 kb
Host smart-4096ae2b-f5d1-4871-9215-0a43cc146167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19131
78847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1913178847
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.2944930479
Short name T1315
Test name
Test status
Simulation time 8390128045 ps
CPU time 7.6 seconds
Started May 07 12:44:21 PM PDT 24
Finished May 07 12:44:31 PM PDT 24
Peak memory 204124 kb
Host smart-22246b24-a899-442b-a1d2-a1529a359367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29449
30479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2944930479
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2486863528
Short name T539
Test name
Test status
Simulation time 69926734 ps
CPU time 1.37 seconds
Started May 07 12:44:14 PM PDT 24
Finished May 07 12:44:18 PM PDT 24
Peak memory 204196 kb
Host smart-18cdf44c-790c-465c-9b69-941a7631afe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24868
63528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2486863528
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3965869227
Short name T556
Test name
Test status
Simulation time 8404308663 ps
CPU time 7.85 seconds
Started May 07 12:44:14 PM PDT 24
Finished May 07 12:44:25 PM PDT 24
Peak memory 204132 kb
Host smart-1b94f272-10ac-4976-9d4f-4b5af9d99a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39658
69227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3965869227
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3050542422
Short name T721
Test name
Test status
Simulation time 8368129609 ps
CPU time 9 seconds
Started May 07 12:44:11 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 204088 kb
Host smart-538ed917-5f93-4d18-851b-8beffeaa020f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30505
42422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3050542422
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1111199039
Short name T599
Test name
Test status
Simulation time 8475257112 ps
CPU time 10.69 seconds
Started May 07 12:44:02 PM PDT 24
Finished May 07 12:44:15 PM PDT 24
Peak memory 204132 kb
Host smart-f04e41ec-0595-47d8-aeda-58888b1f282c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11111
99039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1111199039
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1504351356
Short name T821
Test name
Test status
Simulation time 8414706455 ps
CPU time 8.38 seconds
Started May 07 12:44:15 PM PDT 24
Finished May 07 12:44:26 PM PDT 24
Peak memory 204128 kb
Host smart-97709f2c-eec0-4ecd-b3dc-438b1a2bd542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15043
51356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1504351356
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3612630867
Short name T471
Test name
Test status
Simulation time 8375685017 ps
CPU time 10.64 seconds
Started May 07 12:43:50 PM PDT 24
Finished May 07 12:44:03 PM PDT 24
Peak memory 204132 kb
Host smart-cd004a94-8db8-4888-b9b3-04a137c94880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36126
30867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3612630867
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1254671181
Short name T132
Test name
Test status
Simulation time 8453259444 ps
CPU time 8 seconds
Started May 07 12:44:09 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 204108 kb
Host smart-f60946f1-e147-4530-ab73-662dbb199d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12546
71181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1254671181
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1760063083
Short name T876
Test name
Test status
Simulation time 8414455133 ps
CPU time 7.61 seconds
Started May 07 12:44:03 PM PDT 24
Finished May 07 12:44:13 PM PDT 24
Peak memory 204076 kb
Host smart-9c6ab3da-4d1c-4c8f-96c3-10fa5c760195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17600
63083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1760063083
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.2725146989
Short name T515
Test name
Test status
Simulation time 8410614502 ps
CPU time 7.46 seconds
Started May 07 12:44:12 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 204116 kb
Host smart-ea8a7218-1caa-4f93-bf9f-9f4a11ad920c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27251
46989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.2725146989
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3680004219
Short name T1208
Test name
Test status
Simulation time 8423680400 ps
CPU time 8.34 seconds
Started May 07 12:44:11 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 203684 kb
Host smart-98e5490a-40b2-442c-a993-f44467f0e932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36800
04219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3680004219
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2919421187
Short name T441
Test name
Test status
Simulation time 8398399034 ps
CPU time 8.63 seconds
Started May 07 12:44:09 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 204136 kb
Host smart-ef9c08b4-647c-4761-a9e9-0c1f62cd6f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29194
21187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2919421187
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.4254167682
Short name T41
Test name
Test status
Simulation time 52082861 ps
CPU time 0.67 seconds
Started May 07 12:44:04 PM PDT 24
Finished May 07 12:44:07 PM PDT 24
Peak memory 203956 kb
Host smart-d6aea306-c259-40d3-8995-a715f7d27b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42541
67682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.4254167682
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1326661965
Short name T907
Test name
Test status
Simulation time 22856970557 ps
CPU time 39.93 seconds
Started May 07 12:43:59 PM PDT 24
Finished May 07 12:44:41 PM PDT 24
Peak memory 204404 kb
Host smart-17e0be68-b79a-49c6-a578-b80925022614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13266
61965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1326661965
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.614235338
Short name T642
Test name
Test status
Simulation time 8387039874 ps
CPU time 8.38 seconds
Started May 07 12:44:15 PM PDT 24
Finished May 07 12:44:26 PM PDT 24
Peak memory 204108 kb
Host smart-0e5f1a0a-5ed1-426a-a369-ec4ce01480a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61423
5338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.614235338
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3767341955
Short name T663
Test name
Test status
Simulation time 8473371046 ps
CPU time 9.18 seconds
Started May 07 12:44:14 PM PDT 24
Finished May 07 12:44:25 PM PDT 24
Peak memory 204132 kb
Host smart-a0f900a9-2d23-47bc-854d-6dd4b71c1c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37673
41955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3767341955
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.264781490
Short name T442
Test name
Test status
Simulation time 8399238214 ps
CPU time 7.24 seconds
Started May 07 12:44:14 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 204144 kb
Host smart-0cac1ec4-358f-4fa0-bd50-f473f155027b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26478
1490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.264781490
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1942419345
Short name T702
Test name
Test status
Simulation time 8396898805 ps
CPU time 7.87 seconds
Started May 07 12:44:08 PM PDT 24
Finished May 07 12:44:18 PM PDT 24
Peak memory 204116 kb
Host smart-a685c28d-8dde-4a4a-b490-aaafc4b51f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19424
19345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1942419345
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2723629282
Short name T456
Test name
Test status
Simulation time 8376693463 ps
CPU time 8.92 seconds
Started May 07 12:44:14 PM PDT 24
Finished May 07 12:44:25 PM PDT 24
Peak memory 204116 kb
Host smart-432eeea5-96a2-48b4-84e7-5396fcd386b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27236
29282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2723629282
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.641597786
Short name T384
Test name
Test status
Simulation time 8453458876 ps
CPU time 8.02 seconds
Started May 07 12:44:04 PM PDT 24
Finished May 07 12:44:14 PM PDT 24
Peak memory 204120 kb
Host smart-20332710-60ef-445b-8409-3789756d6635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64159
7786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.641597786
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2588302009
Short name T1027
Test name
Test status
Simulation time 8398114057 ps
CPU time 7.86 seconds
Started May 07 12:44:03 PM PDT 24
Finished May 07 12:44:13 PM PDT 24
Peak memory 204304 kb
Host smart-1927ab12-5575-408c-90d8-dda6f7e9023d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25883
02009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2588302009
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2840612687
Short name T952
Test name
Test status
Simulation time 8388614864 ps
CPU time 8.39 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:27 PM PDT 24
Peak memory 204084 kb
Host smart-9e535218-f57b-4108-ae5e-321463f7f6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28406
12687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2840612687
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.3021488507
Short name T223
Test name
Test status
Simulation time 8467746033 ps
CPU time 8.57 seconds
Started May 07 12:44:10 PM PDT 24
Finished May 07 12:44:20 PM PDT 24
Peak memory 204108 kb
Host smart-599ac141-697b-4878-abf6-7025906057fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3021488507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.3021488507
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.435242335
Short name T854
Test name
Test status
Simulation time 8370912573 ps
CPU time 7.64 seconds
Started May 07 12:44:04 PM PDT 24
Finished May 07 12:44:14 PM PDT 24
Peak memory 204148 kb
Host smart-57959751-17e0-473b-a381-3ec9a2db7ff0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=435242335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.435242335
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.2917742970
Short name T464
Test name
Test status
Simulation time 8448402102 ps
CPU time 7.64 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:26 PM PDT 24
Peak memory 204116 kb
Host smart-a4b00b12-042d-4d31-83c9-b301eae2864f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29177
42970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.2917742970
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.186480318
Short name T1289
Test name
Test status
Simulation time 8375469229 ps
CPU time 7.83 seconds
Started May 07 12:44:18 PM PDT 24
Finished May 07 12:44:28 PM PDT 24
Peak memory 204128 kb
Host smart-12544a0d-d76d-47ee-9af0-8cd7b4fef89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18648
0318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.186480318
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.3243097332
Short name T541
Test name
Test status
Simulation time 8378748973 ps
CPU time 8.08 seconds
Started May 07 12:44:06 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 204124 kb
Host smart-6ba48cae-83f3-4863-9880-a508c5ccf19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32430
97332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3243097332
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.4262605892
Short name T1047
Test name
Test status
Simulation time 157796520 ps
CPU time 1.55 seconds
Started May 07 12:44:10 PM PDT 24
Finished May 07 12:44:13 PM PDT 24
Peak memory 204232 kb
Host smart-50b68307-d7c7-415e-9236-ddd90720a00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42626
05892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.4262605892
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.1921179695
Short name T747
Test name
Test status
Simulation time 8426221348 ps
CPU time 7.65 seconds
Started May 07 12:44:10 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 204136 kb
Host smart-9585f879-737b-4537-ad82-92186bef6cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19211
79695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.1921179695
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.323478349
Short name T1376
Test name
Test status
Simulation time 8380678317 ps
CPU time 7.8 seconds
Started May 07 12:44:13 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 204100 kb
Host smart-6f473027-f84d-4750-a86d-63a7adfd9ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32347
8349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.323478349
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4192514653
Short name T149
Test name
Test status
Simulation time 8407652337 ps
CPU time 7.92 seconds
Started May 07 12:43:54 PM PDT 24
Finished May 07 12:44:09 PM PDT 24
Peak memory 204132 kb
Host smart-16d44de0-7b17-4f73-b13d-a8d6b7609419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41925
14653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4192514653
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2367815867
Short name T339
Test name
Test status
Simulation time 8425853741 ps
CPU time 8.49 seconds
Started May 07 12:44:03 PM PDT 24
Finished May 07 12:44:14 PM PDT 24
Peak memory 204168 kb
Host smart-a52c13ad-5873-469f-9194-bd3dd2aeb0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23678
15867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2367815867
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2727856035
Short name T1235
Test name
Test status
Simulation time 8376746920 ps
CPU time 8.8 seconds
Started May 07 12:43:57 PM PDT 24
Finished May 07 12:44:08 PM PDT 24
Peak memory 204136 kb
Host smart-1dd27dd9-9b02-4270-a428-041f20bc27c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27278
56035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2727856035
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1908245000
Short name T121
Test name
Test status
Simulation time 8446252658 ps
CPU time 8.22 seconds
Started May 07 12:44:09 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 204092 kb
Host smart-b0461da1-1765-4a69-9ea2-cdd8e250b075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19082
45000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1908245000
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.4193874099
Short name T898
Test name
Test status
Simulation time 8413198378 ps
CPU time 7.83 seconds
Started May 07 12:44:04 PM PDT 24
Finished May 07 12:44:14 PM PDT 24
Peak memory 204128 kb
Host smart-cef49429-dece-45d7-90ec-99742d60d5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41938
74099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.4193874099
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2183292042
Short name T1002
Test name
Test status
Simulation time 8409225389 ps
CPU time 7.79 seconds
Started May 07 12:44:00 PM PDT 24
Finished May 07 12:44:09 PM PDT 24
Peak memory 204116 kb
Host smart-77ac1abf-34d4-4088-9de9-cfd01eeec123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21832
92042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2183292042
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1709399909
Short name T1353
Test name
Test status
Simulation time 8380546952 ps
CPU time 8.72 seconds
Started May 07 12:44:08 PM PDT 24
Finished May 07 12:44:19 PM PDT 24
Peak memory 204132 kb
Host smart-b84808ad-1682-40fc-bd74-fdebde48f46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17093
99909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1709399909
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.481334380
Short name T852
Test name
Test status
Simulation time 8395534218 ps
CPU time 8.08 seconds
Started May 07 12:44:04 PM PDT 24
Finished May 07 12:44:15 PM PDT 24
Peak memory 204120 kb
Host smart-1349bf1b-6499-4202-9567-8d478abddccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48133
4380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.481334380
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2454556360
Short name T1194
Test name
Test status
Simulation time 164762234 ps
CPU time 0.74 seconds
Started May 07 12:44:26 PM PDT 24
Finished May 07 12:44:29 PM PDT 24
Peak memory 204004 kb
Host smart-234f4e55-51c9-4eea-9858-b48d1944f281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24545
56360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2454556360
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.593635330
Short name T97
Test name
Test status
Simulation time 29807965682 ps
CPU time 58.05 seconds
Started May 07 12:44:04 PM PDT 24
Finished May 07 12:45:05 PM PDT 24
Peak memory 204420 kb
Host smart-c6620cf5-0c22-438d-b75e-3055b4758111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59363
5330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.593635330
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.261376218
Short name T428
Test name
Test status
Simulation time 8410703480 ps
CPU time 7.63 seconds
Started May 07 12:44:01 PM PDT 24
Finished May 07 12:44:11 PM PDT 24
Peak memory 204120 kb
Host smart-933776d6-35a1-4a5f-a93b-3c6e6c721060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26137
6218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.261376218
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.890157116
Short name T532
Test name
Test status
Simulation time 8421383149 ps
CPU time 7.55 seconds
Started May 07 12:44:01 PM PDT 24
Finished May 07 12:44:10 PM PDT 24
Peak memory 204128 kb
Host smart-0c9b0d6d-f06e-4db8-8d64-becd43457688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89015
7116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.890157116
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.751284806
Short name T633
Test name
Test status
Simulation time 8437574236 ps
CPU time 9.12 seconds
Started May 07 12:44:10 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 204060 kb
Host smart-4c1e6212-dc5c-44f7-b862-ea3a5ae206d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75128
4806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.751284806
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2337676273
Short name T386
Test name
Test status
Simulation time 8382588980 ps
CPU time 7.76 seconds
Started May 07 12:44:15 PM PDT 24
Finished May 07 12:44:25 PM PDT 24
Peak memory 204096 kb
Host smart-1b36d994-58d4-4a05-bcbc-48c117680f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23376
76273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2337676273
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2165698027
Short name T1129
Test name
Test status
Simulation time 8373352785 ps
CPU time 7.65 seconds
Started May 07 12:43:55 PM PDT 24
Finished May 07 12:44:05 PM PDT 24
Peak memory 204112 kb
Host smart-ae86ca91-9465-4af6-a1eb-570ebcaf7f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21656
98027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2165698027
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3743832452
Short name T158
Test name
Test status
Simulation time 8426438494 ps
CPU time 7.91 seconds
Started May 07 12:44:05 PM PDT 24
Finished May 07 12:44:15 PM PDT 24
Peak memory 204124 kb
Host smart-582bc12a-789e-474e-990c-0e849b0c3dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37438
32452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3743832452
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3212087945
Short name T585
Test name
Test status
Simulation time 8381957050 ps
CPU time 9.16 seconds
Started May 07 12:44:05 PM PDT 24
Finished May 07 12:44:16 PM PDT 24
Peak memory 204120 kb
Host smart-772adb33-6a56-40a4-bb5e-18e44aaaa8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32120
87945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3212087945
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.784114160
Short name T1242
Test name
Test status
Simulation time 8404616583 ps
CPU time 8.57 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:28 PM PDT 24
Peak memory 204120 kb
Host smart-346dea05-ca6f-4947-a470-5b5313c7d374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78411
4160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.784114160
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.1948010209
Short name T1007
Test name
Test status
Simulation time 8472013582 ps
CPU time 7.9 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:40 PM PDT 24
Peak memory 204124 kb
Host smart-ebf20ec0-076e-4e30-86bf-16c8262774fe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1948010209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.1948010209
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.3130137432
Short name T1078
Test name
Test status
Simulation time 8378173229 ps
CPU time 8.06 seconds
Started May 07 12:44:30 PM PDT 24
Finished May 07 12:44:41 PM PDT 24
Peak memory 203648 kb
Host smart-ec899874-6115-47c2-bb21-7cd1f8444933
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3130137432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.3130137432
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.4228060682
Short name T807
Test name
Test status
Simulation time 8421904531 ps
CPU time 8.14 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 204084 kb
Host smart-867c5d1b-ef4e-47be-a582-945207ff9115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42280
60682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.4228060682
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1020396561
Short name T404
Test name
Test status
Simulation time 8375722624 ps
CPU time 7.82 seconds
Started May 07 12:44:22 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 204084 kb
Host smart-0a338e09-59fa-4755-bf83-e078518ddbd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10203
96561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1020396561
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.2368499766
Short name T1312
Test name
Test status
Simulation time 8372097347 ps
CPU time 8.5 seconds
Started May 07 12:44:17 PM PDT 24
Finished May 07 12:44:28 PM PDT 24
Peak memory 204088 kb
Host smart-407b31e4-7838-4300-9816-c4551a711ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23684
99766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2368499766
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.4126390133
Short name T735
Test name
Test status
Simulation time 152483710 ps
CPU time 1.2 seconds
Started May 07 12:44:11 PM PDT 24
Finished May 07 12:44:15 PM PDT 24
Peak memory 204204 kb
Host smart-104afb6d-5a83-4bd7-9577-00a036c0498f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41263
90133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.4126390133
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1962428088
Short name T154
Test name
Test status
Simulation time 8440007896 ps
CPU time 9.15 seconds
Started May 07 12:44:15 PM PDT 24
Finished May 07 12:44:27 PM PDT 24
Peak memory 204092 kb
Host smart-af4de3ce-aac5-405d-8a90-2d4940d186a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19624
28088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1962428088
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1479000923
Short name T1300
Test name
Test status
Simulation time 8369272369 ps
CPU time 8.63 seconds
Started May 07 12:44:13 PM PDT 24
Finished May 07 12:44:24 PM PDT 24
Peak memory 204040 kb
Host smart-99ef8207-6c4b-4a45-b3fa-9e96085ce57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14790
00923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1479000923
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3309554980
Short name T602
Test name
Test status
Simulation time 8377255366 ps
CPU time 8.45 seconds
Started May 07 12:44:10 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 204132 kb
Host smart-91c960fc-70f8-4bc0-a41e-7eba1d847d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33095
54980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3309554980
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1298204741
Short name T751
Test name
Test status
Simulation time 8417234729 ps
CPU time 8.87 seconds
Started May 07 12:44:16 PM PDT 24
Finished May 07 12:44:28 PM PDT 24
Peak memory 204212 kb
Host smart-719af030-f322-4ce9-a420-920cf20d075b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12982
04741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1298204741
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3284017427
Short name T1069
Test name
Test status
Simulation time 8371116248 ps
CPU time 7.82 seconds
Started May 07 12:44:14 PM PDT 24
Finished May 07 12:44:24 PM PDT 24
Peak memory 204136 kb
Host smart-86143e27-0384-42ac-b202-47bab6f6d46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32840
17427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3284017427
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1429177156
Short name T136
Test name
Test status
Simulation time 8423131686 ps
CPU time 8.36 seconds
Started May 07 12:44:13 PM PDT 24
Finished May 07 12:44:24 PM PDT 24
Peak memory 204076 kb
Host smart-6753194a-26f0-4d5d-8c29-eba9dc6e6b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14291
77156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1429177156
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2203531904
Short name T458
Test name
Test status
Simulation time 8445315557 ps
CPU time 8.33 seconds
Started May 07 12:44:23 PM PDT 24
Finished May 07 12:44:33 PM PDT 24
Peak memory 204076 kb
Host smart-e9466d33-c789-4440-8617-2a892cb3b87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22035
31904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2203531904
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3181971106
Short name T315
Test name
Test status
Simulation time 8388553615 ps
CPU time 8.51 seconds
Started May 07 12:44:20 PM PDT 24
Finished May 07 12:44:31 PM PDT 24
Peak memory 203936 kb
Host smart-399b1c89-6489-4f8d-a621-ab73222f6967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31819
71106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3181971106
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3810905494
Short name T176
Test name
Test status
Simulation time 8398491444 ps
CPU time 8.41 seconds
Started May 07 12:44:19 PM PDT 24
Finished May 07 12:44:30 PM PDT 24
Peak memory 204116 kb
Host smart-1ae62872-699f-405a-9430-73137ce21c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38109
05494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3810905494
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3819019393
Short name T1323
Test name
Test status
Simulation time 8366271274 ps
CPU time 7.81 seconds
Started May 07 12:44:07 PM PDT 24
Finished May 07 12:44:22 PM PDT 24
Peak memory 204152 kb
Host smart-5d25bbdd-5d38-4800-9fd2-bee5ea4ab569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38190
19393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3819019393
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.563283969
Short name T667
Test name
Test status
Simulation time 49254857 ps
CPU time 0.68 seconds
Started May 07 12:44:12 PM PDT 24
Finished May 07 12:44:15 PM PDT 24
Peak memory 203984 kb
Host smart-6208380a-563b-4375-9c31-b5c18666c9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56328
3969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.563283969
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.4267658085
Short name T221
Test name
Test status
Simulation time 25670214080 ps
CPU time 44.72 seconds
Started May 07 12:44:11 PM PDT 24
Finished May 07 12:44:58 PM PDT 24
Peak memory 204416 kb
Host smart-ef11d81b-c1a8-404d-900c-8732614ef21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42676
58085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.4267658085
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.858333696
Short name T670
Test name
Test status
Simulation time 8381073514 ps
CPU time 9.17 seconds
Started May 07 12:44:15 PM PDT 24
Finished May 07 12:44:27 PM PDT 24
Peak memory 204020 kb
Host smart-9e37b928-9181-473c-a82b-3fdac28d81cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85833
3696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.858333696
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2657258535
Short name T408
Test name
Test status
Simulation time 8482090940 ps
CPU time 9.27 seconds
Started May 07 12:44:14 PM PDT 24
Finished May 07 12:44:25 PM PDT 24
Peak memory 204172 kb
Host smart-3a86fe5d-a504-4783-90b8-50c94529e673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26572
58535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2657258535
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.3243832624
Short name T756
Test name
Test status
Simulation time 8433017660 ps
CPU time 7.88 seconds
Started May 07 12:44:24 PM PDT 24
Finished May 07 12:44:34 PM PDT 24
Peak memory 204300 kb
Host smart-ef9a5666-3642-40ee-b788-d2951d7f8bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32438
32624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.3243832624
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1141452339
Short name T47
Test name
Test status
Simulation time 8369997022 ps
CPU time 10.03 seconds
Started May 07 12:44:11 PM PDT 24
Finished May 07 12:44:23 PM PDT 24
Peak memory 204084 kb
Host smart-f8cb7cdd-6a30-4c3c-8357-74bfb10610bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11414
52339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1141452339
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.239531218
Short name T613
Test name
Test status
Simulation time 8380794499 ps
CPU time 8.45 seconds
Started May 07 12:44:10 PM PDT 24
Finished May 07 12:44:21 PM PDT 24
Peak memory 204100 kb
Host smart-bdcc53aa-fb84-4a1a-8ca2-0f77b0ebbbc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23953
1218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.239531218
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.812543243
Short name T172
Test name
Test status
Simulation time 8452497765 ps
CPU time 7.8 seconds
Started May 07 12:44:29 PM PDT 24
Finished May 07 12:44:39 PM PDT 24
Peak memory 204044 kb
Host smart-6de2b04b-a3c9-451d-8749-9a9b2e636313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81254
3243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.812543243
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2316167446
Short name T552
Test name
Test status
Simulation time 8389149527 ps
CPU time 7.49 seconds
Started May 07 12:44:15 PM PDT 24
Finished May 07 12:44:25 PM PDT 24
Peak memory 204112 kb
Host smart-2843a8cc-df72-473a-b8b0-85edb92b06c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23161
67446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2316167446
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.35766434
Short name T344
Test name
Test status
Simulation time 8426894428 ps
CPU time 8.3 seconds
Started May 07 12:44:21 PM PDT 24
Finished May 07 12:44:32 PM PDT 24
Peak memory 204096 kb
Host smart-b0d4fb6c-d967-48cf-b6be-eddbb9437970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35766
434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.35766434
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.2832338864
Short name T929
Test name
Test status
Simulation time 8463115232 ps
CPU time 10.62 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:52 PM PDT 24
Peak memory 204092 kb
Host smart-fe8afb81-5c94-4287-9ba9-3e2c384eeefd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2832338864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.2832338864
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.1860930969
Short name T403
Test name
Test status
Simulation time 8383023970 ps
CPU time 8.75 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:45 PM PDT 24
Peak memory 204072 kb
Host smart-f9040ca5-e1dd-4467-bfda-0371f50bd7b1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1860930969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.1860930969
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.3213161978
Short name T684
Test name
Test status
Simulation time 8407344084 ps
CPU time 7.72 seconds
Started May 07 12:41:34 PM PDT 24
Finished May 07 12:41:44 PM PDT 24
Peak memory 204040 kb
Host smart-52268f5f-7450-4a6d-9f8b-ebd5d8622167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32131
61978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.3213161978
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.383980506
Short name T1243
Test name
Test status
Simulation time 8378963186 ps
CPU time 8.64 seconds
Started May 07 12:41:31 PM PDT 24
Finished May 07 12:41:41 PM PDT 24
Peak memory 204012 kb
Host smart-278d5191-3ef1-44b7-8a2b-e136ec1492f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38398
0506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.383980506
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.2992769537
Short name T544
Test name
Test status
Simulation time 8385249837 ps
CPU time 7.75 seconds
Started May 07 12:41:26 PM PDT 24
Finished May 07 12:41:35 PM PDT 24
Peak memory 204136 kb
Host smart-c6c8b645-71e4-44a0-b2bd-4a3d88324fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29927
69537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2992769537
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.647152710
Short name T960
Test name
Test status
Simulation time 192264479 ps
CPU time 1.81 seconds
Started May 07 12:41:21 PM PDT 24
Finished May 07 12:41:24 PM PDT 24
Peak memory 204256 kb
Host smart-e41cd95f-036e-4b33-bdad-b152eb93fa2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64715
2710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.647152710
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2903912798
Short name T1236
Test name
Test status
Simulation time 8447265922 ps
CPU time 7.75 seconds
Started May 07 12:41:32 PM PDT 24
Finished May 07 12:41:41 PM PDT 24
Peak memory 204036 kb
Host smart-90214ccd-61fc-4bd8-90d0-a8c205c1a592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29039
12798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2903912798
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1523250538
Short name T191
Test name
Test status
Simulation time 8369360471 ps
CPU time 7.87 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:45 PM PDT 24
Peak memory 204044 kb
Host smart-4f7a0905-84c9-4443-aeab-749d9b512187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15232
50538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1523250538
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2607012140
Short name T839
Test name
Test status
Simulation time 8383281738 ps
CPU time 7.86 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:42 PM PDT 24
Peak memory 203632 kb
Host smart-31142938-e79f-4da4-9e5e-c452200f8b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26070
12140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2607012140
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3370454943
Short name T656
Test name
Test status
Simulation time 8414225147 ps
CPU time 8.45 seconds
Started May 07 12:41:41 PM PDT 24
Finished May 07 12:41:51 PM PDT 24
Peak memory 204144 kb
Host smart-b0a736c2-8a27-476d-bba6-0875f9c9fda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33704
54943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3370454943
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3342375553
Short name T79
Test name
Test status
Simulation time 8369196141 ps
CPU time 9.17 seconds
Started May 07 12:41:30 PM PDT 24
Finished May 07 12:41:41 PM PDT 24
Peak memory 204152 kb
Host smart-44b6b76c-333c-4d8a-8649-e854e7d03bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33423
75553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3342375553
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1676002344
Short name T107
Test name
Test status
Simulation time 8429010349 ps
CPU time 9.88 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:46 PM PDT 24
Peak memory 204104 kb
Host smart-dd8eef15-f7f7-465c-b944-fba8f7380e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16760
02344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1676002344
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2280865536
Short name T645
Test name
Test status
Simulation time 8377490339 ps
CPU time 9.22 seconds
Started May 07 12:41:38 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204092 kb
Host smart-57f7ab4e-633a-4df1-b638-836b2f40b51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22808
65536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2280865536
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3740922347
Short name T26
Test name
Test status
Simulation time 8396012666 ps
CPU time 8.01 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:43 PM PDT 24
Peak memory 204020 kb
Host smart-391bffbf-b2cb-4c5e-811b-23b08767b609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37409
22347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3740922347
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.604489664
Short name T1267
Test name
Test status
Simulation time 8397044023 ps
CPU time 7.84 seconds
Started May 07 12:41:51 PM PDT 24
Finished May 07 12:42:00 PM PDT 24
Peak memory 204040 kb
Host smart-48a9f21a-73d6-490b-9017-f956eaea4ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60448
9664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.604489664
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1373449487
Short name T20
Test name
Test status
Simulation time 8413848294 ps
CPU time 7.52 seconds
Started May 07 12:41:38 PM PDT 24
Finished May 07 12:41:48 PM PDT 24
Peak memory 204104 kb
Host smart-a741f1f0-1505-4580-a378-0454e721cec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13734
49487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1373449487
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.494556854
Short name T1016
Test name
Test status
Simulation time 103987432 ps
CPU time 0.74 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:36 PM PDT 24
Peak memory 203988 kb
Host smart-e450192b-6c36-45ef-9caa-e71a5f442d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49455
6854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.494556854
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2720228242
Short name T840
Test name
Test status
Simulation time 21389206502 ps
CPU time 37.7 seconds
Started May 07 12:41:34 PM PDT 24
Finished May 07 12:42:13 PM PDT 24
Peak memory 204416 kb
Host smart-cb1196a8-521b-4f97-b790-8980fd37e937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
28242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2720228242
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2086869369
Short name T731
Test name
Test status
Simulation time 8425753109 ps
CPU time 8.37 seconds
Started May 07 12:41:31 PM PDT 24
Finished May 07 12:41:40 PM PDT 24
Peak memory 204104 kb
Host smart-3c822382-d371-4363-8a96-a4637e0c84b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20868
69369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2086869369
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.965763606
Short name T52
Test name
Test status
Simulation time 8407219375 ps
CPU time 7.69 seconds
Started May 07 12:41:53 PM PDT 24
Finished May 07 12:42:03 PM PDT 24
Peak memory 204072 kb
Host smart-497e914c-4c85-468d-8b6e-45e0445a964c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96576
3606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.965763606
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1019936302
Short name T582
Test name
Test status
Simulation time 8395524136 ps
CPU time 8.28 seconds
Started May 07 12:41:28 PM PDT 24
Finished May 07 12:41:37 PM PDT 24
Peak memory 204032 kb
Host smart-8ffecf7e-c7fe-4746-bd7a-4245ee1dffa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10199
36302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1019936302
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1966052225
Short name T588
Test name
Test status
Simulation time 8384280008 ps
CPU time 7.8 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204116 kb
Host smart-cc9189b4-ee71-4787-ab22-5ffced4924c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19660
52225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1966052225
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.2581471502
Short name T85
Test name
Test status
Simulation time 8369799588 ps
CPU time 10.46 seconds
Started May 07 12:41:41 PM PDT 24
Finished May 07 12:41:53 PM PDT 24
Peak memory 204080 kb
Host smart-107524f0-8032-468f-a093-e59fb6535393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25814
71502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.2581471502
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.425431733
Short name T96
Test name
Test status
Simulation time 8464254910 ps
CPU time 8.12 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204120 kb
Host smart-4a56b9f3-a31c-43a2-b632-7051a0fff3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42543
1733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.425431733
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2617260074
Short name T215
Test name
Test status
Simulation time 8420924861 ps
CPU time 9.1 seconds
Started May 07 12:41:44 PM PDT 24
Finished May 07 12:41:55 PM PDT 24
Peak memory 204124 kb
Host smart-5af92dab-2428-48fe-84b0-251897c1c6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26172
60074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2617260074
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1215228245
Short name T849
Test name
Test status
Simulation time 8379318666 ps
CPU time 9.82 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:51 PM PDT 24
Peak memory 204108 kb
Host smart-4d8c613b-6291-4f86-9900-8d58b6a8318d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12152
28245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1215228245
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.465177516
Short name T1076
Test name
Test status
Simulation time 8465522348 ps
CPU time 7.47 seconds
Started May 07 12:41:49 PM PDT 24
Finished May 07 12:41:58 PM PDT 24
Peak memory 204132 kb
Host smart-2353646a-5b26-432a-ad1c-8fd868f9262c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=465177516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.465177516
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.4223519317
Short name T979
Test name
Test status
Simulation time 8377459862 ps
CPU time 9.04 seconds
Started May 07 12:41:32 PM PDT 24
Finished May 07 12:41:42 PM PDT 24
Peak memory 204124 kb
Host smart-7fbe1a1e-0e48-4910-ab57-c42c276b2339
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4223519317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.4223519317
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.448179761
Short name T1165
Test name
Test status
Simulation time 8431340422 ps
CPU time 8.01 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204116 kb
Host smart-2b7dd15a-e98f-4c8b-9755-6006d89b8d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44817
9761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.448179761
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3321374448
Short name T1142
Test name
Test status
Simulation time 8380001829 ps
CPU time 7.92 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:45 PM PDT 24
Peak memory 204048 kb
Host smart-899685f8-278a-4785-b41d-e354402dcf8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33213
74448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3321374448
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.447157905
Short name T382
Test name
Test status
Simulation time 8382054211 ps
CPU time 9.67 seconds
Started May 07 12:41:43 PM PDT 24
Finished May 07 12:41:55 PM PDT 24
Peak memory 204120 kb
Host smart-7535c765-cc7a-4faf-99e9-3581be2961bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44715
7905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.447157905
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.48961212
Short name T164
Test name
Test status
Simulation time 8394772982 ps
CPU time 7.67 seconds
Started May 07 12:41:36 PM PDT 24
Finished May 07 12:41:46 PM PDT 24
Peak memory 204136 kb
Host smart-9188ee23-b2d8-4634-89c3-6055d6f7097b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48961
212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.48961212
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2382991329
Short name T999
Test name
Test status
Simulation time 8361423422 ps
CPU time 8.36 seconds
Started May 07 12:41:36 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204132 kb
Host smart-c73c9099-83ea-427d-b4e4-d31a88f549d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23829
91329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2382991329
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3164806079
Short name T449
Test name
Test status
Simulation time 8423401126 ps
CPU time 9.36 seconds
Started May 07 12:41:41 PM PDT 24
Finished May 07 12:41:52 PM PDT 24
Peak memory 204116 kb
Host smart-cf510544-d46b-4b7c-ac94-2cb5028698ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31648
06079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3164806079
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.642968137
Short name T1035
Test name
Test status
Simulation time 8421063863 ps
CPU time 7.87 seconds
Started May 07 12:41:40 PM PDT 24
Finished May 07 12:41:50 PM PDT 24
Peak memory 204156 kb
Host smart-26544ff7-f81b-4057-8701-1277c3af24b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64296
8137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.642968137
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1930625069
Short name T397
Test name
Test status
Simulation time 8382407303 ps
CPU time 7.68 seconds
Started May 07 12:41:38 PM PDT 24
Finished May 07 12:41:48 PM PDT 24
Peak memory 204140 kb
Host smart-f3fd63a2-8bd6-4a27-a45d-0d914e2c6b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19306
25069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1930625069
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3349175348
Short name T120
Test name
Test status
Simulation time 8424876853 ps
CPU time 9.97 seconds
Started May 07 12:41:40 PM PDT 24
Finished May 07 12:41:52 PM PDT 24
Peak memory 204088 kb
Host smart-34e8a969-690b-41c4-9b6d-529d7fdf462c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33491
75348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3349175348
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1002901419
Short name T1087
Test name
Test status
Simulation time 8401891244 ps
CPU time 7.57 seconds
Started May 07 12:41:45 PM PDT 24
Finished May 07 12:41:54 PM PDT 24
Peak memory 204124 kb
Host smart-a9b91a47-39eb-4e92-993b-63a1d81e8348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10029
01419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1002901419
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1033803302
Short name T543
Test name
Test status
Simulation time 8403799919 ps
CPU time 7.79 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:44 PM PDT 24
Peak memory 204036 kb
Host smart-fdf4fbaa-7a65-4821-89bb-7241522e820b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10338
03302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1033803302
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2954780941
Short name T1346
Test name
Test status
Simulation time 8419771032 ps
CPU time 8.69 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:43 PM PDT 24
Peak memory 204128 kb
Host smart-d29dee34-0ca9-4d75-a59b-f0eaa58651c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29547
80941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2954780941
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3842705805
Short name T842
Test name
Test status
Simulation time 8373221119 ps
CPU time 7.61 seconds
Started May 07 12:41:38 PM PDT 24
Finished May 07 12:41:48 PM PDT 24
Peak memory 204128 kb
Host smart-26356e96-5cec-4c4a-9943-a4a691c2fce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38427
05805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3842705805
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.598240970
Short name T834
Test name
Test status
Simulation time 35298899 ps
CPU time 0.66 seconds
Started May 07 12:41:34 PM PDT 24
Finished May 07 12:41:37 PM PDT 24
Peak memory 203988 kb
Host smart-199f0008-066a-47b3-8b4c-29612b6ea975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59824
0970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.598240970
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3550338350
Short name T1114
Test name
Test status
Simulation time 18387819083 ps
CPU time 32.82 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204408 kb
Host smart-33111ef9-333b-4c09-9892-da3f8cbfad33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35503
38350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3550338350
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1985674886
Short name T829
Test name
Test status
Simulation time 8429477820 ps
CPU time 7.97 seconds
Started May 07 12:41:28 PM PDT 24
Finished May 07 12:41:37 PM PDT 24
Peak memory 204120 kb
Host smart-f9f8df2b-6526-4626-8c22-7f264aba0c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19856
74886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1985674886
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.836796809
Short name T752
Test name
Test status
Simulation time 8431115669 ps
CPU time 7.87 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204076 kb
Host smart-d25187c4-cee4-4779-9688-d60438f40c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83679
6809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.836796809
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.1029353901
Short name T1151
Test name
Test status
Simulation time 8416940538 ps
CPU time 8.99 seconds
Started May 07 12:41:24 PM PDT 24
Finished May 07 12:41:34 PM PDT 24
Peak memory 204144 kb
Host smart-97f1752d-1037-4ce7-917e-09221af9034b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10293
53901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.1029353901
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.4123249433
Short name T430
Test name
Test status
Simulation time 8447059874 ps
CPU time 7.94 seconds
Started May 07 12:41:36 PM PDT 24
Finished May 07 12:41:46 PM PDT 24
Peak memory 204076 kb
Host smart-19ddaf95-94f8-49f1-824a-8ec107f094aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41232
49433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.4123249433
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1507771356
Short name T1167
Test name
Test status
Simulation time 8373382437 ps
CPU time 9.8 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:45 PM PDT 24
Peak memory 204120 kb
Host smart-00a1da2a-09dd-4739-979a-87640473669d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15077
71356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1507771356
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1484263994
Short name T1137
Test name
Test status
Simulation time 8432931654 ps
CPU time 8.05 seconds
Started May 07 12:41:40 PM PDT 24
Finished May 07 12:41:50 PM PDT 24
Peak memory 204088 kb
Host smart-81655924-0221-41ae-bb2a-c82a1df4cccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14842
63994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1484263994
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3466282196
Short name T357
Test name
Test status
Simulation time 8372527101 ps
CPU time 10.55 seconds
Started May 07 12:41:30 PM PDT 24
Finished May 07 12:41:42 PM PDT 24
Peak memory 204116 kb
Host smart-1eb301f6-ada5-4af0-acd2-bcd2c1a7f23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34662
82196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3466282196
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2641803185
Short name T577
Test name
Test status
Simulation time 8417020151 ps
CPU time 9.07 seconds
Started May 07 12:41:32 PM PDT 24
Finished May 07 12:41:42 PM PDT 24
Peak memory 204204 kb
Host smart-69582ce9-b7bd-42df-bc5b-051ba6d5be15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26418
03185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2641803185
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.2942711217
Short name T680
Test name
Test status
Simulation time 8465340764 ps
CPU time 8.95 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204116 kb
Host smart-adf7ab5b-55aa-4d48-a367-9b26b848ed78
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2942711217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.2942711217
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.3526115526
Short name T781
Test name
Test status
Simulation time 8386817491 ps
CPU time 9.76 seconds
Started May 07 12:42:00 PM PDT 24
Finished May 07 12:42:12 PM PDT 24
Peak memory 204144 kb
Host smart-10180703-cc6c-4a81-a26e-006b9dac6706
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3526115526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.3526115526
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.3989985914
Short name T1338
Test name
Test status
Simulation time 8432314424 ps
CPU time 9.73 seconds
Started May 07 12:41:36 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204060 kb
Host smart-331e314b-c62d-4945-873e-ea9009c642fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39899
85914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.3989985914
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.4244467671
Short name T380
Test name
Test status
Simulation time 8375793570 ps
CPU time 7.7 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204128 kb
Host smart-f8ac0bf3-ba86-404b-994f-810a44dbbfdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42444
67671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.4244467671
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.3949560328
Short name T1188
Test name
Test status
Simulation time 8378290808 ps
CPU time 10.13 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:51 PM PDT 24
Peak memory 204128 kb
Host smart-84918801-b37a-4239-96ed-5ecfb63a6f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39495
60328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3949560328
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1684202987
Short name T872
Test name
Test status
Simulation time 62878789 ps
CPU time 1.56 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:41 PM PDT 24
Peak memory 204116 kb
Host smart-56b761ea-3741-4159-9911-da79185dbdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16842
02987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1684202987
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.616750097
Short name T918
Test name
Test status
Simulation time 8454728208 ps
CPU time 7.62 seconds
Started May 07 12:41:43 PM PDT 24
Finished May 07 12:41:53 PM PDT 24
Peak memory 204176 kb
Host smart-d95a762e-9aaf-437f-9980-e85759bc4da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61675
0097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.616750097
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1127022439
Short name T1175
Test name
Test status
Simulation time 8379457986 ps
CPU time 8.06 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:04 PM PDT 24
Peak memory 204116 kb
Host smart-eb8487bf-b932-470e-9541-3261e400029d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11270
22439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1127022439
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3489336795
Short name T493
Test name
Test status
Simulation time 8384171747 ps
CPU time 8.39 seconds
Started May 07 12:41:49 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 204044 kb
Host smart-93d836e9-3c95-4fd3-b4c6-9f3e53c7df38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34893
36795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3489336795
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3848996322
Short name T894
Test name
Test status
Simulation time 8407976381 ps
CPU time 7.43 seconds
Started May 07 12:41:49 PM PDT 24
Finished May 07 12:41:58 PM PDT 24
Peak memory 204052 kb
Host smart-abbfc172-cc94-44a7-a511-d261d20f87b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38489
96322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3848996322
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2017837266
Short name T447
Test name
Test status
Simulation time 8374348073 ps
CPU time 7.81 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204148 kb
Host smart-82a5d20c-c1ea-483d-b7c9-1a5e4ec90ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20178
37266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2017837266
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.115813164
Short name T122
Test name
Test status
Simulation time 8419280030 ps
CPU time 7.97 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204032 kb
Host smart-ebadaca9-041f-47f2-ab6e-20178d587c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11581
3164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.115813164
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1884276569
Short name T1262
Test name
Test status
Simulation time 8397025662 ps
CPU time 7.74 seconds
Started May 07 12:41:45 PM PDT 24
Finished May 07 12:41:55 PM PDT 24
Peak memory 204144 kb
Host smart-e9a22f48-1f99-4fc9-b3af-6c4399bf47f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18842
76569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1884276569
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3550809136
Short name T647
Test name
Test status
Simulation time 8402509863 ps
CPU time 8.5 seconds
Started May 07 12:41:49 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 204040 kb
Host smart-a36f7cd0-530b-4366-b749-d06bc3e5806c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35508
09136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3550809136
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2165071499
Short name T715
Test name
Test status
Simulation time 8400690564 ps
CPU time 8 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:44 PM PDT 24
Peak memory 203960 kb
Host smart-4df76eb6-391e-46e2-b5fd-33cceb65320e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21650
71499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2165071499
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.159162663
Short name T21
Test name
Test status
Simulation time 8385989382 ps
CPU time 10.13 seconds
Started May 07 12:41:38 PM PDT 24
Finished May 07 12:41:50 PM PDT 24
Peak memory 204140 kb
Host smart-bcfe43da-35f8-47f7-acae-6f3f623d44a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15916
2663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.159162663
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2517564028
Short name T412
Test name
Test status
Simulation time 56490147 ps
CPU time 0.69 seconds
Started May 07 12:41:50 PM PDT 24
Finished May 07 12:41:52 PM PDT 24
Peak memory 203932 kb
Host smart-deae5fcc-2389-4d30-9c01-c8a859512c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25175
64028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2517564028
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1206123048
Short name T230
Test name
Test status
Simulation time 25784362375 ps
CPU time 46.25 seconds
Started May 07 12:41:45 PM PDT 24
Finished May 07 12:42:33 PM PDT 24
Peak memory 204316 kb
Host smart-72b640c7-9f3f-4edd-9f14-750e922c98eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12061
23048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1206123048
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1290370520
Short name T652
Test name
Test status
Simulation time 8390786535 ps
CPU time 7.78 seconds
Started May 07 12:41:50 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 204120 kb
Host smart-a678ac54-8d55-497d-b8cf-954f25da1f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12903
70520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1290370520
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1167026960
Short name T969
Test name
Test status
Simulation time 8434087053 ps
CPU time 7.9 seconds
Started May 07 12:41:36 PM PDT 24
Finished May 07 12:41:46 PM PDT 24
Peak memory 204132 kb
Host smart-86a85283-2a44-42c6-a3cd-2cf38e1e73ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670
26960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1167026960
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2984500815
Short name T1374
Test name
Test status
Simulation time 8385702389 ps
CPU time 8.29 seconds
Started May 07 12:41:51 PM PDT 24
Finished May 07 12:42:01 PM PDT 24
Peak memory 204152 kb
Host smart-8dc45adc-c1bf-49f8-99a1-f0aeb349f72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29845
00815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2984500815
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.4086530184
Short name T181
Test name
Test status
Simulation time 8413600162 ps
CPU time 8.2 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:45 PM PDT 24
Peak memory 203968 kb
Host smart-ec7577e4-fcc1-420f-a5f8-ca452a216267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40865
30184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.4086530184
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3949460590
Short name T86
Test name
Test status
Simulation time 8377645037 ps
CPU time 7.73 seconds
Started May 07 12:41:44 PM PDT 24
Finished May 07 12:41:54 PM PDT 24
Peak memory 204120 kb
Host smart-e626affe-8cc2-4c84-8110-68feaedb1980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39494
60590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3949460590
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.63274501
Short name T17
Test name
Test status
Simulation time 8453315751 ps
CPU time 8.88 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:50 PM PDT 24
Peak memory 204116 kb
Host smart-0dd187f0-3f0d-416c-8dad-4e8cc905d74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63274
501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.63274501
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3327723831
Short name T896
Test name
Test status
Simulation time 8405629185 ps
CPU time 7.85 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:44 PM PDT 24
Peak memory 204068 kb
Host smart-3751bd70-2484-4020-b2fb-27f5f0edae83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33277
23831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3327723831
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1307490360
Short name T686
Test name
Test status
Simulation time 8400020225 ps
CPU time 9.61 seconds
Started May 07 12:41:41 PM PDT 24
Finished May 07 12:41:52 PM PDT 24
Peak memory 204084 kb
Host smart-a787889a-0f26-4277-9734-868d42463950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13074
90360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1307490360
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.1293567352
Short name T1067
Test name
Test status
Simulation time 8471549948 ps
CPU time 8.21 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:45 PM PDT 24
Peak memory 204136 kb
Host smart-9c88a305-9a75-42e3-adfa-984b27bb51a6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1293567352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.1293567352
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.1303856919
Short name T1032
Test name
Test status
Simulation time 8380023349 ps
CPU time 7.54 seconds
Started May 07 12:41:38 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204108 kb
Host smart-81f4c91a-e1b4-4450-beb2-f661cb9f4a9c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1303856919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.1303856919
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.1092147053
Short name T930
Test name
Test status
Simulation time 8452105332 ps
CPU time 7.54 seconds
Started May 07 12:41:58 PM PDT 24
Finished May 07 12:42:09 PM PDT 24
Peak memory 204024 kb
Host smart-a9cb717a-3ee5-48f1-b369-84a2971724f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10921
47053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.1092147053
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3895731496
Short name T426
Test name
Test status
Simulation time 8423950856 ps
CPU time 10.35 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204048 kb
Host smart-f597d8ae-4ed2-4f0f-bcfd-e16b67c86630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38957
31496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3895731496
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.928296837
Short name T737
Test name
Test status
Simulation time 8433535737 ps
CPU time 7.78 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:46 PM PDT 24
Peak memory 204132 kb
Host smart-7d3cb7fa-c06c-487e-96e0-70ad98764e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92829
6837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.928296837
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2006562465
Short name T1295
Test name
Test status
Simulation time 78114588 ps
CPU time 1.7 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:41 PM PDT 24
Peak memory 204216 kb
Host smart-7fa99550-0cd7-44e6-be71-62f5d8ccdcd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20065
62465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2006562465
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2545104517
Short name T673
Test name
Test status
Simulation time 8450191963 ps
CPU time 7.77 seconds
Started May 07 12:41:49 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 204136 kb
Host smart-0b375f33-0a0e-419d-a8ab-8a0a280b5a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25451
04517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2545104517
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.867027867
Short name T5
Test name
Test status
Simulation time 8367824975 ps
CPU time 7.67 seconds
Started May 07 12:41:53 PM PDT 24
Finished May 07 12:42:02 PM PDT 24
Peak memory 204068 kb
Host smart-ec1fb9a2-1738-4aeb-b55d-81a887d35391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86702
7867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.867027867
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.464806793
Short name T990
Test name
Test status
Simulation time 8449283539 ps
CPU time 8.39 seconds
Started May 07 12:41:50 PM PDT 24
Finished May 07 12:42:00 PM PDT 24
Peak memory 204120 kb
Host smart-da8b5af1-74ab-496b-9ab2-e025cab8e1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46480
6793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.464806793
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3219589438
Short name T691
Test name
Test status
Simulation time 8416905007 ps
CPU time 9.61 seconds
Started May 07 12:41:43 PM PDT 24
Finished May 07 12:41:54 PM PDT 24
Peak memory 204120 kb
Host smart-7545e936-f74e-4f05-9e28-ba2e6258df5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32195
89438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3219589438
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.494973436
Short name T299
Test name
Test status
Simulation time 8370917627 ps
CPU time 8.75 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:50 PM PDT 24
Peak memory 204152 kb
Host smart-71b80192-ec96-4be8-b0a4-67f1244c8993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49497
3436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.494973436
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1763484303
Short name T957
Test name
Test status
Simulation time 8449393640 ps
CPU time 8.17 seconds
Started May 07 12:41:46 PM PDT 24
Finished May 07 12:41:56 PM PDT 24
Peak memory 204100 kb
Host smart-80d6f0f6-83f7-4503-b5c1-8e33f878c609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17634
84303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1763484303
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1302864470
Short name T1265
Test name
Test status
Simulation time 8422067288 ps
CPU time 7.88 seconds
Started May 07 12:41:44 PM PDT 24
Finished May 07 12:41:54 PM PDT 24
Peak memory 204132 kb
Host smart-79c50494-893d-4077-86ea-2792f4b5a3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13028
64470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1302864470
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3408056118
Short name T484
Test name
Test status
Simulation time 8440777894 ps
CPU time 8.21 seconds
Started May 07 12:41:46 PM PDT 24
Finished May 07 12:41:56 PM PDT 24
Peak memory 204116 kb
Host smart-fad7c9e0-9121-4c11-b42d-66e539992954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34080
56118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3408056118
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.4121033851
Short name T953
Test name
Test status
Simulation time 8388049533 ps
CPU time 7.73 seconds
Started May 07 12:41:51 PM PDT 24
Finished May 07 12:42:01 PM PDT 24
Peak memory 204076 kb
Host smart-74491081-648b-4b8a-a1b4-f637b29d2cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41210
33851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.4121033851
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1965292312
Short name T558
Test name
Test status
Simulation time 8371500894 ps
CPU time 8.56 seconds
Started May 07 12:41:39 PM PDT 24
Finished May 07 12:41:50 PM PDT 24
Peak memory 204112 kb
Host smart-ae3cb651-75ea-4885-a06c-2079bc0edaa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19652
92312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1965292312
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3347376618
Short name T372
Test name
Test status
Simulation time 74213765 ps
CPU time 0.67 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 203996 kb
Host smart-04641ecd-760c-473a-bd22-004c8ec350f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33473
76618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3347376618
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.585802619
Short name T920
Test name
Test status
Simulation time 21553333984 ps
CPU time 42.11 seconds
Started May 07 12:41:47 PM PDT 24
Finished May 07 12:42:31 PM PDT 24
Peak memory 204392 kb
Host smart-7847991e-afb6-48c9-a000-8062ba7ba30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58580
2619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.585802619
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3743965576
Short name T892
Test name
Test status
Simulation time 8408888076 ps
CPU time 8.24 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:04 PM PDT 24
Peak memory 204040 kb
Host smart-d6751363-0644-44ab-9359-3a15f42fbf21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37439
65576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3743965576
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2990979437
Short name T1193
Test name
Test status
Simulation time 8402205524 ps
CPU time 9.41 seconds
Started May 07 12:41:44 PM PDT 24
Finished May 07 12:41:55 PM PDT 24
Peak memory 204116 kb
Host smart-0f416fb4-e7de-414d-af47-0461036063d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29909
79437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2990979437
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.325817458
Short name T491
Test name
Test status
Simulation time 8408268300 ps
CPU time 10.48 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:51 PM PDT 24
Peak memory 204136 kb
Host smart-0ac91d0a-6070-4b24-b3ec-522fa97bb74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32581
7458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.325817458
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.479077191
Short name T915
Test name
Test status
Simulation time 8390388931 ps
CPU time 7.75 seconds
Started May 07 12:41:43 PM PDT 24
Finished May 07 12:41:52 PM PDT 24
Peak memory 204044 kb
Host smart-3c143f68-ef4b-4a9e-b2fb-16add032c298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47907
7191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.479077191
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.4154455701
Short name T24
Test name
Test status
Simulation time 8373589472 ps
CPU time 8.6 seconds
Started May 07 12:41:43 PM PDT 24
Finished May 07 12:41:53 PM PDT 24
Peak memory 204128 kb
Host smart-03591fc4-67c4-4b11-aa5c-7d8ab9a104a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41544
55701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.4154455701
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.7199003
Short name T1237
Test name
Test status
Simulation time 8474536135 ps
CPU time 8.48 seconds
Started May 07 12:41:50 PM PDT 24
Finished May 07 12:42:01 PM PDT 24
Peak memory 204088 kb
Host smart-9b750dff-5123-4767-b398-bbc1ff8c6222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71990
03 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.7199003
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1043545727
Short name T845
Test name
Test status
Simulation time 8456548105 ps
CPU time 9.95 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:49 PM PDT 24
Peak memory 204044 kb
Host smart-b4d1cf04-335d-4e69-aeca-9d95d1c733eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10435
45727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1043545727
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2645440562
Short name T1061
Test name
Test status
Simulation time 8397763178 ps
CPU time 8.05 seconds
Started May 07 12:41:46 PM PDT 24
Finished May 07 12:41:56 PM PDT 24
Peak memory 204092 kb
Host smart-9175135f-f875-49ef-8b7b-a1ba6b1dcf70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26454
40562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2645440562
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.4098903595
Short name T1294
Test name
Test status
Simulation time 8458185359 ps
CPU time 9.42 seconds
Started May 07 12:41:52 PM PDT 24
Finished May 07 12:42:03 PM PDT 24
Peak memory 204132 kb
Host smart-3505a8d6-f7d6-470e-81c0-ef9a2a6f2e71
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4098903595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.4098903595
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.2929696817
Short name T317
Test name
Test status
Simulation time 8379126800 ps
CPU time 10.34 seconds
Started May 07 12:42:07 PM PDT 24
Finished May 07 12:42:18 PM PDT 24
Peak memory 204108 kb
Host smart-d4e854e5-75be-4ea7-adaa-79a890d9ec0c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2929696817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.2929696817
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.3697296390
Short name T650
Test name
Test status
Simulation time 8437828770 ps
CPU time 8.21 seconds
Started May 07 12:41:49 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 204092 kb
Host smart-43d2d779-60fd-444c-a828-8005c72e86e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36972
96390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.3697296390
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3981532331
Short name T779
Test name
Test status
Simulation time 8381624593 ps
CPU time 7.98 seconds
Started May 07 12:41:54 PM PDT 24
Finished May 07 12:42:04 PM PDT 24
Peak memory 204048 kb
Host smart-3ac0933f-7bc6-4fb4-9d9d-25e806424308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39815
32331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3981532331
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.2426267414
Short name T973
Test name
Test status
Simulation time 8388395210 ps
CPU time 8.08 seconds
Started May 07 12:41:45 PM PDT 24
Finished May 07 12:41:56 PM PDT 24
Peak memory 204136 kb
Host smart-3789065a-62ef-4778-ae49-44a956751b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24262
67414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2426267414
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2030117919
Short name T939
Test name
Test status
Simulation time 196207438 ps
CPU time 2.11 seconds
Started May 07 12:41:38 PM PDT 24
Finished May 07 12:41:42 PM PDT 24
Peak memory 204248 kb
Host smart-4ba43359-6df8-40b5-a2b5-da0ed9c94635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20301
17919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2030117919
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2112310342
Short name T919
Test name
Test status
Simulation time 8374429019 ps
CPU time 8.05 seconds
Started May 07 12:41:43 PM PDT 24
Finished May 07 12:41:52 PM PDT 24
Peak memory 204084 kb
Host smart-270e02a8-6dbd-4f02-960d-1e6ecdf3583c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21123
10342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2112310342
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3927589168
Short name T193
Test name
Test status
Simulation time 8369761693 ps
CPU time 7.6 seconds
Started May 07 12:41:48 PM PDT 24
Finished May 07 12:41:57 PM PDT 24
Peak memory 204112 kb
Host smart-fda0f551-7b8b-4f8d-8af7-8a0adf578bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39275
89168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3927589168
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1576939712
Short name T914
Test name
Test status
Simulation time 8411234435 ps
CPU time 9.33 seconds
Started May 07 12:41:45 PM PDT 24
Finished May 07 12:41:57 PM PDT 24
Peak memory 204072 kb
Host smart-227eb062-4bee-429c-8db9-e45a5d4b7f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15769
39712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1576939712
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3988761158
Short name T1075
Test name
Test status
Simulation time 8418814527 ps
CPU time 8.6 seconds
Started May 07 12:41:59 PM PDT 24
Finished May 07 12:42:10 PM PDT 24
Peak memory 204144 kb
Host smart-13d48bef-81c3-437d-833e-02c5e4d8948a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39887
61158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3988761158
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3545443862
Short name T1038
Test name
Test status
Simulation time 8420610823 ps
CPU time 7.83 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:44 PM PDT 24
Peak memory 204052 kb
Host smart-6ecf7e05-54d8-4c89-b4e7-c5b94400e24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35454
43862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3545443862
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2153877825
Short name T103
Test name
Test status
Simulation time 8438522822 ps
CPU time 8.3 seconds
Started May 07 12:41:49 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 204172 kb
Host smart-26d256c1-91cb-4d90-b916-053172bcdc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21538
77825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2153877825
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1533514658
Short name T1098
Test name
Test status
Simulation time 8388967767 ps
CPU time 8.89 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:43 PM PDT 24
Peak memory 204140 kb
Host smart-428011c0-5b86-4767-a1ea-9865a149bd7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15335
14658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1533514658
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.604865046
Short name T1322
Test name
Test status
Simulation time 8384777957 ps
CPU time 9.82 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:50 PM PDT 24
Peak memory 204064 kb
Host smart-bc1183b4-544b-41ee-b0e9-2177f736e234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60486
5046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.604865046
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3740266986
Short name T1060
Test name
Test status
Simulation time 8398315181 ps
CPU time 8.51 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204120 kb
Host smart-444ee69a-e7ae-4872-a6c8-b605379e432d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37402
66986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3740266986
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.236391185
Short name T828
Test name
Test status
Simulation time 8364902841 ps
CPU time 8.16 seconds
Started May 07 12:41:37 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204148 kb
Host smart-91639014-4ecd-4629-a35c-5ff5f00c7512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23639
1185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.236391185
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.404243935
Short name T455
Test name
Test status
Simulation time 49416843 ps
CPU time 0.69 seconds
Started May 07 12:41:36 PM PDT 24
Finished May 07 12:41:39 PM PDT 24
Peak memory 204000 kb
Host smart-caef289f-a07f-4104-b924-05537e0cc537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40424
3935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.404243935
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1158706177
Short name T1174
Test name
Test status
Simulation time 26547881270 ps
CPU time 50.33 seconds
Started May 07 12:41:55 PM PDT 24
Finished May 07 12:42:48 PM PDT 24
Peak memory 204380 kb
Host smart-d5a06d01-98d2-4410-8b96-0dcc6451c2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11587
06177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1158706177
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.4004807208
Short name T313
Test name
Test status
Simulation time 8406875296 ps
CPU time 8.02 seconds
Started May 07 12:41:56 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 204128 kb
Host smart-aeb4291f-44d9-4ce4-bce3-b9092949a682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40048
07208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.4004807208
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1486963706
Short name T1121
Test name
Test status
Simulation time 8389363006 ps
CPU time 8.18 seconds
Started May 07 12:41:51 PM PDT 24
Finished May 07 12:42:01 PM PDT 24
Peak memory 204104 kb
Host smart-45d1e89a-7cba-4b99-b7b4-56145e1bd56e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14869
63706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1486963706
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.2897627391
Short name T1362
Test name
Test status
Simulation time 8401350899 ps
CPU time 8.93 seconds
Started May 07 12:41:35 PM PDT 24
Finished May 07 12:41:46 PM PDT 24
Peak memory 204136 kb
Host smart-d79b51a6-aade-44be-b7da-09cbc9349bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28976
27391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.2897627391
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.976668879
Short name T1332
Test name
Test status
Simulation time 8385227027 ps
CPU time 8.12 seconds
Started May 07 12:41:51 PM PDT 24
Finished May 07 12:42:01 PM PDT 24
Peak memory 204096 kb
Host smart-e0aad1c1-b3bf-4f56-85d9-9ea08905a61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97666
8879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.976668879
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3321092807
Short name T1335
Test name
Test status
Simulation time 8368406690 ps
CPU time 9.8 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:44 PM PDT 24
Peak memory 204120 kb
Host smart-1c71fb6a-fa48-4e64-9d84-211148b2849a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33210
92807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3321092807
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.460246749
Short name T700
Test name
Test status
Simulation time 8454060398 ps
CPU time 7.81 seconds
Started May 07 12:41:33 PM PDT 24
Finished May 07 12:41:42 PM PDT 24
Peak memory 204088 kb
Host smart-22bd9a5c-8ac1-4c76-93ba-4f11b6265e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46024
6749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.460246749
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2532611922
Short name T687
Test name
Test status
Simulation time 8374121569 ps
CPU time 8.55 seconds
Started May 07 12:41:36 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 204080 kb
Host smart-a541246f-f96b-4cbd-807b-1af8f1efc9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25326
11922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2532611922
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3797740278
Short name T1043
Test name
Test status
Simulation time 8382421630 ps
CPU time 7.7 seconds
Started May 07 12:41:50 PM PDT 24
Finished May 07 12:41:59 PM PDT 24
Peak memory 204056 kb
Host smart-c642bb4f-34d8-40f8-afb6-9771ecc79af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37977
40278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3797740278
Directory /workspace/9.usbdev_stall_trans/latest
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