Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	468304	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	512208	1		T3	5		T4	310		T5	139

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	712351	1		T3	5		T4	231		T5	90
values[0x0]	133552	1		T3	4		T4	436		T5	193
values[0x1]	134609	1		T3	5		T4	413		T5	189

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	355448	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	625064	1		T3	8		T4	394		T5	185

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3713	1		T4	1		T5	2		T16	17
valid_sources[0x01]	2970	1		T5	4		T16	8		T36	10
valid_sources[0x02]	3505	1		T4	6		T5	2		T16	68
valid_sources[0x03]	3600	1		T5	3		T16	36		T36	14
valid_sources[0x04]	3013	1		T4	2		T16	17		T36	11
valid_sources[0x05]	9596	1		T4	6		T5	1		T16	25
valid_sources[0x06]	3172	1		T5	4		T16	47		T36	13
valid_sources[0x07]	3224	1		T5	1		T16	22		T36	9
valid_sources[0x08]	4116	1		T4	10		T5	2		T16	29
valid_sources[0x09]	6281	1		T4	3		T16	20		T36	9
valid_sources[0x0a]	3818	1		T4	1		T5	1		T16	19
valid_sources[0x0b]	3878	1		T16	54		T36	14		T20	4
valid_sources[0x0c]	3399	1		T4	5		T5	2		T16	47
valid_sources[0x0d]	3790	1		T5	2		T16	41		T36	11
valid_sources[0x0e]	3350	1		T4	9		T5	1		T16	27
valid_sources[0x0f]	3321	1		T4	3		T5	1		T16	4
valid_sources[0x10]	3875	1		T4	6		T16	44		T36	9
valid_sources[0x11]	3450	1		T4	2		T5	1		T34	1
valid_sources[0x12]	3314	1		T4	7		T5	2		T16	16
valid_sources[0x13]	3133	1		T4	2		T5	2		T16	27
valid_sources[0x14]	3665	1		T4	15		T5	1		T21	1
valid_sources[0x15]	3477	1		T4	3		T16	6		T36	12
valid_sources[0x16]	4832	1		T5	6		T16	23		T36	10
valid_sources[0x17]	3353	1		T4	7		T5	8		T34	1
valid_sources[0x18]	2902	1		T5	1		T16	25		T36	11
valid_sources[0x19]	3264	1		T4	5		T5	3		T16	22
valid_sources[0x1a]	2928	1		T4	1		T5	3		T16	12
valid_sources[0x1b]	3270	1		T4	4		T5	1		T16	35
valid_sources[0x1c]	3389	1		T5	3		T16	29		T36	11
valid_sources[0x1d]	3402	1		T5	1		T16	32		T36	6
valid_sources[0x1e]	3009	1		T4	4		T5	5		T16	32
valid_sources[0x1f]	3011	1		T4	6		T5	1		T16	49
valid_sources[0x20]	3087	1		T5	1		T23	1		T33	3
valid_sources[0x21]	3624	1		T4	5		T5	2		T16	24
valid_sources[0x22]	6736	1		T4	2		T5	1		T16	20
valid_sources[0x23]	3376	1		T4	1		T5	1		T16	16
valid_sources[0x24]	6519	1		T4	14		T5	2		T16	22
valid_sources[0x25]	3271	1		T4	14		T5	1		T16	41
valid_sources[0x26]	4691	1		T4	8		T16	51		T36	14
valid_sources[0x27]	3172	1		T4	7		T16	23		T36	10
valid_sources[0x28]	3889	1		T4	10		T5	3		T16	45
valid_sources[0x29]	3924	1		T5	3		T16	59		T36	13
valid_sources[0x2a]	3037	1		T4	10		T43	15		T16	34
valid_sources[0x2b]	8984	1		T4	15		T22	4		T16	8
valid_sources[0x2c]	3331	1		T4	33		T5	2		T16	26
valid_sources[0x2d]	3534	1		T4	1		T5	1		T16	9
valid_sources[0x2e]	3992	1		T4	3		T5	3		T16	20
valid_sources[0x2f]	3907	1		T4	2		T5	1		T16	37
valid_sources[0x30]	3130	1		T4	29		T16	19		T36	16
valid_sources[0x31]	3381	1		T4	9		T5	4		T16	3
valid_sources[0x32]	3657	1		T5	1		T16	31		T40	6
valid_sources[0x33]	3140	1		T5	1		T16	7		T36	11
valid_sources[0x34]	2967	1		T4	7		T5	1		T16	27
valid_sources[0x35]	8558	1		T4	14		T5	1		T16	27
valid_sources[0x36]	3149	1		T4	2		T16	20		T36	28
valid_sources[0x37]	3194	1		T4	2		T5	5		T16	28
valid_sources[0x38]	3118	1		T4	9		T5	3		T16	17
valid_sources[0x39]	6197	1		T4	2		T14	2		T16	8
valid_sources[0x3a]	3269	1		T5	1		T16	2		T45	1
valid_sources[0x3b]	3908	1		T16	12		T53	1		T36	12
valid_sources[0x3c]	3452	1		T4	1		T5	1		T16	39
valid_sources[0x3d]	3155	1		T3	1		T5	3		T16	14
valid_sources[0x3e]	3318	1		T4	3		T16	16		T36	14
valid_sources[0x3f]	3952	1		T5	2		T16	31		T36	10
valid_sources[0x40]	3732	1		T3	1		T5	2		T21	1
valid_sources[0x41]	3639	1		T4	8		T5	2		T16	56
valid_sources[0x42]	3298	1		T4	2		T5	3		T16	23
valid_sources[0x43]	3414	1		T4	7		T5	4		T9	23
valid_sources[0x44]	3455	1		T4	1		T5	1		T16	21
valid_sources[0x45]	3274	1		T4	1		T5	2		T16	39
valid_sources[0x46]	3695	1		T4	1		T5	1		T16	22
valid_sources[0x47]	3347	1		T4	3		T21	1		T16	34
valid_sources[0x48]	6085	1		T4	3		T16	20		T36	10
valid_sources[0x49]	3040	1		T4	4		T5	6		T10	1
valid_sources[0x4a]	3499	1		T5	4		T16	35		T36	12
valid_sources[0x4b]	4177	1		T4	8		T5	1		T16	31
valid_sources[0x4c]	3029	1		T5	3		T14	1		T16	35
valid_sources[0x4d]	3215	1		T4	2		T5	1		T23	2
valid_sources[0x4e]	3496	1		T5	1		T16	25		T36	10
valid_sources[0x4f]	3412	1		T4	11		T5	2		T16	33
valid_sources[0x50]	3657	1		T5	2		T16	9		T44	1
valid_sources[0x51]	3346	1		T16	8		T36	12		T294	10
valid_sources[0x52]	3380	1		T16	26		T36	19		T20	11
valid_sources[0x53]	6741	1		T5	1		T16	23		T36	15
valid_sources[0x54]	3401	1		T4	4		T5	1		T16	8
valid_sources[0x55]	3520	1		T4	6		T5	3		T16	50
valid_sources[0x56]	3643	1		T5	2		T16	18		T53	1
valid_sources[0x57]	3074	1		T5	2		T24	2		T16	40
valid_sources[0x58]	3592	1		T5	3		T16	36		T36	17
valid_sources[0x59]	3131	1		T5	4		T16	36		T36	9
valid_sources[0x5a]	3599	1		T4	2		T5	2		T16	21
valid_sources[0x5b]	4113	1		T4	10		T10	1		T16	36
valid_sources[0x5c]	3313	1		T4	22		T24	12		T16	40
valid_sources[0x5d]	3867	1		T4	6		T5	1		T16	43
valid_sources[0x5e]	3892	1		T5	1		T16	15		T36	4
valid_sources[0x5f]	3339	1		T4	6		T5	2		T16	20
valid_sources[0x60]	3020	1		T4	1		T5	2		T16	27
valid_sources[0x61]	3399	1		T4	17		T16	41		T45	1
valid_sources[0x62]	3256	1		T4	6		T5	1		T16	37
valid_sources[0x63]	3341	1		T4	1		T16	38		T36	9
valid_sources[0x64]	3923	1		T4	11		T5	2		T16	21
valid_sources[0x65]	3723	1		T5	2		T16	36		T45	2
valid_sources[0x66]	3120	1		T4	7		T5	2		T16	25
valid_sources[0x67]	3697	1		T5	1		T16	31		T36	26
valid_sources[0x68]	4445	1		T4	5		T16	13		T36	6
valid_sources[0x69]	3557	1		T4	13		T16	36		T36	14
valid_sources[0x6a]	6815	1		T4	41		T5	3		T16	10
valid_sources[0x6b]	3115	1		T4	6		T16	24		T36	12
valid_sources[0x6c]	3026	1		T4	1		T5	3		T16	17
valid_sources[0x6d]	4729	1		T4	2		T5	1		T16	41
valid_sources[0x6e]	3183	1		T4	10		T5	4		T16	39
valid_sources[0x6f]	3647	1		T4	1		T16	54		T36	14
valid_sources[0x70]	3678	1		T5	1		T16	44		T36	15
valid_sources[0x71]	3297	1		T34	1		T16	48		T36	9
valid_sources[0x72]	3486	1		T4	22		T16	20		T36	11
valid_sources[0x73]	6566	1		T4	1		T5	3		T16	18
valid_sources[0x74]	6330	1		T4	7		T5	2		T16	27
valid_sources[0x75]	6557	1		T16	23		T44	7		T36	14
valid_sources[0x76]	3689	1		T5	7		T16	20		T36	15
valid_sources[0x77]	3843	1		T4	4		T5	1		T16	39
valid_sources[0x78]	3168	1		T5	4		T23	1		T16	18
valid_sources[0x79]	3508	1		T4	9		T16	23		T36	23
valid_sources[0x7a]	3431	1		T5	4		T16	37		T36	13
valid_sources[0x7b]	6959	1		T4	13		T5	2		T22	5
valid_sources[0x7c]	3896	1		T5	2		T16	10		T36	12
valid_sources[0x7d]	3001	1		T14	2		T16	20		T36	12
valid_sources[0x7e]	3752	1		T4	2		T5	2		T16	31
valid_sources[0x7f]	3316	1		T4	3		T5	2		T16	16
valid_sources[0x80]	2969	1		T5	1		T16	49		T36	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

294325

1

T3

1

T4

110

T5

41

values[0x0]

all_enables

biggest_size

112472

1

T3

1

T4

136

T5

69

values[0x1]

all_enables

biggest_size

105411

1

T3

3

T4

64

T5

29