Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	483127	1		T3	9		T4	770		T5	333
full_word	513273	1		T3	5		T4	310		T5	139

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	996120	1		T3	14		T4	1080		T5	472
auto[TlIntgErrCmd]	99	1		T64	2		T215	4		T217	6
auto[TlIntgErrData]	104	1		T64	3		T215	4		T217	7
auto[TlIntgErrBoth]	77	1		T64	5		T215	2		T217	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	714361	1		T3	5		T4	231		T5	90
auto[1]	282039	1		T3	9		T4	849		T5	382

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	419730	1		T3	4		T4	121		T5	49
auto[TlIntgErrNone]	partial	auto[1]	63146	1		T3	5		T4	649		T5	284
auto[TlIntgErrNone]	full_word	auto[0]	294512	1		T3	1		T4	110		T5	41
auto[TlIntgErrNone]	full_word	auto[1]	218732	1		T3	4		T4	200		T5	98
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T64	1		T215	1		T217	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T64	1		T215	2		T217	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T215	1		T269	1		T288	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T239	1		T287	2		T289	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T64	3		T215	1		T217	3
auto[TlIntgErrData]	partial	auto[1]	49	1		T215	3		T217	3		T239	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T239	1		T290	1		T220	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T217	1		T288	1		T291	1
auto[TlIntgErrBoth]	partial	auto[0]	24	1		T64	1		T215	1		T217	3
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T64	3		T215	1		T217	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T64	1		T217	1		T220	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T289	1		T292	1		T293	1