Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.68	93.83	68.66	94.27		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	541172410	12154	0	0
ep_in_enable_rd_A	541172410	3189	0	0
ep_out_enable_rd_A	541172410	3021	0	0
in_iso_rd_A	541172410	2887	0	0
intr_enable_rd_A	541172410	5051	0	0
out_iso_rd_A	541172410	3375	0	0
phy_config_rd_A	541172410	2011	0	0
phy_pins_drive_rd_A	541172410	2885	0	0
rxenable_setup_rd_A	541172410	3200	0	0
set_nak_out_rd_A	541172410	3326	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	12154	0	0
T63	7287	390	0	0
T64	54529	3	0	0
T65	8429	296	0	0
T215	18987	1	0	0
T216	5387	21	0	0
T217	28419	5	0	0
T221	10273	758	0	0
T234	7318	23	0	0
T238	6652	19	0	0
T239	30784	8	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	3189	0	0
T70	9521	5	0	0
T71	3272	8	0	0
T213	6308	16	0	0
T214	4614	17	0	0
T217	28419	225	0	0
T236	31819	499	0	0
T237	7894	32	0	0
T239	30784	490	0	0
T253	2700	45	0	0
T269	21059	222	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	3021	0	0
T70	9521	4	0	0
T71	3272	50	0	0
T213	6308	1	0	0
T214	4614	23	0	0
T217	28419	204	0	0
T236	31819	463	0	0
T237	7894	51	0	0
T239	30784	406	0	0
T253	2700	52	0	0
T270	4734	8	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	2887	0	0
T65	8429	1	0	0
T70	9521	8	0	0
T71	3272	87	0	0
T213	6308	21	0	0
T214	4614	38	0	0
T217	28419	212	0	0
T236	31819	474	0	0
T237	7894	90	0	0
T239	30784	440	0	0
T253	2700	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	5051	0	0
T70	9521	5	0	0
T71	3272	128	0	0
T72	2136	6	0	0
T75	1658	35	0	0
T77	2514	16	0	0
T213	6308	66	0	0
T214	4614	12	0	0
T217	28419	332	0	0
T239	30784	798	0	0
T253	2700	79	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	3375	0	0
T71	3272	4	0	0
T213	6308	45	0	0
T214	4614	18	0	0
T217	28419	193	0	0
T236	31819	527	0	0
T237	7894	76	0	0
T239	30784	625	0	0
T253	2700	36	0	0
T269	21059	192	0	0
T270	4734	45	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	2011	0	0
T70	9521	3	0	0
T71	3272	29	0	0
T213	6308	23	0	0
T214	4614	19	0	0
T217	28419	142	0	0
T236	31819	327	0	0
T237	7894	40	0	0
T239	30784	302	0	0
T253	2700	20	0	0
T270	4734	1	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	2885	0	0
T70	9521	2	0	0
T71	3272	68	0	0
T213	6308	47	0	0
T214	4614	21	0	0
T217	28419	208	0	0
T236	31819	526	0	0
T237	7894	57	0	0
T239	30784	429	0	0
T253	2700	36	0	0
T270	4734	18	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	3200	0	0
T70	9521	6	0	0
T71	3272	5	0	0
T213	6308	5	0	0
T217	28419	315	0	0
T236	31819	442	0	0
T237	7894	102	0	0
T239	30784	415	0	0
T253	2700	5	0	0
T269	21059	214	0	0
T270	4734	6	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	3326	0	0
T70	9521	4	0	0
T71	3272	10	0	0
T213	6308	23	0	0
T214	4614	4	0	0
T217	28419	254	0	0
T236	31819	582	0	0
T237	7894	57	0	0
T239	30784	402	0	0
T253	2700	2	0	0
T269	21059	289	0	0