Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wake_events_cdc	68.40	94.12	46.15			83.33	50.00
tb.dut.u_reg.u_wake_control_cdc	97.73	100.00	90.91			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wake_events_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.40	94.12	46.15			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.51	84.38	50.00			73.68	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.47	99.76	98.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	69.28	81.63	53.06			67.44	75.00
u_src_to_dst_req	56.41	92.31	33.33			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_wake_control_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	96.08	96.43			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.47	99.76	98.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.88	87.50	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Unreachable
1	0	Covered	T69,T70,T71

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T69,T71,T64
1	1	Covered	T69,T70,T71

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T2
1	0	Covered	T69,T71,T64

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T70,T71
1	1	Covered	T69,T71,T64

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T2

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T3,T4,T5
0	1	-	Covered	T69,T70,T71
0	0	1	Covered	T69,T71,T64
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T3,T4,T5
0	1	-	Covered	T69,T70,T71
0	0	1	Covered	T69,T71,T64
0	0	0	Covered	T3,T4,T5

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1082344820	204895	0	0
DstReqKnown_A	23769282	23736434	0	0
SrcAckBusyChk_A	1082344820	853	0	0
SrcBusyKnown_A	1082344820	1082008228	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082344820	204895	0	0
T64	54529	6329	0	0
T69	27873	14962	0	0
T70	9521	131	0	0
T71	3272	134	0	0
T212	1888	113	0	0
T213	6308	1802	0	0
T214	4614	385	0	0
T215	18987	2096	0	0
T216	5387	267	0	0
T217	28419	1600	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23769282	23736434	0	0
T3	9192	9182	0	0
T4	418	406	0	0
T5	260	246	0	0
T9	23580	23560	0	0
T10	22214	22188	0	0
T14	19446	19428	0	0
T21	14276	14244	0	0
T22	33430	33400	0	0
T23	20862	20846	0	0
T24	28304	28292	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082344820	853	0	0
T64	54529	10	0	0
T69	27873	124	0	0
T71	3272	2	0	0
T212	1888	1	0	0
T213	6308	9	0	0
T214	4614	3	0	0
T215	18987	10	0	0
T216	5387	2	0	0
T217	28419	19	0	0
T218	4357	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082344820	1082008228	0	0
T3	812574	812430	0	0
T4	17826	17678	0	0
T5	9526	9326	0	0
T9	807308	807122	0	0
T10	803612	803314	0	0
T14	805408	805248	0	0
T21	804300	803982	0	0
T22	803974	803700	0	0
T23	806968	806820	0	0
T24	807772	807578	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	65	0	0
ALWAYS	71	5	4	80.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	7	7	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65		unreachable
71	1	1
72	1	1
73	1	1
74		unreachable
75	1	1
76	0	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123		unreachable
124		unreachable
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150		unreachable
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Total	Covered	Percent
Conditions	13	6	46.15
Logical	13	6	46.15
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T2
1	0	Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T2

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	71	3	2	66.67
IF	115	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T3,T4,T5
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T3,T4,T5
0	1	-	Unreachable
0	0	1	Covered	T2
0	0	0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	541172410	0	0	0
DstReqKnown_A	11884641	11868217	0	0
SrcAckBusyChk_A	541172410	0	0	0
SrcBusyKnown_A	541172410	541004114	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11884641	11868217	0	0
T3	4596	4591	0	0
T4	209	203	0	0
T5	130	123	0	0
T9	11790	11780	0	0
T10	11107	11094	0	0
T14	9723	9714	0	0
T21	7138	7122	0	0
T22	16715	16700	0	0
T23	10431	10423	0	0
T24	14152	14146	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Unreachable
1	0	Covered	T69,T70,T71

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T69,T71,T64
1	1	Covered	T69,T70,T71

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Unreachable
1	0	Covered	T69,T71,T64

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T70,T71
1	1	Covered	T69,T71,T64

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T3,T4,T5
0	1	-	Covered	T69,T70,T71
0	0	1	Covered	T69,T71,T64
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T3,T4,T5
0	1	-	Covered	T69,T70,T71
0	0	1	Covered	T69,T71,T64
0	0	0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	541172410	204895	0	0
DstReqKnown_A	11884641	11868217	0	0
SrcAckBusyChk_A	541172410	853	0	0
SrcBusyKnown_A	541172410	541004114	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	204895	0	0
T64	54529	6329	0	0
T69	27873	14962	0	0
T70	9521	131	0	0
T71	3272	134	0	0
T212	1888	113	0	0
T213	6308	1802	0	0
T214	4614	385	0	0
T215	18987	2096	0	0
T216	5387	267	0	0
T217	28419	1600	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11884641	11868217	0	0
T3	4596	4591	0	0
T4	209	203	0	0
T5	130	123	0	0
T9	11790	11780	0	0
T10	11107	11094	0	0
T14	9723	9714	0	0
T21	7138	7122	0	0
T22	16715	16700	0	0
T23	10431	10423	0	0
T24	14152	14146	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	853	0	0
T64	54529	10	0	0
T69	27873	124	0	0
T71	3272	2	0	0
T212	1888	1	0	0
T213	6308	9	0	0
T214	4614	3	0	0
T215	18987	10	0	0
T216	5387	2	0	0
T217	28419	19	0	0
T218	4357	11	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541172410	541004114	0	0
T3	406287	406215	0	0
T4	8913	8839	0	0
T5	4763	4663	0	0
T9	403654	403561	0	0
T10	401806	401657	0	0
T14	402704	402624	0	0
T21	402150	401991	0	0
T22	401987	401850	0	0
T23	403484	403410	0	0
T24	403886	403789	0	0