Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	472645	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	511288	1		T1	6		T2	4		T3	20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	714643	1		T1	3		T2	4		T3	21
values[0x0]	134174	1		T1	2		T2	4		T3	4
values[0x1]	135116	1		T1	5		T2	4		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	359117	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	624816	1		T1	7		T2	6		T3	22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3362	1		T34	15		T55	28		T56	3
valid_sources[0x01]	3496	1		T42	1		T123	1		T34	15
valid_sources[0x02]	3581	1		T31	9		T26	3		T34	10
valid_sources[0x03]	3367	1		T89	2		T34	5		T55	5
valid_sources[0x04]	3287	1		T43	2		T330	1		T34	14
valid_sources[0x05]	4461	1		T34	4		T94	2		T56	4
valid_sources[0x06]	3450	1		T330	2		T34	9		T331	1
valid_sources[0x07]	4629	1		T24	1		T34	11		T56	2
valid_sources[0x08]	3572	1		T32	1		T34	15		T246	1
valid_sources[0x09]	3329	1		T3	1		T34	18		T7	4
valid_sources[0x0a]	3465	1		T24	1		T34	16		T56	2
valid_sources[0x0b]	6307	1		T26	1		T34	6		T56	3
valid_sources[0x0c]	4148	1		T330	1		T34	8		T55	15
valid_sources[0x0d]	6721	1		T22	1		T43	1		T153	2
valid_sources[0x0e]	3285	1		T34	12		T56	8		T35	18
valid_sources[0x0f]	3298	1		T34	14		T94	1		T56	4
valid_sources[0x10]	3635	1		T49	1		T34	12		T56	3
valid_sources[0x11]	3699	1		T1	10		T34	11		T246	1
valid_sources[0x12]	3557	1		T21	1		T34	15		T56	3
valid_sources[0x13]	3747	1		T23	1		T34	15		T57	1
valid_sources[0x14]	3706	1		T34	15		T55	12		T56	4
valid_sources[0x15]	3272	1		T49	1		T34	19		T332	2
valid_sources[0x16]	3744	1		T22	1		T52	1		T34	8
valid_sources[0x17]	3816	1		T34	7		T332	1		T333	1
valid_sources[0x18]	3740	1		T54	469		T34	14		T56	2
valid_sources[0x19]	3479	1		T3	2		T34	7		T56	7
valid_sources[0x1a]	3565	1		T34	9		T56	4		T99	23
valid_sources[0x1b]	4021	1		T93	1		T34	12		T56	2
valid_sources[0x1c]	3780	1		T34	17		T55	4		T56	4
valid_sources[0x1d]	3292	1		T34	8		T56	6		T35	32
valid_sources[0x1e]	3488	1		T32	1		T34	11		T94	1
valid_sources[0x1f]	3350	1		T26	2		T34	17		T55	2
valid_sources[0x20]	4321	1		T34	5		T331	1		T55	5
valid_sources[0x21]	3234	1		T58	1		T330	1		T34	12
valid_sources[0x22]	3710	1		T34	11		T56	4		T334	8
valid_sources[0x23]	3137	1		T17	1		T335	1		T34	7
valid_sources[0x24]	3881	1		T3	1		T34	8		T55	4
valid_sources[0x25]	3663	1		T49	1		T34	9		T332	2
valid_sources[0x26]	3930	1		T24	1		T50	2		T34	7
valid_sources[0x27]	3250	1		T123	2		T34	12		T56	4
valid_sources[0x28]	3911	1		T34	6		T55	25		T56	4
valid_sources[0x29]	3599	1		T42	1		T34	10		T56	3
valid_sources[0x2a]	3465	1		T34	12		T56	4		T185	1
valid_sources[0x2b]	3178	1		T34	11		T56	4		T35	1
valid_sources[0x2c]	6460	1		T34	9		T332	1		T56	3
valid_sources[0x2d]	3559	1		T58	1		T28	3		T34	8
valid_sources[0x2e]	3301	1		T22	1		T34	7		T56	5
valid_sources[0x2f]	3280	1		T42	1		T34	4		T332	1
valid_sources[0x30]	3590	1		T17	1		T34	22		T57	1
valid_sources[0x31]	3612	1		T39	15		T34	8		T57	2
valid_sources[0x32]	3263	1		T335	1		T26	1		T34	12
valid_sources[0x33]	3358	1		T3	3		T153	1		T34	9
valid_sources[0x34]	3436	1		T58	1		T93	1		T34	8
valid_sources[0x35]	3304	1		T3	2		T17	1		T34	14
valid_sources[0x36]	3254	1		T19	10		T34	9		T117	1
valid_sources[0x37]	3542	1		T34	9		T55	3		T56	2
valid_sources[0x38]	3581	1		T34	12		T55	7		T336	1
valid_sources[0x39]	3555	1		T34	13		T336	1		T56	3
valid_sources[0x3a]	6674	1		T41	10		T34	14		T55	41
valid_sources[0x3b]	3549	1		T18	12		T34	16		T331	1
valid_sources[0x3c]	3267	1		T43	1		T34	4		T331	1
valid_sources[0x3d]	3638	1		T153	6		T34	14		T56	2
valid_sources[0x3e]	3455	1		T337	10		T34	7		T55	21
valid_sources[0x3f]	7155	1		T33	3336		T34	15		T56	2
valid_sources[0x40]	3818	1		T34	9		T331	1		T29	1
valid_sources[0x41]	3296	1		T43	1		T34	11		T338	2
valid_sources[0x42]	3552	1		T34	8		T157	15		T55	20
valid_sources[0x43]	3356	1		T22	1		T93	2		T34	16
valid_sources[0x44]	3747	1		T52	5		T34	9		T55	6
valid_sources[0x45]	4565	1		T34	16		T55	9		T56	1
valid_sources[0x46]	3937	1		T93	1		T34	13		T56	2
valid_sources[0x47]	3222	1		T34	11		T55	1		T56	3
valid_sources[0x48]	3293	1		T34	7		T56	6		T339	9
valid_sources[0x49]	3393	1		T24	1		T34	16		T56	2
valid_sources[0x4a]	3514	1		T34	14		T246	1		T56	4
valid_sources[0x4b]	3808	1		T34	11		T56	4		T340	2
valid_sources[0x4c]	3282	1		T34	7		T56	3		T135	1
valid_sources[0x4d]	3391	1		T330	1		T28	2		T34	4
valid_sources[0x4e]	3462	1		T58	1		T34	11		T56	3
valid_sources[0x4f]	3433	1		T34	12		T56	2		T141	1
valid_sources[0x50]	3569	1		T58	1		T52	5		T34	7
valid_sources[0x51]	3415	1		T42	1		T34	17		T336	1
valid_sources[0x52]	3467	1		T34	6		T55	7		T56	1
valid_sources[0x53]	3402	1		T3	1		T89	8		T32	1
valid_sources[0x54]	3512	1		T34	15		T55	11		T56	1
valid_sources[0x55]	6596	1		T34	14		T56	5		T30	1
valid_sources[0x56]	3669	1		T34	18		T101	1		T56	1
valid_sources[0x57]	6623	1		T34	9		T56	4		T30	1
valid_sources[0x58]	3265	1		T22	2		T34	16		T7	2
valid_sources[0x59]	4580	1		T92	12		T34	16		T338	1
valid_sources[0x5a]	3638	1		T91	5		T34	24		T56	3
valid_sources[0x5b]	3386	1		T153	1		T34	3		T6	7
valid_sources[0x5c]	3785	1		T23	1		T58	1		T93	1
valid_sources[0x5d]	3154	1		T159	2		T34	14		T56	4
valid_sources[0x5e]	6757	1		T34	26		T56	3		T341	1
valid_sources[0x5f]	3636	1		T3	1		T9	6		T34	12
valid_sources[0x60]	3337	1		T34	8		T56	2		T141	1
valid_sources[0x61]	3476	1		T3	2		T34	16		T56	3
valid_sources[0x62]	6664	1		T335	1		T52	2		T34	12
valid_sources[0x63]	3243	1		T34	6		T331	2		T55	15
valid_sources[0x64]	6791	1		T93	1		T26	1		T34	14
valid_sources[0x65]	3912	1		T32	2		T330	1		T34	15
valid_sources[0x66]	4480	1		T50	1		T330	1		T34	12
valid_sources[0x67]	3323	1		T23	1		T34	8		T55	19
valid_sources[0x68]	3990	1		T58	1		T28	3		T34	12
valid_sources[0x69]	3445	1		T34	10		T55	63		T56	4
valid_sources[0x6a]	3762	1		T49	1		T34	11		T56	2
valid_sources[0x6b]	3725	1		T34	12		T94	4		T56	3
valid_sources[0x6c]	3631	1		T58	1		T34	8		T56	6
valid_sources[0x6d]	3253	1		T23	1		T34	19		T56	3
valid_sources[0x6e]	3846	1		T34	9		T55	7		T56	5
valid_sources[0x6f]	3406	1		T26	2		T330	1		T34	11
valid_sources[0x70]	3230	1		T3	1		T17	1		T32	1
valid_sources[0x71]	3344	1		T58	1		T34	12		T56	1
valid_sources[0x72]	3396	1		T28	3		T34	16		T56	5
valid_sources[0x73]	3578	1		T43	1		T34	21		T56	3
valid_sources[0x74]	3487	1		T16	8		T58	1		T34	6
valid_sources[0x75]	3348	1		T49	1		T17	1		T342	4
valid_sources[0x76]	3644	1		T93	2		T34	11		T246	1
valid_sources[0x77]	3181	1		T34	14		T56	1		T135	1
valid_sources[0x78]	3544	1		T342	4		T34	11		T56	4
valid_sources[0x79]	3932	1		T22	1		T34	11		T55	43
valid_sources[0x7a]	3452	1		T26	4		T34	19		T56	4
valid_sources[0x7b]	3517	1		T58	1		T50	1		T123	6
valid_sources[0x7c]	3434	1		T49	1		T42	1		T34	9
valid_sources[0x7d]	3483	1		T58	1		T34	13		T55	16
valid_sources[0x7e]	3581	1		T26	3		T34	5		T56	7
valid_sources[0x7f]	3335	1		T3	2		T34	14		T56	4
valid_sources[0x80]	7025	1		T22	1		T34	10		T246	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

294138

1

T1

1

T2

1

T3

17

values[0x0]

all_enables

biggest_size

112493

1

T1

2

T2

3

T3

3

values[0x1]

all_enables

biggest_size

104657

1

T1

3

T19

2

T20

2