Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	487678	1		T1	4		T2	8		T3	6
full_word	512302	1		T1	6		T2	4		T3	20

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	999680	1		T1	10		T2	12		T3	26
auto[TlIntgErrCmd]	111	1		T60	6		T233	3		T234	4
auto[TlIntgErrData]	101	1		T60	5		T233	5		T234	6
auto[TlIntgErrBoth]	88	1		T60	9		T233	2		T263	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	716547	1		T1	3		T2	4		T3	21
auto[1]	283433	1		T1	7		T2	8		T3	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	422096	1		T1	2		T2	3		T3	4
auto[TlIntgErrNone]	partial	auto[1]	65306	1		T1	2		T2	5		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	294317	1		T1	1		T2	1		T3	17
auto[TlIntgErrNone]	full_word	auto[1]	217961	1		T1	5		T2	3		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T60	3		T233	3		T234	1
auto[TlIntgErrCmd]	partial	auto[1]	63	1		T60	3		T234	3		T265	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T325	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T325	1		T324	1		T322	1
auto[TlIntgErrData]	partial	auto[0]	49	1		T60	3		T234	4		T263	5
auto[TlIntgErrData]	partial	auto[1]	39	1		T60	2		T233	4		T234	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T265	1		T322	1		T326	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T233	1		T234	1		T263	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T60	1		T265	1		T327	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T60	8		T233	2		T263	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T325	1		T328	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T265	1		T324	1		T329	1