Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.68	93.83	68.66	94.27		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	541312953	12164	0	0
ep_in_enable_rd_A	541312953	2463	0	0
ep_out_enable_rd_A	541312953	2492	0	0
in_iso_rd_A	541312953	2450	0	0
intr_enable_rd_A	541312953	3660	0	0
out_iso_rd_A	541312953	2412	0	0
phy_config_rd_A	541312953	1859	0	0
phy_pins_drive_rd_A	541312953	2050	0	0
rxenable_setup_rd_A	541312953	2209	0	0
set_nak_out_rd_A	541312953	2660	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541312953	12164	0	0
T59	7607	28	0	0
T60	17458	4	0	0
T61	2637	213	0	0
T233	10078	2	0	0
T234	12284	3	0	0
T235	6826	406	0	0
T239	10166	618	0	0
T255	3674	579	0	0
T263	32592	1	0	0
T264	5362	23	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541312953	2463	0	0
T59	7607	52	0	0
T66	4298	32	0	0
T232	12689	62	0	0
T236	12380	13	0	0
T281	10732	79	0	0
T292	2437	6	0	0
T303	18372	177	0	0
T304	5514	27	0	0
T305	2463	29	0	0
T306	13368	13	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541312953	2492	0	0
T59	7607	129	0	0
T66	4298	29	0	0
T232	12689	93	0	0
T236	12380	23	0	0
T281	10732	98	0	0
T292	2437	30	0	0
T303	18372	163	0	0
T304	5514	5	0	0
T305	2463	32	0	0
T306	13368	98	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541312953	2450	0	0
T59	7607	2	0	0
T66	4298	10	0	0
T232	12689	64	0	0
T236	12380	8	0	0
T281	10732	89	0	0
T292	2437	33	0	0
T303	18372	209	0	0
T304	5514	13	0	0
T305	2463	13	0	0
T306	13368	66	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541312953	3660	0	0
T59	7607	93	0	0
T66	4298	14	0	0
T73	1535	17	0	0
T77	1704	13	0	0
T232	12689	66	0	0
T236	12380	32	0	0
T281	10732	100	0	0
T292	2437	30	0	0
T303	18372	202	0	0
T307	3945	4	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541312953	2412	0	0
T59	7607	15	0	0
T66	4298	63	0	0
T232	12689	38	0	0
T236	12380	23	0	0
T256	13579	2	0	0
T281	10732	79	0	0
T303	18372	191	0	0
T304	5514	39	0	0
T305	2463	23	0	0
T306	13368	23	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541312953	1859	0	0
T59	7607	34	0	0
T66	4298	12	0	0
T232	12689	24	0	0
T236	12380	23	0	0
T281	10732	112	0	0
T292	2437	25	0	0
T303	18372	210	0	0
T304	5514	14	0	0
T306	13368	39	0	0
T308	38061	234	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541312953	2050	0	0
T59	7607	41	0	0
T66	4298	21	0	0
T232	12689	83	0	0
T236	12380	10	0	0
T281	10732	107	0	0
T292	2437	1	0	0
T303	18372	193	0	0
T304	5514	26	0	0
T305	2463	4	0	0
T306	13368	42	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541312953	2209	0	0
T59	7607	19	0	0
T66	4298	26	0	0
T232	12689	66	0	0
T236	12380	15	0	0
T281	10732	100	0	0
T292	2437	25	0	0
T303	18372	196	0	0
T304	5514	20	0	0
T306	13368	65	0	0
T308	38061	258	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541312953	2660	0	0
T59	7607	34	0	0
T66	4298	16	0	0
T232	12689	80	0	0
T236	12380	14	0	0
T281	10732	94	0	0
T292	2437	18	0	0
T303	18372	169	0	0
T304	5514	42	0	0
T306	13368	40	0	0
T308	38061	265	0	0