Module Definition
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Module : prim_subreg
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_wake_events_bus_reset 55.71 57.14 50.00 60.00
tb.dut.u_reg.u_wake_events_disconnected 60.48 71.43 50.00 60.00
tb.dut.u_reg.u_wake_events_bus_not_idle 60.48 71.43 50.00 60.00
tb.dut.u_reg.u_intr_state_pkt_received 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_pkt_sent 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_av_out_empty 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_rx_full 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_av_setup_empty 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_wake_events_module_active 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_disconnected 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_host_lost 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_link_reset 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_link_suspend 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_link_resume 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_av_overflow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_link_in_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_crc_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_pid_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_bitstuff_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_frame 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_powered 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_link_out_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_pkt_received 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_pkt_sent 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_disconnected 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_host_lost 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_link_reset 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_link_suspend 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_link_resume 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_av_out_empty 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_full 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_av_overflow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_link_in_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_crc_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_pid_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_bitstuff_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_frame 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_powered 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_link_out_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_av_setup_empty 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usbctrl_enable 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usbctrl_resume_link_active 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usbctrl_device_address 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_sent_sent_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_0_buffer_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_0_size_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_0_sending_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_0_pend_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_0_rdy_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_1_buffer_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_1_size_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_1_sending_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_1_pend_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_1_rdy_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_2_buffer_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_2_size_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_2_sending_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_2_pend_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_2_rdy_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_3_buffer_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_3_size_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_3_sending_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_3_pend_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_3_rdy_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_4_buffer_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_4_size_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_4_sending_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_4_pend_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_4_rdy_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_5_buffer_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_5_size_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_5_sending_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_5_pend_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_5_rdy_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_6_buffer_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_6_size_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_6_sending_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_6_pend_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_6_rdy_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_7_buffer_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_7_size_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_7_sending_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_7_pend_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_7_rdy_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_8_buffer_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_8_size_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_8_sending_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_8_pend_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_8_rdy_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_9_buffer_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_9_size_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_9_sending_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_9_pend_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_9_rdy_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_10_buffer_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_10_size_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_10_sending_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_10_pend_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_10_rdy_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_11_buffer_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_11_size_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_11_sending_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_11_pend_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_configin_11_rdy_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_out_iso_iso_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_8 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_9 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_10 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_in_iso_iso_11 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_dp_o 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_dn_o 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_d_o 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_se0_o 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_oe_o 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_rx_enable_o 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_dp_pullup_en_o 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_dn_pullup_en_o 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_config_use_diff_rcvr 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_config_tx_use_d_se0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_config_eop_single_bit 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_config_pinflip 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_config_usb_ref_disable 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_phy_config_tx_osc_test_mode 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_avout_rst 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_avsetup_rst 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rx_rst 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Module : prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_usbctrl_device_address

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_0_size_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_1_size_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_2_size_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_3_size_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_4_size_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_5_size_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_6_size_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_7_size_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_8_size_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_9_size_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_10_size_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_11_size_11

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_pkt_received

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_pkt_sent

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_av_out_empty

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_rx_full

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_av_setup_empty

SCORECOND
65.24 50.00
tb.dut.u_reg.u_wake_events_module_active

SCORECOND
60.48 50.00
tb.dut.u_reg.u_wake_events_disconnected

SCORECOND
55.71 50.00
tb.dut.u_reg.u_wake_events_bus_reset

SCORECOND
60.48 50.00
tb.dut.u_reg.u_wake_events_bus_not_idle

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_disconnected

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_host_lost

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_link_reset

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_link_suspend

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_link_resume

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_av_overflow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_link_in_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_crc_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_pid_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_bitstuff_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_frame

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_powered

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_link_out_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_sent_sent_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_0_sending_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_0_pend_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_1_sending_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_1_pend_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_2_sending_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_2_pend_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_3_sending_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_3_pend_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_4_sending_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_4_pend_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_5_sending_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_5_pend_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_6_sending_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_6_pend_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_7_sending_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_7_pend_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_8_sending_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_8_pend_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_9_sending_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_9_pend_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_10_sending_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_10_pend_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_11_sending_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_11_pend_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_pkt_received

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_pkt_sent

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_disconnected

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_host_lost

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_link_reset

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_link_suspend

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_link_resume

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_av_out_empty

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_full

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_av_overflow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_link_in_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_crc_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_pid_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_bitstuff_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_frame

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_powered

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_link_out_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_av_setup_empty

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usbctrl_enable

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usbctrl_resume_link_active

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_out_enable_enable_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ep_in_enable_enable_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_setup_setup_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_rxenable_out_out_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_set_nak_out_enable_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_stall_endpoint_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_stall_endpoint_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_0_rdy_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_1_rdy_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_2_rdy_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_3_rdy_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_4_rdy_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_5_rdy_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_6_rdy_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_7_rdy_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_8_rdy_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_9_rdy_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_10_rdy_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_11_rdy_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_out_iso_iso_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_in_iso_iso_11

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_dp_o

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_dn_o

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_d_o

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_se0_o

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_oe_o

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_rx_enable_o

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_dp_pullup_en_o

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_dn_pullup_en_o

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_pins_drive_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_config_use_diff_rcvr

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_config_tx_use_d_se0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_config_eop_single_bit

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_config_pinflip

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_config_usb_ref_disable

SCORECOND
100.00 100.00
tb.dut.u_reg.u_phy_config_tx_osc_test_mode

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_avout_rst

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_avsetup_rst

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rx_rst

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=5,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_0_buffer_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_1_buffer_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_2_buffer_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_3_buffer_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_4_buffer_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_5_buffer_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_6_buffer_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_7_buffer_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_8_buffer_8

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_9_buffer_9

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_10_buffer_10

SCORECOND
100.00 100.00
tb.dut.u_reg.u_configin_11_buffer_11

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T41,T33

Branch Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%