USBDEV Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 10.230s 8.446ms 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.950s 67.596us 5 5 100.00
V1 csr_rw usbdev_csr_rw 0.980s 71.848us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 8.110s 1.438ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.740s 382.769us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.460s 111.728us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 0.980s 71.848us 20 20 100.00
usbdev_csr_aliasing 3.740s 382.769us 5 5 100.00
V1 mem_walk usbdev_mem_walk 3.770s 162.506us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.490s 228.637us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 10.280s 8.459ms 50 50 100.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 0.780s 126.984us 50 50 100.00
V2 av_buffer usbdev_av_buffer 10.160s 8.417ms 50 50 100.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling phy_config_eop_single_bit_handling 0 0 --
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 10.360s 8.362ms 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 10.260s 8.424ms 50 50 100.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 10.200s 8.369ms 50 50 100.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 9.540s 8.393ms 50 50 100.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 10.450s 8.424ms 50 50 100.00
V2 in_stall usbdev_in_stall 10.220s 8.410ms 50 50 100.00
V2 out_iso out_iso 0 0 --
V2 in_iso usbdev_in_iso 10.330s 8.434ms 50 50 100.00
V2 pkt_received usbdev_pkt_received 10.370s 8.378ms 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 10.500s 8.417ms 50 50 100.00
V2 disconnected disconnected 0 0 --
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend link_suspend 0 0 --
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err link_in_err 0 0 --
V2 rx_crc_err rx_crc_err 0 0 --
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err rx_bitstuff_err 0 0 --
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 10.370s 8.387ms 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 10.220s 8.385ms 50 50 100.00
V2 in_data_stage in_data_stage 0 0 --
V2 out_data_stage out_data_stage 0 0 --
V2 endpoint_access endpoint_access 0 0 --
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 10.100s 8.411ms 49 50 98.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 10.100s 8.373ms 50 50 100.00
V2 nak_trans usbdev_nak_trans 10.040s 8.468ms 50 50 100.00
V2 stall_trans usbdev_stall_trans 10.460s 8.421ms 50 50 100.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 10.420s 8.379ms 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 10.250s 8.392ms 50 50 100.00
V2 streaming_test streaming_test 0 0 --
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 1.111m 31.853ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume aon_wake_resume 0 0 --
V2 aon_wake_reset aon_wake_reset 0 0 --
V2 aon_wake_disconnect aon_wake_disconnect 0 0 --
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 15.970s 9.424ms 50 50 100.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 2.320s 332.717us 50 50 100.00
V2 intr_test usbdev_intr_test 0.740s 82.216us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.290s 313.055us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.290s 313.055us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.950s 67.596us 5 5 100.00
usbdev_csr_rw 0.980s 71.848us 20 20 100.00
usbdev_csr_aliasing 3.740s 382.769us 5 5 100.00
usbdev_same_csr_outstanding 1.690s 264.371us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.950s 67.596us 5 5 100.00
usbdev_csr_rw 0.980s 71.848us 20 20 100.00
usbdev_csr_aliasing 3.740s 382.769us 5 5 100.00
usbdev_same_csr_outstanding 1.690s 264.371us 20 20 100.00
V2 TOTAL 1239 1240 99.92
V2S tl_intg_err usbdev_sec_cm 1.490s 795.179us 5 5 100.00
usbdev_tl_intg_err 5.610s 1.254ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.610s 1.254ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 2.274m 5.110ms 1 1 100.00
random_length_in_trans 10.390s 8.390ms 50 50 100.00
min_length_in_transaction 10.110s 8.387ms 50 50 100.00
max_length_in_transaction 10.340s 8.471ms 50 50 100.00
usbdev_stress_all_with_rand_reset 0.720s 81.099us 0 50 0.00
usbdev_stress_all 0.670s 0 50 0.00
TOTAL 1380 1481 93.18

Testplan Progress

Items Total Written Passing Progress
N.A. 3 3 1 33.33
V1 8 8 8 100.00
V2 78 26 25 32.05
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
89.18 96.70 89.94 97.32 51.56 94.63 97.56 96.58

Failure Buckets

Past Results