Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4332474	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	527573	1		T1	4		T2	3		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4578433	1		T1	3079		T2	2923		T3	3080
values[0x0]	140761	1		T1	3		T2	1		T3	4
values[0x1]	140853	1		T1	3		T2	7		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3254319	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	1605728	1		T1	765		T2	741		T3	762

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17319	1		T1	20		T2	10		T3	8
valid_sources[0x01]	20473	1		T1	8		T2	13		T3	15
valid_sources[0x02]	14200	1		T1	10		T2	14		T3	8
valid_sources[0x03]	20227	1		T1	10		T2	6		T3	16
valid_sources[0x04]	15194	1		T1	12		T2	11		T3	13
valid_sources[0x05]	20270	1		T1	18		T2	13		T3	14
valid_sources[0x06]	15567	1		T1	22		T2	17		T3	8
valid_sources[0x07]	18397	1		T1	13		T2	11		T3	21
valid_sources[0x08]	28249	1		T1	10		T2	16		T3	11
valid_sources[0x09]	20696	1		T1	12		T2	9		T3	11
valid_sources[0x0a]	23707	1		T1	8		T2	13		T3	10
valid_sources[0x0b]	17238	1		T1	19		T2	16		T3	7
valid_sources[0x0c]	17847	1		T1	7		T2	13		T3	15
valid_sources[0x0d]	17905	1		T1	11		T2	10		T3	12
valid_sources[0x0e]	21676	1		T1	7		T2	13		T3	9
valid_sources[0x0f]	23426	1		T1	13		T2	16		T3	10
valid_sources[0x10]	23328	1		T1	17		T2	14		T3	14
valid_sources[0x11]	14497	1		T1	9		T2	9		T3	11
valid_sources[0x12]	21482	1		T1	18		T2	7		T3	8
valid_sources[0x13]	17466	1		T1	11		T2	13		T3	9
valid_sources[0x14]	17863	1		T1	15		T2	16		T3	12
valid_sources[0x15]	21427	1		T1	9		T2	15		T3	13
valid_sources[0x16]	20730	1		T1	13		T2	13		T3	12
valid_sources[0x17]	20742	1		T1	14		T2	16		T3	10
valid_sources[0x18]	19206	1		T1	15		T2	18		T3	13
valid_sources[0x19]	15070	1		T1	4		T2	7		T3	11
valid_sources[0x1a]	20229	1		T1	7		T2	10		T3	14
valid_sources[0x1b]	23121	1		T1	11		T2	11		T3	17
valid_sources[0x1c]	17952	1		T1	9		T2	9		T3	13
valid_sources[0x1d]	17546	1		T1	8		T2	5		T3	10
valid_sources[0x1e]	17031	1		T1	20		T2	8		T3	12
valid_sources[0x1f]	15200	1		T1	5		T2	11		T3	14
valid_sources[0x20]	14148	1		T1	19		T2	13		T3	8
valid_sources[0x21]	14808	1		T1	7		T2	10		T3	12
valid_sources[0x22]	17055	1		T1	14		T2	11		T3	13
valid_sources[0x23]	17930	1		T1	15		T2	11		T3	12
valid_sources[0x24]	21642	1		T1	17		T2	11		T3	9
valid_sources[0x25]	14399	1		T1	12		T2	9		T3	14
valid_sources[0x26]	21453	1		T1	11		T2	16		T3	8
valid_sources[0x27]	26845	1		T1	21		T2	12		T3	11
valid_sources[0x28]	14787	1		T1	20		T2	14		T3	15
valid_sources[0x29]	20833	1		T1	15		T2	14		T3	9
valid_sources[0x2a]	20551	1		T1	14		T2	10		T3	11
valid_sources[0x2b]	15537	1		T1	15		T2	9		T3	8
valid_sources[0x2c]	20579	1		T1	20		T2	13		T3	8
valid_sources[0x2d]	19952	1		T1	11		T2	7		T3	15
valid_sources[0x2e]	20326	1		T1	5		T2	7		T3	15
valid_sources[0x2f]	15764	1		T1	7		T2	8		T3	18
valid_sources[0x30]	14125	1		T1	8		T2	13		T3	9
valid_sources[0x31]	21163	1		T1	9		T2	12		T3	22
valid_sources[0x32]	15140	1		T1	5		T2	7		T3	19
valid_sources[0x33]	20167	1		T1	6		T2	10		T3	16
valid_sources[0x34]	20493	1		T1	16		T2	11		T3	12
valid_sources[0x35]	26934	1		T1	8		T2	10		T3	12
valid_sources[0x36]	17540	1		T1	11		T2	20		T3	11
valid_sources[0x37]	18203	1		T1	6		T2	12		T3	21
valid_sources[0x38]	14794	1		T1	10		T2	10		T3	14
valid_sources[0x39]	23118	1		T1	14		T2	13		T3	14
valid_sources[0x3a]	14759	1		T1	20		T2	11		T3	10
valid_sources[0x3b]	29039	1		T1	16		T2	11		T3	13
valid_sources[0x3c]	17268	1		T1	21		T2	12		T3	13
valid_sources[0x3d]	17976	1		T1	13		T2	11		T3	8
valid_sources[0x3e]	17426	1		T1	9		T2	10		T3	10
valid_sources[0x3f]	23862	1		T1	14		T2	9		T3	11
valid_sources[0x40]	20593	1		T1	7		T2	7		T3	13
valid_sources[0x41]	17642	1		T1	18		T2	13		T3	20
valid_sources[0x42]	17654	1		T1	17		T2	9		T3	11
valid_sources[0x43]	14510	1		T1	13		T2	10		T3	14
valid_sources[0x44]	20168	1		T1	12		T2	13		T3	12
valid_sources[0x45]	21033	1		T1	7		T2	8		T3	19
valid_sources[0x46]	15059	1		T1	10		T2	9		T3	16
valid_sources[0x47]	18011	1		T1	15		T2	16		T3	17
valid_sources[0x48]	18644	1		T1	6		T2	12		T3	16
valid_sources[0x49]	24632	1		T1	12		T2	10		T3	8
valid_sources[0x4a]	18352	1		T1	26		T2	11		T3	11
valid_sources[0x4b]	17453	1		T1	14		T2	17		T3	15
valid_sources[0x4c]	18955	1		T1	10		T2	8		T3	10
valid_sources[0x4d]	18155	1		T1	16		T2	11		T3	10
valid_sources[0x4e]	26931	1		T1	14		T2	15		T3	18
valid_sources[0x4f]	19980	1		T1	9		T2	15		T3	16
valid_sources[0x50]	14679	1		T1	10		T2	9		T3	9
valid_sources[0x51]	14423	1		T1	3		T2	9		T3	13
valid_sources[0x52]	17439	1		T1	5		T2	11		T3	14
valid_sources[0x53]	14617	1		T1	5		T2	12		T3	13
valid_sources[0x54]	17510	1		T1	3		T2	10		T3	13
valid_sources[0x55]	21422	1		T1	8		T2	10		T3	16
valid_sources[0x56]	20505	1		T1	6		T2	10		T3	12
valid_sources[0x57]	23500	1		T1	12		T2	9		T3	10
valid_sources[0x58]	17537	1		T1	17		T2	13		T3	15
valid_sources[0x59]	17862	1		T1	19		T2	9		T3	11
valid_sources[0x5a]	18679	1		T1	20		T2	12		T3	14
valid_sources[0x5b]	18949	1		T1	17		T2	11		T3	14
valid_sources[0x5c]	15037	1		T1	31		T2	14		T3	11
valid_sources[0x5d]	19889	1		T1	5		T2	14		T3	13
valid_sources[0x5e]	18103	1		T1	5		T2	15		T3	12
valid_sources[0x5f]	17555	1		T1	14		T2	6		T3	8
valid_sources[0x60]	17460	1		T1	8		T2	15		T3	9
valid_sources[0x61]	18088	1		T1	8		T2	16		T3	10
valid_sources[0x62]	19905	1		T1	11		T2	14		T3	11
valid_sources[0x63]	17852	1		T1	13		T2	8		T3	10
valid_sources[0x64]	21058	1		T1	12		T2	11		T3	10
valid_sources[0x65]	17126	1		T1	14		T2	15		T3	10
valid_sources[0x66]	20533	1		T1	4		T2	11		T3	12
valid_sources[0x67]	20468	1		T1	19		T2	6		T3	12
valid_sources[0x68]	21308	1		T1	7		T2	12		T3	11
valid_sources[0x69]	15457	1		T1	13		T2	21		T3	4
valid_sources[0x6a]	27333	1		T1	13		T2	18		T3	11
valid_sources[0x6b]	17914	1		T1	15		T2	8		T3	7
valid_sources[0x6c]	17899	1		T1	17		T2	10		T3	14
valid_sources[0x6d]	17289	1		T1	6		T2	8		T3	9
valid_sources[0x6e]	17041	1		T1	8		T2	9		T3	9
valid_sources[0x6f]	17330	1		T1	10		T2	11		T3	7
valid_sources[0x70]	23964	1		T1	8		T2	7		T3	13
valid_sources[0x71]	14623	1		T1	6		T2	19		T3	13
valid_sources[0x72]	24753	1		T1	27		T2	10		T3	6
valid_sources[0x73]	14768	1		T1	5		T2	5		T3	14
valid_sources[0x74]	23042	1		T1	12		T2	15		T3	9
valid_sources[0x75]	27920	1		T1	11		T2	14		T3	12
valid_sources[0x76]	20897	1		T1	6		T2	6		T3	22
valid_sources[0x77]	17977	1		T1	13		T2	14		T3	10
valid_sources[0x78]	23323	1		T1	11		T2	16		T3	11
valid_sources[0x79]	17040	1		T1	6		T2	16		T3	14
valid_sources[0x7a]	20006	1		T1	16		T2	10		T3	7
valid_sources[0x7b]	17776	1		T1	18		T2	12		T3	16
valid_sources[0x7c]	29149	1		T1	14		T2	11		T3	9
valid_sources[0x7d]	17709	1		T1	13		T2	13		T3	7
valid_sources[0x7e]	20945	1		T1	20		T2	18		T3	21
valid_sources[0x7f]	23349	1		T1	9		T2	12		T3	7
valid_sources[0x80]	20337	1		T1	10		T2	15		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

299568

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

118543

1

T1

2

T2

1

T3

4

values[0x1]

all_enables

biggest_size

109462

1

T1

1

T2

1

T3

1