Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	4347242	1		T1	3081		T2	2928		T3	3082
full_word	528539	1		T1	4		T2	3		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4875491	1		T1	3085		T2	2931		T3	3088
auto[TlIntgErrCmd]	94	1		T192	9		T195	4		T196	6
auto[TlIntgErrData]	104	1		T192	6		T195	2		T196	11
auto[TlIntgErrBoth]	92	1		T192	5		T195	4		T196	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4580299	1		T1	3079		T2	2923		T3	3080
auto[1]	295482	1		T1	6		T2	8		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	4280421	1		T1	3078		T2	2922		T3	3079
auto[TlIntgErrNone]	partial	auto[1]	66548	1		T1	3		T2	6		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	299744	1		T1	1		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	228778	1		T1	3		T2	2		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T192	2		T195	3		T196	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T192	7		T196	2		T236	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T195	1		T237	1		T238	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T236	1		T239	1		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1		T192	4		T196	3		T236	7
auto[TlIntgErrData]	partial	auto[1]	55	1		T192	2		T195	2		T196	7
auto[TlIntgErrData]	full_word	auto[0]	5	1		T196	1		T237	2		T240	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T192	3		T195	3		T196	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T192	1		T195	1		T196	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T192	1		T241	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T240	1		T242	1		T243	1