Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.48	92.59	68.66	94.50		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	607635845	11613	0	0
ep_in_enable_rd_A	607635845	3342	0	0
ep_out_enable_rd_A	607635845	3103	0	0
in_iso_rd_A	607635845	3018	0	0
intr_enable_rd_A	607635845	4313	0	0
out_iso_rd_A	607635845	3040	0	0
phy_config_rd_A	607635845	2230	0	0
phy_pins_drive_rd_A	607635845	2532	0	0
rxenable_setup_rd_A	607635845	3003	0	0
set_nak_out_rd_A	607635845	3021	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607635845	11613	0	0
T55	7939	38	0	0
T56	4556	10	0	0
T57	3204	463	0	0
T191	4954	883	0	0
T192	35556	7	0	0
T195	15476	2	0	0
T197	10308	573	0	0
T201	5625	192	0	0
T207	10926	14	0	0
T208	5643	6	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607635845	3342	0	0
T56	4556	56	0	0
T59	7759	67	0	0
T188	3929	1	0	0
T192	35556	593	0	0
T207	10926	51	0	0
T216	3517	20	0	0
T221	61343	349	0	0
T231	93614	482	0	0
T232	9218	42	0	0
T233	4991	49	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607635845	3103	0	0
T56	4556	7	0	0
T59	7759	98	0	0
T188	3929	15	0	0
T192	35556	554	0	0
T207	10926	56	0	0
T216	3517	15	0	0
T221	61343	244	0	0
T231	93614	407	0	0
T232	9218	10	0	0
T234	7740	58	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607635845	3018	0	0
T56	4556	32	0	0
T59	7759	69	0	0
T188	3929	21	0	0
T192	35556	538	0	0
T207	10926	82	0	0
T216	3517	25	0	0
T221	61343	233	0	0
T231	93614	405	0	0
T232	9218	77	0	0
T233	4991	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607635845	4313	0	0
T56	4556	6	0	0
T59	7759	44	0	0
T66	2039	23	0	0
T188	3929	5	0	0
T192	35556	926	0	0
T203	9510	5	0	0
T207	10926	83	0	0
T216	3517	41	0	0
T231	93614	449	0	0
T235	1762	7	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607635845	3040	0	0
T56	4556	51	0	0
T59	7759	42	0	0
T188	3929	30	0	0
T192	35556	642	0	0
T207	10926	54	0	0
T216	3517	32	0	0
T221	61343	294	0	0
T231	93614	436	0	0
T232	9218	68	0	0
T233	4991	3	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607635845	2230	0	0
T56	4556	8	0	0
T59	7759	62	0	0
T188	3929	55	0	0
T192	35556	211	0	0
T207	10926	56	0	0
T216	3517	17	0	0
T221	61343	273	0	0
T231	93614	445	0	0
T232	9218	76	0	0
T233	4991	31	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607635845	2532	0	0
T56	4556	42	0	0
T59	7759	9	0	0
T188	3929	34	0	0
T192	35556	347	0	0
T207	10926	15	0	0
T216	3517	22	0	0
T221	61343	261	0	0
T231	93614	452	0	0
T232	9218	75	0	0
T233	4991	43	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607635845	3003	0	0
T56	4556	45	0	0
T59	7759	27	0	0
T188	3929	17	0	0
T192	35556	529	0	0
T207	10926	10	0	0
T216	3517	34	0	0
T221	61343	234	0	0
T231	93614	444	0	0
T232	9218	74	0	0
T233	4991	6	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607635845	3021	0	0
T56	4556	51	0	0
T59	7759	28	0	0
T188	3929	32	0	0
T192	35556	547	0	0
T207	10926	69	0	0
T221	61343	348	0	0
T231	93614	406	0	0
T232	9218	51	0	0
T233	4991	7	0	0
T234	7740	25	0	0