Unified Coverage Report :: Module :: usb_fs_rx

Module : usb_fs_rx

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.94	99.51	91.75			93.55

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_rx	94.94	99.51	91.75			93.55

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_rx

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.94	99.51	91.75			93.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.94	99.51	91.75			93.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.22	100.00	91.67				100.00	u_usb_fs_nb_pe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_rx

	Line No.	Total	Covered	Percent
TOTAL		204	203	99.51
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
ALWAYS	125	5	5	100.00
ALWAYS	135	11	11	100.00
ALWAYS	154	5	5	100.00
ALWAYS	172	5	5	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
ALWAYS	252	5	5	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	294	3	3	100.00
ALWAYS	302	9	8	88.89
CONT_ASSIGN	325	1	1	100.00
ALWAYS	329	8	8	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
ALWAYS	350	3	3	100.00
CONT_ASSIGN	358	1	1	100.00
ALWAYS	373	12	12	100.00
ALWAYS	399	5	5	100.00
ALWAYS	409	5	5	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
ALWAYS	431	5	5	100.00
ALWAYS	440	3	3	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
ALWAYS	463	5	5	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	481	5	5	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
ALWAYS	503	5	5	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
ALWAYS	552	5	5	100.00
ALWAYS	565	7	7	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
ALWAYS	596	5	5	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	615	1	1	100.00
ALWAYS	618	8	8	100.00
ALWAYS	635	32	32	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
125	1	1
126	1	1
127	1	1
129	1	1
130	1	1
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
154	1	1
156	1	1
159	1	1
164	1	1
165	1	1
			MISSING_ELSE
172	1	1
174	1	1
177	1	1
182	1	1
183	1	1
			MISSING_ELSE
224	1	1
225	1	1
245	1	1
246	1	1
249	1	1
252	1	1
253	1	1
255	1	1
256	1	1
258	1	1
279	1	1
280	1	1
285	1	1
289	1	1
290	1	1
294	1	1
295	1	1
297	1	1
302	1	1
305	1	1
306	0	1
308	1	1
309	1	1
313	1	1
314	1	1
317	1	1
320	1	1
325	1	1
329	1	1
330	1	1
331	1	1
333	1	1
334	1	1
335	1	1
337	1	1
338	1	1
346	1	1
347	1	1
350	1	1
351	1	1
353	1	1
358	1	1
373	1	1
374	1	1
375	1	1
376	1	1
377	1	1
381	1	1
382	1	1
383	1	1
384	1	1
385	1	1
386	1	1
390	1	1
399	1	1
400	1	1
401	1	1
402	1	1
404	1	1
409	1	1
410	1	1
412	1	1
413	1	1
415	1	1
421	1	1
427	1	1
431	1	1
432	1	1
433	1	1
434	1	1
435	1	1
			MISSING_ELSE
440	1	1
441	1	1
443	1	1
447	1	1
459	1	1
460	1	1
463	1	1
464	1	1
465	1	1
466	1	1
468	1	1
477	1	1
478	1	1
481	1	1
483	1	1
484	1	1
			MISSING_ELSE
487	1	1
488	1	1
			MISSING_ELSE
499	1	1
500	1	1
503	1	1
505	1	1
506	1	1
			MISSING_ELSE
509	1	1
510	1	1
			MISSING_ELSE
521	1	1
522	1	1
523	1	1
525	1	1
528	1	1
530	1	1
536	1	1
537	1	1
540	1	1
545	1	1
552	1	1
554	1	1
555	1	1
			MISSING_ELSE
558	1	1
559	1	1
			MISSING_ELSE
565	1	1
566	1	1
567	1	1
569	1	1
570	1	1
571	1	1
572	1	1
			MISSING_ELSE
576	1	1
577	1	1
578	1	1
579	1	1
581	1	1
582	1	1
591	1	1
592	1	1
593	1	1
596	1	1
598	1	1
599	1	1
			MISSING_ELSE
602	1	1
603	1	1
			MISSING_ELSE
613	1	1
614	1	1
615	1	1
618	1	1
619	1	1
621	1	1
622	1	1
623	1	1
			MISSING_ELSE
625	1	1
626	1	1
627	1	1
			MISSING_ELSE
635	1	1
636	1	1
637	1	1
638	1	1
639	1	1
640	1	1
641	1	1
642	1	1
643	1	1
644	1	1
645	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
652	1	1
653	1	1
654	1	1
655	1	1
656	1	1
657	1	1
659	1	1
660	1	1
661	1	1
662	1	1
663	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1

---

Cond Coverage for Module : usb_fs_rx

	Total	Covered	Percent
Conditions	206	189	91.75
Logical	206	189	91.75
Non-Logical	0	0
Event	0	0

 LINE       73
 EXPRESSION (cfg_pinflip_i ? usb_dn_i : usb_dp_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       74
 EXPRESSION (cfg_pinflip_i ? usb_dp_i : usb_dn_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 EXPRESSION (usb_d_i ^ cfg_pinflip_i)
             ---1---   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       130
 EXPRESSION (usb_d_flipped ? DJ[1:0] : DK[1:0])
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       156
 EXPRESSION (line_state_q == DT)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (dpair != line_state_q[1:0])
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       174
 EXPRESSION (diff_state_q == DT)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       182
 EXPRESSION (ddiff != diff_state_q[1:0])
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 EXPRESSION ((line_state_q == SE0) || ((line_state_q == DT) && (line_state_qq == SE0)))
             ----------1----------    ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION (line_state_q == SE0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION ((line_state_q == DT) && (line_state_qq == SE0))
                 ----------1---------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION (line_state_q == DT)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION (line_state_qq == SE0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       225
 EXPRESSION (cfg_use_diff_rcvr_i ? (use_se ? line_state_q : diff_state_q) : line_state_q)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       225
 SUB-EXPRESSION (use_se ? line_state_q : diff_state_q)
                 ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       245
 EXPRESSION (bit_phase_q == 2'b1)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       246
 EXPRESSION (bit_phase_q == 2'd2)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       249
 EXPRESSION ((line_state_rx == DT) ? 0 : ((bit_phase_q + 1)))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       249
 SUB-EXPRESSION (line_state_rx == DT)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       279
 EXPRESSION (packet_valid_d & ((~packet_valid_q)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       280
 EXPRESSION (((~packet_valid_d)) & packet_valid_q)
             ---------1---------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       285
 EXPRESSION ((cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0)) || (line_history_q[3:0] == 4'b0) || bitstuff_error_q || see_preamble)
             ---------------------------1---------------------------    --------------2--------------    --------3-------    ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T44,T45,T46
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T2,T3

 LINE       285
 SUB-EXPRESSION (cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0))
                 ----------1---------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       285
 SUB-EXPRESSION (line_history_q[1:0] == 2'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       285
 SUB-EXPRESSION (line_history_q[3:0] == 4'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION ((line_history_q[3:0] == 4'b1001) & ((~tx_en_i)) & ((~in_packet_q)))
             ----------------1---------------   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       289
 SUB-EXPRESSION (line_history_q[3:0] == 4'b1001)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (see_eop ? 1'b0 : (see_sop ? 1'b1 : in_packet_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       290
 SUB-EXPRESSION (see_sop ? 1'b1 : in_packet_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       308
 EXPRESSION (((!packet_valid_q)) && (line_history_q[11:0] == 12'b011001100101))
             ---------1---------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       308
 SUB-EXPRESSION (line_history_q[11:0] == 12'b011001100101)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       313
 EXPRESSION (packet_valid_q && see_eop)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       325
 EXPRESSION (line_state_valid ? ({line_history_q[9:0], line_state_rx[1:0]}) : line_history_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       346
 EXPRESSION ((((~tx_en_i)) & line_state_valid) ? (line_state_q == DJ) : rx_idle_det_q)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       346
 SUB-EXPRESSION (((~tx_en_i)) & line_state_valid)
                 ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       346
 SUB-EXPRESSION (line_state_q == DJ)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION (diff_rx_ok_i & ((~tx_en_i)) & (line_history_q[1:0] == 2'b10))
             ------1-----   ------2-----   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (line_history_q[1:0] == 2'b10)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       381
 EXPRESSION (packet_valid_q && line_state_valid)
             -------1------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       421
 EXPRESSION (dvalid_raw && ( ! (bitstuff_history_q[5:0] == 6'b111111) ))
             -----1----    ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

 LINE       421
 SUB-EXPRESSION ( ! (bitstuff_history_q[5:0] == 6'b111111) )
                    -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       421
 SUB-EXPRESSION (bitstuff_history_q[5:0] == 6'b111111)
                -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       427
 EXPRESSION (bitstuff_history_q == 7'b1111111)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T45,T46

 LINE       434
 EXPRESSION (bitstuff_error && dvalid_raw)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       447
 EXPRESSION (bitstuff_error_q && packet_end)
             --------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       459
 EXPRESSION (full_pid_q[4:1] == (~full_pid_q[8:5]))
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (dvalid && ((!pid_complete)))
             ---1--    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       477
 EXPRESSION (crc5_q == 5'b01100)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       478
 EXPRESSION (din ^ crc5_q[4])
             -1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       487
 EXPRESSION (dvalid && pid_complete)
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       499
 EXPRESSION (crc16_q == 16'b1000000000001101)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       500
 EXPRESSION (din ^ crc16_q[15])
             -1-   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       509
 EXPRESSION (dvalid && pid_complete)
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       521
 EXPRESSION (full_pid_q[2:1] == 2'b1)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       522
 EXPRESSION (full_pid_q[2:1] == 2'b11)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       523
 EXPRESSION (full_pid_q[2:1] == 2'b10)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       525
 EXPRESSION ((packet_valid_q & pid_valid & pid_complete) && (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre))
             ---------------------1---------------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       525
 SUB-EXPRESSION (packet_valid_q & pid_valid & pid_complete)
                 -------1------   ----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T46,T84,T90
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T1,T2,T3

 LINE       525
 SUB-EXPRESSION (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       530
 EXPRESSION 
 Number  Term
      1  pid_valid && 
      2  ((!bitstuff_error_q)) && 
      3  ((pkt_is_handshake && valid_handshake_len) || (pkt_is_data && valid_data_len && crc16_valid) || (pkt_is_token && valid_token_len && crc5_valid)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       530
 SUB-EXPRESSION ((pkt_is_handshake && valid_handshake_len) || (pkt_is_data && valid_data_len && crc16_valid) || (pkt_is_token && valid_token_len && crc5_valid))
                 --------------------1--------------------    -----------------------2----------------------    -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       530
 SUB-EXPRESSION (pkt_is_handshake && valid_handshake_len)
                 --------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T84,T181,T182
1	1	Covered	T1,T2,T3

 LINE       530
 SUB-EXPRESSION (pkt_is_data && valid_data_len && crc16_valid)
                 -----1-----    -------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T26,T183,T184
1	1	0	Covered	T3,T4,T6
1	1	1	Covered	T2,T3,T4

 LINE       530
 SUB-EXPRESSION (pkt_is_token && valid_token_len && crc5_valid)
                 ------1-----    -------2-------    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Covered	T3,T11,T28
1	1	0	Covered	T28,T29,T30
1	1	1	Covered	T1,T2,T3

 LINE       536
 EXPRESSION (pkt_is_token & packet_end & ((!crc5_valid)))
             ------1-----   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T28,T29,T30

 LINE       537
 EXPRESSION (pkt_is_data & packet_end & ((!crc16_valid)))
             -----1-----   -----2----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T44,T45,T46

 LINE       540
 EXPRESSION (((!pid_valid)) && packet_end)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T46,T84,T90

 LINE       558
 EXPRESSION (dvalid && pid_complete && pkt_is_token && ((!token_payload_done)))
             ---1--    ------2-----    ------3-----    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T2,T3,T4
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       569
 EXPRESSION (token_payload_done && pkt_is_token)
             ---------1--------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       598
 EXPRESSION (packet_start || rx_data_buffer_full)
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       602
 EXPRESSION (dvalid && pid_complete && pkt_is_data)
             ---1--    ------2-----    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T3,T4

 LINE       613
 EXPRESSION (rx_data_len16_q & ((~|rx_data_len_q)))
             -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

 LINE       614
 EXPRESSION (rx_data_len16_q & ((~|rx_data_len_q[2:0])))
             -------1-------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

 LINE       625
 EXPRESSION (dvalid && pid_complete)
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       626
 EXPRESSION (rx_data_len16_q | ((&rx_data_len_q)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6

---

Branch Coverage for Module : usb_fs_rx

	Line No.	Total	Covered	Percent
Branches		93	87	93.55
TERNARY	73	2	1	50.00
TERNARY	74	2	1	50.00
TERNARY	225	3	1	33.33
TERNARY	249	2	2	100.00
TERNARY	290	3	3	100.00
TERNARY	325	2	2	100.00
TERNARY	346	2	2	100.00
IF	125	3	2	66.67
IF	135	3	3	100.00
IF	156	3	3	100.00
IF	174	3	3	100.00
IF	252	3	3	100.00
IF	294	2	2	100.00
IF	302	5	4	80.00
IF	329	3	3	100.00
IF	350	2	2	100.00
CASE	373	5	5	100.00
IF	381	6	6	100.00
IF	399	3	3	100.00
IF	409	3	3	100.00
IF	432	3	3	100.00
IF	440	2	2	100.00
IF	463	3	3	100.00
IF	483	2	2	100.00
IF	487	2	2	100.00
IF	505	2	2	100.00
IF	509	2	2	100.00
IF	554	2	2	100.00
IF	558	2	2	100.00
IF	569	2	2	100.00
IF	598	2	2	100.00
IF	602	2	2	100.00
IF	621	2	2	100.00
IF	625	2	2	100.00
IF	635	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	73	(cfg_pinflip_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	74	(cfg_pinflip_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	225	(cfg_use_diff_rcvr_i) ? 
-2-:	225	(use_se) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	249	((line_state_rx == DT)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	290	(see_eop) ? 
-2-:	290	(see_sop) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	325	(line_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	346	(((~tx_en_i) & line_state_valid)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	125	if (tx_en_i)
-2-:	130	(usb_d_flipped) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	135	if ((!rst_ni))
-2-:	140	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	if ((line_state_q == DT))
-2-:	164	if ((dpair != line_state_q[1:0]))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	174	if ((diff_state_q == DT))
-2-:	182	if ((ddiff != diff_state_q[1:0]))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	if ((!rst_ni))
-2-:	255	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	294	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	302	if (line_state_valid)
-2-:	305	if ((~diff_rx_ok_i))
-3-:	308	if (((!packet_valid_q) && (line_history_q[11:0] == 12'b011001100101)))
-4-:	313	if ((packet_valid_q && see_eop))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Not Covered
1	0	1	-	Covered	T1,T2,T3
1	0	0	1	Covered	T1,T2,T3
1	0	0	0	Covered	T1,T2,T3
0	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	329	if ((!rst_ni))
-2-:	333	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	350	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	373	case (line_history_q[3:0])

Branches:

-1-	Status	Tests
4'b0101	Covered	T1,T2,T3
4'b0110	Covered	T1,T2,T3
4'b1001	Covered	T1,T2,T3
4'b1010	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	381	if ((packet_valid_q && line_state_valid))
-2-:	382	case (line_history_q[3:0])

Branches:

-1-	-2-	Status	Tests
1	4'b0101	Covered	T1,T2,T3
1	4'b0110	Covered	T1,T2,T3
1	4'b1001	Covered	T1,T2,T3
1	4'b1010	Covered	T1,T2,T3
1	default	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	399	if (packet_end)
-2-:	401	if (dvalid_raw)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	409	if ((!rst_ni))
-2-:	412	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	432	if (packet_start)
-2-:	434	if ((bitstuff_error && dvalid_raw))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T44,T45,T46
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	463	if ((dvalid && (!pid_complete)))
-2-:	465	if (packet_start)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	483	if (packet_start)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	487	if ((dvalid && pid_complete))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	505	if (packet_start)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	if ((dvalid && pid_complete))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	554	if (packet_start)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((((dvalid && pid_complete) && pkt_is_token) && (!token_payload_done)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	569	if ((token_payload_done && pkt_is_token))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	598	if ((packet_start || rx_data_buffer_full))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	602	if (((dvalid && pid_complete) && pkt_is_data))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	621	if (packet_start)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	625	if ((dvalid && pid_complete))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	635	if ((!rst_ni))
-2-:	647	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3