Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T82	4		T79	7		T81	4
all_values[1]	269	1		T82	4		T79	7		T81	4
all_values[2]	269	1		T82	4		T79	7		T81	4
all_values[3]	269	1		T82	4		T79	7		T81	4
all_values[4]	269	1		T82	4		T79	7		T81	4
all_values[5]	269	1		T82	4		T79	7		T81	4
all_values[6]	269	1		T82	4		T79	7		T81	4
all_values[7]	269	1		T82	4		T79	7		T81	4
all_values[8]	269	1		T82	4		T79	7		T81	4
all_values[9]	269	1		T82	4		T79	7		T81	4
all_values[10]	269	1		T82	4		T79	7		T81	4
all_values[11]	269	1		T82	4		T79	7		T81	4
all_values[12]	269	1		T82	4		T79	7		T81	4
all_values[13]	269	1		T82	4		T79	7		T81	4
all_values[14]	269	1		T82	4		T79	7		T81	4
all_values[15]	269	1		T82	4		T79	7		T81	4
all_values[16]	269	1		T82	4		T79	7		T81	4
all_values[17]	269	1		T82	4		T79	7		T81	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2574	1		T82	40		T79	74		T81	44
auto[1]	2268	1		T82	32		T79	52		T81	28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	892	1		T82	16		T79	10		T81	24
auto[1]	3950	1		T82	56		T79	116		T81	48

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2859	1		T82	45		T79	73		T81	48
auto[1]	1983	1		T82	27		T79	53		T81	24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	24	1		T82	2		T83	1		T280	4
all_values[0]	auto[0]	auto[0]	auto[1]	47	1		T81	1		T83	1		T287	1
all_values[0]	auto[0]	auto[1]	auto[0]	18	1		T83	1		T282	2		T288	2
all_values[0]	auto[0]	auto[1]	auto[1]	71	1		T82	1		T79	3		T81	2
all_values[0]	auto[1]	auto[0]	auto[1]	59	1		T79	2		T81	1		T83	2
all_values[0]	auto[1]	auto[1]	auto[1]	50	1		T82	1		T79	2		T84	2
all_values[1]	auto[0]	auto[0]	auto[0]	33	1		T81	4		T83	5		T288	1
all_values[1]	auto[0]	auto[0]	auto[1]	57	1		T82	2		T79	3		T84	1
all_values[1]	auto[0]	auto[1]	auto[0]	21	1		T282	1		T289	2		T285	2
all_values[1]	auto[0]	auto[1]	auto[1]	39	1		T79	1		T84	1		T280	1
all_values[1]	auto[1]	auto[0]	auto[1]	76	1		T79	2		T84	1		T83	1
all_values[1]	auto[1]	auto[1]	auto[1]	43	1		T82	2		T79	1		T84	1
all_values[2]	auto[0]	auto[0]	auto[0]	28	1		T84	2		T83	1		T280	2
all_values[2]	auto[0]	auto[0]	auto[1]	51	1		T79	1		T81	1		T84	1
all_values[2]	auto[0]	auto[1]	auto[0]	30	1		T81	2		T290	2		T289	1
all_values[2]	auto[0]	auto[1]	auto[1]	55	1		T82	1		T79	1		T83	1
all_values[2]	auto[1]	auto[0]	auto[1]	57	1		T82	1		T79	2		T81	1
all_values[2]	auto[1]	auto[1]	auto[1]	48	1		T82	2		T79	3		T83	4
all_values[3]	auto[0]	auto[0]	auto[0]	19	1		T79	2		T83	1		T280	1
all_values[3]	auto[0]	auto[0]	auto[1]	61	1		T81	1		T84	2		T83	1
all_values[3]	auto[0]	auto[1]	auto[0]	13	1		T79	1		T81	2		T280	1
all_values[3]	auto[0]	auto[1]	auto[1]	59	1		T82	1		T79	1		T83	2
all_values[3]	auto[1]	auto[0]	auto[1]	62	1		T82	2		T79	1		T81	1
all_values[3]	auto[1]	auto[1]	auto[1]	55	1		T82	1		T79	2		T83	2
all_values[4]	auto[0]	auto[0]	auto[0]	37	1		T81	1		T280	1		T291	4
all_values[4]	auto[0]	auto[0]	auto[1]	53	1		T82	2		T79	3		T83	1
all_values[4]	auto[0]	auto[1]	auto[0]	26	1		T84	4		T281	4		T287	2
all_values[4]	auto[0]	auto[1]	auto[1]	51	1		T79	2		T81	1		T83	3
all_values[4]	auto[1]	auto[0]	auto[1]	54	1		T82	1		T79	2		T81	1
all_values[4]	auto[1]	auto[1]	auto[1]	48	1		T82	1		T81	1		T83	1
all_values[5]	auto[0]	auto[0]	auto[0]	27	1		T79	1		T81	1		T83	1
all_values[5]	auto[0]	auto[0]	auto[1]	57	1		T79	2		T81	1		T84	2
all_values[5]	auto[0]	auto[1]	auto[0]	20	1		T84	1		T83	1		T282	4
all_values[5]	auto[0]	auto[1]	auto[1]	61	1		T82	2		T79	2		T287	1
all_values[5]	auto[1]	auto[0]	auto[1]	58	1		T79	2		T81	2		T83	1
all_values[5]	auto[1]	auto[1]	auto[1]	46	1		T82	2		T84	1		T83	3
all_values[6]	auto[0]	auto[0]	auto[0]	34	1		T82	1		T79	1		T83	1
all_values[6]	auto[0]	auto[0]	auto[1]	35	1		T82	1		T79	1		T81	1
all_values[6]	auto[0]	auto[1]	auto[0]	25	1		T81	2		T83	2		T281	3
all_values[6]	auto[0]	auto[1]	auto[1]	62	1		T82	1		T79	2		T83	1
all_values[6]	auto[1]	auto[0]	auto[1]	59	1		T82	1		T79	1		T81	1
all_values[6]	auto[1]	auto[1]	auto[1]	54	1		T79	2		T83	2		T280	1
all_values[7]	auto[0]	auto[0]	auto[0]	22	1		T81	2		T83	1		T281	1
all_values[7]	auto[0]	auto[0]	auto[1]	54	1		T82	2		T79	1		T83	2
all_values[7]	auto[0]	auto[1]	auto[0]	13	1		T82	1		T84	4		T281	1
all_values[7]	auto[0]	auto[1]	auto[1]	58	1		T79	2		T81	1		T83	1
all_values[7]	auto[1]	auto[0]	auto[1]	71	1		T79	3		T83	2		T280	3
all_values[7]	auto[1]	auto[1]	auto[1]	51	1		T82	1		T79	1		T81	1
all_values[8]	auto[0]	auto[0]	auto[0]	22	1		T82	2		T280	1		T287	1
all_values[8]	auto[0]	auto[0]	auto[1]	61	1		T79	2		T81	2		T84	1
all_values[8]	auto[0]	auto[1]	auto[0]	24	1		T82	2		T84	1		T281	1
all_values[8]	auto[0]	auto[1]	auto[1]	61	1		T81	1		T83	1		T280	1
all_values[8]	auto[1]	auto[0]	auto[1]	44	1		T79	4		T84	1		T83	2
all_values[8]	auto[1]	auto[1]	auto[1]	57	1		T79	1		T81	1		T84	1
all_values[9]	auto[0]	auto[0]	auto[0]	23	1		T82	1		T83	3		T280	1
all_values[9]	auto[0]	auto[0]	auto[1]	57	1		T79	2		T84	1		T83	1
all_values[9]	auto[0]	auto[1]	auto[0]	23	1		T81	1		T84	1		T83	1
all_values[9]	auto[0]	auto[1]	auto[1]	49	1		T82	1		T79	2		T81	1
all_values[9]	auto[1]	auto[0]	auto[1]	74	1		T82	1		T79	1		T84	1
all_values[9]	auto[1]	auto[1]	auto[1]	43	1		T82	1		T79	2		T81	2
all_values[10]	auto[0]	auto[0]	auto[0]	26	1		T79	1		T287	2		T288	2
all_values[10]	auto[0]	auto[0]	auto[1]	57	1		T82	2		T79	2		T81	2
all_values[10]	auto[0]	auto[1]	auto[0]	16	1		T79	1		T284	2		T285	1
all_values[10]	auto[0]	auto[1]	auto[1]	62	1		T79	2		T84	1		T83	2
all_values[10]	auto[1]	auto[0]	auto[1]	58	1		T82	2		T79	1		T84	2
all_values[10]	auto[1]	auto[1]	auto[1]	50	1		T81	2		T84	1		T83	1
all_values[11]	auto[0]	auto[0]	auto[0]	33	1		T82	2		T81	4		T83	1
all_values[11]	auto[0]	auto[0]	auto[1]	60	1		T79	2		T84	2		T83	1
all_values[11]	auto[0]	auto[1]	auto[0]	20	1		T287	1		T288	1		T290	2
all_values[11]	auto[0]	auto[1]	auto[1]	55	1		T82	1		T79	2		T83	1
all_values[11]	auto[1]	auto[0]	auto[1]	70	1		T82	1		T79	1		T84	2
all_values[11]	auto[1]	auto[1]	auto[1]	31	1		T79	2		T83	1		T280	1
all_values[12]	auto[0]	auto[0]	auto[0]	32	1		T82	3		T79	1		T81	1
all_values[12]	auto[0]	auto[0]	auto[1]	50	1		T79	2		T81	1		T83	2
all_values[12]	auto[0]	auto[1]	auto[0]	20	1		T82	1		T84	1		T292	2
all_values[12]	auto[0]	auto[1]	auto[1]	56	1		T79	1		T84	1		T83	1
all_values[12]	auto[1]	auto[0]	auto[1]	53	1		T79	2		T81	2		T83	1
all_values[12]	auto[1]	auto[1]	auto[1]	58	1		T79	1		T84	2		T83	2
all_values[13]	auto[0]	auto[0]	auto[0]	40	1		T79	1		T83	4		T280	3
all_values[13]	auto[0]	auto[0]	auto[1]	50	1		T82	1		T79	2		T81	3
all_values[13]	auto[0]	auto[1]	auto[0]	22	1		T84	1		T280	1		T288	5
all_values[13]	auto[0]	auto[1]	auto[1]	59	1		T82	2		T79	2		T84	2
all_values[13]	auto[1]	auto[0]	auto[1]	43	1		T81	1		T83	1		T287	1
all_values[13]	auto[1]	auto[1]	auto[1]	55	1		T82	1		T79	2		T84	1
all_values[14]	auto[0]	auto[0]	auto[0]	22	1		T81	1		T83	2		T290	1
all_values[14]	auto[0]	auto[0]	auto[1]	62	1		T82	1		T79	3		T81	1
all_values[14]	auto[0]	auto[1]	auto[0]	14	1		T84	1		T83	1		T282	2
all_values[14]	auto[0]	auto[1]	auto[1]	47	1		T82	2		T79	1		T84	2
all_values[14]	auto[1]	auto[0]	auto[1]	78	1		T79	2		T81	2		T280	1
all_values[14]	auto[1]	auto[1]	auto[1]	46	1		T82	1		T79	1		T84	1
all_values[15]	auto[0]	auto[0]	auto[0]	26	1		T79	1		T81	2		T83	1
all_values[15]	auto[0]	auto[0]	auto[1]	55	1		T82	2		T79	2		T84	1
all_values[15]	auto[0]	auto[1]	auto[0]	30	1		T280	2		T286	1		T284	2
all_values[15]	auto[0]	auto[1]	auto[1]	52	1		T79	2		T81	1		T84	2
all_values[15]	auto[1]	auto[0]	auto[1]	58	1		T82	2		T79	2		T84	1
all_values[15]	auto[1]	auto[1]	auto[1]	48	1		T81	1		T281	1		T282	1
all_values[16]	auto[0]	auto[0]	auto[0]	33	1		T81	1		T281	1		T287	2
all_values[16]	auto[0]	auto[0]	auto[1]	46	1		T82	1		T79	3		T83	1
all_values[16]	auto[0]	auto[1]	auto[0]	27	1		T82	1		T84	4		T281	1
all_values[16]	auto[0]	auto[1]	auto[1]	52	1		T82	1		T79	1		T81	2
all_values[16]	auto[1]	auto[0]	auto[1]	65	1		T79	3		T81	1		T83	3
all_values[16]	auto[1]	auto[1]	auto[1]	46	1		T82	1		T83	2		T280	2
all_values[17]	auto[0]	auto[0]	auto[0]	29	1		T83	1		T280	1		T281	2
all_values[17]	auto[0]	auto[0]	auto[1]	56	1		T82	2		T79	2		T84	1
all_values[17]	auto[0]	auto[1]	auto[0]	20	1		T287	1		T282	2		T289	2
all_values[17]	auto[0]	auto[1]	auto[1]	49	1		T79	3		T81	1		T83	2
all_values[17]	auto[1]	auto[0]	auto[1]	56	1		T82	2		T79	2		T84	3
all_values[17]	auto[1]	auto[1]	auto[1]	59	1		T81	3		T83	3		T287	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal