Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.57 96.68 90.75 97.00 60.94 94.71 97.35 96.58


Total test records in report: 1868
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T1776 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1131911957 May 16 02:53:01 PM PDT 24 May 16 02:53:03 PM PDT 24 80457314 ps
T286 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2980184530 May 16 02:52:51 PM PDT 24 May 16 02:52:52 PM PDT 24 29915509 ps
T247 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2552570299 May 16 02:53:22 PM PDT 24 May 16 02:53:27 PM PDT 24 344790675 ps
T259 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.236346374 May 16 02:53:03 PM PDT 24 May 16 02:53:05 PM PDT 24 59634095 ps
T1777 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4131581358 May 16 02:53:30 PM PDT 24 May 16 02:53:32 PM PDT 24 74470294 ps
T292 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1949584907 May 16 02:53:43 PM PDT 24 May 16 02:53:46 PM PDT 24 39685103 ps
T278 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.919235049 May 16 02:52:31 PM PDT 24 May 16 02:52:35 PM PDT 24 213908558 ps
T1778 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1217158184 May 16 02:53:53 PM PDT 24 May 16 02:53:55 PM PDT 24 27597026 ps
T260 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3933673882 May 16 02:53:30 PM PDT 24 May 16 02:53:32 PM PDT 24 58942633 ps
T284 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3363502269 May 16 02:53:40 PM PDT 24 May 16 02:53:42 PM PDT 24 77462394 ps
T285 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.423283853 May 16 02:53:44 PM PDT 24 May 16 02:53:46 PM PDT 24 32061835 ps
T1779 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1924743660 May 16 02:52:08 PM PDT 24 May 16 02:52:11 PM PDT 24 60103468 ps
T1780 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.624932376 May 16 02:53:11 PM PDT 24 May 16 02:53:13 PM PDT 24 30753649 ps
T1781 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2812557208 May 16 02:52:33 PM PDT 24 May 16 02:52:37 PM PDT 24 300694717 ps
T1782 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.706252840 May 16 02:53:22 PM PDT 24 May 16 02:53:28 PM PDT 24 370799894 ps
T261 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1312122339 May 16 02:52:10 PM PDT 24 May 16 02:52:20 PM PDT 24 1268180490 ps
T1783 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.517841082 May 16 02:53:32 PM PDT 24 May 16 02:53:35 PM PDT 24 212593386 ps
T1784 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.50588435 May 16 02:52:52 PM PDT 24 May 16 02:52:58 PM PDT 24 483398092 ps
T1785 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2547082148 May 16 02:52:32 PM PDT 24 May 16 02:52:34 PM PDT 24 214216645 ps
T1786 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.140204715 May 16 02:52:52 PM PDT 24 May 16 02:52:54 PM PDT 24 36627165 ps
T279 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.381514181 May 16 02:53:29 PM PDT 24 May 16 02:53:31 PM PDT 24 114642775 ps
T1787 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.845620498 May 16 02:53:07 PM PDT 24 May 16 02:53:08 PM PDT 24 51971359 ps
T1788 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1123260001 May 16 02:53:00 PM PDT 24 May 16 02:53:02 PM PDT 24 42979105 ps
T234 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.205633417 May 16 02:53:26 PM PDT 24 May 16 02:53:29 PM PDT 24 249245625 ps
T1789 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1371969730 May 16 02:53:55 PM PDT 24 May 16 02:53:58 PM PDT 24 39714102 ps
T1790 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3415722344 May 16 02:53:22 PM PDT 24 May 16 02:53:26 PM PDT 24 137374163 ps
T262 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2371593432 May 16 02:52:41 PM PDT 24 May 16 02:52:44 PM PDT 24 80131575 ps
T1791 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.991949723 May 16 02:52:59 PM PDT 24 May 16 02:53:01 PM PDT 24 56709252 ps
T1792 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.724878360 May 16 02:53:00 PM PDT 24 May 16 02:53:03 PM PDT 24 216429614 ps
T1793 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3572799965 May 16 02:53:22 PM PDT 24 May 16 02:53:24 PM PDT 24 29947045 ps
T263 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3953154545 May 16 02:52:50 PM PDT 24 May 16 02:52:53 PM PDT 24 68953857 ps
T1794 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.942648965 May 16 02:53:42 PM PDT 24 May 16 02:53:45 PM PDT 24 27175774 ps
T296 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3499607578 May 16 02:52:19 PM PDT 24 May 16 02:52:22 PM PDT 24 390686849 ps
T283 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2285360379 May 16 02:52:50 PM PDT 24 May 16 02:52:52 PM PDT 24 98580461 ps
T1795 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.50475077 May 16 02:52:08 PM PDT 24 May 16 02:52:14 PM PDT 24 718313383 ps
T1796 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.727252247 May 16 02:52:41 PM PDT 24 May 16 02:52:45 PM PDT 24 385523292 ps
T297 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1440573034 May 16 02:53:20 PM PDT 24 May 16 02:53:27 PM PDT 24 1238392515 ps
T1797 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1457462399 May 16 02:53:47 PM PDT 24 May 16 02:53:49 PM PDT 24 28409755 ps
T264 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3637192269 May 16 02:52:40 PM PDT 24 May 16 02:52:42 PM PDT 24 38998815 ps
T1798 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4159852781 May 16 02:53:45 PM PDT 24 May 16 02:53:46 PM PDT 24 30127310 ps
T1799 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2902862497 May 16 02:53:22 PM PDT 24 May 16 02:53:25 PM PDT 24 136497110 ps
T1800 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2861267089 May 16 02:53:01 PM PDT 24 May 16 02:53:04 PM PDT 24 73620226 ps
T265 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2297795293 May 16 02:52:32 PM PDT 24 May 16 02:52:38 PM PDT 24 607089532 ps
T300 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3256039588 May 16 02:53:03 PM PDT 24 May 16 02:53:06 PM PDT 24 276166261 ps
T1801 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.839350904 May 16 02:53:44 PM PDT 24 May 16 02:53:46 PM PDT 24 49167267 ps
T1802 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2853186040 May 16 02:53:42 PM PDT 24 May 16 02:53:45 PM PDT 24 29766364 ps
T1803 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.198511284 May 16 02:53:53 PM PDT 24 May 16 02:53:56 PM PDT 24 30767430 ps
T1804 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1356163176 May 16 02:52:17 PM PDT 24 May 16 02:52:19 PM PDT 24 35925554 ps
T1805 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1027154909 May 16 02:52:50 PM PDT 24 May 16 02:52:53 PM PDT 24 160564293 ps
T1806 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2731277217 May 16 02:53:31 PM PDT 24 May 16 02:53:33 PM PDT 24 39555399 ps
T1807 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3498300612 May 16 02:53:53 PM PDT 24 May 16 02:53:54 PM PDT 24 38100886 ps
T1808 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2389519777 May 16 02:52:30 PM PDT 24 May 16 02:52:32 PM PDT 24 124711958 ps
T1809 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.327062235 May 16 02:53:42 PM PDT 24 May 16 02:53:44 PM PDT 24 46657052 ps
T235 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.860293368 May 16 02:53:12 PM PDT 24 May 16 02:53:16 PM PDT 24 176669753 ps
T1810 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2030468598 May 16 02:53:23 PM PDT 24 May 16 02:53:25 PM PDT 24 34449195 ps
T1811 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1836694907 May 16 02:52:30 PM PDT 24 May 16 02:52:35 PM PDT 24 471696314 ps
T1812 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.573436946 May 16 02:53:11 PM PDT 24 May 16 02:53:14 PM PDT 24 55441080 ps
T1813 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3533922603 May 16 02:53:43 PM PDT 24 May 16 02:53:45 PM PDT 24 47836682 ps
T1814 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3857844342 May 16 02:53:35 PM PDT 24 May 16 02:53:37 PM PDT 24 119716354 ps
T1815 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.883376577 May 16 02:53:22 PM PDT 24 May 16 02:53:24 PM PDT 24 36598053 ps
T1816 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2574421194 May 16 02:53:02 PM PDT 24 May 16 02:53:06 PM PDT 24 114253729 ps
T1817 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2308746580 May 16 02:52:33 PM PDT 24 May 16 02:52:37 PM PDT 24 341942753 ps
T1818 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3961080254 May 16 02:52:09 PM PDT 24 May 16 02:52:12 PM PDT 24 71905178 ps
T1819 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3392121703 May 16 02:53:21 PM PDT 24 May 16 02:53:24 PM PDT 24 93932717 ps
T1820 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3717022596 May 16 02:53:42 PM PDT 24 May 16 02:53:44 PM PDT 24 34742976 ps
T1821 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.435315153 May 16 02:53:29 PM PDT 24 May 16 02:53:31 PM PDT 24 170726204 ps
T1822 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3671425487 May 16 02:53:42 PM PDT 24 May 16 02:53:45 PM PDT 24 54510718 ps
T1823 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2991491408 May 16 02:53:10 PM PDT 24 May 16 02:53:15 PM PDT 24 232673439 ps
T1824 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2652721140 May 16 02:53:35 PM PDT 24 May 16 02:53:38 PM PDT 24 426034019 ps
T1825 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2505154771 May 16 02:53:00 PM PDT 24 May 16 02:53:02 PM PDT 24 33928984 ps
T1826 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3526890989 May 16 02:52:40 PM PDT 24 May 16 02:52:43 PM PDT 24 162985316 ps
T1827 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3808225420 May 16 02:52:39 PM PDT 24 May 16 02:52:49 PM PDT 24 1682668151 ps
T1828 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1588313349 May 16 02:53:23 PM PDT 24 May 16 02:53:27 PM PDT 24 674681779 ps
T293 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.29718574 May 16 02:53:11 PM PDT 24 May 16 02:53:18 PM PDT 24 523835624 ps
T1829 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3797714151 May 16 02:52:09 PM PDT 24 May 16 02:52:11 PM PDT 24 108477302 ps
T1830 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2164085933 May 16 02:52:51 PM PDT 24 May 16 02:52:54 PM PDT 24 111305585 ps
T1831 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1666256711 May 16 02:52:50 PM PDT 24 May 16 02:52:54 PM PDT 24 363859330 ps
T1832 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.456414559 May 16 02:52:53 PM PDT 24 May 16 02:53:05 PM PDT 24 1990441653 ps
T1833 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3568677651 May 16 02:52:29 PM PDT 24 May 16 02:52:32 PM PDT 24 95420259 ps
T1834 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4179136638 May 16 02:52:41 PM PDT 24 May 16 02:52:43 PM PDT 24 34137304 ps
T1835 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1545050646 May 16 02:53:22 PM PDT 24 May 16 02:53:24 PM PDT 24 41160671 ps
T1836 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1714033365 May 16 02:53:54 PM PDT 24 May 16 02:53:58 PM PDT 24 28505668 ps
T1837 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.437466828 May 16 02:53:20 PM PDT 24 May 16 02:53:24 PM PDT 24 77547180 ps
T1838 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4057550448 May 16 02:52:20 PM PDT 24 May 16 02:52:24 PM PDT 24 127265168 ps
T68 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1465949982 May 16 02:52:52 PM PDT 24 May 16 02:52:55 PM PDT 24 100906254 ps
T299 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.786271096 May 16 02:53:21 PM PDT 24 May 16 02:53:26 PM PDT 24 725503097 ps
T1839 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2416763678 May 16 02:53:30 PM PDT 24 May 16 02:53:32 PM PDT 24 46671782 ps
T1840 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.4241507841 May 16 02:52:19 PM PDT 24 May 16 02:52:21 PM PDT 24 92125109 ps
T1841 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3957058917 May 16 02:53:29 PM PDT 24 May 16 02:53:32 PM PDT 24 48387126 ps
T1842 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.18052367 May 16 02:53:11 PM PDT 24 May 16 02:53:15 PM PDT 24 394509881 ps
T69 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2364408027 May 16 02:52:19 PM PDT 24 May 16 02:52:20 PM PDT 24 191640940 ps
T1843 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4063703999 May 16 02:52:18 PM PDT 24 May 16 02:52:21 PM PDT 24 254434056 ps
T1844 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2202735510 May 16 02:53:10 PM PDT 24 May 16 02:53:16 PM PDT 24 346608617 ps
T1845 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3973306769 May 16 02:53:20 PM PDT 24 May 16 02:53:22 PM PDT 24 149569712 ps
T1846 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4029391468 May 16 02:52:50 PM PDT 24 May 16 02:52:52 PM PDT 24 44381165 ps
T294 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1082187391 May 16 02:52:33 PM PDT 24 May 16 02:52:39 PM PDT 24 621347937 ps
T1847 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.528797614 May 16 02:53:45 PM PDT 24 May 16 02:53:46 PM PDT 24 33697467 ps
T1848 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2117976956 May 16 02:53:11 PM PDT 24 May 16 02:53:14 PM PDT 24 79147646 ps
T1849 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1350480173 May 16 02:52:19 PM PDT 24 May 16 02:52:21 PM PDT 24 48371567 ps
T1850 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3591854113 May 16 02:53:19 PM PDT 24 May 16 02:53:20 PM PDT 24 55739039 ps
T1851 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.313410119 May 16 02:53:02 PM PDT 24 May 16 02:53:04 PM PDT 24 82372784 ps
T1852 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3449816045 May 16 02:53:11 PM PDT 24 May 16 02:53:15 PM PDT 24 207765423 ps
T1853 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4246526892 May 16 02:53:11 PM PDT 24 May 16 02:53:14 PM PDT 24 53600771 ps
T1854 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2786853742 May 16 02:53:13 PM PDT 24 May 16 02:53:15 PM PDT 24 46373812 ps
T1855 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1708096719 May 16 02:52:53 PM PDT 24 May 16 02:52:55 PM PDT 24 54711064 ps
T1856 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1624891274 May 16 02:53:48 PM PDT 24 May 16 02:53:49 PM PDT 24 45107966 ps
T1857 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2502067880 May 16 02:52:33 PM PDT 24 May 16 02:52:35 PM PDT 24 24570009 ps
T1858 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1924545472 May 16 02:53:12 PM PDT 24 May 16 02:53:15 PM PDT 24 58409471 ps
T1859 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2882870463 May 16 02:52:32 PM PDT 24 May 16 02:52:34 PM PDT 24 45493807 ps
T1860 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1921383504 May 16 02:52:51 PM PDT 24 May 16 02:52:53 PM PDT 24 27930302 ps
T1861 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2281635705 May 16 02:52:41 PM PDT 24 May 16 02:52:43 PM PDT 24 130038837 ps
T1862 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2189386375 May 16 02:52:32 PM PDT 24 May 16 02:52:35 PM PDT 24 206516111 ps
T1863 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3540351357 May 16 02:53:43 PM PDT 24 May 16 02:53:46 PM PDT 24 77123166 ps
T1864 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1048227540 May 16 02:53:13 PM PDT 24 May 16 02:53:15 PM PDT 24 34319248 ps
T1865 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.690910474 May 16 02:53:21 PM PDT 24 May 16 02:53:25 PM PDT 24 160079198 ps
T1866 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2367069978 May 16 02:53:22 PM PDT 24 May 16 02:53:24 PM PDT 24 38822169 ps
T1867 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.477178406 May 16 02:53:12 PM PDT 24 May 16 02:53:16 PM PDT 24 112113591 ps
T1868 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2381290620 May 16 02:53:31 PM PDT 24 May 16 02:53:38 PM PDT 24 794037166 ps

Test location /workspace/coverage/default/43.usbdev_smoke.1574786706
Short name T19
Test name
Test status
Simulation time 8447107827 ps
CPU time 12.93 seconds
Started May 16 03:24:43 PM PDT 24
Finished May 16 03:25:06 PM PDT 24
Peak memory 204840 kb
Host smart-aaee05e5-e7fb-4387-b3d8-0b4a07f4b170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15747
86706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1574786706
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.240223689
Short name T4
Test name
Test status
Simulation time 19927819801 ps
CPU time 37.12 seconds
Started May 16 03:20:43 PM PDT 24
Finished May 16 03:21:26 PM PDT 24
Peak memory 204840 kb
Host smart-46de68ec-8d5c-4188-a432-f2962b34c5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24022
3689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.240223689
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2255633914
Short name T83
Test name
Test status
Simulation time 49593091 ps
CPU time 0.7 seconds
Started May 16 02:53:53 PM PDT 24
Finished May 16 02:53:56 PM PDT 24
Peak memory 203628 kb
Host smart-e2da3702-f087-42b5-baed-445d2f111d63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2255633914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2255633914
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3209983015
Short name T70
Test name
Test status
Simulation time 77899970 ps
CPU time 1.22 seconds
Started May 16 02:52:29 PM PDT 24
Finished May 16 02:52:31 PM PDT 24
Peak memory 212568 kb
Host smart-087e78b8-2795-4b51-be07-b26c040b5b44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209983015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3209983015
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.879525161
Short name T22
Test name
Test status
Simulation time 8460552740 ps
CPU time 11.48 seconds
Started May 16 03:20:01 PM PDT 24
Finished May 16 03:20:23 PM PDT 24
Peak memory 204792 kb
Host smart-6d31ac45-cc86-41b7-8e50-327eb0a58b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87952
5161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.879525161
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.312801416
Short name T79
Test name
Test status
Simulation time 33635786 ps
CPU time 0.67 seconds
Started May 16 02:53:41 PM PDT 24
Finished May 16 02:53:43 PM PDT 24
Peak memory 203656 kb
Host smart-07dbc693-c9e0-4709-ac75-62070b241763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=312801416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.312801416
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1643665457
Short name T5
Test name
Test status
Simulation time 11544668626 ps
CPU time 14.84 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204728 kb
Host smart-a5710731-7af2-47d3-aebb-b1b38d52fb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16436
65457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1643665457
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2714256939
Short name T237
Test name
Test status
Simulation time 741546726 ps
CPU time 4.92 seconds
Started May 16 02:52:52 PM PDT 24
Finished May 16 02:52:58 PM PDT 24
Peak memory 204252 kb
Host smart-90212e6d-a912-4157-9d28-ad92bfd11312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2714256939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2714256939
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.575085581
Short name T42
Test name
Test status
Simulation time 8363747217 ps
CPU time 10.46 seconds
Started May 16 03:21:17 PM PDT 24
Finished May 16 03:21:32 PM PDT 24
Peak memory 204668 kb
Host smart-c5f99dc5-f49c-494c-8c71-aababf91d7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57508
5581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.575085581
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2103484662
Short name T26
Test name
Test status
Simulation time 8455411836 ps
CPU time 12.46 seconds
Started May 16 03:20:06 PM PDT 24
Finished May 16 03:20:27 PM PDT 24
Peak memory 204876 kb
Host smart-b7ec54f8-febe-4a96-9cd9-7bb44242a53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21034
84662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2103484662
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2369858159
Short name T394
Test name
Test status
Simulation time 8372335045 ps
CPU time 10.82 seconds
Started May 16 03:21:34 PM PDT 24
Finished May 16 03:21:55 PM PDT 24
Peak memory 204892 kb
Host smart-f8317fef-6853-419b-a7ca-36ef472492c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23698
58159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2369858159
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2627269794
Short name T139
Test name
Test status
Simulation time 8488515027 ps
CPU time 13.05 seconds
Started May 16 03:24:17 PM PDT 24
Finished May 16 03:24:43 PM PDT 24
Peak memory 204884 kb
Host smart-c6a836cc-373c-48c5-8636-7c7bde7483f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26272
69794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2627269794
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2004501654
Short name T40
Test name
Test status
Simulation time 8992562858 ps
CPU time 12.07 seconds
Started May 16 03:23:52 PM PDT 24
Finished May 16 03:24:16 PM PDT 24
Peak memory 204856 kb
Host smart-402ad99a-f878-468f-8334-f23a90cfecba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20045
01654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2004501654
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3334029711
Short name T29
Test name
Test status
Simulation time 8384260157 ps
CPU time 12.67 seconds
Started May 16 03:23:09 PM PDT 24
Finished May 16 03:23:28 PM PDT 24
Peak memory 204852 kb
Host smart-c8a1b874-c729-4bc1-b2ca-df3452036c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33340
29711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3334029711
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1973390066
Short name T1
Test name
Test status
Simulation time 144095486 ps
CPU time 0.95 seconds
Started May 16 02:52:41 PM PDT 24
Finished May 16 02:52:43 PM PDT 24
Peak memory 204092 kb
Host smart-03ba83de-fac0-4528-9b49-67c3a51edf2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1973390066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1973390066
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.451507031
Short name T62
Test name
Test status
Simulation time 179533863 ps
CPU time 0.98 seconds
Started May 16 03:18:48 PM PDT 24
Finished May 16 03:18:55 PM PDT 24
Peak memory 220472 kb
Host smart-33bc8a6c-4898-403e-8d2d-0b27170d7a6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=451507031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.451507031
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.2340373355
Short name T99
Test name
Test status
Simulation time 8419769593 ps
CPU time 14.48 seconds
Started May 16 03:23:42 PM PDT 24
Finished May 16 03:24:05 PM PDT 24
Peak memory 204872 kb
Host smart-55d51afd-9b11-495c-b630-d0912ff6e01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23403
73355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.2340373355
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3363502269
Short name T284
Test name
Test status
Simulation time 77462394 ps
CPU time 0.78 seconds
Started May 16 02:53:40 PM PDT 24
Finished May 16 02:53:42 PM PDT 24
Peak memory 203628 kb
Host smart-7d16ada9-9e65-4a31-8681-f6b8f4d03c4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3363502269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3363502269
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1056678531
Short name T41
Test name
Test status
Simulation time 8439871569 ps
CPU time 11.96 seconds
Started May 16 03:20:46 PM PDT 24
Finished May 16 03:21:03 PM PDT 24
Peak memory 204684 kb
Host smart-f145a235-cc81-4206-bc70-659ff84ce849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10566
78531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1056678531
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.86958730
Short name T57
Test name
Test status
Simulation time 8458038657 ps
CPU time 14.1 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204612 kb
Host smart-6df4b623-227f-4b9c-8223-2b54a2be9de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86958
730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.86958730
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1049581617
Short name T244
Test name
Test status
Simulation time 221989973 ps
CPU time 2.66 seconds
Started May 16 02:52:08 PM PDT 24
Finished May 16 02:52:11 PM PDT 24
Peak memory 204276 kb
Host smart-1eb25799-6268-455d-83b0-3e357d4cb0cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1049581617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1049581617
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3391323596
Short name T35
Test name
Test status
Simulation time 8435411662 ps
CPU time 11.58 seconds
Started May 16 03:24:58 PM PDT 24
Finished May 16 03:25:16 PM PDT 24
Peak memory 204884 kb
Host smart-185e79e8-8eec-4f02-ba24-f2a0c668fae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33913
23596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3391323596
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3179524404
Short name T289
Test name
Test status
Simulation time 30711413 ps
CPU time 0.7 seconds
Started May 16 02:53:42 PM PDT 24
Finished May 16 02:53:44 PM PDT 24
Peak memory 203660 kb
Host smart-dffe4d49-bf3f-44c8-9676-f72548313e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3179524404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3179524404
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.327062235
Short name T1809
Test name
Test status
Simulation time 46657052 ps
CPU time 0.72 seconds
Started May 16 02:53:42 PM PDT 24
Finished May 16 02:53:44 PM PDT 24
Peak memory 203708 kb
Host smart-e48f25cf-5967-4d6d-96dd-7329626fd235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=327062235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.327062235
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1082187391
Short name T294
Test name
Test status
Simulation time 621347937 ps
CPU time 4.9 seconds
Started May 16 02:52:33 PM PDT 24
Finished May 16 02:52:39 PM PDT 24
Peak memory 204252 kb
Host smart-5c854353-3a0b-48a1-8e45-9b872590c611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1082187391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1082187391
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2125246755
Short name T76
Test name
Test status
Simulation time 8405457255 ps
CPU time 13.19 seconds
Started May 16 03:22:06 PM PDT 24
Finished May 16 03:22:31 PM PDT 24
Peak memory 204796 kb
Host smart-96668d8c-b5d8-4642-9a73-61bf9287aa50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21252
46755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2125246755
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3293924558
Short name T277
Test name
Test status
Simulation time 1247509161 ps
CPU time 5.99 seconds
Started May 16 02:53:11 PM PDT 24
Finished May 16 02:53:19 PM PDT 24
Peak memory 204252 kb
Host smart-68102f7a-4160-4b12-88c6-a2f183816e47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3293924558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3293924558
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3091551597
Short name T267
Test name
Test status
Simulation time 89034957 ps
CPU time 1.15 seconds
Started May 16 02:53:12 PM PDT 24
Finished May 16 02:53:15 PM PDT 24
Peak memory 204212 kb
Host smart-0c7e12a6-e341-4c44-85dc-1603b72a241b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3091551597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3091551597
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.590592436
Short name T231
Test name
Test status
Simulation time 5102479238 ps
CPU time 136.52 seconds
Started May 16 03:18:44 PM PDT 24
Finished May 16 03:21:06 PM PDT 24
Peak memory 204880 kb
Host smart-7144211e-056a-4f4f-836c-d86b91847e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59059
2436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.590592436
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2513521048
Short name T152
Test name
Test status
Simulation time 9120388649 ps
CPU time 14.49 seconds
Started May 16 03:22:47 PM PDT 24
Finished May 16 03:23:11 PM PDT 24
Peak memory 204860 kb
Host smart-8f6d4d65-4514-4d35-b4e8-dc263fe16c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25135
21048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2513521048
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2364408027
Short name T69
Test name
Test status
Simulation time 191640940 ps
CPU time 1 seconds
Started May 16 02:52:19 PM PDT 24
Finished May 16 02:52:20 PM PDT 24
Peak memory 204076 kb
Host smart-0a851253-54dc-4109-b97e-826d8965064b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2364408027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2364408027
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2501853093
Short name T192
Test name
Test status
Simulation time 9648850017 ps
CPU time 14.97 seconds
Started May 16 03:23:20 PM PDT 24
Finished May 16 03:23:42 PM PDT 24
Peak memory 204832 kb
Host smart-8a33e6b6-8158-415f-ab7f-ec9d5283dff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25018
53093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2501853093
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1781906851
Short name T415
Test name
Test status
Simulation time 8361526831 ps
CPU time 13.89 seconds
Started May 16 03:18:57 PM PDT 24
Finished May 16 03:19:17 PM PDT 24
Peak memory 204864 kb
Host smart-b1926e20-19be-445f-b2fe-2d9724935c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17819
06851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1781906851
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3458866690
Short name T185
Test name
Test status
Simulation time 8448786599 ps
CPU time 12.55 seconds
Started May 16 03:21:17 PM PDT 24
Finished May 16 03:21:35 PM PDT 24
Peak memory 204792 kb
Host smart-fd949257-48f4-487b-b4cc-4c52f83c120b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34588
66690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3458866690
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2552570299
Short name T247
Test name
Test status
Simulation time 344790675 ps
CPU time 3.64 seconds
Started May 16 02:53:22 PM PDT 24
Finished May 16 02:53:27 PM PDT 24
Peak memory 212496 kb
Host smart-941c968b-73a6-44a5-85a1-02320d8ea49d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2552570299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2552570299
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3977887241
Short name T226
Test name
Test status
Simulation time 8409344500 ps
CPU time 11.03 seconds
Started May 16 03:18:59 PM PDT 24
Finished May 16 03:19:15 PM PDT 24
Peak memory 204872 kb
Host smart-778c3864-df10-4e00-bd05-3504b8b26a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39778
87241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3977887241
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.73843785
Short name T209
Test name
Test status
Simulation time 8396859138 ps
CPU time 12.38 seconds
Started May 16 03:20:30 PM PDT 24
Finished May 16 03:20:48 PM PDT 24
Peak memory 204816 kb
Host smart-d31f8fe9-b7e0-4590-95f3-de2f64025472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73843
785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.73843785
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.38558570
Short name T165
Test name
Test status
Simulation time 8377548596 ps
CPU time 11.74 seconds
Started May 16 03:21:04 PM PDT 24
Finished May 16 03:21:21 PM PDT 24
Peak memory 204896 kb
Host smart-6e29bac1-836d-4c02-8c76-6dce5be1dcfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38558
570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.38558570
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1062710580
Short name T219
Test name
Test status
Simulation time 8373224892 ps
CPU time 14.02 seconds
Started May 16 03:21:36 PM PDT 24
Finished May 16 03:22:00 PM PDT 24
Peak memory 204920 kb
Host smart-930894e7-3dfa-414e-b618-f3dccde35596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10627
10580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1062710580
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3728212800
Short name T202
Test name
Test status
Simulation time 8434245957 ps
CPU time 12.27 seconds
Started May 16 03:21:43 PM PDT 24
Finished May 16 03:22:06 PM PDT 24
Peak memory 204892 kb
Host smart-a5be4ad2-f719-4a22-82d4-9ef1a8f7cd8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37282
12800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3728212800
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3401666329
Short name T171
Test name
Test status
Simulation time 8429759148 ps
CPU time 11.3 seconds
Started May 16 03:22:14 PM PDT 24
Finished May 16 03:22:37 PM PDT 24
Peak memory 204656 kb
Host smart-dd3636ec-2cbb-4440-a50c-7c0752ffdb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34016
66329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3401666329
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3454369272
Short name T216
Test name
Test status
Simulation time 8385386488 ps
CPU time 11.3 seconds
Started May 16 03:23:12 PM PDT 24
Finished May 16 03:23:29 PM PDT 24
Peak memory 204888 kb
Host smart-b90dd81c-bc45-4de4-aad4-ea88f76e5ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34543
69272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3454369272
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2030481117
Short name T214
Test name
Test status
Simulation time 8408547212 ps
CPU time 11.77 seconds
Started May 16 03:23:19 PM PDT 24
Finished May 16 03:23:37 PM PDT 24
Peak memory 204836 kb
Host smart-3d2755ca-5ec2-49cd-b840-065c240aadf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20304
81117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2030481117
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3647541472
Short name T189
Test name
Test status
Simulation time 8381531843 ps
CPU time 12.77 seconds
Started May 16 03:23:42 PM PDT 24
Finished May 16 03:24:04 PM PDT 24
Peak memory 204804 kb
Host smart-092d0604-5fb3-4757-9a15-71ccc5cdedd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36475
41472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3647541472
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.1952582237
Short name T331
Test name
Test status
Simulation time 8381273888 ps
CPU time 11.99 seconds
Started May 16 03:18:49 PM PDT 24
Finished May 16 03:19:07 PM PDT 24
Peak memory 204880 kb
Host smart-c9b8b8d1-4ea3-4e45-acf7-c83654b0d6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19525
82237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.1952582237
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.3239825934
Short name T24
Test name
Test status
Simulation time 8464628498 ps
CPU time 10.92 seconds
Started May 16 03:20:26 PM PDT 24
Finished May 16 03:20:43 PM PDT 24
Peak memory 204812 kb
Host smart-ffb2cc03-542c-4e37-928b-e451f72865a4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3239825934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.3239825934
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.755543182
Short name T1539
Test name
Test status
Simulation time 9604001429 ps
CPU time 14.06 seconds
Started May 16 03:22:37 PM PDT 24
Finished May 16 03:23:03 PM PDT 24
Peak memory 204776 kb
Host smart-2b93780e-799a-4661-a345-d01ef47fcbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75554
3182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.755543182
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2024433118
Short name T1726
Test name
Test status
Simulation time 27624209910 ps
CPU time 55.56 seconds
Started May 16 03:18:43 PM PDT 24
Finished May 16 03:19:45 PM PDT 24
Peak memory 204708 kb
Host smart-273f2340-65e0-46da-ac57-abff2dd75188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20244
33118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2024433118
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3960298876
Short name T624
Test name
Test status
Simulation time 8373899040 ps
CPU time 10.88 seconds
Started May 16 03:18:52 PM PDT 24
Finished May 16 03:19:09 PM PDT 24
Peak memory 204692 kb
Host smart-31628c9d-6ad7-43b1-b0c7-564590b0012d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39602
98876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3960298876
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3287967246
Short name T121
Test name
Test status
Simulation time 8420159473 ps
CPU time 13.73 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:10 PM PDT 24
Peak memory 204892 kb
Host smart-e0a1f9c6-ee38-462f-8b3f-bc514319316f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32879
67246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3287967246
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3515182686
Short name T130
Test name
Test status
Simulation time 8435411876 ps
CPU time 11.61 seconds
Started May 16 03:20:28 PM PDT 24
Finished May 16 03:20:45 PM PDT 24
Peak memory 204860 kb
Host smart-69e00b79-8a3c-40b9-933e-a9ad325f422b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35151
82686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3515182686
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.4128492739
Short name T138
Test name
Test status
Simulation time 8431741392 ps
CPU time 11.81 seconds
Started May 16 03:20:26 PM PDT 24
Finished May 16 03:20:43 PM PDT 24
Peak memory 204904 kb
Host smart-23d5e44c-e2fb-4422-a1b9-e8f18cbf9f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41284
92739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.4128492739
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1765833242
Short name T147
Test name
Test status
Simulation time 8487300078 ps
CPU time 10.82 seconds
Started May 16 03:20:45 PM PDT 24
Finished May 16 03:21:01 PM PDT 24
Peak memory 204844 kb
Host smart-132a9e14-ea9b-4fd5-a172-c2bc9ab65cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17658
33242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1765833242
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3552447207
Short name T198
Test name
Test status
Simulation time 8379296834 ps
CPU time 10.72 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:09 PM PDT 24
Peak memory 204792 kb
Host smart-314b253b-b5cc-4fb6-b55c-87cf9f3a18dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35524
47207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3552447207
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3463735294
Short name T119
Test name
Test status
Simulation time 8453470926 ps
CPU time 11.15 seconds
Started May 16 03:21:03 PM PDT 24
Finished May 16 03:21:19 PM PDT 24
Peak memory 204772 kb
Host smart-2c77be97-9ea7-4eab-8461-f01c3d4bfd1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34637
35294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3463735294
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1701400491
Short name T1398
Test name
Test status
Simulation time 8453179525 ps
CPU time 11.14 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:31 PM PDT 24
Peak memory 204656 kb
Host smart-d15a3d81-3236-4ec0-96d8-2fffd06e088c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17014
00491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1701400491
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3979872178
Short name T164
Test name
Test status
Simulation time 8388381812 ps
CPU time 11.74 seconds
Started May 16 03:19:06 PM PDT 24
Finished May 16 03:19:23 PM PDT 24
Peak memory 204940 kb
Host smart-a69294b9-7ad8-4e01-80f7-05047adbb5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39798
72178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3979872178
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2880960410
Short name T126
Test name
Test status
Simulation time 8461186385 ps
CPU time 11.32 seconds
Started May 16 03:22:07 PM PDT 24
Finished May 16 03:22:30 PM PDT 24
Peak memory 204892 kb
Host smart-d39a097c-23b0-4770-bba7-25030c63d85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28809
60410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2880960410
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2270323460
Short name T135
Test name
Test status
Simulation time 8397544815 ps
CPU time 11.66 seconds
Started May 16 03:22:15 PM PDT 24
Finished May 16 03:22:38 PM PDT 24
Peak memory 204256 kb
Host smart-fde17620-9945-4ea4-8d33-b55210e93bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22703
23460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2270323460
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3565914513
Short name T103
Test name
Test status
Simulation time 8381224894 ps
CPU time 12.08 seconds
Started May 16 03:22:25 PM PDT 24
Finished May 16 03:22:48 PM PDT 24
Peak memory 204784 kb
Host smart-9783c62f-a129-4bb0-bf1e-3e06a2fc9ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35659
14513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3565914513
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1065388837
Short name T1259
Test name
Test status
Simulation time 8425737753 ps
CPU time 11.12 seconds
Started May 16 03:22:28 PM PDT 24
Finished May 16 03:22:51 PM PDT 24
Peak memory 204868 kb
Host smart-87f4d6e4-2ee0-4d98-bd2b-900e476c4f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10653
88837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1065388837
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.32122681
Short name T127
Test name
Test status
Simulation time 8494437268 ps
CPU time 11.83 seconds
Started May 16 03:23:52 PM PDT 24
Finished May 16 03:24:16 PM PDT 24
Peak memory 204892 kb
Host smart-1094c2d4-198b-42ca-881f-ba0c1407edfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32122
681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.32122681
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1830934551
Short name T100
Test name
Test status
Simulation time 8403680656 ps
CPU time 11.86 seconds
Started May 16 03:19:27 PM PDT 24
Finished May 16 03:19:44 PM PDT 24
Peak memory 204956 kb
Host smart-6c5ab1fb-1b97-40ed-abd8-172b2f35048a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18309
34551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1830934551
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3342970990
Short name T222
Test name
Test status
Simulation time 8443575685 ps
CPU time 11.09 seconds
Started May 16 03:24:58 PM PDT 24
Finished May 16 03:25:15 PM PDT 24
Peak memory 204892 kb
Host smart-6183bab0-3f7b-4067-aeec-a3e3d5f8ec8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33429
70990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3342970990
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1314880794
Short name T125
Test name
Test status
Simulation time 8435104342 ps
CPU time 12.43 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:25:45 PM PDT 24
Peak memory 204936 kb
Host smart-3e52d252-dd96-42a3-ada8-ef55e3e71b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13148
80794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1314880794
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2795860253
Short name T74
Test name
Test status
Simulation time 162575550 ps
CPU time 2.14 seconds
Started May 16 02:52:09 PM PDT 24
Finished May 16 02:52:12 PM PDT 24
Peak memory 204260 kb
Host smart-904e188f-efa5-47a0-a617-a58066c1852e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2795860253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2795860253
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1312122339
Short name T261
Test name
Test status
Simulation time 1268180490 ps
CPU time 9.01 seconds
Started May 16 02:52:10 PM PDT 24
Finished May 16 02:52:20 PM PDT 24
Peak memory 204216 kb
Host smart-16c8e3b1-6255-429b-96dd-b52b5695ac9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1312122339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1312122339
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2424573536
Short name T80
Test name
Test status
Simulation time 37398080 ps
CPU time 0.78 seconds
Started May 16 02:52:09 PM PDT 24
Finished May 16 02:52:11 PM PDT 24
Peak memory 204076 kb
Host smart-b5a2a9b5-39bf-4bd6-ad7d-b1eac3c85d2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2424573536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2424573536
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2938496607
Short name T1775
Test name
Test status
Simulation time 118303321 ps
CPU time 3.03 seconds
Started May 16 02:52:19 PM PDT 24
Finished May 16 02:52:23 PM PDT 24
Peak memory 212524 kb
Host smart-f7823404-0a77-49aa-954d-22647a193df3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938496607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2938496607
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3961080254
Short name T1818
Test name
Test status
Simulation time 71905178 ps
CPU time 1.03 seconds
Started May 16 02:52:09 PM PDT 24
Finished May 16 02:52:12 PM PDT 24
Peak memory 204248 kb
Host smart-68a5ea51-0227-4b6c-9f63-906a83f9fae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3961080254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3961080254
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.114631783
Short name T280
Test name
Test status
Simulation time 33124560 ps
CPU time 0.64 seconds
Started May 16 02:52:09 PM PDT 24
Finished May 16 02:52:11 PM PDT 24
Peak memory 203704 kb
Host smart-cdf136b3-35cd-49e4-991f-df40d5691ea0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=114631783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.114631783
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3797714151
Short name T1829
Test name
Test status
Simulation time 108477302 ps
CPU time 1.48 seconds
Started May 16 02:52:09 PM PDT 24
Finished May 16 02:52:11 PM PDT 24
Peak memory 204132 kb
Host smart-78831d16-6d35-4fa8-855d-fe69452b9c06
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3797714151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3797714151
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.50475077
Short name T1795
Test name
Test status
Simulation time 718313383 ps
CPU time 4.62 seconds
Started May 16 02:52:08 PM PDT 24
Finished May 16 02:52:14 PM PDT 24
Peak memory 204200 kb
Host smart-06d6c39e-1283-4b36-a4f5-b9b19b032856
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=50475077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.50475077
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1924743660
Short name T1779
Test name
Test status
Simulation time 60103468 ps
CPU time 1.45 seconds
Started May 16 02:52:08 PM PDT 24
Finished May 16 02:52:11 PM PDT 24
Peak memory 204268 kb
Host smart-4c3e96cb-f4e5-469c-8295-74d79a432609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1924743660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1924743660
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4294529346
Short name T295
Test name
Test status
Simulation time 374540225 ps
CPU time 2.38 seconds
Started May 16 02:52:09 PM PDT 24
Finished May 16 02:52:12 PM PDT 24
Peak memory 204200 kb
Host smart-54ba8e3a-7601-4684-8d72-5e8a425d825e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4294529346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.4294529346
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.919235049
Short name T278
Test name
Test status
Simulation time 213908558 ps
CPU time 2.22 seconds
Started May 16 02:52:31 PM PDT 24
Finished May 16 02:52:35 PM PDT 24
Peak memory 204168 kb
Host smart-aeba31f7-d68d-46c6-8035-b62a6044ffb7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=919235049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.919235049
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2857092405
Short name T255
Test name
Test status
Simulation time 261474192 ps
CPU time 4.51 seconds
Started May 16 02:52:29 PM PDT 24
Finished May 16 02:52:35 PM PDT 24
Peak memory 204192 kb
Host smart-fbb1de2f-f9cb-4170-b3ad-4d2ebd837b87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2857092405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2857092405
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1356163176
Short name T1804
Test name
Test status
Simulation time 35925554 ps
CPU time 0.91 seconds
Started May 16 02:52:17 PM PDT 24
Finished May 16 02:52:19 PM PDT 24
Peak memory 204180 kb
Host smart-0d31eda6-461d-46c5-85d7-f85614b26dab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1356163176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1356163176
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1350480173
Short name T1849
Test name
Test status
Simulation time 48371567 ps
CPU time 0.69 seconds
Started May 16 02:52:19 PM PDT 24
Finished May 16 02:52:21 PM PDT 24
Peak memory 203620 kb
Host smart-ab96ba8f-c5ff-43ad-a44f-3be643095bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1350480173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1350480173
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.4241507841
Short name T1840
Test name
Test status
Simulation time 92125109 ps
CPU time 1.47 seconds
Started May 16 02:52:19 PM PDT 24
Finished May 16 02:52:21 PM PDT 24
Peak memory 204184 kb
Host smart-e7f7e2f4-2d82-45fc-a907-d0df2a1b0d3b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4241507841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.4241507841
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4063703999
Short name T1843
Test name
Test status
Simulation time 254434056 ps
CPU time 2.53 seconds
Started May 16 02:52:18 PM PDT 24
Finished May 16 02:52:21 PM PDT 24
Peak memory 204232 kb
Host smart-97cd7ddd-5510-451b-9a85-9105f45c3013
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4063703999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.4063703999
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2189386375
Short name T1862
Test name
Test status
Simulation time 206516111 ps
CPU time 1.72 seconds
Started May 16 02:52:32 PM PDT 24
Finished May 16 02:52:35 PM PDT 24
Peak memory 204160 kb
Host smart-b7292d14-fc22-4772-b77c-5715f55c1ce5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2189386375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2189386375
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4057550448
Short name T1838
Test name
Test status
Simulation time 127265168 ps
CPU time 3.51 seconds
Started May 16 02:52:20 PM PDT 24
Finished May 16 02:52:24 PM PDT 24
Peak memory 204276 kb
Host smart-81d92802-b2d2-4bb2-ae85-44b893e8d759
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4057550448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.4057550448
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3499607578
Short name T296
Test name
Test status
Simulation time 390686849 ps
CPU time 2.68 seconds
Started May 16 02:52:19 PM PDT 24
Finished May 16 02:52:22 PM PDT 24
Peak memory 204216 kb
Host smart-d193f6c0-a6e6-42c9-9f9a-5b50f4fd99c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3499607578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3499607578
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.860293368
Short name T235
Test name
Test status
Simulation time 176669753 ps
CPU time 2.38 seconds
Started May 16 02:53:12 PM PDT 24
Finished May 16 02:53:16 PM PDT 24
Peak memory 212456 kb
Host smart-96abb8b0-0703-4dc8-9d17-4e5fe586d7be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860293368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.860293368
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1048227540
Short name T1864
Test name
Test status
Simulation time 34319248 ps
CPU time 0.84 seconds
Started May 16 02:53:13 PM PDT 24
Finished May 16 02:53:15 PM PDT 24
Peak memory 204108 kb
Host smart-eb9fb500-8934-4ea6-aae4-a38fc2480bba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1048227540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1048227540
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2786853742
Short name T1854
Test name
Test status
Simulation time 46373812 ps
CPU time 0.67 seconds
Started May 16 02:53:13 PM PDT 24
Finished May 16 02:53:15 PM PDT 24
Peak memory 203660 kb
Host smart-1e6b4256-f569-4170-9c53-a3b2d90d26ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2786853742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2786853742
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.477178406
Short name T1867
Test name
Test status
Simulation time 112113591 ps
CPU time 1.64 seconds
Started May 16 02:53:12 PM PDT 24
Finished May 16 02:53:16 PM PDT 24
Peak memory 204232 kb
Host smart-8ff439c7-9e1c-4be9-aa34-f0cc298d15a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=477178406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.477178406
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2202735510
Short name T1844
Test name
Test status
Simulation time 346608617 ps
CPU time 3.59 seconds
Started May 16 02:53:10 PM PDT 24
Finished May 16 02:53:16 PM PDT 24
Peak memory 204284 kb
Host smart-39b2e1fd-95a4-40e7-8f00-3a8f3e65a691
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2202735510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2202735510
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.18052367
Short name T1842
Test name
Test status
Simulation time 394509881 ps
CPU time 2.58 seconds
Started May 16 02:53:11 PM PDT 24
Finished May 16 02:53:15 PM PDT 24
Peak memory 204184 kb
Host smart-6c1815b2-c000-477c-8410-ad83b01bf5cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=18052367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.18052367
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3449816045
Short name T1852
Test name
Test status
Simulation time 207765423 ps
CPU time 1.9 seconds
Started May 16 02:53:11 PM PDT 24
Finished May 16 02:53:15 PM PDT 24
Peak memory 212480 kb
Host smart-3da7333b-04cf-4986-bff9-1ab01c0b4c38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449816045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3449816045
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4246526892
Short name T1853
Test name
Test status
Simulation time 53600771 ps
CPU time 0.79 seconds
Started May 16 02:53:11 PM PDT 24
Finished May 16 02:53:14 PM PDT 24
Peak memory 204052 kb
Host smart-12a2e6b3-6d55-49ba-96a8-82f4ae493933
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4246526892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.4246526892
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.624932376
Short name T1780
Test name
Test status
Simulation time 30753649 ps
CPU time 0.63 seconds
Started May 16 02:53:11 PM PDT 24
Finished May 16 02:53:13 PM PDT 24
Peak memory 203648 kb
Host smart-54fecfa4-36f2-4f54-8b4e-24a4cbdce056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=624932376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.624932376
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1924545472
Short name T1858
Test name
Test status
Simulation time 58409471 ps
CPU time 1.6 seconds
Started May 16 02:53:12 PM PDT 24
Finished May 16 02:53:15 PM PDT 24
Peak memory 204252 kb
Host smart-8fbf53d1-b9a0-47fa-b563-a487acecfd50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1924545472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1924545472
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1574467956
Short name T248
Test name
Test status
Simulation time 88414493 ps
CPU time 2.31 seconds
Started May 16 02:53:21 PM PDT 24
Finished May 16 02:53:25 PM PDT 24
Peak memory 212476 kb
Host smart-d05a5ed3-c2d8-4b7e-9d33-df780248fff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574467956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1574467956
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3591854113
Short name T1850
Test name
Test status
Simulation time 55739039 ps
CPU time 0.85 seconds
Started May 16 02:53:19 PM PDT 24
Finished May 16 02:53:20 PM PDT 24
Peak memory 204104 kb
Host smart-907e6071-6d97-4b40-90e4-94ea190cec89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3591854113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3591854113
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1314577212
Short name T84
Test name
Test status
Simulation time 36079064 ps
CPU time 0.67 seconds
Started May 16 02:53:21 PM PDT 24
Finished May 16 02:53:23 PM PDT 24
Peak memory 203604 kb
Host smart-a2a71510-49b5-4826-946e-3c44797a25de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1314577212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1314577212
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3101076485
Short name T115
Test name
Test status
Simulation time 109535171 ps
CPU time 1.35 seconds
Started May 16 02:53:21 PM PDT 24
Finished May 16 02:53:23 PM PDT 24
Peak memory 204240 kb
Host smart-8519ba9f-857c-4c14-b886-aa47b53de871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3101076485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3101076485
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1107334545
Short name T243
Test name
Test status
Simulation time 179773179 ps
CPU time 2.21 seconds
Started May 16 02:53:25 PM PDT 24
Finished May 16 02:53:29 PM PDT 24
Peak memory 204232 kb
Host smart-accbecc9-5c37-46f4-8c6b-e5e56b292cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1107334545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1107334545
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1440573034
Short name T297
Test name
Test status
Simulation time 1238392515 ps
CPU time 5.03 seconds
Started May 16 02:53:20 PM PDT 24
Finished May 16 02:53:27 PM PDT 24
Peak memory 204188 kb
Host smart-0324cbee-94bb-462e-89f3-63d5c2778273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1440573034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1440573034
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3289350258
Short name T1772
Test name
Test status
Simulation time 101080798 ps
CPU time 1.32 seconds
Started May 16 02:53:22 PM PDT 24
Finished May 16 02:53:25 PM PDT 24
Peak memory 212524 kb
Host smart-87f52de0-4623-407d-bf2b-f3b370a6e026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289350258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3289350258
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2902862497
Short name T1799
Test name
Test status
Simulation time 136497110 ps
CPU time 0.87 seconds
Started May 16 02:53:22 PM PDT 24
Finished May 16 02:53:25 PM PDT 24
Peak memory 204116 kb
Host smart-f0c3713c-b6fb-4d68-a45b-f2914c793194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2902862497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2902862497
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2367069978
Short name T1866
Test name
Test status
Simulation time 38822169 ps
CPU time 0.68 seconds
Started May 16 02:53:22 PM PDT 24
Finished May 16 02:53:24 PM PDT 24
Peak memory 203632 kb
Host smart-13caddca-855f-40af-bcb2-88137a79c93c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2367069978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2367069978
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3973306769
Short name T1845
Test name
Test status
Simulation time 149569712 ps
CPU time 1.25 seconds
Started May 16 02:53:20 PM PDT 24
Finished May 16 02:53:22 PM PDT 24
Peak memory 204176 kb
Host smart-6b13e1d3-34db-4fb9-a352-5b6432e5020d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3973306769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3973306769
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2902060138
Short name T232
Test name
Test status
Simulation time 109841748 ps
CPU time 1.71 seconds
Started May 16 02:53:20 PM PDT 24
Finished May 16 02:53:24 PM PDT 24
Peak memory 204296 kb
Host smart-c0cfd989-358a-4391-b123-0c94f0c614ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2902060138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2902060138
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1588313349
Short name T1828
Test name
Test status
Simulation time 674681779 ps
CPU time 3.06 seconds
Started May 16 02:53:23 PM PDT 24
Finished May 16 02:53:27 PM PDT 24
Peak memory 204188 kb
Host smart-dfecab44-e9e0-4f3e-a1f1-e8d620c02e29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1588313349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1588313349
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3415722344
Short name T1790
Test name
Test status
Simulation time 137374163 ps
CPU time 1.85 seconds
Started May 16 02:53:22 PM PDT 24
Finished May 16 02:53:26 PM PDT 24
Peak memory 212472 kb
Host smart-a11ba56c-0d6f-4b5c-b8c0-3fe64a374f19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415722344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3415722344
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.883376577
Short name T1815
Test name
Test status
Simulation time 36598053 ps
CPU time 0.82 seconds
Started May 16 02:53:22 PM PDT 24
Finished May 16 02:53:24 PM PDT 24
Peak memory 204148 kb
Host smart-d721a213-cc34-4bb9-8caa-fe0736ea9d0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=883376577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.883376577
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2030468598
Short name T1810
Test name
Test status
Simulation time 34449195 ps
CPU time 0.65 seconds
Started May 16 02:53:23 PM PDT 24
Finished May 16 02:53:25 PM PDT 24
Peak memory 203640 kb
Host smart-60d7e787-fe49-4cfe-a689-b46bd5bbe752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2030468598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.2030468598
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2250437464
Short name T270
Test name
Test status
Simulation time 56241241 ps
CPU time 1.09 seconds
Started May 16 02:53:20 PM PDT 24
Finished May 16 02:53:23 PM PDT 24
Peak memory 204228 kb
Host smart-3cd47d59-c597-43c4-8603-0c1efe868a2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2250437464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2250437464
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.690910474
Short name T1865
Test name
Test status
Simulation time 160079198 ps
CPU time 1.82 seconds
Started May 16 02:53:21 PM PDT 24
Finished May 16 02:53:25 PM PDT 24
Peak memory 204232 kb
Host smart-dff4eb1e-0043-46ef-a029-fb30692e97d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=690910474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.690910474
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2940508215
Short name T236
Test name
Test status
Simulation time 220201655 ps
CPU time 2.28 seconds
Started May 16 02:53:25 PM PDT 24
Finished May 16 02:53:29 PM PDT 24
Peak memory 204204 kb
Host smart-6dfb1325-24c6-4676-9d58-73f50b0b075d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2940508215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2940508215
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.378817807
Short name T73
Test name
Test status
Simulation time 83684617 ps
CPU time 1.32 seconds
Started May 16 02:53:20 PM PDT 24
Finished May 16 02:53:23 PM PDT 24
Peak memory 213672 kb
Host smart-1363bf31-2b21-41f2-b564-2943d93a4330
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378817807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.378817807
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3392121703
Short name T1819
Test name
Test status
Simulation time 93932717 ps
CPU time 1.03 seconds
Started May 16 02:53:21 PM PDT 24
Finished May 16 02:53:24 PM PDT 24
Peak memory 204228 kb
Host smart-e22ec643-7617-48fa-a55f-02c78fd6d73f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3392121703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3392121703
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3572799965
Short name T1793
Test name
Test status
Simulation time 29947045 ps
CPU time 0.65 seconds
Started May 16 02:53:22 PM PDT 24
Finished May 16 02:53:24 PM PDT 24
Peak memory 203568 kb
Host smart-b7babe68-af3f-47ce-8956-2c725b0b6c87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3572799965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3572799965
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.205633417
Short name T234
Test name
Test status
Simulation time 249245625 ps
CPU time 1.88 seconds
Started May 16 02:53:26 PM PDT 24
Finished May 16 02:53:29 PM PDT 24
Peak memory 204224 kb
Host smart-7f14297d-cdba-4fea-ad31-11227d9f9162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=205633417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.205633417
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.437466828
Short name T1837
Test name
Test status
Simulation time 77547180 ps
CPU time 2.14 seconds
Started May 16 02:53:20 PM PDT 24
Finished May 16 02:53:24 PM PDT 24
Peak memory 204304 kb
Host smart-b4cd1be4-9c02-4a97-a21a-09c5b530dc88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=437466828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.437466828
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.786271096
Short name T299
Test name
Test status
Simulation time 725503097 ps
CPU time 3.05 seconds
Started May 16 02:53:21 PM PDT 24
Finished May 16 02:53:26 PM PDT 24
Peak memory 204264 kb
Host smart-3d94c3fe-ae40-48cb-909d-b01b905bacc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=786271096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.786271096
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.517841082
Short name T1783
Test name
Test status
Simulation time 212593386 ps
CPU time 1.92 seconds
Started May 16 02:53:32 PM PDT 24
Finished May 16 02:53:35 PM PDT 24
Peak memory 215568 kb
Host smart-0d70cea6-f9c3-4c35-a1d1-5143969e49c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517841082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.517841082
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3957058917
Short name T1841
Test name
Test status
Simulation time 48387126 ps
CPU time 0.98 seconds
Started May 16 02:53:29 PM PDT 24
Finished May 16 02:53:32 PM PDT 24
Peak memory 204172 kb
Host smart-6fe65b48-9223-47cf-8528-d513495dde3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3957058917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3957058917
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1545050646
Short name T1835
Test name
Test status
Simulation time 41160671 ps
CPU time 0.68 seconds
Started May 16 02:53:22 PM PDT 24
Finished May 16 02:53:24 PM PDT 24
Peak memory 203624 kb
Host smart-b025b29f-8aef-4f0a-88f9-9dbe837d9d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1545050646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1545050646
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.435315153
Short name T1821
Test name
Test status
Simulation time 170726204 ps
CPU time 1.52 seconds
Started May 16 02:53:29 PM PDT 24
Finished May 16 02:53:31 PM PDT 24
Peak memory 204248 kb
Host smart-f140da74-2842-4ca1-bb53-3657b0300554
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=435315153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.435315153
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.706252840
Short name T1782
Test name
Test status
Simulation time 370799894 ps
CPU time 4.25 seconds
Started May 16 02:53:22 PM PDT 24
Finished May 16 02:53:28 PM PDT 24
Peak memory 204136 kb
Host smart-08fd89a4-fc74-45b9-ae76-a865752e5c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=706252840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.706252840
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.381514181
Short name T279
Test name
Test status
Simulation time 114642775 ps
CPU time 1.14 seconds
Started May 16 02:53:29 PM PDT 24
Finished May 16 02:53:31 PM PDT 24
Peak memory 212532 kb
Host smart-af0e29e6-62d0-4e36-8375-b7aa6431aaa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381514181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.381514181
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3933673882
Short name T260
Test name
Test status
Simulation time 58942633 ps
CPU time 1.03 seconds
Started May 16 02:53:30 PM PDT 24
Finished May 16 02:53:32 PM PDT 24
Peak memory 204168 kb
Host smart-5659f5c6-38c5-4910-b8e3-3371d9a34d9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3933673882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3933673882
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.104189369
Short name T1774
Test name
Test status
Simulation time 40117867 ps
CPU time 0.71 seconds
Started May 16 02:53:35 PM PDT 24
Finished May 16 02:53:36 PM PDT 24
Peak memory 203680 kb
Host smart-1b7d09d7-7ff3-4cb0-822a-fc331691ea2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=104189369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.104189369
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1768677670
Short name T269
Test name
Test status
Simulation time 48784561 ps
CPU time 1.11 seconds
Started May 16 02:53:30 PM PDT 24
Finished May 16 02:53:33 PM PDT 24
Peak memory 204272 kb
Host smart-34349e9b-1c19-4f78-a1e4-d87eefd11148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1768677670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1768677670
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.425337924
Short name T65
Test name
Test status
Simulation time 214683538 ps
CPU time 2.92 seconds
Started May 16 02:53:29 PM PDT 24
Finished May 16 02:53:33 PM PDT 24
Peak memory 204208 kb
Host smart-450526d4-6922-4bbc-97a0-5615c1a594a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=425337924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.425337924
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.794316410
Short name T233
Test name
Test status
Simulation time 691904899 ps
CPU time 4.07 seconds
Started May 16 02:53:31 PM PDT 24
Finished May 16 02:53:37 PM PDT 24
Peak memory 204212 kb
Host smart-d6aa00f8-56e1-4e3f-9d1c-a9e2a1a30f8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=794316410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.794316410
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2768704010
Short name T67
Test name
Test status
Simulation time 93058534 ps
CPU time 2.2 seconds
Started May 16 02:53:29 PM PDT 24
Finished May 16 02:53:33 PM PDT 24
Peak memory 212576 kb
Host smart-f9f6822c-c9c4-465d-bc36-49fc3822b748
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768704010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2768704010
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.775466819
Short name T72
Test name
Test status
Simulation time 91019766 ps
CPU time 1.04 seconds
Started May 16 02:53:30 PM PDT 24
Finished May 16 02:53:32 PM PDT 24
Peak memory 204224 kb
Host smart-72c22bd8-ad96-44c9-b2af-5b151e33b65d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=775466819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.775466819
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2416763678
Short name T1839
Test name
Test status
Simulation time 46671782 ps
CPU time 0.67 seconds
Started May 16 02:53:30 PM PDT 24
Finished May 16 02:53:32 PM PDT 24
Peak memory 203636 kb
Host smart-a14813e1-960e-4200-9374-b0a9754f6981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2416763678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2416763678
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2768804248
Short name T117
Test name
Test status
Simulation time 358719926 ps
CPU time 1.87 seconds
Started May 16 02:53:35 PM PDT 24
Finished May 16 02:53:37 PM PDT 24
Peak memory 204236 kb
Host smart-0c312ad5-32b0-4a1c-9b65-732f9b99fb2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2768804248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2768804248
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1596461042
Short name T246
Test name
Test status
Simulation time 147607872 ps
CPU time 1.53 seconds
Started May 16 02:53:29 PM PDT 24
Finished May 16 02:53:31 PM PDT 24
Peak memory 204276 kb
Host smart-916a4674-f22e-489e-b6ae-b2a983261a17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1596461042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1596461042
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2652721140
Short name T1824
Test name
Test status
Simulation time 426034019 ps
CPU time 2.77 seconds
Started May 16 02:53:35 PM PDT 24
Finished May 16 02:53:38 PM PDT 24
Peak memory 204244 kb
Host smart-1dbba5b1-b96f-4fce-82d3-94fcab026055
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2652721140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2652721140
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3540351357
Short name T1863
Test name
Test status
Simulation time 77123166 ps
CPU time 1.2 seconds
Started May 16 02:53:43 PM PDT 24
Finished May 16 02:53:46 PM PDT 24
Peak memory 212500 kb
Host smart-8478368f-45a3-48df-a5d0-e610cceeb6ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540351357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3540351357
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4087765019
Short name T71
Test name
Test status
Simulation time 59123519 ps
CPU time 0.99 seconds
Started May 16 02:53:33 PM PDT 24
Finished May 16 02:53:34 PM PDT 24
Peak memory 204268 kb
Host smart-fc3e2c3b-0ed9-40e8-ab25-41d80be58538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4087765019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4087765019
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2731277217
Short name T1806
Test name
Test status
Simulation time 39555399 ps
CPU time 0.64 seconds
Started May 16 02:53:31 PM PDT 24
Finished May 16 02:53:33 PM PDT 24
Peak memory 203624 kb
Host smart-4aa5a7e0-61d0-4c5d-8ee6-44033128e198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2731277217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2731277217
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4131581358
Short name T1777
Test name
Test status
Simulation time 74470294 ps
CPU time 1.06 seconds
Started May 16 02:53:30 PM PDT 24
Finished May 16 02:53:32 PM PDT 24
Peak memory 204188 kb
Host smart-ac8ad1c3-96fd-49ac-a922-818613d190a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4131581358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.4131581358
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3857844342
Short name T1814
Test name
Test status
Simulation time 119716354 ps
CPU time 1.69 seconds
Started May 16 02:53:35 PM PDT 24
Finished May 16 02:53:37 PM PDT 24
Peak memory 204276 kb
Host smart-4db09067-0431-4eb5-9587-fefbbfa37dcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3857844342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3857844342
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2381290620
Short name T1868
Test name
Test status
Simulation time 794037166 ps
CPU time 5.3 seconds
Started May 16 02:53:31 PM PDT 24
Finished May 16 02:53:38 PM PDT 24
Peak memory 204224 kb
Host smart-308a7c75-265f-489e-9aae-61009b204469
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2381290620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2381290620
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3832532590
Short name T257
Test name
Test status
Simulation time 96855099 ps
CPU time 2.03 seconds
Started May 16 02:52:30 PM PDT 24
Finished May 16 02:52:33 PM PDT 24
Peak memory 204172 kb
Host smart-2eddb803-8edb-49f7-8cb1-7641b39398ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3832532590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3832532590
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2297795293
Short name T265
Test name
Test status
Simulation time 607089532 ps
CPU time 4.38 seconds
Started May 16 02:52:32 PM PDT 24
Finished May 16 02:52:38 PM PDT 24
Peak memory 204236 kb
Host smart-6f01b11f-9137-4334-aba8-65628b9577ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2297795293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2297795293
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3537734772
Short name T256
Test name
Test status
Simulation time 74716184 ps
CPU time 0.91 seconds
Started May 16 02:52:30 PM PDT 24
Finished May 16 02:52:32 PM PDT 24
Peak memory 204112 kb
Host smart-d4c1fe5c-e290-40d8-b7aa-3e087ae1dc4f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3537734772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3537734772
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3936530814
Short name T249
Test name
Test status
Simulation time 97653206 ps
CPU time 1.34 seconds
Started May 16 02:52:34 PM PDT 24
Finished May 16 02:52:37 PM PDT 24
Peak memory 212456 kb
Host smart-45c00040-d8a0-4309-a6f4-74370a29182f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936530814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3936530814
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2882870463
Short name T1859
Test name
Test status
Simulation time 45493807 ps
CPU time 0.77 seconds
Started May 16 02:52:32 PM PDT 24
Finished May 16 02:52:34 PM PDT 24
Peak memory 204092 kb
Host smart-337fcd13-1400-4da9-99c4-21e60400a509
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2882870463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2882870463
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2502067880
Short name T1857
Test name
Test status
Simulation time 24570009 ps
CPU time 0.65 seconds
Started May 16 02:52:33 PM PDT 24
Finished May 16 02:52:35 PM PDT 24
Peak memory 203652 kb
Host smart-73b8da02-0c2c-40de-a6c1-111085ce1c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2502067880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2502067880
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3568677651
Short name T1833
Test name
Test status
Simulation time 95420259 ps
CPU time 1.43 seconds
Started May 16 02:52:29 PM PDT 24
Finished May 16 02:52:32 PM PDT 24
Peak memory 212448 kb
Host smart-fbfe6c39-dd7c-40c9-b841-664f334d3a25
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3568677651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3568677651
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1836694907
Short name T1811
Test name
Test status
Simulation time 471696314 ps
CPU time 4.27 seconds
Started May 16 02:52:30 PM PDT 24
Finished May 16 02:52:35 PM PDT 24
Peak memory 204200 kb
Host smart-c248992c-03a0-4c2d-a347-e5b4e5f92042
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1836694907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1836694907
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2547082148
Short name T1785
Test name
Test status
Simulation time 214216645 ps
CPU time 1.78 seconds
Started May 16 02:52:32 PM PDT 24
Finished May 16 02:52:34 PM PDT 24
Peak memory 204172 kb
Host smart-41517984-513e-45b7-af7d-110afca20596
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2547082148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2547082148
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2812557208
Short name T1781
Test name
Test status
Simulation time 300694717 ps
CPU time 2.97 seconds
Started May 16 02:52:33 PM PDT 24
Finished May 16 02:52:37 PM PDT 24
Peak memory 212460 kb
Host smart-9ea1125e-6a61-4581-b368-08688a1fe0dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2812557208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2812557208
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.651931866
Short name T290
Test name
Test status
Simulation time 26524256 ps
CPU time 0.67 seconds
Started May 16 02:53:42 PM PDT 24
Finished May 16 02:53:45 PM PDT 24
Peak memory 203688 kb
Host smart-9f0a098f-d346-437b-bcdd-b0155bfaf42b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=651931866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.651931866
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4159852781
Short name T1798
Test name
Test status
Simulation time 30127310 ps
CPU time 0.66 seconds
Started May 16 02:53:45 PM PDT 24
Finished May 16 02:53:46 PM PDT 24
Peak memory 203608 kb
Host smart-6d1ffe69-52e7-42b8-aca2-ad8da4007782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4159852781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4159852781
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1268454557
Short name T287
Test name
Test status
Simulation time 32034138 ps
CPU time 0.65 seconds
Started May 16 02:53:42 PM PDT 24
Finished May 16 02:53:44 PM PDT 24
Peak memory 203620 kb
Host smart-59a2505e-5cd0-4cc7-b39f-432414dc4870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1268454557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1268454557
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.423283853
Short name T285
Test name
Test status
Simulation time 32061835 ps
CPU time 0.66 seconds
Started May 16 02:53:44 PM PDT 24
Finished May 16 02:53:46 PM PDT 24
Peak memory 203656 kb
Host smart-d441307f-95d2-4fa1-a650-ccee83507930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=423283853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.423283853
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.942648965
Short name T1794
Test name
Test status
Simulation time 27175774 ps
CPU time 0.64 seconds
Started May 16 02:53:42 PM PDT 24
Finished May 16 02:53:45 PM PDT 24
Peak memory 203704 kb
Host smart-02ebe7f5-8b11-4b50-bb00-67fccb00ea05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=942648965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.942648965
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.528797614
Short name T1847
Test name
Test status
Simulation time 33697467 ps
CPU time 0.68 seconds
Started May 16 02:53:45 PM PDT 24
Finished May 16 02:53:46 PM PDT 24
Peak memory 203604 kb
Host smart-8a6d58b1-b36d-4db2-92e4-45e25d5a2c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=528797614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.528797614
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.839350904
Short name T1801
Test name
Test status
Simulation time 49167267 ps
CPU time 0.71 seconds
Started May 16 02:53:44 PM PDT 24
Finished May 16 02:53:46 PM PDT 24
Peak memory 203624 kb
Host smart-b6cdd726-2f6c-4392-92ad-b1d5353d0806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=839350904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.839350904
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1949584907
Short name T292
Test name
Test status
Simulation time 39685103 ps
CPU time 0.67 seconds
Started May 16 02:53:43 PM PDT 24
Finished May 16 02:53:46 PM PDT 24
Peak memory 203636 kb
Host smart-d3fb99c9-31fa-4ae2-9521-913a5e6d16f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1949584907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1949584907
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3179994919
Short name T1769
Test name
Test status
Simulation time 67608701 ps
CPU time 1.91 seconds
Started May 16 02:52:41 PM PDT 24
Finished May 16 02:52:44 PM PDT 24
Peak memory 204140 kb
Host smart-696cea46-a849-4b25-93c6-bdaff4629677
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3179994919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3179994919
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3808225420
Short name T1827
Test name
Test status
Simulation time 1682668151 ps
CPU time 9.14 seconds
Started May 16 02:52:39 PM PDT 24
Finished May 16 02:52:49 PM PDT 24
Peak memory 204220 kb
Host smart-56899931-e36a-420a-ac01-3f458818c2f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3808225420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3808225420
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3526890989
Short name T1826
Test name
Test status
Simulation time 162985316 ps
CPU time 1.88 seconds
Started May 16 02:52:40 PM PDT 24
Finished May 16 02:52:43 PM PDT 24
Peak memory 212480 kb
Host smart-870d16a5-5ef1-4a19-8736-1a90b7988ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526890989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3526890989
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3637192269
Short name T264
Test name
Test status
Simulation time 38998815 ps
CPU time 0.81 seconds
Started May 16 02:52:40 PM PDT 24
Finished May 16 02:52:42 PM PDT 24
Peak memory 204088 kb
Host smart-e99ad7f2-30f0-46a9-a315-72821032b8cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3637192269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3637192269
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4179136638
Short name T1834
Test name
Test status
Simulation time 34137304 ps
CPU time 0.68 seconds
Started May 16 02:52:41 PM PDT 24
Finished May 16 02:52:43 PM PDT 24
Peak memory 203644 kb
Host smart-f15f5929-f318-4a09-93c1-4520fa4d100c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4179136638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.4179136638
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2371593432
Short name T262
Test name
Test status
Simulation time 80131575 ps
CPU time 2.24 seconds
Started May 16 02:52:41 PM PDT 24
Finished May 16 02:52:44 PM PDT 24
Peak memory 212436 kb
Host smart-73ca52bf-6a98-4754-9783-79a6db5e8c90
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2371593432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2371593432
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.727252247
Short name T1796
Test name
Test status
Simulation time 385523292 ps
CPU time 2.76 seconds
Started May 16 02:52:41 PM PDT 24
Finished May 16 02:52:45 PM PDT 24
Peak memory 204212 kb
Host smart-c4ebf6a1-49af-4b3a-bc35-9fec597c3d2b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=727252247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.727252247
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.80058446
Short name T266
Test name
Test status
Simulation time 52807613 ps
CPU time 1.07 seconds
Started May 16 02:52:41 PM PDT 24
Finished May 16 02:52:43 PM PDT 24
Peak memory 204200 kb
Host smart-89b14ace-80b7-4ca0-8fd5-74b9422622a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=80058446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.80058446
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2389519777
Short name T1808
Test name
Test status
Simulation time 124711958 ps
CPU time 1.61 seconds
Started May 16 02:52:30 PM PDT 24
Finished May 16 02:52:32 PM PDT 24
Peak memory 204272 kb
Host smart-cd75d0a8-baaf-4ed1-8de9-d80fd5f7070d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2389519777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2389519777
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2308746580
Short name T1817
Test name
Test status
Simulation time 341942753 ps
CPU time 2.84 seconds
Started May 16 02:52:33 PM PDT 24
Finished May 16 02:52:37 PM PDT 24
Peak memory 204196 kb
Host smart-bd3824b1-5b9c-4b9d-a0c0-92f3e13d4515
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2308746580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2308746580
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3533922603
Short name T1813
Test name
Test status
Simulation time 47836682 ps
CPU time 0.7 seconds
Started May 16 02:53:43 PM PDT 24
Finished May 16 02:53:45 PM PDT 24
Peak memory 203672 kb
Host smart-0039996b-7c59-4deb-8fad-2910250296ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3533922603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3533922603
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2853186040
Short name T1802
Test name
Test status
Simulation time 29766364 ps
CPU time 0.66 seconds
Started May 16 02:53:42 PM PDT 24
Finished May 16 02:53:45 PM PDT 24
Peak memory 203688 kb
Host smart-8872f5ce-f480-453e-b3c3-3b38ae6651b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2853186040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2853186040
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3671425487
Short name T1822
Test name
Test status
Simulation time 54510718 ps
CPU time 0.69 seconds
Started May 16 02:53:42 PM PDT 24
Finished May 16 02:53:45 PM PDT 24
Peak memory 203656 kb
Host smart-161e2c54-fc00-42a5-890e-a480b8ffa859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3671425487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3671425487
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3717022596
Short name T1820
Test name
Test status
Simulation time 34742976 ps
CPU time 0.71 seconds
Started May 16 02:53:42 PM PDT 24
Finished May 16 02:53:44 PM PDT 24
Peak memory 203600 kb
Host smart-6af11c4b-6734-4256-b50a-e3f2cd3f7c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3717022596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3717022596
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1624891274
Short name T1856
Test name
Test status
Simulation time 45107966 ps
CPU time 0.7 seconds
Started May 16 02:53:48 PM PDT 24
Finished May 16 02:53:49 PM PDT 24
Peak memory 203612 kb
Host smart-4615c6f3-33fe-4ca2-af7c-00701603e07d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1624891274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1624891274
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1457462399
Short name T1797
Test name
Test status
Simulation time 28409755 ps
CPU time 0.65 seconds
Started May 16 02:53:47 PM PDT 24
Finished May 16 02:53:49 PM PDT 24
Peak memory 203616 kb
Host smart-7d945a25-2e4a-4d62-b865-8434b36253c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1457462399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1457462399
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.198511284
Short name T1803
Test name
Test status
Simulation time 30767430 ps
CPU time 0.69 seconds
Started May 16 02:53:53 PM PDT 24
Finished May 16 02:53:56 PM PDT 24
Peak memory 203644 kb
Host smart-ea9f1d82-9b5d-42a2-9ea5-8b0b0c8ee0c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=198511284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.198511284
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1027154909
Short name T1805
Test name
Test status
Simulation time 160564293 ps
CPU time 2.14 seconds
Started May 16 02:52:50 PM PDT 24
Finished May 16 02:52:53 PM PDT 24
Peak memory 204208 kb
Host smart-57b96395-71df-44d8-9a63-f1f116aad9b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1027154909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1027154909
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.456414559
Short name T1832
Test name
Test status
Simulation time 1990441653 ps
CPU time 10.53 seconds
Started May 16 02:52:53 PM PDT 24
Finished May 16 02:53:05 PM PDT 24
Peak memory 204228 kb
Host smart-87f8b505-83ac-4c2c-931f-ceb7f0448cae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=456414559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.456414559
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1465949982
Short name T68
Test name
Test status
Simulation time 100906254 ps
CPU time 0.97 seconds
Started May 16 02:52:52 PM PDT 24
Finished May 16 02:52:55 PM PDT 24
Peak memory 204140 kb
Host smart-3e141949-11dc-4a08-9b47-33463d0f0258
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1465949982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1465949982
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2285360379
Short name T283
Test name
Test status
Simulation time 98580461 ps
CPU time 1.18 seconds
Started May 16 02:52:50 PM PDT 24
Finished May 16 02:52:52 PM PDT 24
Peak memory 212460 kb
Host smart-3733eda7-f554-4907-994f-bf6e09370c6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285360379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2285360379
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3583420953
Short name T268
Test name
Test status
Simulation time 32165307 ps
CPU time 0.81 seconds
Started May 16 02:52:52 PM PDT 24
Finished May 16 02:52:54 PM PDT 24
Peak memory 204120 kb
Host smart-627976ba-77a3-42b1-9d8b-4ca6b6aa1e8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3583420953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3583420953
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2980184530
Short name T286
Test name
Test status
Simulation time 29915509 ps
CPU time 0.67 seconds
Started May 16 02:52:51 PM PDT 24
Finished May 16 02:52:52 PM PDT 24
Peak memory 203640 kb
Host smart-6c2dca08-4d83-4585-a188-cb503e17fb58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2980184530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2980184530
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3953154545
Short name T263
Test name
Test status
Simulation time 68953857 ps
CPU time 2.17 seconds
Started May 16 02:52:50 PM PDT 24
Finished May 16 02:52:53 PM PDT 24
Peak memory 212436 kb
Host smart-4b5210f5-a494-4df3-8167-2e2819c36c5c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3953154545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3953154545
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.50588435
Short name T1784
Test name
Test status
Simulation time 483398092 ps
CPU time 4.17 seconds
Started May 16 02:52:52 PM PDT 24
Finished May 16 02:52:58 PM PDT 24
Peak memory 204200 kb
Host smart-69adc4b2-7710-494e-bc91-3ad94a2e47d1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=50588435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.50588435
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4029391468
Short name T1846
Test name
Test status
Simulation time 44381165 ps
CPU time 1.05 seconds
Started May 16 02:52:50 PM PDT 24
Finished May 16 02:52:52 PM PDT 24
Peak memory 204264 kb
Host smart-22725c8a-8f8d-46ae-94b4-516c41ab098b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4029391468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.4029391468
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2281635705
Short name T1861
Test name
Test status
Simulation time 130038837 ps
CPU time 1.26 seconds
Started May 16 02:52:41 PM PDT 24
Finished May 16 02:52:43 PM PDT 24
Peak memory 204316 kb
Host smart-3bd5fa11-6962-4375-8b7f-57b39fa8b814
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2281635705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2281635705
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.180788743
Short name T298
Test name
Test status
Simulation time 308738479 ps
CPU time 2.91 seconds
Started May 16 02:52:41 PM PDT 24
Finished May 16 02:52:45 PM PDT 24
Peak memory 204188 kb
Host smart-a1a426b0-eb06-4aa5-8930-c1f45fd50b23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=180788743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.180788743
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3654525880
Short name T282
Test name
Test status
Simulation time 30837491 ps
CPU time 0.64 seconds
Started May 16 02:53:52 PM PDT 24
Finished May 16 02:53:53 PM PDT 24
Peak memory 203612 kb
Host smart-f0a886fe-080d-44b8-8f8a-6a3f86ba33cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3654525880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3654525880
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1377626167
Short name T82
Test name
Test status
Simulation time 34768696 ps
CPU time 0.64 seconds
Started May 16 02:53:53 PM PDT 24
Finished May 16 02:53:55 PM PDT 24
Peak memory 203628 kb
Host smart-fd4dbd53-ff04-4dcd-be8d-34077e1e6bbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1377626167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1377626167
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3498300612
Short name T1807
Test name
Test status
Simulation time 38100886 ps
CPU time 0.68 seconds
Started May 16 02:53:53 PM PDT 24
Finished May 16 02:53:54 PM PDT 24
Peak memory 203624 kb
Host smart-502b7797-33e0-41a0-a452-72f6c406f54e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3498300612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3498300612
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1371969730
Short name T1789
Test name
Test status
Simulation time 39714102 ps
CPU time 0.66 seconds
Started May 16 02:53:55 PM PDT 24
Finished May 16 02:53:58 PM PDT 24
Peak memory 203628 kb
Host smart-7ab0a68e-a7af-4713-bef6-edd825aa9988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1371969730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1371969730
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.165356197
Short name T81
Test name
Test status
Simulation time 31821739 ps
CPU time 0.66 seconds
Started May 16 02:53:53 PM PDT 24
Finished May 16 02:53:55 PM PDT 24
Peak memory 203604 kb
Host smart-a349ddc6-359d-405c-92e2-0d171fbe0200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=165356197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.165356197
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2815056052
Short name T281
Test name
Test status
Simulation time 33804177 ps
CPU time 0.67 seconds
Started May 16 02:53:53 PM PDT 24
Finished May 16 02:53:56 PM PDT 24
Peak memory 203824 kb
Host smart-f336b12d-a96a-4c27-b6f8-ed51d363ea94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2815056052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2815056052
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1217158184
Short name T1778
Test name
Test status
Simulation time 27597026 ps
CPU time 0.65 seconds
Started May 16 02:53:53 PM PDT 24
Finished May 16 02:53:55 PM PDT 24
Peak memory 203628 kb
Host smart-e70ff2bc-9adb-4695-9557-9913944d15be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1217158184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1217158184
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3683962503
Short name T291
Test name
Test status
Simulation time 30049977 ps
CPU time 0.65 seconds
Started May 16 02:53:53 PM PDT 24
Finished May 16 02:53:55 PM PDT 24
Peak memory 203644 kb
Host smart-9a55455d-e98c-453c-b255-a1e741f9c539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3683962503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3683962503
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1714033365
Short name T1836
Test name
Test status
Simulation time 28505668 ps
CPU time 0.69 seconds
Started May 16 02:53:54 PM PDT 24
Finished May 16 02:53:58 PM PDT 24
Peak memory 203652 kb
Host smart-b81142dd-336e-41ef-8a86-dee1023363f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1714033365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1714033365
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2892782645
Short name T1771
Test name
Test status
Simulation time 32405839 ps
CPU time 0.65 seconds
Started May 16 02:53:53 PM PDT 24
Finished May 16 02:53:55 PM PDT 24
Peak memory 203616 kb
Host smart-9cece89e-ff77-4953-8189-5dac975dbd2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2892782645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2892782645
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2164085933
Short name T1830
Test name
Test status
Simulation time 111305585 ps
CPU time 1.4 seconds
Started May 16 02:52:51 PM PDT 24
Finished May 16 02:52:54 PM PDT 24
Peak memory 212448 kb
Host smart-df0ec779-71cb-4695-85ce-11788eadff8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164085933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2164085933
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.140204715
Short name T1786
Test name
Test status
Simulation time 36627165 ps
CPU time 0.81 seconds
Started May 16 02:52:52 PM PDT 24
Finished May 16 02:52:54 PM PDT 24
Peak memory 204100 kb
Host smart-cde9fbca-5b83-4cb9-b92c-942e1f271fa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=140204715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.140204715
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1921383504
Short name T1860
Test name
Test status
Simulation time 27930302 ps
CPU time 0.66 seconds
Started May 16 02:52:51 PM PDT 24
Finished May 16 02:52:53 PM PDT 24
Peak memory 203656 kb
Host smart-2cbcaa5f-3c3e-46f5-a1b0-973bbe9512a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1921383504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1921383504
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1708096719
Short name T1855
Test name
Test status
Simulation time 54711064 ps
CPU time 1.02 seconds
Started May 16 02:52:53 PM PDT 24
Finished May 16 02:52:55 PM PDT 24
Peak memory 204220 kb
Host smart-df6239ca-b73b-4a59-8f00-da8aed5c42bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1708096719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1708096719
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.928189305
Short name T66
Test name
Test status
Simulation time 329859750 ps
CPU time 3.17 seconds
Started May 16 02:52:51 PM PDT 24
Finished May 16 02:52:56 PM PDT 24
Peak memory 212420 kb
Host smart-a03a78dd-33aa-412a-92a3-2f1c058e2e74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=928189305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.928189305
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2861267089
Short name T1800
Test name
Test status
Simulation time 73620226 ps
CPU time 1.73 seconds
Started May 16 02:53:01 PM PDT 24
Finished May 16 02:53:04 PM PDT 24
Peak memory 212456 kb
Host smart-4d62d23b-fb82-4153-8b6f-3b2bfab7f43e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861267089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2861267089
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3499095698
Short name T258
Test name
Test status
Simulation time 37918444 ps
CPU time 0.79 seconds
Started May 16 02:53:00 PM PDT 24
Finished May 16 02:53:02 PM PDT 24
Peak memory 204040 kb
Host smart-3f217265-5702-4a00-a089-8200c3b3bb15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3499095698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3499095698
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2081632882
Short name T1773
Test name
Test status
Simulation time 37942622 ps
CPU time 0.68 seconds
Started May 16 02:53:00 PM PDT 24
Finished May 16 02:53:02 PM PDT 24
Peak memory 203624 kb
Host smart-7426268a-a724-4bef-b353-2f45e1899a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2081632882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2081632882
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.845620498
Short name T1787
Test name
Test status
Simulation time 51971359 ps
CPU time 1.16 seconds
Started May 16 02:53:07 PM PDT 24
Finished May 16 02:53:08 PM PDT 24
Peak memory 204180 kb
Host smart-e05cba9c-5971-4fcd-84f6-c7a6a00d70f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=845620498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.845620498
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1948369602
Short name T245
Test name
Test status
Simulation time 98378026 ps
CPU time 3.19 seconds
Started May 16 02:52:51 PM PDT 24
Finished May 16 02:52:56 PM PDT 24
Peak memory 204324 kb
Host smart-639421d9-ff49-4a90-95c8-0f7230167390
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1948369602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1948369602
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1666256711
Short name T1831
Test name
Test status
Simulation time 363859330 ps
CPU time 2.78 seconds
Started May 16 02:52:50 PM PDT 24
Finished May 16 02:52:54 PM PDT 24
Peak memory 204188 kb
Host smart-2b3a96e0-dd37-447d-9575-74b1e21bce02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1666256711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1666256711
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.313410119
Short name T1851
Test name
Test status
Simulation time 82372784 ps
CPU time 1.38 seconds
Started May 16 02:53:02 PM PDT 24
Finished May 16 02:53:04 PM PDT 24
Peak memory 212444 kb
Host smart-b5e69111-caf8-4568-8feb-9b31eab5a698
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313410119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.313410119
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.236346374
Short name T259
Test name
Test status
Simulation time 59634095 ps
CPU time 0.91 seconds
Started May 16 02:53:03 PM PDT 24
Finished May 16 02:53:05 PM PDT 24
Peak memory 204100 kb
Host smart-2632dab0-8f79-41f2-bde5-88d60f5ed2a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=236346374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.236346374
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3598219636
Short name T288
Test name
Test status
Simulation time 82022123 ps
CPU time 0.77 seconds
Started May 16 02:53:02 PM PDT 24
Finished May 16 02:53:04 PM PDT 24
Peak memory 203688 kb
Host smart-7da966c6-b5e6-4a33-8b1f-8f79f75c94b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3598219636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3598219636
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1131911957
Short name T1776
Test name
Test status
Simulation time 80457314 ps
CPU time 1.15 seconds
Started May 16 02:53:01 PM PDT 24
Finished May 16 02:53:03 PM PDT 24
Peak memory 204180 kb
Host smart-02767743-4698-45a5-a109-856fee73f64b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1131911957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1131911957
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.724878360
Short name T1792
Test name
Test status
Simulation time 216429614 ps
CPU time 2.19 seconds
Started May 16 02:53:00 PM PDT 24
Finished May 16 02:53:03 PM PDT 24
Peak memory 204268 kb
Host smart-1cbc1485-c06f-4f1f-956f-18fc8f36de55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=724878360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.724878360
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3256039588
Short name T300
Test name
Test status
Simulation time 276166261 ps
CPU time 2.59 seconds
Started May 16 02:53:03 PM PDT 24
Finished May 16 02:53:06 PM PDT 24
Peak memory 204184 kb
Host smart-d27417d6-b29d-45dc-8a39-b13f0662caa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3256039588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3256039588
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.262309220
Short name T1770
Test name
Test status
Simulation time 67168457 ps
CPU time 1.69 seconds
Started May 16 02:53:02 PM PDT 24
Finished May 16 02:53:05 PM PDT 24
Peak memory 212444 kb
Host smart-f83e908a-be03-43a0-a286-0d0556bd7a71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262309220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.262309220
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1123260001
Short name T1788
Test name
Test status
Simulation time 42979105 ps
CPU time 0.8 seconds
Started May 16 02:53:00 PM PDT 24
Finished May 16 02:53:02 PM PDT 24
Peak memory 204108 kb
Host smart-83ee77c1-4b3f-4239-8fc9-de1f7fd0cb67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1123260001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1123260001
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2505154771
Short name T1825
Test name
Test status
Simulation time 33928984 ps
CPU time 0.7 seconds
Started May 16 02:53:00 PM PDT 24
Finished May 16 02:53:02 PM PDT 24
Peak memory 203624 kb
Host smart-984fcb4f-a127-42e6-86ba-43a2c444613a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2505154771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2505154771
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.991949723
Short name T1791
Test name
Test status
Simulation time 56709252 ps
CPU time 1.16 seconds
Started May 16 02:52:59 PM PDT 24
Finished May 16 02:53:01 PM PDT 24
Peak memory 204200 kb
Host smart-b2a42e88-dc80-4813-a8fb-361618df6f5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=991949723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.991949723
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2574421194
Short name T1816
Test name
Test status
Simulation time 114253729 ps
CPU time 3.1 seconds
Started May 16 02:53:02 PM PDT 24
Finished May 16 02:53:06 PM PDT 24
Peak memory 204264 kb
Host smart-e4499203-a26d-4294-980a-711a4722705c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2574421194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2574421194
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.123656907
Short name T276
Test name
Test status
Simulation time 644399172 ps
CPU time 4.5 seconds
Started May 16 02:53:02 PM PDT 24
Finished May 16 02:53:07 PM PDT 24
Peak memory 204204 kb
Host smart-ab73a337-cbe8-44a5-942a-d0c7c6769b53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=123656907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.123656907
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2177308088
Short name T116
Test name
Test status
Simulation time 56866407 ps
CPU time 1.84 seconds
Started May 16 02:53:10 PM PDT 24
Finished May 16 02:53:13 PM PDT 24
Peak memory 212436 kb
Host smart-d1057342-24b8-471f-90cd-6d171c93accf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177308088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2177308088
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4172585318
Short name T271
Test name
Test status
Simulation time 58922723 ps
CPU time 0.88 seconds
Started May 16 02:53:11 PM PDT 24
Finished May 16 02:53:14 PM PDT 24
Peak memory 204084 kb
Host smart-5a37e7b5-c16a-4bcc-a379-ccd4c0c93495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4172585318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4172585318
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.573436946
Short name T1812
Test name
Test status
Simulation time 55441080 ps
CPU time 0.7 seconds
Started May 16 02:53:11 PM PDT 24
Finished May 16 02:53:14 PM PDT 24
Peak memory 203628 kb
Host smart-4059ec82-2781-43d4-96b0-123cde6eda28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=573436946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.573436946
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2117976956
Short name T1848
Test name
Test status
Simulation time 79147646 ps
CPU time 1.14 seconds
Started May 16 02:53:11 PM PDT 24
Finished May 16 02:53:14 PM PDT 24
Peak memory 204224 kb
Host smart-708d97f1-4d78-47c4-a312-168682dd6e86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2117976956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2117976956
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2991491408
Short name T1823
Test name
Test status
Simulation time 232673439 ps
CPU time 3.04 seconds
Started May 16 02:53:10 PM PDT 24
Finished May 16 02:53:15 PM PDT 24
Peak memory 212464 kb
Host smart-25477290-fe90-4390-a661-79d5b672ab9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2991491408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2991491408
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.29718574
Short name T293
Test name
Test status
Simulation time 523835624 ps
CPU time 4.97 seconds
Started May 16 02:53:11 PM PDT 24
Finished May 16 02:53:18 PM PDT 24
Peak memory 204248 kb
Host smart-9eb2d2b0-0c85-49ae-9819-21bc82b81151
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=29718574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.29718574
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.1833562075
Short name T1172
Test name
Test status
Simulation time 8506144935 ps
CPU time 11.83 seconds
Started May 16 03:18:54 PM PDT 24
Finished May 16 03:19:12 PM PDT 24
Peak memory 204824 kb
Host smart-9395b2a3-a121-437b-8561-ab9a64dd07d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1833562075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.1833562075
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.3380382454
Short name T499
Test name
Test status
Simulation time 8384176656 ps
CPU time 11.68 seconds
Started May 16 03:18:56 PM PDT 24
Finished May 16 03:19:14 PM PDT 24
Peak memory 204808 kb
Host smart-f59c44bd-221a-427b-93f8-c44dd2ea8965
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3380382454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.3380382454
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.3913915684
Short name T346
Test name
Test status
Simulation time 8466728235 ps
CPU time 13.26 seconds
Started May 16 03:18:54 PM PDT 24
Finished May 16 03:19:14 PM PDT 24
Peak memory 204888 kb
Host smart-c00b56c8-bdc0-40a9-8026-7466dcc4ecb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39139
15684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.3913915684
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.600188880
Short name T370
Test name
Test status
Simulation time 8383639646 ps
CPU time 11.79 seconds
Started May 16 03:18:46 PM PDT 24
Finished May 16 03:19:03 PM PDT 24
Peak memory 204812 kb
Host smart-b4b2ea80-c710-48e2-8135-93a95d838542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60018
8880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.600188880
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.2928878643
Short name T1547
Test name
Test status
Simulation time 8373364858 ps
CPU time 12.4 seconds
Started May 16 03:18:43 PM PDT 24
Finished May 16 03:19:01 PM PDT 24
Peak memory 204672 kb
Host smart-6543936f-3917-43b6-a091-428e2dccece7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29288
78643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.2928878643
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.1467051071
Short name T1046
Test name
Test status
Simulation time 8861503975 ps
CPU time 13.24 seconds
Started May 16 03:18:43 PM PDT 24
Finished May 16 03:19:02 PM PDT 24
Peak memory 204924 kb
Host smart-6ba7a600-7b73-4112-bae7-a5f961ad64b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14670
51071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.1467051071
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.4283320814
Short name T469
Test name
Test status
Simulation time 8372488573 ps
CPU time 10.82 seconds
Started May 16 03:18:42 PM PDT 24
Finished May 16 03:18:58 PM PDT 24
Peak memory 204884 kb
Host smart-c28951ed-6d31-4725-a0fe-410d0aa4c2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42833
20814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.4283320814
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.449661376
Short name T329
Test name
Test status
Simulation time 8392406376 ps
CPU time 10.96 seconds
Started May 16 03:18:41 PM PDT 24
Finished May 16 03:18:57 PM PDT 24
Peak memory 204912 kb
Host smart-57382b8f-2aea-4e39-bd5d-eb88ea51fbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44966
1376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.449661376
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1240408283
Short name T507
Test name
Test status
Simulation time 9060628399 ps
CPU time 12.75 seconds
Started May 16 03:18:44 PM PDT 24
Finished May 16 03:19:03 PM PDT 24
Peak memory 204872 kb
Host smart-ffb97c9a-3d92-4789-b1b8-8339e3292568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12404
08283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1240408283
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.50067578
Short name T867
Test name
Test status
Simulation time 8405429045 ps
CPU time 12.22 seconds
Started May 16 03:18:42 PM PDT 24
Finished May 16 03:19:00 PM PDT 24
Peak memory 204780 kb
Host smart-1367e1ff-3591-404e-8d2a-12417f1cd995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50067
578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.50067578
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.606314464
Short name T684
Test name
Test status
Simulation time 8394369025 ps
CPU time 11.99 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:09 PM PDT 24
Peak memory 204884 kb
Host smart-417b2db9-39ac-4e14-beb3-14b027568e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60631
4464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.606314464
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3930925734
Short name T1652
Test name
Test status
Simulation time 8371764318 ps
CPU time 13.67 seconds
Started May 16 03:18:56 PM PDT 24
Finished May 16 03:19:16 PM PDT 24
Peak memory 204856 kb
Host smart-8ba3147c-82f8-4ff0-bf06-75a66f04a859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39309
25734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3930925734
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.593336822
Short name T155
Test name
Test status
Simulation time 8448170070 ps
CPU time 10.81 seconds
Started May 16 03:18:39 PM PDT 24
Finished May 16 03:18:55 PM PDT 24
Peak memory 204828 kb
Host smart-2c621366-bc0b-41ff-811c-3415e5faad24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59333
6822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.593336822
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.2199786443
Short name T999
Test name
Test status
Simulation time 8385566032 ps
CPU time 13.39 seconds
Started May 16 03:18:41 PM PDT 24
Finished May 16 03:19:00 PM PDT 24
Peak memory 204928 kb
Host smart-498decab-610e-4fd5-b4c8-351639ef726c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21997
86443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2199786443
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.32287715
Short name T408
Test name
Test status
Simulation time 11543953261 ps
CPU time 18.76 seconds
Started May 16 03:18:42 PM PDT 24
Finished May 16 03:19:07 PM PDT 24
Peak memory 204840 kb
Host smart-c49c9046-2360-40f3-a3b2-3104b8656b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32287
715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.32287715
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2904283684
Short name T1628
Test name
Test status
Simulation time 8415469127 ps
CPU time 11.18 seconds
Started May 16 03:18:42 PM PDT 24
Finished May 16 03:18:59 PM PDT 24
Peak memory 204824 kb
Host smart-c0ac8f80-01a6-491b-83c5-831872af7d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29042
83684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2904283684
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1498126335
Short name T387
Test name
Test status
Simulation time 8370988754 ps
CPU time 11.65 seconds
Started May 16 03:18:41 PM PDT 24
Finished May 16 03:18:58 PM PDT 24
Peak memory 204800 kb
Host smart-df1c57d4-0be6-4681-b01f-0b6f0a8c750c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14981
26335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1498126335
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.4181391756
Short name T140
Test name
Test status
Simulation time 8455180482 ps
CPU time 11.37 seconds
Started May 16 03:18:41 PM PDT 24
Finished May 16 03:18:57 PM PDT 24
Peak memory 204912 kb
Host smart-ab29c544-e486-4465-8959-4c1999a83d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41813
91756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.4181391756
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3484257911
Short name T555
Test name
Test status
Simulation time 8411889309 ps
CPU time 12.41 seconds
Started May 16 03:18:41 PM PDT 24
Finished May 16 03:18:59 PM PDT 24
Peak memory 204864 kb
Host smart-fe5faf34-dd50-4a74-9bb9-baf3ea2a72e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34842
57911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3484257911
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3376424254
Short name T1423
Test name
Test status
Simulation time 8391789222 ps
CPU time 11.37 seconds
Started May 16 03:18:42 PM PDT 24
Finished May 16 03:18:58 PM PDT 24
Peak memory 204868 kb
Host smart-3c1e7ae2-af2a-4d76-b335-9a5de0b36472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33764
24254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3376424254
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.669688774
Short name T1674
Test name
Test status
Simulation time 8413098253 ps
CPU time 13.67 seconds
Started May 16 03:18:42 PM PDT 24
Finished May 16 03:19:02 PM PDT 24
Peak memory 204932 kb
Host smart-7b341098-2610-4fe5-a899-6d3d2af949ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66968
8774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.669688774
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3873661887
Short name T1748
Test name
Test status
Simulation time 8419859974 ps
CPU time 10.77 seconds
Started May 16 03:18:49 PM PDT 24
Finished May 16 03:19:06 PM PDT 24
Peak memory 204872 kb
Host smart-efe91989-aa9f-4eb4-84b4-5b82f19ac878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38736
61887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3873661887
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1974014107
Short name T770
Test name
Test status
Simulation time 8445398976 ps
CPU time 10.91 seconds
Started May 16 03:18:48 PM PDT 24
Finished May 16 03:19:05 PM PDT 24
Peak memory 204752 kb
Host smart-35078967-009a-4a2f-aacf-855938efe030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19740
14107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1974014107
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.698271289
Short name T1677
Test name
Test status
Simulation time 8385836343 ps
CPU time 11.92 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:09 PM PDT 24
Peak memory 204744 kb
Host smart-d49e097b-8b0a-40a0-a7ea-19e4671cf3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69827
1289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.698271289
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1750040006
Short name T33
Test name
Test status
Simulation time 8369422780 ps
CPU time 12.41 seconds
Started May 16 03:18:54 PM PDT 24
Finished May 16 03:19:13 PM PDT 24
Peak memory 204828 kb
Host smart-a9409e8f-8bac-4d4d-9e58-f37937125ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17500
40006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1750040006
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.152651525
Short name T358
Test name
Test status
Simulation time 8374420764 ps
CPU time 13.35 seconds
Started May 16 03:18:51 PM PDT 24
Finished May 16 03:19:10 PM PDT 24
Peak memory 204824 kb
Host smart-22b82987-6ad8-491b-9f77-0f1b773231ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15265
1525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.152651525
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.4248697035
Short name T78
Test name
Test status
Simulation time 8454772091 ps
CPU time 11.65 seconds
Started May 16 03:18:48 PM PDT 24
Finished May 16 03:19:06 PM PDT 24
Peak memory 204724 kb
Host smart-f4a0b4f2-d84a-4b07-ad9d-f97e987f2951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42486
97035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.4248697035
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.2572156000
Short name T1465
Test name
Test status
Simulation time 8461025108 ps
CPU time 12.29 seconds
Started May 16 03:18:49 PM PDT 24
Finished May 16 03:19:07 PM PDT 24
Peak memory 204812 kb
Host smart-6df87963-4562-4afd-97c9-0ac11bd75a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25721
56000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.2572156000
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2396437008
Short name T336
Test name
Test status
Simulation time 8378805235 ps
CPU time 12.09 seconds
Started May 16 03:18:49 PM PDT 24
Finished May 16 03:19:07 PM PDT 24
Peak memory 204848 kb
Host smart-96ccdb97-e0f9-4dc7-94ce-dfeca9cb9731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23964
37008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2396437008
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.454696034
Short name T1229
Test name
Test status
Simulation time 8400599762 ps
CPU time 11.08 seconds
Started May 16 03:18:49 PM PDT 24
Finished May 16 03:19:06 PM PDT 24
Peak memory 204672 kb
Host smart-d56c1f3d-8084-4eda-aaa3-1272423c0022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45469
6034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.454696034
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1779959935
Short name T1613
Test name
Test status
Simulation time 8445203455 ps
CPU time 11.08 seconds
Started May 16 03:18:44 PM PDT 24
Finished May 16 03:19:01 PM PDT 24
Peak memory 204872 kb
Host smart-7f2efadf-4a08-4abe-8a7b-74655f3d83ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17799
59935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1779959935
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.259116828
Short name T1640
Test name
Test status
Simulation time 8468465618 ps
CPU time 11.63 seconds
Started May 16 03:18:47 PM PDT 24
Finished May 16 03:19:04 PM PDT 24
Peak memory 204888 kb
Host smart-8c85d609-2821-4c9f-a7cd-3ca5a647f0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25911
6828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.259116828
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.110842540
Short name T1470
Test name
Test status
Simulation time 8466241470 ps
CPU time 10.99 seconds
Started May 16 03:18:58 PM PDT 24
Finished May 16 03:19:15 PM PDT 24
Peak memory 204896 kb
Host smart-2ef1737c-fd9f-4e48-ae47-cd476735f95a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=110842540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.110842540
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.104582303
Short name T1007
Test name
Test status
Simulation time 8433635298 ps
CPU time 11.08 seconds
Started May 16 03:19:04 PM PDT 24
Finished May 16 03:19:20 PM PDT 24
Peak memory 204872 kb
Host smart-71636e94-2e72-44e9-9373-1d96732d2f2b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=104582303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.104582303
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.1260760939
Short name T1014
Test name
Test status
Simulation time 8398454818 ps
CPU time 14.48 seconds
Started May 16 03:18:58 PM PDT 24
Finished May 16 03:19:18 PM PDT 24
Peak memory 204868 kb
Host smart-030ae893-964f-4cdf-ad6f-5cf32ddd42e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12607
60939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.1260760939
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.6307945
Short name T1598
Test name
Test status
Simulation time 8392332651 ps
CPU time 11.51 seconds
Started May 16 03:18:49 PM PDT 24
Finished May 16 03:19:07 PM PDT 24
Peak memory 204944 kb
Host smart-192f3336-7947-4914-8a76-cf650d29b0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63079
45 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.6307945
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1563711714
Short name T55
Test name
Test status
Simulation time 8394943502 ps
CPU time 12.87 seconds
Started May 16 03:18:53 PM PDT 24
Finished May 16 03:19:11 PM PDT 24
Peak memory 204872 kb
Host smart-3ef1fa4e-b519-48d2-9230-54f986ddeb38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15637
11714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1563711714
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.4048581507
Short name T210
Test name
Test status
Simulation time 9153158208 ps
CPU time 13.58 seconds
Started May 16 03:18:53 PM PDT 24
Finished May 16 03:19:13 PM PDT 24
Peak memory 204824 kb
Host smart-52fcbb9c-150b-49b6-93b8-f3d4d3d142ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40485
81507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.4048581507
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1116212208
Short name T706
Test name
Test status
Simulation time 8369583970 ps
CPU time 12 seconds
Started May 16 03:18:54 PM PDT 24
Finished May 16 03:19:13 PM PDT 24
Peak memory 204864 kb
Host smart-f690e4e5-22c2-4340-a20e-d1171b7f9736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11162
12208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1116212208
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.264581502
Short name T518
Test name
Test status
Simulation time 8370033159 ps
CPU time 10.72 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:06 PM PDT 24
Peak memory 204896 kb
Host smart-56cd7338-d7a1-420d-8d83-a4536864a19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26458
1502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.264581502
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.382191825
Short name T603
Test name
Test status
Simulation time 9123386287 ps
CPU time 12.44 seconds
Started May 16 03:18:55 PM PDT 24
Finished May 16 03:19:14 PM PDT 24
Peak memory 204804 kb
Host smart-5f120599-575e-4cee-837b-a7106bd5919a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38219
1825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.382191825
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2413184351
Short name T1197
Test name
Test status
Simulation time 8426129506 ps
CPU time 12.46 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:08 PM PDT 24
Peak memory 204812 kb
Host smart-ef0c97c2-4078-47b7-a365-a3a7e7d50c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24131
84351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2413184351
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2908590486
Short name T1623
Test name
Test status
Simulation time 8437633477 ps
CPU time 13.33 seconds
Started May 16 03:18:57 PM PDT 24
Finished May 16 03:19:16 PM PDT 24
Peak memory 204928 kb
Host smart-87420adc-e897-4033-9c36-4275fa712035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29085
90486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2908590486
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2982200968
Short name T1629
Test name
Test status
Simulation time 8425631528 ps
CPU time 12.75 seconds
Started May 16 03:18:59 PM PDT 24
Finished May 16 03:19:17 PM PDT 24
Peak memory 204892 kb
Host smart-b2c75b7f-ebe2-4f04-93cf-e28a2a983a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29822
00968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2982200968
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1519271036
Short name T1573
Test name
Test status
Simulation time 8476643831 ps
CPU time 10.72 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:07 PM PDT 24
Peak memory 204892 kb
Host smart-4748d60b-fb93-46c5-b804-65c197268533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15192
71036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1519271036
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1700962934
Short name T1387
Test name
Test status
Simulation time 8423535637 ps
CPU time 12.41 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:09 PM PDT 24
Peak memory 204860 kb
Host smart-a75f9082-aa23-4d5e-83f1-8b8dd9557edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17009
62934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1700962934
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.840059476
Short name T1417
Test name
Test status
Simulation time 11549481183 ps
CPU time 14.63 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:11 PM PDT 24
Peak memory 204840 kb
Host smart-0e292acc-1aa7-442a-856a-c97ec91b2949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84005
9476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.840059476
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.279248656
Short name T902
Test name
Test status
Simulation time 8417422555 ps
CPU time 10.8 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:07 PM PDT 24
Peak memory 204796 kb
Host smart-16a3bc89-4d67-42c3-948e-12b31d6453f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27924
8656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.279248656
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.22862459
Short name T737
Test name
Test status
Simulation time 8374319624 ps
CPU time 11.69 seconds
Started May 16 03:18:52 PM PDT 24
Finished May 16 03:19:09 PM PDT 24
Peak memory 204816 kb
Host smart-81d2a90e-91b5-4827-b8dc-17172300ad87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.22862459
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.748195974
Short name T504
Test name
Test status
Simulation time 8441122627 ps
CPU time 11.87 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:09 PM PDT 24
Peak memory 204880 kb
Host smart-1b410625-8f3c-4102-b982-171cec343e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74819
5974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.748195974
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.939012030
Short name T912
Test name
Test status
Simulation time 8434186861 ps
CPU time 14.28 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:11 PM PDT 24
Peak memory 204848 kb
Host smart-0a5c5dd9-aca3-4996-946c-90fab8d51cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93901
2030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.939012030
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2014681892
Short name T755
Test name
Test status
Simulation time 8410403981 ps
CPU time 10.85 seconds
Started May 16 03:18:49 PM PDT 24
Finished May 16 03:19:06 PM PDT 24
Peak memory 204776 kb
Host smart-6d3a9b22-276e-42c9-813e-91aa8f9eb646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20146
81892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2014681892
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.2616461061
Short name T726
Test name
Test status
Simulation time 8422999762 ps
CPU time 11.66 seconds
Started May 16 03:18:59 PM PDT 24
Finished May 16 03:19:16 PM PDT 24
Peak memory 204776 kb
Host smart-c1be1d75-d122-4da5-9563-c369ce9f5f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26164
61061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.2616461061
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1281973320
Short name T1276
Test name
Test status
Simulation time 8391861251 ps
CPU time 12.39 seconds
Started May 16 03:18:56 PM PDT 24
Finished May 16 03:19:14 PM PDT 24
Peak memory 204816 kb
Host smart-e81ef92b-188f-4c72-b43c-48caa6094b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12819
73320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1281973320
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1294785625
Short name T1054
Test name
Test status
Simulation time 29623568164 ps
CPU time 68.18 seconds
Started May 16 03:18:51 PM PDT 24
Finished May 16 03:20:05 PM PDT 24
Peak memory 204840 kb
Host smart-18d2fcd7-8b95-4bac-a7ab-2eed90681492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12947
85625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1294785625
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2408617581
Short name T1469
Test name
Test status
Simulation time 8418650240 ps
CPU time 12 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:08 PM PDT 24
Peak memory 204820 kb
Host smart-7408a47a-2532-4b25-a11c-c4758336c208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24086
17581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2408617581
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2480298051
Short name T1460
Test name
Test status
Simulation time 8456491664 ps
CPU time 12.36 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:08 PM PDT 24
Peak memory 204896 kb
Host smart-a19acab0-2986-47ab-aa74-28f417af4e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24802
98051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2480298051
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1704570017
Short name T1025
Test name
Test status
Simulation time 8408384975 ps
CPU time 11.06 seconds
Started May 16 03:18:57 PM PDT 24
Finished May 16 03:19:14 PM PDT 24
Peak memory 204828 kb
Host smart-f0718667-67d4-436f-93c8-c050fe114dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17045
70017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1704570017
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3846615625
Short name T505
Test name
Test status
Simulation time 8366931588 ps
CPU time 12.63 seconds
Started May 16 03:18:53 PM PDT 24
Finished May 16 03:19:11 PM PDT 24
Peak memory 204892 kb
Host smart-10de76c8-5c37-477f-88b1-0ba166913b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38466
15625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3846615625
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1054759390
Short name T64
Test name
Test status
Simulation time 1001608315 ps
CPU time 1.69 seconds
Started May 16 03:19:04 PM PDT 24
Finished May 16 03:19:10 PM PDT 24
Peak memory 220480 kb
Host smart-54c4290f-a2f1-4f2f-be8e-cb6c3ac5b629
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1054759390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1054759390
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1617939259
Short name T172
Test name
Test status
Simulation time 8379889722 ps
CPU time 11.47 seconds
Started May 16 03:19:04 PM PDT 24
Finished May 16 03:19:20 PM PDT 24
Peak memory 204784 kb
Host smart-a4fc8dbc-3bce-4a78-b467-c1accecb5674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16179
39259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1617939259
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1157901160
Short name T881
Test name
Test status
Simulation time 8429094734 ps
CPU time 11.81 seconds
Started May 16 03:18:52 PM PDT 24
Finished May 16 03:19:09 PM PDT 24
Peak memory 204784 kb
Host smart-8305d12f-1f3d-4d24-a14d-d3e76f4a4429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11579
01160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1157901160
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3014056947
Short name T1420
Test name
Test status
Simulation time 8461309555 ps
CPU time 11.7 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:09 PM PDT 24
Peak memory 204880 kb
Host smart-5f7492b2-8d32-4af4-834e-754e7ad65501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30140
56947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3014056947
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1578953038
Short name T1180
Test name
Test status
Simulation time 8405279933 ps
CPU time 12.76 seconds
Started May 16 03:18:50 PM PDT 24
Finished May 16 03:19:10 PM PDT 24
Peak memory 204880 kb
Host smart-9e565773-60a2-4e76-87e9-443a2551e7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15789
53038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1578953038
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.3225493909
Short name T1090
Test name
Test status
Simulation time 8377393232 ps
CPU time 11.28 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:41 PM PDT 24
Peak memory 204684 kb
Host smart-32bcff6a-334e-4f76-9831-f9e1134140d0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3225493909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.3225493909
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.1329361804
Short name T934
Test name
Test status
Simulation time 8444511346 ps
CPU time 11.1 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:41 PM PDT 24
Peak memory 204856 kb
Host smart-923d7dee-eda1-4176-ba43-c9b62e830479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13293
61804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.1329361804
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.666734644
Short name T1736
Test name
Test status
Simulation time 8379117774 ps
CPU time 11.61 seconds
Started May 16 03:20:15 PM PDT 24
Finished May 16 03:20:32 PM PDT 24
Peak memory 204848 kb
Host smart-d2ea6c6d-64e3-4f1d-a7aa-c75061c8e557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66673
4644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.666734644
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3377844542
Short name T1189
Test name
Test status
Simulation time 9555844314 ps
CPU time 13.86 seconds
Started May 16 03:20:18 PM PDT 24
Finished May 16 03:20:37 PM PDT 24
Peak memory 204828 kb
Host smart-8108940e-66ac-49d7-a8d4-490150a0dba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33778
44542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3377844542
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.939347756
Short name T664
Test name
Test status
Simulation time 8377638863 ps
CPU time 13.66 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:44 PM PDT 24
Peak memory 204872 kb
Host smart-2ff20f75-72e1-4563-9642-a5625c9d362f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93934
7756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.939347756
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1578537234
Short name T1297
Test name
Test status
Simulation time 8392489240 ps
CPU time 11.34 seconds
Started May 16 03:20:16 PM PDT 24
Finished May 16 03:20:33 PM PDT 24
Peak memory 204928 kb
Host smart-e64b86f4-3b28-4065-8357-694c223cbd57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15785
37234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1578537234
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3560877890
Short name T874
Test name
Test status
Simulation time 8621421637 ps
CPU time 14.41 seconds
Started May 16 03:20:15 PM PDT 24
Finished May 16 03:20:35 PM PDT 24
Peak memory 204836 kb
Host smart-d7c1518e-c091-4856-b438-cc6662d45326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35608
77890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3560877890
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.925063810
Short name T375
Test name
Test status
Simulation time 8427146552 ps
CPU time 13.47 seconds
Started May 16 03:20:26 PM PDT 24
Finished May 16 03:20:45 PM PDT 24
Peak memory 204844 kb
Host smart-367b16e5-2d6a-479f-b43a-c95dc4ad3698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92506
3810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.925063810
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2832418815
Short name T49
Test name
Test status
Simulation time 8371233537 ps
CPU time 11.08 seconds
Started May 16 03:20:30 PM PDT 24
Finished May 16 03:20:47 PM PDT 24
Peak memory 204856 kb
Host smart-4ba9b2cf-61b4-4d8b-b578-4cf4c1c32366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28324
18815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2832418815
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2998405048
Short name T320
Test name
Test status
Simulation time 8549608762 ps
CPU time 12.73 seconds
Started May 16 03:20:18 PM PDT 24
Finished May 16 03:20:36 PM PDT 24
Peak memory 204888 kb
Host smart-58e4dc85-e9ff-4f9a-8ce4-257474650e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29984
05048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2998405048
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1107105906
Short name T1313
Test name
Test status
Simulation time 8426652031 ps
CPU time 11.39 seconds
Started May 16 03:20:19 PM PDT 24
Finished May 16 03:20:35 PM PDT 24
Peak memory 204908 kb
Host smart-5b6eb3ba-8159-4110-8f5f-abb82918e558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11071
05906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1107105906
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.2322254520
Short name T631
Test name
Test status
Simulation time 11533317063 ps
CPU time 14.68 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:45 PM PDT 24
Peak memory 204764 kb
Host smart-06972e27-e510-4ad7-8ec0-3c82b3ffd25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23222
54520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.2322254520
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1411887804
Short name T1034
Test name
Test status
Simulation time 8434666584 ps
CPU time 11.02 seconds
Started May 16 03:20:24 PM PDT 24
Finished May 16 03:20:39 PM PDT 24
Peak memory 204756 kb
Host smart-1322c056-689c-42e4-bdcc-37bc9dd756ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14118
87804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1411887804
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.4047013494
Short name T852
Test name
Test status
Simulation time 8371117448 ps
CPU time 10.96 seconds
Started May 16 03:20:24 PM PDT 24
Finished May 16 03:20:40 PM PDT 24
Peak memory 204736 kb
Host smart-61f23a21-5a7f-4c19-ba90-7d333ebf3e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40470
13494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.4047013494
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.501543670
Short name T559
Test name
Test status
Simulation time 8415596657 ps
CPU time 12.26 seconds
Started May 16 03:20:24 PM PDT 24
Finished May 16 03:20:40 PM PDT 24
Peak memory 204944 kb
Host smart-52d07fbc-2d48-426b-8200-01e8189899f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50154
3670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.501543670
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.595965181
Short name T515
Test name
Test status
Simulation time 8463754262 ps
CPU time 12.44 seconds
Started May 16 03:20:24 PM PDT 24
Finished May 16 03:20:42 PM PDT 24
Peak memory 204756 kb
Host smart-822cea04-2fa4-4bd6-9da5-542a6dfbc43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59596
5181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.595965181
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2786519834
Short name T1279
Test name
Test status
Simulation time 8417649721 ps
CPU time 13.4 seconds
Started May 16 03:20:26 PM PDT 24
Finished May 16 03:20:45 PM PDT 24
Peak memory 204884 kb
Host smart-bed85a39-8023-46e0-8ea0-621edb30d0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27865
19834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2786519834
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.765089946
Short name T1409
Test name
Test status
Simulation time 8426928509 ps
CPU time 10.94 seconds
Started May 16 03:20:24 PM PDT 24
Finished May 16 03:20:40 PM PDT 24
Peak memory 204884 kb
Host smart-fc263bbb-b3d3-4d7e-9b19-94303cb1fb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76508
9946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.765089946
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.442105740
Short name T1084
Test name
Test status
Simulation time 8399088877 ps
CPU time 13.84 seconds
Started May 16 03:20:27 PM PDT 24
Finished May 16 03:20:46 PM PDT 24
Peak memory 204696 kb
Host smart-01dd9cee-9bfe-449c-a362-5ccb46e1d7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44210
5740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.442105740
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3149528426
Short name T671
Test name
Test status
Simulation time 8370378871 ps
CPU time 10.79 seconds
Started May 16 03:20:27 PM PDT 24
Finished May 16 03:20:44 PM PDT 24
Peak memory 204692 kb
Host smart-b3515993-67ed-45b6-bba8-b2555d0b1c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31495
28426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3149528426
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.4215371944
Short name T880
Test name
Test status
Simulation time 8368223534 ps
CPU time 12.29 seconds
Started May 16 03:20:27 PM PDT 24
Finished May 16 03:20:45 PM PDT 24
Peak memory 204780 kb
Host smart-7b3809fe-9746-4fe0-9c1c-614cd12dd943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42153
71944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.4215371944
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1878378113
Short name T1699
Test name
Test status
Simulation time 25102026567 ps
CPU time 45.64 seconds
Started May 16 03:20:26 PM PDT 24
Finished May 16 03:21:17 PM PDT 24
Peak memory 204784 kb
Host smart-b7a254ab-af8e-44a8-bac6-01ea1202d953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18783
78113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1878378113
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.945903297
Short name T376
Test name
Test status
Simulation time 8376207958 ps
CPU time 11.67 seconds
Started May 16 03:20:23 PM PDT 24
Finished May 16 03:20:39 PM PDT 24
Peak memory 204840 kb
Host smart-14602009-d876-4c7f-909a-ea8169e62b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94590
3297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.945903297
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1787309053
Short name T1049
Test name
Test status
Simulation time 8465891296 ps
CPU time 11.48 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:42 PM PDT 24
Peak memory 204852 kb
Host smart-d73abfb9-7497-4646-a08f-893855a1ecf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17873
09053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1787309053
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.1957622961
Short name T1560
Test name
Test status
Simulation time 8422538504 ps
CPU time 12.26 seconds
Started May 16 03:20:26 PM PDT 24
Finished May 16 03:20:43 PM PDT 24
Peak memory 204832 kb
Host smart-e75edee7-fd0e-47b3-aaf3-1b50cf791e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19576
22961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.1957622961
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1339104058
Short name T1752
Test name
Test status
Simulation time 8368812104 ps
CPU time 12.37 seconds
Started May 16 03:20:23 PM PDT 24
Finished May 16 03:20:39 PM PDT 24
Peak memory 204764 kb
Host smart-b95e5ac6-4763-462f-9bee-8c2ad0e1ef79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13391
04058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1339104058
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3548006254
Short name T179
Test name
Test status
Simulation time 8372380213 ps
CPU time 12.59 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:43 PM PDT 24
Peak memory 204900 kb
Host smart-f13d68a8-d6ee-419c-ad3f-40d8de9f44cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35480
06254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3548006254
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.961809095
Short name T104
Test name
Test status
Simulation time 8399313450 ps
CPU time 11.89 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:42 PM PDT 24
Peak memory 204880 kb
Host smart-a7c4d895-1598-434f-81e4-0174b3e8ef97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96180
9095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.961809095
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2249744337
Short name T997
Test name
Test status
Simulation time 8410930915 ps
CPU time 10.72 seconds
Started May 16 03:20:19 PM PDT 24
Finished May 16 03:20:34 PM PDT 24
Peak memory 204852 kb
Host smart-504cf02d-3003-423e-be82-a3c69d6b4512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22497
44337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2249744337
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1190452103
Short name T301
Test name
Test status
Simulation time 8382190335 ps
CPU time 11.38 seconds
Started May 16 03:20:24 PM PDT 24
Finished May 16 03:20:40 PM PDT 24
Peak memory 204776 kb
Host smart-b80f41fb-4e7d-46ae-866b-1e3877f01bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11904
52103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1190452103
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.572204760
Short name T1043
Test name
Test status
Simulation time 8397605368 ps
CPU time 12.15 seconds
Started May 16 03:20:30 PM PDT 24
Finished May 16 03:20:48 PM PDT 24
Peak memory 204888 kb
Host smart-35329734-9a67-4414-9130-0e80434f6bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57220
4760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.572204760
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.4188317027
Short name T1245
Test name
Test status
Simulation time 8463987012 ps
CPU time 12.67 seconds
Started May 16 03:20:33 PM PDT 24
Finished May 16 03:20:53 PM PDT 24
Peak memory 204904 kb
Host smart-6db1358e-7211-4c1d-8a6b-35b90ac252a5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4188317027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.4188317027
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.565207984
Short name T1260
Test name
Test status
Simulation time 8376051325 ps
CPU time 12.53 seconds
Started May 16 03:20:31 PM PDT 24
Finished May 16 03:20:50 PM PDT 24
Peak memory 204844 kb
Host smart-75488652-b2b9-42d9-90c0-7feb0a1655e9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=565207984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.565207984
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.575951755
Short name T159
Test name
Test status
Simulation time 8412707963 ps
CPU time 12.02 seconds
Started May 16 03:20:34 PM PDT 24
Finished May 16 03:20:53 PM PDT 24
Peak memory 204892 kb
Host smart-c9534d95-128e-46dd-be99-62b7b36bdb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57595
1755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.575951755
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.651627127
Short name T1586
Test name
Test status
Simulation time 8385245662 ps
CPU time 11.28 seconds
Started May 16 03:20:27 PM PDT 24
Finished May 16 03:20:44 PM PDT 24
Peak memory 204852 kb
Host smart-2119b435-fcef-4ee7-8ab4-acb56c650566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65162
7127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.651627127
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2849794926
Short name T909
Test name
Test status
Simulation time 8389042347 ps
CPU time 12.26 seconds
Started May 16 03:20:23 PM PDT 24
Finished May 16 03:20:40 PM PDT 24
Peak memory 204776 kb
Host smart-2ca6c15e-ffdc-430e-a5f8-f5113e43b6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28497
94926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2849794926
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.4231025061
Short name T1353
Test name
Test status
Simulation time 8477878185 ps
CPU time 14.06 seconds
Started May 16 03:20:30 PM PDT 24
Finished May 16 03:20:50 PM PDT 24
Peak memory 204872 kb
Host smart-f8c66415-6a9d-473a-8d86-652e5ed22068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42310
25061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.4231025061
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1095977434
Short name T1490
Test name
Test status
Simulation time 8381678419 ps
CPU time 11.99 seconds
Started May 16 03:20:28 PM PDT 24
Finished May 16 03:20:45 PM PDT 24
Peak memory 204768 kb
Host smart-d5b96bd1-dd90-45ec-a981-23c0cbea5f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10959
77434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1095977434
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3118313276
Short name T1077
Test name
Test status
Simulation time 8376862605 ps
CPU time 13.54 seconds
Started May 16 03:20:28 PM PDT 24
Finished May 16 03:20:47 PM PDT 24
Peak memory 204828 kb
Host smart-a90c2c65-7e3b-4d16-be7c-88c88dbcb8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31183
13276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3118313276
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.118257506
Short name T843
Test name
Test status
Simulation time 8472766201 ps
CPU time 13.5 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:44 PM PDT 24
Peak memory 204868 kb
Host smart-6abfeca0-f302-4100-916c-28576beef446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11825
7506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.118257506
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1927420761
Short name T1004
Test name
Test status
Simulation time 8480528923 ps
CPU time 11.3 seconds
Started May 16 03:20:35 PM PDT 24
Finished May 16 03:20:53 PM PDT 24
Peak memory 204952 kb
Host smart-426c0aca-3068-4155-881f-0b03526cf3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19274
20761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1927420761
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3085923524
Short name T1768
Test name
Test status
Simulation time 8395006274 ps
CPU time 11.62 seconds
Started May 16 03:20:31 PM PDT 24
Finished May 16 03:20:50 PM PDT 24
Peak memory 204792 kb
Host smart-622d194a-553e-41c5-98cd-51c368168db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30859
23524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3085923524
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.336034942
Short name T1064
Test name
Test status
Simulation time 8436576811 ps
CPU time 11.88 seconds
Started May 16 03:20:26 PM PDT 24
Finished May 16 03:20:43 PM PDT 24
Peak memory 204836 kb
Host smart-276e7f7b-873f-4db1-af42-621e6d73bc7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33603
4942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.336034942
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3357481239
Short name T454
Test name
Test status
Simulation time 8407888450 ps
CPU time 11.61 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:42 PM PDT 24
Peak memory 204924 kb
Host smart-97327e02-baaa-4176-a1c1-d543fe02caa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33574
81239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3357481239
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.3821244925
Short name T691
Test name
Test status
Simulation time 11503284703 ps
CPU time 14.47 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:44 PM PDT 24
Peak memory 204896 kb
Host smart-fe233e12-d053-41e4-838e-0eecad370eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38212
44925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3821244925
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.704699392
Short name T872
Test name
Test status
Simulation time 8412542032 ps
CPU time 13.19 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:43 PM PDT 24
Peak memory 204840 kb
Host smart-d787787f-7ffd-4bf1-a4ea-3d5b50b7b472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70469
9392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.704699392
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.934497267
Short name T1329
Test name
Test status
Simulation time 8368177945 ps
CPU time 11.25 seconds
Started May 16 03:20:27 PM PDT 24
Finished May 16 03:20:43 PM PDT 24
Peak memory 204732 kb
Host smart-131b4c4c-7e73-488c-9dc6-21fa8384eacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93449
7267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.934497267
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1263648520
Short name T566
Test name
Test status
Simulation time 8454654771 ps
CPU time 12.07 seconds
Started May 16 03:20:32 PM PDT 24
Finished May 16 03:20:51 PM PDT 24
Peak memory 204848 kb
Host smart-66d51362-e480-4901-b238-3d32584fef15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12636
48520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1263648520
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3501853919
Short name T705
Test name
Test status
Simulation time 8415538116 ps
CPU time 12.61 seconds
Started May 16 03:20:31 PM PDT 24
Finished May 16 03:20:50 PM PDT 24
Peak memory 204808 kb
Host smart-b7e36b18-2823-45a0-89b1-ad2c1a3b670f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35018
53919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3501853919
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1916534175
Short name T1062
Test name
Test status
Simulation time 8402589525 ps
CPU time 11.02 seconds
Started May 16 03:20:38 PM PDT 24
Finished May 16 03:20:55 PM PDT 24
Peak memory 204864 kb
Host smart-c48cfbdd-c6dc-41e6-80e4-cd6392fca45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19165
34175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1916534175
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.1641150069
Short name T841
Test name
Test status
Simulation time 8372452680 ps
CPU time 11.02 seconds
Started May 16 03:20:35 PM PDT 24
Finished May 16 03:20:52 PM PDT 24
Peak memory 204904 kb
Host smart-bb0d27ac-94b8-48a0-a8d0-246380addbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16411
50069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.1641150069
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2722038143
Short name T1696
Test name
Test status
Simulation time 8379040736 ps
CPU time 11.4 seconds
Started May 16 03:20:33 PM PDT 24
Finished May 16 03:20:52 PM PDT 24
Peak memory 204792 kb
Host smart-0e0161af-16e2-4fc0-ba39-fd49ead52ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27220
38143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2722038143
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1132639564
Short name T12
Test name
Test status
Simulation time 8389596378 ps
CPU time 12.02 seconds
Started May 16 03:20:32 PM PDT 24
Finished May 16 03:20:51 PM PDT 24
Peak memory 204820 kb
Host smart-e7352446-521b-4478-829f-9a67bc8b3bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11326
39564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1132639564
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1370357918
Short name T1095
Test name
Test status
Simulation time 15701971757 ps
CPU time 29.71 seconds
Started May 16 03:20:34 PM PDT 24
Finished May 16 03:21:11 PM PDT 24
Peak memory 204804 kb
Host smart-43e8fb81-64ec-4de7-9e5d-15a86023962b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13703
57918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1370357918
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2302958072
Short name T922
Test name
Test status
Simulation time 8396151366 ps
CPU time 11.56 seconds
Started May 16 03:20:34 PM PDT 24
Finished May 16 03:20:52 PM PDT 24
Peak memory 204888 kb
Host smart-d7eb1b23-a93a-4d58-9fb7-a767f9a29d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23029
58072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2302958072
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2914434150
Short name T1735
Test name
Test status
Simulation time 8433940495 ps
CPU time 13.01 seconds
Started May 16 03:20:32 PM PDT 24
Finished May 16 03:20:52 PM PDT 24
Peak memory 204888 kb
Host smart-4b76d7d7-2b7b-4b12-91ed-ad2721e14a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29144
34150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2914434150
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.2212554303
Short name T1103
Test name
Test status
Simulation time 8405740344 ps
CPU time 10.75 seconds
Started May 16 03:20:32 PM PDT 24
Finished May 16 03:20:50 PM PDT 24
Peak memory 204848 kb
Host smart-9f0c96b8-f56b-49f4-8d58-79c3faefb713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22125
54303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.2212554303
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.61561667
Short name T743
Test name
Test status
Simulation time 8411292319 ps
CPU time 11.17 seconds
Started May 16 03:20:36 PM PDT 24
Finished May 16 03:20:54 PM PDT 24
Peak memory 204856 kb
Host smart-836f7041-7c9d-43bf-a974-8858cb2d9341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61561
667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.61561667
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2462602560
Short name T1656
Test name
Test status
Simulation time 8375186450 ps
CPU time 13.24 seconds
Started May 16 03:20:34 PM PDT 24
Finished May 16 03:20:54 PM PDT 24
Peak memory 204800 kb
Host smart-aa7193c0-32c5-44f2-8a7c-21ca636408d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24626
02560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2462602560
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.321251986
Short name T796
Test name
Test status
Simulation time 8384134802 ps
CPU time 11.28 seconds
Started May 16 03:20:33 PM PDT 24
Finished May 16 03:20:51 PM PDT 24
Peak memory 204888 kb
Host smart-1cf8119d-0bda-453b-b23e-986b5f60e0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32125
1986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.321251986
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.829790167
Short name T464
Test name
Test status
Simulation time 8440949996 ps
CPU time 11.28 seconds
Started May 16 03:20:25 PM PDT 24
Finished May 16 03:20:41 PM PDT 24
Peak memory 204812 kb
Host smart-e034b5c7-5ecd-48aa-8ada-1e987f52a21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82979
0167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.829790167
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2774668959
Short name T1286
Test name
Test status
Simulation time 8416430648 ps
CPU time 11.51 seconds
Started May 16 03:20:31 PM PDT 24
Finished May 16 03:20:50 PM PDT 24
Peak memory 204872 kb
Host smart-de2c953e-f075-4f62-94eb-f73e90518a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27746
68959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2774668959
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2001448527
Short name T1400
Test name
Test status
Simulation time 8419459479 ps
CPU time 12.44 seconds
Started May 16 03:20:35 PM PDT 24
Finished May 16 03:20:54 PM PDT 24
Peak memory 204988 kb
Host smart-a5e196c3-b21a-4a54-8f86-92eb447a2a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20014
48527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2001448527
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.691612344
Short name T1096
Test name
Test status
Simulation time 8467665319 ps
CPU time 13.74 seconds
Started May 16 03:20:43 PM PDT 24
Finished May 16 03:21:02 PM PDT 24
Peak memory 204908 kb
Host smart-1f903351-c8fa-4aec-b5ff-19405684d106
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=691612344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.691612344
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.81594051
Short name T25
Test name
Test status
Simulation time 8402627327 ps
CPU time 13.91 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:03 PM PDT 24
Peak memory 204844 kb
Host smart-a60a621f-a40c-4a0e-ac39-cc22dca665a1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=81594051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.81594051
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.4057295250
Short name T498
Test name
Test status
Simulation time 8427600172 ps
CPU time 11.67 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:01 PM PDT 24
Peak memory 204880 kb
Host smart-166cef7a-ca71-4f3f-ab5f-28b0a8088a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40572
95250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.4057295250
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3381746638
Short name T1151
Test name
Test status
Simulation time 8398668493 ps
CPU time 12.47 seconds
Started May 16 03:20:37 PM PDT 24
Finished May 16 03:20:56 PM PDT 24
Peak memory 204904 kb
Host smart-bf3ab677-f6d2-4506-9862-cf6f95e29a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33817
46638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3381746638
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.839519548
Short name T1324
Test name
Test status
Simulation time 8377041600 ps
CPU time 12.1 seconds
Started May 16 03:20:32 PM PDT 24
Finished May 16 03:20:51 PM PDT 24
Peak memory 204688 kb
Host smart-d050f1e9-61f0-490e-8975-18b2fcdd2f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83951
9548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.839519548
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.4211088610
Short name T17
Test name
Test status
Simulation time 8622507309 ps
CPU time 11.7 seconds
Started May 16 03:20:32 PM PDT 24
Finished May 16 03:20:51 PM PDT 24
Peak memory 204936 kb
Host smart-eaee6638-92bd-4144-bfda-280b6ac0050b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42110
88610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.4211088610
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3693174288
Short name T8
Test name
Test status
Simulation time 8404796047 ps
CPU time 11.28 seconds
Started May 16 03:20:45 PM PDT 24
Finished May 16 03:21:02 PM PDT 24
Peak memory 204764 kb
Host smart-d3a7551f-58ae-4678-bfde-c07929282a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36931
74288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3693174288
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.407978772
Short name T925
Test name
Test status
Simulation time 8393344287 ps
CPU time 11.37 seconds
Started May 16 03:20:37 PM PDT 24
Finished May 16 03:20:55 PM PDT 24
Peak memory 204884 kb
Host smart-70c9e0e8-49e4-4db7-9587-4062d6aae9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40797
8772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.407978772
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2142966887
Short name T581
Test name
Test status
Simulation time 9070640018 ps
CPU time 12.43 seconds
Started May 16 03:20:37 PM PDT 24
Finished May 16 03:20:56 PM PDT 24
Peak memory 204912 kb
Host smart-8d01cac0-e41c-4b02-9682-7abf745edeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21429
66887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2142966887
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.429040526
Short name T1564
Test name
Test status
Simulation time 8615430977 ps
CPU time 14.66 seconds
Started May 16 03:20:33 PM PDT 24
Finished May 16 03:20:54 PM PDT 24
Peak memory 204884 kb
Host smart-c661b001-fbba-4adc-aa31-b383e789ea31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42904
0526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.429040526
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1556018478
Short name T590
Test name
Test status
Simulation time 8424291401 ps
CPU time 12.29 seconds
Started May 16 03:20:45 PM PDT 24
Finished May 16 03:21:03 PM PDT 24
Peak memory 204748 kb
Host smart-a16564ab-2046-4e1b-b1c7-c383ade88961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15560
18478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1556018478
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.448746430
Short name T614
Test name
Test status
Simulation time 8371435551 ps
CPU time 12.43 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:02 PM PDT 24
Peak memory 204836 kb
Host smart-0801ba27-1bd5-46d7-a047-0b52495c4c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44874
6430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.448746430
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2482355980
Short name T995
Test name
Test status
Simulation time 8465710789 ps
CPU time 13.25 seconds
Started May 16 03:20:32 PM PDT 24
Finished May 16 03:20:52 PM PDT 24
Peak memory 204876 kb
Host smart-a4764041-8a2b-4bd4-a293-f29780d461fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24823
55980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2482355980
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.383275523
Short name T27
Test name
Test status
Simulation time 8400931431 ps
CPU time 12.37 seconds
Started May 16 03:20:47 PM PDT 24
Finished May 16 03:21:04 PM PDT 24
Peak memory 204832 kb
Host smart-856d8c51-2219-41d7-94e1-97185dc376c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38327
5523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.383275523
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.149185038
Short name T1723
Test name
Test status
Simulation time 11554426259 ps
CPU time 15.91 seconds
Started May 16 03:20:47 PM PDT 24
Finished May 16 03:21:08 PM PDT 24
Peak memory 204816 kb
Host smart-abb224aa-c65d-4b74-a713-b2b749729cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14918
5038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.149185038
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.614769625
Short name T111
Test name
Test status
Simulation time 8425609050 ps
CPU time 11.22 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:01 PM PDT 24
Peak memory 204808 kb
Host smart-7173cbb9-9a3e-45d2-87e6-ff9512b670e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61476
9625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.614769625
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1931738788
Short name T639
Test name
Test status
Simulation time 8370446781 ps
CPU time 13.22 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:03 PM PDT 24
Peak memory 204836 kb
Host smart-8543c880-76bf-4d55-83db-eb0794f7879a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19317
38788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1931738788
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3671892183
Short name T1219
Test name
Test status
Simulation time 8406663657 ps
CPU time 14.14 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:04 PM PDT 24
Peak memory 204840 kb
Host smart-559c6231-b4c6-47a8-83ac-f37113d07b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36718
92183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3671892183
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.530165257
Short name T1695
Test name
Test status
Simulation time 8401129562 ps
CPU time 11.41 seconds
Started May 16 03:20:48 PM PDT 24
Finished May 16 03:21:04 PM PDT 24
Peak memory 204828 kb
Host smart-dc4d9d7f-6530-408b-af20-b07f496ff524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53016
5257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.530165257
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2137604184
Short name T666
Test name
Test status
Simulation time 8385044470 ps
CPU time 10.67 seconds
Started May 16 03:20:46 PM PDT 24
Finished May 16 03:21:02 PM PDT 24
Peak memory 204796 kb
Host smart-8e8e25e1-19a6-416b-b474-edc4053538ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21376
04184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2137604184
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.958827383
Short name T186
Test name
Test status
Simulation time 8477829303 ps
CPU time 13.42 seconds
Started May 16 03:20:42 PM PDT 24
Finished May 16 03:21:02 PM PDT 24
Peak memory 204840 kb
Host smart-062e8684-9711-469f-98d5-4d19a76318d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95882
7383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.958827383
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.1365072792
Short name T1335
Test name
Test status
Simulation time 8381217520 ps
CPU time 11.55 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:01 PM PDT 24
Peak memory 204780 kb
Host smart-a1914711-9c37-40a7-968b-bf9229736695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13650
72792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.1365072792
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.945755258
Short name T1521
Test name
Test status
Simulation time 8376393623 ps
CPU time 12.23 seconds
Started May 16 03:20:45 PM PDT 24
Finished May 16 03:21:03 PM PDT 24
Peak memory 204812 kb
Host smart-3becdaa7-7c6d-49ff-9629-2fc5050c61cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94575
5258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.945755258
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.4288261167
Short name T1235
Test name
Test status
Simulation time 8407484605 ps
CPU time 10.85 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:01 PM PDT 24
Peak memory 204912 kb
Host smart-6aac449e-6440-40f9-a389-fe571dfbb2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42882
61167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.4288261167
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1656663678
Short name T314
Test name
Test status
Simulation time 8415416821 ps
CPU time 10.91 seconds
Started May 16 03:20:43 PM PDT 24
Finished May 16 03:21:00 PM PDT 24
Peak memory 204880 kb
Host smart-7c96de35-cfbc-460e-837c-e311c5791eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16566
63678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1656663678
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.2087726885
Short name T451
Test name
Test status
Simulation time 8390673394 ps
CPU time 10.76 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:00 PM PDT 24
Peak memory 204796 kb
Host smart-5b93f035-a8f3-4f3e-809b-a29338f0547e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20877
26885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.2087726885
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2998827538
Short name T34
Test name
Test status
Simulation time 8369854284 ps
CPU time 10.89 seconds
Started May 16 03:20:43 PM PDT 24
Finished May 16 03:20:59 PM PDT 24
Peak memory 204804 kb
Host smart-1d3655a4-7ae1-48c5-9bde-a3fc890cc90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29988
27538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2998827538
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2252652430
Short name T178
Test name
Test status
Simulation time 8390878611 ps
CPU time 11.61 seconds
Started May 16 03:20:46 PM PDT 24
Finished May 16 03:21:03 PM PDT 24
Peak memory 204680 kb
Host smart-8cb89e27-bd5f-4b1f-88f6-f1eb419bebbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526
52430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2252652430
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2715759466
Short name T1378
Test name
Test status
Simulation time 8403843826 ps
CPU time 11.48 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:01 PM PDT 24
Peak memory 204780 kb
Host smart-ef466f93-2d14-4235-9eef-49a08d0d3041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27157
59466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2715759466
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.678138019
Short name T176
Test name
Test status
Simulation time 8446846414 ps
CPU time 12.59 seconds
Started May 16 03:20:35 PM PDT 24
Finished May 16 03:20:54 PM PDT 24
Peak memory 204872 kb
Host smart-8ac3de50-28b8-4de8-888f-233939bb1a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67813
8019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.678138019
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1426842761
Short name T787
Test name
Test status
Simulation time 8410801948 ps
CPU time 12.06 seconds
Started May 16 03:20:43 PM PDT 24
Finished May 16 03:21:01 PM PDT 24
Peak memory 204748 kb
Host smart-c4e9fc37-14bc-4585-a8f7-4a4d8c4d8cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14268
42761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1426842761
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2960847832
Short name T962
Test name
Test status
Simulation time 8404144459 ps
CPU time 12.04 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:01 PM PDT 24
Peak memory 204772 kb
Host smart-11e248df-a3be-46a7-a8a4-03b5e7e7ce96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29608
47832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2960847832
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.1253313147
Short name T1191
Test name
Test status
Simulation time 8476484337 ps
CPU time 10.8 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:09 PM PDT 24
Peak memory 204884 kb
Host smart-62c4889f-6737-45a6-8da6-57a0ce7edb6e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1253313147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.1253313147
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.1818768314
Short name T1574
Test name
Test status
Simulation time 8379067161 ps
CPU time 14.83 seconds
Started May 16 03:20:55 PM PDT 24
Finished May 16 03:21:14 PM PDT 24
Peak memory 204808 kb
Host smart-b6ce5b55-ff9c-44fa-9e42-50000a39c70c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1818768314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.1818768314
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.1701994959
Short name T971
Test name
Test status
Simulation time 8425367078 ps
CPU time 12.75 seconds
Started May 16 03:20:53 PM PDT 24
Finished May 16 03:21:10 PM PDT 24
Peak memory 204856 kb
Host smart-490b028d-91e5-4b31-b280-fce5577e2ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17019
94959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.1701994959
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.4080742836
Short name T1519
Test name
Test status
Simulation time 8378856538 ps
CPU time 11.92 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:02 PM PDT 24
Peak memory 204856 kb
Host smart-4f587e2d-bd48-4b3e-8f17-0e49273356b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40807
42836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.4080742836
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2372996658
Short name T1567
Test name
Test status
Simulation time 9575210964 ps
CPU time 14.15 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:12 PM PDT 24
Peak memory 204876 kb
Host smart-01e5e030-ec4e-4358-a161-461da9fbfd3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23729
96658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2372996658
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1627606294
Short name T558
Test name
Test status
Simulation time 8372018264 ps
CPU time 11.3 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:10 PM PDT 24
Peak memory 204844 kb
Host smart-6695fb10-c38d-422d-9fe1-50ff01d6229a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16276
06294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1627606294
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2196302159
Short name T645
Test name
Test status
Simulation time 8380055417 ps
CPU time 10.79 seconds
Started May 16 03:20:57 PM PDT 24
Finished May 16 03:21:12 PM PDT 24
Peak memory 204836 kb
Host smart-2a571ea2-6495-4bc5-a9ad-174e3fe80a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21963
02159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2196302159
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2167733845
Short name T1176
Test name
Test status
Simulation time 8498844272 ps
CPU time 12.91 seconds
Started May 16 03:20:53 PM PDT 24
Finished May 16 03:21:10 PM PDT 24
Peak memory 204908 kb
Host smart-3b3ca226-1f77-4266-8eb4-92276b9082b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21677
33845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2167733845
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3848209873
Short name T1152
Test name
Test status
Simulation time 8429424854 ps
CPU time 14.45 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:13 PM PDT 24
Peak memory 204852 kb
Host smart-ef2047fa-eda9-4323-a021-95bd03896a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38482
09873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3848209873
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2370602210
Short name T1551
Test name
Test status
Simulation time 8436787196 ps
CPU time 11.32 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:10 PM PDT 24
Peak memory 204872 kb
Host smart-2ef7254f-f1b8-4d21-a60b-6a2671da375e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23706
02210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2370602210
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2787667480
Short name T1312
Test name
Test status
Simulation time 8457603227 ps
CPU time 11.18 seconds
Started May 16 03:20:55 PM PDT 24
Finished May 16 03:21:10 PM PDT 24
Peak memory 204760 kb
Host smart-74297660-5f70-4e1e-aef9-cdacbb7d0266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27876
67480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2787667480
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.3392727053
Short name T1607
Test name
Test status
Simulation time 8419523760 ps
CPU time 14.18 seconds
Started May 16 03:20:55 PM PDT 24
Finished May 16 03:21:13 PM PDT 24
Peak memory 204836 kb
Host smart-57171b91-6063-4755-8112-271ca9b868be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33927
27053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3392727053
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.631348005
Short name T1051
Test name
Test status
Simulation time 11527111296 ps
CPU time 15.87 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:13 PM PDT 24
Peak memory 204864 kb
Host smart-47ff1584-11d7-4a73-8a3f-490cf22e3b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63134
8005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.631348005
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.4017510216
Short name T553
Test name
Test status
Simulation time 8419099656 ps
CPU time 12.06 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:10 PM PDT 24
Peak memory 204800 kb
Host smart-b632f885-b83d-4975-837a-0cf066aa37c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40175
10216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.4017510216
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.99345826
Short name T239
Test name
Test status
Simulation time 8378370419 ps
CPU time 10.71 seconds
Started May 16 03:20:57 PM PDT 24
Finished May 16 03:21:11 PM PDT 24
Peak memory 204832 kb
Host smart-d80db20e-1747-448a-8f4b-cb34566ccaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99345
826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.99345826
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.552807195
Short name T1487
Test name
Test status
Simulation time 8422731320 ps
CPU time 13 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:11 PM PDT 24
Peak memory 204820 kb
Host smart-ec6d4aed-e839-414b-b6fc-a890fdf09333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55280
7195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.552807195
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.3228623008
Short name T521
Test name
Test status
Simulation time 8420319575 ps
CPU time 11.32 seconds
Started May 16 03:20:56 PM PDT 24
Finished May 16 03:21:11 PM PDT 24
Peak memory 204888 kb
Host smart-45b238f5-8a2f-43c5-bb18-1c829f1ce727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32286
23008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3228623008
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2633189731
Short name T1767
Test name
Test status
Simulation time 8408973453 ps
CPU time 10.98 seconds
Started May 16 03:20:53 PM PDT 24
Finished May 16 03:21:08 PM PDT 24
Peak memory 204900 kb
Host smart-66520af8-65ab-4f14-9641-37444220c582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26331
89731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2633189731
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1233087205
Short name T1349
Test name
Test status
Simulation time 8386386861 ps
CPU time 11.28 seconds
Started May 16 03:20:53 PM PDT 24
Finished May 16 03:21:08 PM PDT 24
Peak memory 204876 kb
Host smart-75412dc7-65d1-49f6-936f-015089727fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12330
87205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1233087205
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.1814698871
Short name T397
Test name
Test status
Simulation time 8457282319 ps
CPU time 13.98 seconds
Started May 16 03:20:55 PM PDT 24
Finished May 16 03:21:13 PM PDT 24
Peak memory 204808 kb
Host smart-f2f6325d-bcf5-4804-bc7e-275809e11b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18146
98871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.1814698871
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.2012233325
Short name T561
Test name
Test status
Simulation time 8375200024 ps
CPU time 14.29 seconds
Started May 16 03:20:53 PM PDT 24
Finished May 16 03:21:11 PM PDT 24
Peak memory 204816 kb
Host smart-bc7de116-86d5-4709-9647-a05c6150170b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20122
33325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.2012233325
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.3378722489
Short name T1479
Test name
Test status
Simulation time 8364071375 ps
CPU time 11.24 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:09 PM PDT 24
Peak memory 204808 kb
Host smart-95d2f556-47de-4df5-8e2f-f45b8c4027e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33787
22489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.3378722489
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2186795738
Short name T541
Test name
Test status
Simulation time 28890966838 ps
CPU time 53.45 seconds
Started May 16 03:20:53 PM PDT 24
Finished May 16 03:21:50 PM PDT 24
Peak memory 204824 kb
Host smart-9999af94-df2c-4355-ad58-670956744127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867
95738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2186795738
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.216555176
Short name T657
Test name
Test status
Simulation time 8412642056 ps
CPU time 10.93 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:09 PM PDT 24
Peak memory 204708 kb
Host smart-a89c27d5-8023-435a-82eb-82f0aec667c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655
5176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.216555176
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3278422002
Short name T599
Test name
Test status
Simulation time 8399870828 ps
CPU time 11.1 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:09 PM PDT 24
Peak memory 204888 kb
Host smart-cd817191-10af-478a-ba98-605d8e25c380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32784
22002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3278422002
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.1632187469
Short name T490
Test name
Test status
Simulation time 8390611647 ps
CPU time 12.61 seconds
Started May 16 03:20:56 PM PDT 24
Finished May 16 03:21:12 PM PDT 24
Peak memory 204816 kb
Host smart-d67559da-ab9e-4b65-bf74-4b619daf6a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16321
87469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.1632187469
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3914785170
Short name T1246
Test name
Test status
Simulation time 8371139984 ps
CPU time 11.95 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:10 PM PDT 24
Peak memory 204880 kb
Host smart-63f31dec-cec1-42d5-9600-0c9504a5f976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39147
85170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3914785170
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3169467456
Short name T1128
Test name
Test status
Simulation time 8366029345 ps
CPU time 11.6 seconds
Started May 16 03:20:54 PM PDT 24
Finished May 16 03:21:10 PM PDT 24
Peak memory 204896 kb
Host smart-cf73bc04-41cc-434c-a7a8-5025e5e0f17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31694
67456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3169467456
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3082980468
Short name T1474
Test name
Test status
Simulation time 8479506176 ps
CPU time 12.2 seconds
Started May 16 03:20:44 PM PDT 24
Finished May 16 03:21:02 PM PDT 24
Peak memory 204892 kb
Host smart-db7f96de-3912-4aaa-8201-d5cb93817fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30829
80468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3082980468
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2045760032
Short name T21
Test name
Test status
Simulation time 8371977151 ps
CPU time 11.69 seconds
Started May 16 03:20:55 PM PDT 24
Finished May 16 03:21:10 PM PDT 24
Peak memory 204880 kb
Host smart-cba5ae53-25b0-4c37-9a7a-de8ca9b5d9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20457
60032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2045760032
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2854644513
Short name T831
Test name
Test status
Simulation time 8415243463 ps
CPU time 10.28 seconds
Started May 16 03:20:56 PM PDT 24
Finished May 16 03:21:10 PM PDT 24
Peak memory 204892 kb
Host smart-7e6dbb6f-3658-4f76-9f85-54fbd9c6753a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28546
44513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2854644513
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.125171862
Short name T1491
Test name
Test status
Simulation time 8463750589 ps
CPU time 10.58 seconds
Started May 16 03:21:06 PM PDT 24
Finished May 16 03:21:23 PM PDT 24
Peak memory 204876 kb
Host smart-809f8a76-cea5-44fb-bff0-3c0b8fd5e9c2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=125171862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.125171862
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.203095544
Short name T807
Test name
Test status
Simulation time 8400153094 ps
CPU time 12.07 seconds
Started May 16 03:21:07 PM PDT 24
Finished May 16 03:21:26 PM PDT 24
Peak memory 204896 kb
Host smart-689bd894-2665-4f07-9e16-902ebec6d9b3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=203095544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.203095544
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.2293851882
Short name T473
Test name
Test status
Simulation time 8431793440 ps
CPU time 11.16 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:21 PM PDT 24
Peak memory 204828 kb
Host smart-83fa5c73-3882-4237-ad42-538f14f007a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22938
51882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.2293851882
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.103101077
Short name T723
Test name
Test status
Simulation time 8381108608 ps
CPU time 11.64 seconds
Started May 16 03:20:56 PM PDT 24
Finished May 16 03:21:11 PM PDT 24
Peak memory 204852 kb
Host smart-60a70bb6-c144-43fd-b793-5c43286757b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10310
1077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.103101077
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.2493485822
Short name T90
Test name
Test status
Simulation time 8422064076 ps
CPU time 11.48 seconds
Started May 16 03:21:09 PM PDT 24
Finished May 16 03:21:26 PM PDT 24
Peak memory 204804 kb
Host smart-5ca2ca28-b015-4cfb-b5e3-615711dd2ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24934
85822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.2493485822
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3103086611
Short name T1379
Test name
Test status
Simulation time 8388020371 ps
CPU time 12.61 seconds
Started May 16 03:21:09 PM PDT 24
Finished May 16 03:21:28 PM PDT 24
Peak memory 204856 kb
Host smart-147845eb-86f0-40ca-9d62-eb9e6a84dfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31030
86611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3103086611
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.372287243
Short name T1638
Test name
Test status
Simulation time 8399503238 ps
CPU time 10.79 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:22 PM PDT 24
Peak memory 204884 kb
Host smart-53ae033f-24bb-4784-967b-02f1ccb66c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37228
7243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.372287243
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1915191117
Short name T1009
Test name
Test status
Simulation time 9066092594 ps
CPU time 13.05 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:23 PM PDT 24
Peak memory 204992 kb
Host smart-ea88dfb5-82cd-4b2f-aa49-9cd860800f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19151
91117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1915191117
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.4079199466
Short name T1150
Test name
Test status
Simulation time 8520830115 ps
CPU time 11.92 seconds
Started May 16 03:21:07 PM PDT 24
Finished May 16 03:21:25 PM PDT 24
Peak memory 204912 kb
Host smart-352ac59a-fcfc-4cba-8817-b9418896ff3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40791
99466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.4079199466
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2059188093
Short name T851
Test name
Test status
Simulation time 8383420988 ps
CPU time 11.93 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:22 PM PDT 24
Peak memory 204800 kb
Host smart-3ce525bc-f22e-4fb5-8e5b-07931349f4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20591
88093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2059188093
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1866441250
Short name T1641
Test name
Test status
Simulation time 8385224268 ps
CPU time 11.38 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:21 PM PDT 24
Peak memory 204848 kb
Host smart-b18ef4eb-7c23-4df2-8d87-98e209bd2f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18664
41250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1866441250
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.1130417864
Short name T458
Test name
Test status
Simulation time 8454235716 ps
CPU time 10.63 seconds
Started May 16 03:21:04 PM PDT 24
Finished May 16 03:21:20 PM PDT 24
Peak memory 204792 kb
Host smart-3d7b5049-b83f-4841-a0ca-219ed255325d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11304
17864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.1130417864
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3402957120
Short name T1060
Test name
Test status
Simulation time 11519583364 ps
CPU time 14.09 seconds
Started May 16 03:21:11 PM PDT 24
Finished May 16 03:21:30 PM PDT 24
Peak memory 204792 kb
Host smart-da5dc657-c8e5-48c6-ab67-26de2764a774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34029
57120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3402957120
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.28713364
Short name T949
Test name
Test status
Simulation time 8421490857 ps
CPU time 11.88 seconds
Started May 16 03:21:06 PM PDT 24
Finished May 16 03:21:24 PM PDT 24
Peak memory 204832 kb
Host smart-58ca06a0-df42-4aad-99fc-93623ae25397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28713
364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.28713364
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.959984245
Short name T609
Test name
Test status
Simulation time 8374076694 ps
CPU time 14.26 seconds
Started May 16 03:21:03 PM PDT 24
Finished May 16 03:21:22 PM PDT 24
Peak memory 204844 kb
Host smart-f9b1ca13-6649-4ed1-8f97-22908730bebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95998
4245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.959984245
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.3538091467
Short name T1221
Test name
Test status
Simulation time 8421101622 ps
CPU time 12.66 seconds
Started May 16 03:21:04 PM PDT 24
Finished May 16 03:21:22 PM PDT 24
Peak memory 204912 kb
Host smart-e5c785c2-4d63-45bf-adcb-c5d48386eee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35380
91467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3538091467
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1761814276
Short name T398
Test name
Test status
Simulation time 8423318553 ps
CPU time 10.53 seconds
Started May 16 03:21:07 PM PDT 24
Finished May 16 03:21:24 PM PDT 24
Peak memory 204848 kb
Host smart-6c84b310-8596-4f51-a982-1a92f7ec2d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17618
14276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1761814276
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3212544672
Short name T863
Test name
Test status
Simulation time 8389738039 ps
CPU time 12.06 seconds
Started May 16 03:21:04 PM PDT 24
Finished May 16 03:21:21 PM PDT 24
Peak memory 204868 kb
Host smart-8e120d31-78c1-44c7-a447-d495fece5f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32125
44672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3212544672
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.3433671477
Short name T586
Test name
Test status
Simulation time 8388374668 ps
CPU time 11.43 seconds
Started May 16 03:21:06 PM PDT 24
Finished May 16 03:21:23 PM PDT 24
Peak memory 204768 kb
Host smart-525cc975-1764-4c7e-b789-9a51284a6ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34336
71477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.3433671477
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2869942025
Short name T594
Test name
Test status
Simulation time 8372221967 ps
CPU time 12.22 seconds
Started May 16 03:21:04 PM PDT 24
Finished May 16 03:21:21 PM PDT 24
Peak memory 204832 kb
Host smart-4550dddd-865f-43f3-be4d-dfcc9c32082a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28699
42025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2869942025
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2412014629
Short name T1113
Test name
Test status
Simulation time 8368605340 ps
CPU time 12.2 seconds
Started May 16 03:21:06 PM PDT 24
Finished May 16 03:21:25 PM PDT 24
Peak memory 204832 kb
Host smart-440baa86-dc1c-46fc-8678-bdd62f1fb6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24120
14629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2412014629
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.837628981
Short name T1104
Test name
Test status
Simulation time 27257033499 ps
CPU time 50.73 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:22:01 PM PDT 24
Peak memory 204804 kb
Host smart-3c2ecc77-9c64-4c36-8942-bfec7fc72112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83762
8981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.837628981
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3541691050
Short name T1203
Test name
Test status
Simulation time 8449156418 ps
CPU time 15.15 seconds
Started May 16 03:21:04 PM PDT 24
Finished May 16 03:21:24 PM PDT 24
Peak memory 204848 kb
Host smart-9793a492-33b6-426d-901a-0cfdc336ed57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35416
91050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3541691050
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1683290996
Short name T1439
Test name
Test status
Simulation time 8399353894 ps
CPU time 11.94 seconds
Started May 16 03:21:09 PM PDT 24
Finished May 16 03:21:27 PM PDT 24
Peak memory 204860 kb
Host smart-692b30da-a1e4-41ae-a8e8-40ab347245ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16832
90996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1683290996
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.799079581
Short name T87
Test name
Test status
Simulation time 8378713579 ps
CPU time 13.58 seconds
Started May 16 03:21:09 PM PDT 24
Finished May 16 03:21:29 PM PDT 24
Peak memory 204852 kb
Host smart-9acd8aa2-6910-4475-938e-bca11d343b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79907
9581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.799079581
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3019178215
Short name T1127
Test name
Test status
Simulation time 8365062675 ps
CPU time 12.46 seconds
Started May 16 03:21:08 PM PDT 24
Finished May 16 03:21:27 PM PDT 24
Peak memory 204880 kb
Host smart-096f2c6d-92ac-45f7-a833-e77f626c7c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30191
78215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3019178215
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.862389827
Short name T1108
Test name
Test status
Simulation time 8407684147 ps
CPU time 11.27 seconds
Started May 16 03:21:04 PM PDT 24
Finished May 16 03:21:21 PM PDT 24
Peak memory 204756 kb
Host smart-e471b950-a34d-4874-a3a2-1fe88769f5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86238
9827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.862389827
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1771506509
Short name T993
Test name
Test status
Simulation time 8374030566 ps
CPU time 13.11 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:24 PM PDT 24
Peak memory 204836 kb
Host smart-a2e26c1e-2381-4233-9fa2-b776d5b29252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17715
06509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1771506509
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1243825079
Short name T833
Test name
Test status
Simulation time 8478444594 ps
CPU time 12.7 seconds
Started May 16 03:20:55 PM PDT 24
Finished May 16 03:21:12 PM PDT 24
Peak memory 204804 kb
Host smart-c4b082be-71f0-43e3-a033-5181eb3d7aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12438
25079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1243825079
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3039276207
Short name T1729
Test name
Test status
Simulation time 8410619434 ps
CPU time 11.78 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:22 PM PDT 24
Peak memory 204992 kb
Host smart-a718c277-c820-415c-bb15-abb4b5a9c752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30392
76207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3039276207
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1558912145
Short name T970
Test name
Test status
Simulation time 8389142501 ps
CPU time 11.07 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:23 PM PDT 24
Peak memory 204916 kb
Host smart-1d8b4aee-28c9-4b34-bafc-35ab3fc88645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15589
12145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1558912145
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.3684967916
Short name T44
Test name
Test status
Simulation time 8499063076 ps
CPU time 12.63 seconds
Started May 16 03:21:20 PM PDT 24
Finished May 16 03:21:38 PM PDT 24
Peak memory 204888 kb
Host smart-b5029161-1ed4-4f99-99dc-4e77761e8a56
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3684967916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.3684967916
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.4144325321
Short name T1647
Test name
Test status
Simulation time 8396276824 ps
CPU time 11.55 seconds
Started May 16 03:21:19 PM PDT 24
Finished May 16 03:21:36 PM PDT 24
Peak memory 204748 kb
Host smart-199cf133-9514-42cf-927f-f8995f5be181
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4144325321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.4144325321
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.2821369086
Short name T1644
Test name
Test status
Simulation time 8393844076 ps
CPU time 13.21 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:33 PM PDT 24
Peak memory 204700 kb
Host smart-e36483b5-742d-4103-be9e-4bb83da741c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28213
69086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2821369086
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2818426940
Short name T1667
Test name
Test status
Simulation time 8392554505 ps
CPU time 12.6 seconds
Started May 16 03:21:04 PM PDT 24
Finished May 16 03:21:21 PM PDT 24
Peak memory 204840 kb
Host smart-1d7cf232-a281-410f-98ba-8e24e534b7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184
26940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2818426940
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.94685896
Short name T220
Test name
Test status
Simulation time 9072344869 ps
CPU time 12.95 seconds
Started May 16 03:21:03 PM PDT 24
Finished May 16 03:21:21 PM PDT 24
Peak memory 204928 kb
Host smart-97dee5fd-4503-4628-925e-d1e8214a5209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94685
896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.94685896
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3967147252
Short name T1018
Test name
Test status
Simulation time 8364220402 ps
CPU time 12.4 seconds
Started May 16 03:21:06 PM PDT 24
Finished May 16 03:21:25 PM PDT 24
Peak memory 204740 kb
Host smart-ec712831-0f0e-4bd1-a2d1-7e1468009434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39671
47252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3967147252
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.1346114166
Short name T1659
Test name
Test status
Simulation time 8390938519 ps
CPU time 10.76 seconds
Started May 16 03:21:07 PM PDT 24
Finished May 16 03:21:24 PM PDT 24
Peak memory 204868 kb
Host smart-8a012971-3a6b-492f-8a8f-5986a0d1168f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13461
14166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1346114166
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.400930989
Short name T414
Test name
Test status
Simulation time 9231716740 ps
CPU time 12.71 seconds
Started May 16 03:21:04 PM PDT 24
Finished May 16 03:21:22 PM PDT 24
Peak memory 204876 kb
Host smart-ac2b521b-7608-4b4d-b7d3-6be4667f8af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40093
0989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.400930989
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2150837114
Short name T877
Test name
Test status
Simulation time 8581814753 ps
CPU time 15.01 seconds
Started May 16 03:21:06 PM PDT 24
Finished May 16 03:21:27 PM PDT 24
Peak memory 204880 kb
Host smart-ba730945-b337-4877-8d34-d0d0f59ec8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21508
37114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2150837114
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.791500618
Short name T1343
Test name
Test status
Simulation time 8393521831 ps
CPU time 12.32 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:32 PM PDT 24
Peak memory 204880 kb
Host smart-9e28ad50-4959-45c6-b39a-15e4b58423ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79150
0618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.791500618
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1102776833
Short name T560
Test name
Test status
Simulation time 8371732165 ps
CPU time 10.49 seconds
Started May 16 03:21:15 PM PDT 24
Finished May 16 03:21:30 PM PDT 24
Peak memory 204856 kb
Host smart-2bd0fb9e-99cd-46d5-a923-8b46a79859c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11027
76833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1102776833
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2920667869
Short name T642
Test name
Test status
Simulation time 8410925847 ps
CPU time 11.18 seconds
Started May 16 03:21:11 PM PDT 24
Finished May 16 03:21:27 PM PDT 24
Peak memory 204840 kb
Host smart-1a8053d6-3110-414f-b51e-3f17784f8fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29206
67869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2920667869
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3089834224
Short name T1347
Test name
Test status
Simulation time 8415877183 ps
CPU time 12.7 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:24 PM PDT 24
Peak memory 204872 kb
Host smart-2ac32bde-0693-4e09-b616-2c8fd6ea29d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30898
34224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3089834224
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.1978028388
Short name T1601
Test name
Test status
Simulation time 11516284024 ps
CPU time 16.86 seconds
Started May 16 03:21:03 PM PDT 24
Finished May 16 03:21:24 PM PDT 24
Peak memory 204780 kb
Host smart-9b5d8fcd-61cb-4340-9de4-62b639723145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19780
28388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1978028388
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2266511692
Short name T1565
Test name
Test status
Simulation time 8416095469 ps
CPU time 12.25 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:24 PM PDT 24
Peak memory 204832 kb
Host smart-8bd79088-f1f5-4e5c-9aad-25e625fe9c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22665
11692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2266511692
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.787289201
Short name T381
Test name
Test status
Simulation time 8369582614 ps
CPU time 11.06 seconds
Started May 16 03:21:06 PM PDT 24
Finished May 16 03:21:23 PM PDT 24
Peak memory 204840 kb
Host smart-2ec681ae-b9b5-4570-a4c1-e07e9c83723e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78728
9201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.787289201
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3948100338
Short name T146
Test name
Test status
Simulation time 8437135627 ps
CPU time 11.73 seconds
Started May 16 03:21:04 PM PDT 24
Finished May 16 03:21:20 PM PDT 24
Peak memory 204908 kb
Host smart-dd6514b5-2e77-45a4-883d-0c02b1d21328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39481
00338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3948100338
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2200470210
Short name T1513
Test name
Test status
Simulation time 8418617567 ps
CPU time 10.86 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:21 PM PDT 24
Peak memory 204812 kb
Host smart-845f9604-4604-4d1e-a7a7-6bc2fe3af122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22004
70210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2200470210
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.4158866780
Short name T20
Test name
Test status
Simulation time 8410745931 ps
CPU time 11.66 seconds
Started May 16 03:21:05 PM PDT 24
Finished May 16 03:21:21 PM PDT 24
Peak memory 204920 kb
Host smart-56fa9741-ba2b-4f8e-96ab-9aa1c9ab8f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41588
66780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.4158866780
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3331140683
Short name T315
Test name
Test status
Simulation time 8375958510 ps
CPU time 12.01 seconds
Started May 16 03:21:08 PM PDT 24
Finished May 16 03:21:27 PM PDT 24
Peak memory 204800 kb
Host smart-67337626-1975-4de9-a2f7-da09f8c2c361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33311
40683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3331140683
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.3046129408
Short name T1210
Test name
Test status
Simulation time 8416704963 ps
CPU time 11.83 seconds
Started May 16 03:21:17 PM PDT 24
Finished May 16 03:21:34 PM PDT 24
Peak memory 204796 kb
Host smart-6ec7e403-41dd-4064-9917-56a64b6f6ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30461
29408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.3046129408
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.44804326
Short name T1027
Test name
Test status
Simulation time 8379418762 ps
CPU time 11.38 seconds
Started May 16 03:21:19 PM PDT 24
Finished May 16 03:21:36 PM PDT 24
Peak memory 204812 kb
Host smart-e0b82a41-6333-4cbc-86a1-38963b7110ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44804
326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.44804326
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3971365459
Short name T1475
Test name
Test status
Simulation time 8365474848 ps
CPU time 12.41 seconds
Started May 16 03:21:17 PM PDT 24
Finished May 16 03:21:34 PM PDT 24
Peak memory 204892 kb
Host smart-4736f7c8-280e-47c0-a121-bd1546f97bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39713
65459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3971365459
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2592599828
Short name T820
Test name
Test status
Simulation time 15712238517 ps
CPU time 25.83 seconds
Started May 16 03:21:06 PM PDT 24
Finished May 16 03:21:39 PM PDT 24
Peak memory 204820 kb
Host smart-bb520393-6078-41f5-8ff5-066183b655b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25925
99828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2592599828
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1969785251
Short name T1529
Test name
Test status
Simulation time 8409069475 ps
CPU time 10.58 seconds
Started May 16 03:21:09 PM PDT 24
Finished May 16 03:21:26 PM PDT 24
Peak memory 204812 kb
Host smart-2eb55362-e5b4-4d77-b066-17574901ad21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19697
85251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1969785251
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3860179503
Short name T443
Test name
Test status
Simulation time 8443646434 ps
CPU time 11.17 seconds
Started May 16 03:21:09 PM PDT 24
Finished May 16 03:21:26 PM PDT 24
Peak memory 204908 kb
Host smart-51f44255-ecc1-449a-8609-6c227e61dbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38601
79503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3860179503
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.3979388433
Short name T781
Test name
Test status
Simulation time 8392612381 ps
CPU time 11.02 seconds
Started May 16 03:21:08 PM PDT 24
Finished May 16 03:21:25 PM PDT 24
Peak memory 204756 kb
Host smart-0bf3743b-d0a1-427e-bae1-f8460a2d0056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39793
88433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.3979388433
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3992765666
Short name T547
Test name
Test status
Simulation time 8374414560 ps
CPU time 13.32 seconds
Started May 16 03:21:08 PM PDT 24
Finished May 16 03:21:28 PM PDT 24
Peak memory 204816 kb
Host smart-cfc21944-86cc-45cf-98cb-8226064b4329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39927
65666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3992765666
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3607155694
Short name T694
Test name
Test status
Simulation time 8377097662 ps
CPU time 10.92 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:31 PM PDT 24
Peak memory 204776 kb
Host smart-618e467b-7528-40cc-974a-166c68673c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36071
55694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3607155694
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2808171687
Short name T399
Test name
Test status
Simulation time 8401078926 ps
CPU time 11.92 seconds
Started May 16 03:21:08 PM PDT 24
Finished May 16 03:21:27 PM PDT 24
Peak memory 204880 kb
Host smart-2fe1c62a-872a-47d5-a718-8dfa55a5a0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28081
71687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2808171687
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.865622013
Short name T430
Test name
Test status
Simulation time 8457001533 ps
CPU time 11.25 seconds
Started May 16 03:21:07 PM PDT 24
Finished May 16 03:21:25 PM PDT 24
Peak memory 204828 kb
Host smart-3abb7f54-80c8-452d-950e-0524b06f84be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86562
2013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.865622013
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1827818912
Short name T1081
Test name
Test status
Simulation time 8374849128 ps
CPU time 13.03 seconds
Started May 16 03:21:07 PM PDT 24
Finished May 16 03:21:27 PM PDT 24
Peak memory 204812 kb
Host smart-c20359d0-3897-475c-96a1-05d1ff434230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18278
18912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1827818912
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.184728367
Short name T493
Test name
Test status
Simulation time 8468345164 ps
CPU time 11.66 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:32 PM PDT 24
Peak memory 204856 kb
Host smart-59e844aa-0305-49a2-9485-ae259e513a91
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=184728367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.184728367
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.762885738
Short name T1331
Test name
Test status
Simulation time 8398076191 ps
CPU time 11.33 seconds
Started May 16 03:21:24 PM PDT 24
Finished May 16 03:21:41 PM PDT 24
Peak memory 204820 kb
Host smart-399b677f-f0d2-4a97-8472-33d49fef2f17
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=762885738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.762885738
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.2088812904
Short name T1296
Test name
Test status
Simulation time 8438170384 ps
CPU time 12.69 seconds
Started May 16 03:21:17 PM PDT 24
Finished May 16 03:21:35 PM PDT 24
Peak memory 204928 kb
Host smart-11f1d230-0fed-4296-af46-9a78d315d0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20888
12904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.2088812904
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2299535982
Short name T1432
Test name
Test status
Simulation time 8413550988 ps
CPU time 11.41 seconds
Started May 16 03:21:23 PM PDT 24
Finished May 16 03:21:41 PM PDT 24
Peak memory 204844 kb
Host smart-d59eaefd-ef1d-4ab0-8c2e-238ef30ba781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22995
35982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2299535982
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.4140442618
Short name T1073
Test name
Test status
Simulation time 8387800541 ps
CPU time 12.89 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:34 PM PDT 24
Peak memory 204872 kb
Host smart-29897d49-4430-43c8-b254-134981c1d786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41404
42618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.4140442618
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_enable.1379211274
Short name T659
Test name
Test status
Simulation time 8392923148 ps
CPU time 11.18 seconds
Started May 16 03:21:24 PM PDT 24
Finished May 16 03:21:41 PM PDT 24
Peak memory 204884 kb
Host smart-b686a95c-adb7-4477-b6ff-1132ec2686ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13792
11274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1379211274
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2919943627
Short name T1231
Test name
Test status
Simulation time 9069028019 ps
CPU time 13.55 seconds
Started May 16 03:21:20 PM PDT 24
Finished May 16 03:21:39 PM PDT 24
Peak memory 204880 kb
Host smart-765115fb-7ef2-4d42-9f6e-17774dfe7276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29199
43627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2919943627
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2288776967
Short name T1754
Test name
Test status
Simulation time 8445244400 ps
CPU time 12.68 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:34 PM PDT 24
Peak memory 204800 kb
Host smart-c5d75e65-7189-4e45-9bd0-e5f609e96b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22887
76967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2288776967
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1164154513
Short name T1419
Test name
Test status
Simulation time 8437311415 ps
CPU time 10.41 seconds
Started May 16 03:21:21 PM PDT 24
Finished May 16 03:21:37 PM PDT 24
Peak memory 204828 kb
Host smart-223fc34c-e899-4daf-a998-90457e8adae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11641
54513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1164154513
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1785633695
Short name T612
Test name
Test status
Simulation time 8371223172 ps
CPU time 14.63 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:34 PM PDT 24
Peak memory 204792 kb
Host smart-eeaeb7ff-154f-4654-b4f4-8c794f968abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17856
33695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1785633695
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.366744478
Short name T838
Test name
Test status
Simulation time 8447642335 ps
CPU time 11.25 seconds
Started May 16 03:21:17 PM PDT 24
Finished May 16 03:21:33 PM PDT 24
Peak memory 204808 kb
Host smart-5ca86f5d-151e-4b4f-8df7-4384f050a1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36674
4478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.366744478
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2568130820
Short name T1178
Test name
Test status
Simulation time 8418884011 ps
CPU time 11.42 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:32 PM PDT 24
Peak memory 204808 kb
Host smart-e5c37d89-9b89-48de-b3f4-b93e5ccea22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25681
30820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2568130820
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1368239279
Short name T1422
Test name
Test status
Simulation time 11571254553 ps
CPU time 14.25 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:35 PM PDT 24
Peak memory 204864 kb
Host smart-026c8468-ac74-4cd8-b05f-82d1ad057b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13682
39279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1368239279
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3024942415
Short name T1430
Test name
Test status
Simulation time 8416315382 ps
CPU time 12.22 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:32 PM PDT 24
Peak memory 204796 kb
Host smart-a05db5ea-f9db-4be0-a6f1-c707ec512cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30249
42415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3024942415
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3728779895
Short name T479
Test name
Test status
Simulation time 8377243049 ps
CPU time 11.08 seconds
Started May 16 03:21:20 PM PDT 24
Finished May 16 03:21:37 PM PDT 24
Peak memory 204840 kb
Host smart-9ee09c6d-da77-4c53-8a54-cbbc88477f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37287
79895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3728779895
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1674910464
Short name T613
Test name
Test status
Simulation time 8418986146 ps
CPU time 11.07 seconds
Started May 16 03:21:17 PM PDT 24
Finished May 16 03:21:33 PM PDT 24
Peak memory 204748 kb
Host smart-9743a9df-d0b9-4f8c-a1c4-acf507aa6d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16749
10464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1674910464
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.4180957926
Short name T785
Test name
Test status
Simulation time 8396422890 ps
CPU time 11.59 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:33 PM PDT 24
Peak memory 204880 kb
Host smart-ddbf2300-bd01-400d-a0a6-27d12d6f8b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41809
57926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.4180957926
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1499137788
Short name T367
Test name
Test status
Simulation time 8408787889 ps
CPU time 11.91 seconds
Started May 16 03:21:19 PM PDT 24
Finished May 16 03:21:36 PM PDT 24
Peak memory 204904 kb
Host smart-eb4d44f3-81c8-4af4-bd1e-529e4e953392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14991
37788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1499137788
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2145293604
Short name T1516
Test name
Test status
Simulation time 8387161502 ps
CPU time 13.37 seconds
Started May 16 03:21:15 PM PDT 24
Finished May 16 03:21:32 PM PDT 24
Peak memory 204756 kb
Host smart-3c520ab4-a711-4f35-9e57-6467bdadbf36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21452
93604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2145293604
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.149142354
Short name T704
Test name
Test status
Simulation time 8399104625 ps
CPU time 11.05 seconds
Started May 16 03:21:19 PM PDT 24
Finished May 16 03:21:36 PM PDT 24
Peak memory 204872 kb
Host smart-10c34a10-f1b5-4b4a-b7aa-b1df4dda02ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14914
2354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.149142354
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.28720088
Short name T1690
Test name
Test status
Simulation time 8373878209 ps
CPU time 10.76 seconds
Started May 16 03:21:18 PM PDT 24
Finished May 16 03:21:34 PM PDT 24
Peak memory 204792 kb
Host smart-dc060c80-520f-4e72-a358-45b73dcf6504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28720
088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.28720088
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1270315767
Short name T1742
Test name
Test status
Simulation time 8395661273 ps
CPU time 12.57 seconds
Started May 16 03:21:15 PM PDT 24
Finished May 16 03:21:32 PM PDT 24
Peak memory 204804 kb
Host smart-9a7d4c07-6ed8-4fe5-84d9-671e0c90b744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12703
15767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1270315767
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.811463804
Short name T1342
Test name
Test status
Simulation time 21659041585 ps
CPU time 43.92 seconds
Started May 16 03:21:19 PM PDT 24
Finished May 16 03:22:08 PM PDT 24
Peak memory 204620 kb
Host smart-407e8bb1-51b7-424c-a76b-a48651d169ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81146
3804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.811463804
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3388173787
Short name T75
Test name
Test status
Simulation time 8381924010 ps
CPU time 12.21 seconds
Started May 16 03:21:18 PM PDT 24
Finished May 16 03:21:35 PM PDT 24
Peak memory 204836 kb
Host smart-a66799aa-add3-4b1a-9bc1-0c1a173da54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33881
73787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3388173787
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1608957141
Short name T1207
Test name
Test status
Simulation time 8402101693 ps
CPU time 10.95 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:32 PM PDT 24
Peak memory 204852 kb
Host smart-3bb60036-6a94-43ae-8f48-81057a713f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16089
57141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1608957141
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.2447965357
Short name T1332
Test name
Test status
Simulation time 8400593266 ps
CPU time 11.54 seconds
Started May 16 03:21:17 PM PDT 24
Finished May 16 03:21:33 PM PDT 24
Peak memory 204864 kb
Host smart-f5f2ab37-77e4-4cce-afcd-2ab9b3878f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24479
65357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.2447965357
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.4186594929
Short name T1344
Test name
Test status
Simulation time 8377335429 ps
CPU time 11.73 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:33 PM PDT 24
Peak memory 204824 kb
Host smart-ff8ef097-740f-4e56-9e79-1e3b42b933ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41865
94929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.4186594929
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1040464252
Short name T598
Test name
Test status
Simulation time 8383097095 ps
CPU time 13.53 seconds
Started May 16 03:21:22 PM PDT 24
Finished May 16 03:21:42 PM PDT 24
Peak memory 204900 kb
Host smart-d2aac4a3-6e99-46eb-8c38-1151397f6865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10404
64252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1040464252
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.7535363
Short name T385
Test name
Test status
Simulation time 8368204145 ps
CPU time 11.56 seconds
Started May 16 03:21:18 PM PDT 24
Finished May 16 03:21:34 PM PDT 24
Peak memory 204780 kb
Host smart-b49dfca2-83fa-4e0a-8486-07bcba20c89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75353
63 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.7535363
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.708627451
Short name T860
Test name
Test status
Simulation time 8470367257 ps
CPU time 11.81 seconds
Started May 16 03:21:14 PM PDT 24
Finished May 16 03:21:30 PM PDT 24
Peak memory 204820 kb
Host smart-e7b1b6a1-ee0f-4330-97ff-99c0c833e742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70862
7451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.708627451
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.683049435
Short name T739
Test name
Test status
Simulation time 8400948554 ps
CPU time 12.71 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:33 PM PDT 24
Peak memory 204816 kb
Host smart-641281cd-0ed3-4e9d-a926-862276f345bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68304
9435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.683049435
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3765267410
Short name T1639
Test name
Test status
Simulation time 8428314264 ps
CPU time 12.73 seconds
Started May 16 03:21:18 PM PDT 24
Finished May 16 03:21:36 PM PDT 24
Peak memory 204812 kb
Host smart-89b8de4b-165a-470d-bbab-505e63d1a76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37652
67410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3765267410
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.3438280865
Short name T950
Test name
Test status
Simulation time 8476255519 ps
CPU time 11.65 seconds
Started May 16 03:21:26 PM PDT 24
Finished May 16 03:21:44 PM PDT 24
Peak memory 204900 kb
Host smart-62bd0111-d82e-4be5-be95-9143390dd37b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3438280865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.3438280865
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.2387009127
Short name T350
Test name
Test status
Simulation time 8385217807 ps
CPU time 11.82 seconds
Started May 16 03:21:30 PM PDT 24
Finished May 16 03:21:50 PM PDT 24
Peak memory 204752 kb
Host smart-0b47fc0b-5640-4d44-a397-19ed2ba2b024
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2387009127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.2387009127
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.2784836230
Short name T1115
Test name
Test status
Simulation time 8463089048 ps
CPU time 11.42 seconds
Started May 16 03:21:31 PM PDT 24
Finished May 16 03:21:52 PM PDT 24
Peak memory 204836 kb
Host smart-85db47cc-caa8-4d70-a4e3-8f335ed279e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27848
36230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.2784836230
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1652337346
Short name T782
Test name
Test status
Simulation time 8405049184 ps
CPU time 14.32 seconds
Started May 16 03:21:16 PM PDT 24
Finished May 16 03:21:36 PM PDT 24
Peak memory 204760 kb
Host smart-b20c9177-c67b-42da-80d9-a3c7e72351b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16523
37346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1652337346
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.214774770
Short name T1057
Test name
Test status
Simulation time 8364306181 ps
CPU time 11.53 seconds
Started May 16 03:21:26 PM PDT 24
Finished May 16 03:21:44 PM PDT 24
Peak memory 204820 kb
Host smart-e55bf191-1827-4ce0-8536-21cf27390ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21477
4770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.214774770
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3913039210
Short name T1462
Test name
Test status
Simulation time 8375595011 ps
CPU time 11.72 seconds
Started May 16 03:21:28 PM PDT 24
Finished May 16 03:21:47 PM PDT 24
Peak memory 204876 kb
Host smart-f45df08b-2bad-46f1-a9a8-885194d71449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39130
39210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3913039210
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.2598630856
Short name T1088
Test name
Test status
Simulation time 9081014954 ps
CPU time 12.27 seconds
Started May 16 03:21:27 PM PDT 24
Finished May 16 03:21:47 PM PDT 24
Peak memory 204908 kb
Host smart-94c73305-a462-4c8d-a8a9-c91e90cd9430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25986
30856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.2598630856
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1113814574
Short name T58
Test name
Test status
Simulation time 8383655277 ps
CPU time 11.87 seconds
Started May 16 03:21:32 PM PDT 24
Finished May 16 03:21:53 PM PDT 24
Peak memory 204836 kb
Host smart-9734e613-c3ed-4d22-894c-09fbc021227d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11138
14574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1113814574
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.484679224
Short name T1340
Test name
Test status
Simulation time 8391129988 ps
CPU time 10.99 seconds
Started May 16 03:21:25 PM PDT 24
Finished May 16 03:21:43 PM PDT 24
Peak memory 204840 kb
Host smart-8681e72c-3374-4bb9-b569-8e9d8e9992b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48467
9224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.484679224
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2675283523
Short name T533
Test name
Test status
Simulation time 8464577956 ps
CPU time 11.26 seconds
Started May 16 03:21:27 PM PDT 24
Finished May 16 03:21:45 PM PDT 24
Peak memory 204892 kb
Host smart-95cf7942-1f1d-4b10-9017-908a7569b751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26752
83523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2675283523
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3071141810
Short name T1750
Test name
Test status
Simulation time 8437410095 ps
CPU time 12.99 seconds
Started May 16 03:21:28 PM PDT 24
Finished May 16 03:21:50 PM PDT 24
Peak memory 204848 kb
Host smart-be504014-fe40-428f-9764-ec9b5baea489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30711
41810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3071141810
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2726721148
Short name T1626
Test name
Test status
Simulation time 8410141095 ps
CPU time 12.24 seconds
Started May 16 03:21:27 PM PDT 24
Finished May 16 03:21:47 PM PDT 24
Peak memory 204828 kb
Host smart-4c3e017d-4701-44d0-9eeb-a658689f8782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27267
21148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2726721148
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2255055298
Short name T395
Test name
Test status
Simulation time 11561169428 ps
CPU time 15.21 seconds
Started May 16 03:21:25 PM PDT 24
Finished May 16 03:21:47 PM PDT 24
Peak memory 204872 kb
Host smart-39538463-33b5-4144-bdca-b1889b8815da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22550
55298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2255055298
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1716799949
Short name T445
Test name
Test status
Simulation time 8422844091 ps
CPU time 12.8 seconds
Started May 16 03:21:26 PM PDT 24
Finished May 16 03:21:46 PM PDT 24
Peak memory 204824 kb
Host smart-4122b58f-fd47-46fd-8aac-6da7e3136264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17167
99949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1716799949
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2482447521
Short name T240
Test name
Test status
Simulation time 8381544177 ps
CPU time 12.06 seconds
Started May 16 03:21:27 PM PDT 24
Finished May 16 03:21:47 PM PDT 24
Peak memory 204712 kb
Host smart-bfa2589e-01d2-4378-aba1-660374939b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24824
47521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2482447521
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4105372683
Short name T128
Test name
Test status
Simulation time 8418004578 ps
CPU time 12.88 seconds
Started May 16 03:21:26 PM PDT 24
Finished May 16 03:21:46 PM PDT 24
Peak memory 204872 kb
Host smart-47571658-1ed3-4e26-909a-cefa30180b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41053
72683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4105372683
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.131590411
Short name T377
Test name
Test status
Simulation time 8420349668 ps
CPU time 12.27 seconds
Started May 16 03:21:26 PM PDT 24
Finished May 16 03:21:45 PM PDT 24
Peak memory 204840 kb
Host smart-2107be45-216d-4269-a800-7ce3b3429ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13159
0411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.131590411
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2448269376
Short name T1522
Test name
Test status
Simulation time 8412778773 ps
CPU time 11.54 seconds
Started May 16 03:21:30 PM PDT 24
Finished May 16 03:21:50 PM PDT 24
Peak memory 204756 kb
Host smart-4047723c-adb6-4ee3-b80e-71a6e41199fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24482
69376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2448269376
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1410026994
Short name T1217
Test name
Test status
Simulation time 8415514517 ps
CPU time 11.25 seconds
Started May 16 03:21:29 PM PDT 24
Finished May 16 03:21:49 PM PDT 24
Peak memory 204756 kb
Host smart-5a72f3ac-6000-4e73-a6e7-21a067b15214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14100
26994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1410026994
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1521392383
Short name T167
Test name
Test status
Simulation time 8379955714 ps
CPU time 11.92 seconds
Started May 16 03:21:30 PM PDT 24
Finished May 16 03:21:50 PM PDT 24
Peak memory 204820 kb
Host smart-40326a6d-7452-4fa6-8745-7202da76ee54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15213
92383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1521392383
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.980491054
Short name T957
Test name
Test status
Simulation time 8382481341 ps
CPU time 11.67 seconds
Started May 16 03:21:27 PM PDT 24
Finished May 16 03:21:46 PM PDT 24
Peak memory 204824 kb
Host smart-31f8bfa2-395e-4d34-a753-f77e9ef930c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98049
1054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.980491054
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1118657056
Short name T1122
Test name
Test status
Simulation time 8394107838 ps
CPU time 10.66 seconds
Started May 16 03:21:27 PM PDT 24
Finished May 16 03:21:45 PM PDT 24
Peak memory 204788 kb
Host smart-6a0d3566-9701-4551-a8fa-6df3f34301cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11186
57056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1118657056
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1083279816
Short name T1094
Test name
Test status
Simulation time 8377715424 ps
CPU time 13.03 seconds
Started May 16 03:21:28 PM PDT 24
Finished May 16 03:21:48 PM PDT 24
Peak memory 204852 kb
Host smart-2060a24b-fda5-47d0-8c62-e4a5a54ba28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10832
79816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1083279816
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3996206582
Short name T251
Test name
Test status
Simulation time 15712470278 ps
CPU time 29.71 seconds
Started May 16 03:21:25 PM PDT 24
Finished May 16 03:22:02 PM PDT 24
Peak memory 204816 kb
Host smart-37c9c292-b940-4d93-be43-f3e99e8353d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39962
06582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3996206582
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.976727098
Short name T448
Test name
Test status
Simulation time 8393591210 ps
CPU time 13.94 seconds
Started May 16 03:21:29 PM PDT 24
Finished May 16 03:21:51 PM PDT 24
Peak memory 204884 kb
Host smart-ab0078cf-d65d-4878-be8b-b25461da71e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97672
7098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.976727098
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.535617398
Short name T1636
Test name
Test status
Simulation time 8466770866 ps
CPU time 11.91 seconds
Started May 16 03:21:26 PM PDT 24
Finished May 16 03:21:46 PM PDT 24
Peak memory 204872 kb
Host smart-3d73294c-054d-4f02-b57d-bda99ac1c5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53561
7398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.535617398
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.1252514715
Short name T1160
Test name
Test status
Simulation time 8430515734 ps
CPU time 10.58 seconds
Started May 16 03:21:27 PM PDT 24
Finished May 16 03:21:45 PM PDT 24
Peak memory 204804 kb
Host smart-c8645d66-7bcc-43e5-95e3-7edcbf340b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12525
14715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.1252514715
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.982926442
Short name T736
Test name
Test status
Simulation time 8363364154 ps
CPU time 12.5 seconds
Started May 16 03:21:29 PM PDT 24
Finished May 16 03:21:50 PM PDT 24
Peak memory 204676 kb
Host smart-5ac01efb-af5d-416e-a6f5-15b7768eadaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98292
6442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.982926442
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.244318356
Short name T757
Test name
Test status
Simulation time 8372662871 ps
CPU time 12.4 seconds
Started May 16 03:21:29 PM PDT 24
Finished May 16 03:21:50 PM PDT 24
Peak memory 204820 kb
Host smart-c946f564-460d-4fea-8627-3909aaacd8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24431
8356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.244318356
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.17591065
Short name T522
Test name
Test status
Simulation time 8381428176 ps
CPU time 12.81 seconds
Started May 16 03:21:28 PM PDT 24
Finished May 16 03:21:49 PM PDT 24
Peak memory 204836 kb
Host smart-0be6add1-aad5-4e54-a1a6-40fd71c9ed73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17591
065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.17591065
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.191808929
Short name T649
Test name
Test status
Simulation time 8435527686 ps
CPU time 11.49 seconds
Started May 16 03:21:18 PM PDT 24
Finished May 16 03:21:34 PM PDT 24
Peak memory 204896 kb
Host smart-68656a3c-4766-4413-b377-e0ba1a2eb90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19180
8929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.191808929
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2485878007
Short name T562
Test name
Test status
Simulation time 8395921991 ps
CPU time 13.52 seconds
Started May 16 03:21:24 PM PDT 24
Finished May 16 03:21:44 PM PDT 24
Peak memory 204832 kb
Host smart-a5695161-ff90-4e65-9c66-402695cda71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24858
78007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2485878007
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.491059897
Short name T920
Test name
Test status
Simulation time 8396459277 ps
CPU time 13.35 seconds
Started May 16 03:21:32 PM PDT 24
Finished May 16 03:21:54 PM PDT 24
Peak memory 204928 kb
Host smart-2700a8ee-8bdb-4582-b117-1d2c1bd15a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49105
9897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.491059897
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.102409454
Short name T678
Test name
Test status
Simulation time 8468523593 ps
CPU time 10.76 seconds
Started May 16 03:21:36 PM PDT 24
Finished May 16 03:21:57 PM PDT 24
Peak memory 204880 kb
Host smart-3ee5c6d7-5fab-40bc-a864-0e02594b9ea7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=102409454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.102409454
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.1627761137
Short name T1232
Test name
Test status
Simulation time 8391502656 ps
CPU time 11.21 seconds
Started May 16 03:21:37 PM PDT 24
Finished May 16 03:21:58 PM PDT 24
Peak memory 204888 kb
Host smart-2439dce9-1418-4d6b-86d9-a90ba27d4233
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1627761137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.1627761137
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.2943443001
Short name T1390
Test name
Test status
Simulation time 8442045327 ps
CPU time 10.87 seconds
Started May 16 03:21:37 PM PDT 24
Finished May 16 03:21:58 PM PDT 24
Peak memory 204876 kb
Host smart-7d416022-fda4-4afe-ba1b-99651737622b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29434
43001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.2943443001
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1638012187
Short name T110
Test name
Test status
Simulation time 8386394354 ps
CPU time 10.68 seconds
Started May 16 03:21:29 PM PDT 24
Finished May 16 03:21:49 PM PDT 24
Peak memory 204908 kb
Host smart-632f496e-9e3e-4fef-9d44-09aa89182e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16380
12187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1638012187
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3674651919
Short name T1204
Test name
Test status
Simulation time 8955012377 ps
CPU time 12.57 seconds
Started May 16 03:21:26 PM PDT 24
Finished May 16 03:21:45 PM PDT 24
Peak memory 204868 kb
Host smart-9d52da1d-7d87-48c7-96ce-abe36b0f5be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36746
51919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3674651919
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.651809856
Short name T793
Test name
Test status
Simulation time 8365621496 ps
CPU time 10.82 seconds
Started May 16 03:21:31 PM PDT 24
Finished May 16 03:21:51 PM PDT 24
Peak memory 204820 kb
Host smart-1e281d93-7098-4e63-9e2c-7cc182978819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65180
9856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.651809856
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2111225628
Short name T1579
Test name
Test status
Simulation time 8384538524 ps
CPU time 11.22 seconds
Started May 16 03:21:26 PM PDT 24
Finished May 16 03:21:45 PM PDT 24
Peak memory 204896 kb
Host smart-a4a7cb60-fc0d-4eb7-b526-46ce2c8602ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21112
25628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2111225628
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3816865775
Short name T630
Test name
Test status
Simulation time 9097114143 ps
CPU time 11.46 seconds
Started May 16 03:21:27 PM PDT 24
Finished May 16 03:21:46 PM PDT 24
Peak memory 204884 kb
Host smart-c3d0cdbc-82b6-4d21-84b6-b41bc18f9315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38168
65775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3816865775
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2410539762
Short name T893
Test name
Test status
Simulation time 8467060875 ps
CPU time 13.04 seconds
Started May 16 03:21:29 PM PDT 24
Finished May 16 03:21:51 PM PDT 24
Peak memory 204816 kb
Host smart-80f14e96-948f-470a-82ed-6b5e2eff0983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24105
39762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2410539762
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3577870048
Short name T1496
Test name
Test status
Simulation time 8402362309 ps
CPU time 11.89 seconds
Started May 16 03:21:39 PM PDT 24
Finished May 16 03:22:01 PM PDT 24
Peak memory 204824 kb
Host smart-80eb5240-eb84-4441-8f56-37f9af410c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35778
70048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3577870048
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3803854253
Short name T1662
Test name
Test status
Simulation time 8405648692 ps
CPU time 13.2 seconds
Started May 16 03:21:27 PM PDT 24
Finished May 16 03:21:48 PM PDT 24
Peak memory 204792 kb
Host smart-bc2f3024-b2f4-4028-801e-cca187a75a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38038
54253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3803854253
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3083324571
Short name T537
Test name
Test status
Simulation time 8456939258 ps
CPU time 11.13 seconds
Started May 16 03:21:25 PM PDT 24
Finished May 16 03:21:43 PM PDT 24
Peak memory 204700 kb
Host smart-52f9f2de-3031-476b-bfc9-89243f2de0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30833
24571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3083324571
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3519791937
Short name T996
Test name
Test status
Simulation time 11530249282 ps
CPU time 15.91 seconds
Started May 16 03:21:33 PM PDT 24
Finished May 16 03:21:58 PM PDT 24
Peak memory 204852 kb
Host smart-c75337a5-802c-4bbd-8745-182cf05cb66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35197
91937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3519791937
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1492433153
Short name T784
Test name
Test status
Simulation time 8418721118 ps
CPU time 11.42 seconds
Started May 16 03:21:28 PM PDT 24
Finished May 16 03:21:47 PM PDT 24
Peak memory 204832 kb
Host smart-8dbdf57d-8378-4659-bd5f-52f0089cbd2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14924
33153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1492433153
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.110089722
Short name T1612
Test name
Test status
Simulation time 8375369854 ps
CPU time 12.89 seconds
Started May 16 03:21:25 PM PDT 24
Finished May 16 03:21:45 PM PDT 24
Peak memory 204840 kb
Host smart-d552dab1-fa97-4780-9333-79db4e4d960e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11008
9722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.110089722
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3679160206
Short name T143
Test name
Test status
Simulation time 8441309173 ps
CPU time 10.82 seconds
Started May 16 03:21:27 PM PDT 24
Finished May 16 03:21:46 PM PDT 24
Peak memory 204804 kb
Host smart-0479101b-b2cc-4cf3-b5f4-e94a77ee1aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36791
60206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3679160206
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.666211188
Short name T1058
Test name
Test status
Simulation time 8414460364 ps
CPU time 12.99 seconds
Started May 16 03:21:31 PM PDT 24
Finished May 16 03:21:53 PM PDT 24
Peak memory 204796 kb
Host smart-642d6855-81cb-46aa-b8f5-1ec0d9826d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66621
1188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.666211188
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2948015582
Short name T1056
Test name
Test status
Simulation time 8389454841 ps
CPU time 11.98 seconds
Started May 16 03:21:30 PM PDT 24
Finished May 16 03:21:51 PM PDT 24
Peak memory 204848 kb
Host smart-29b0a343-8f38-4322-a828-d3f4d9713979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29480
15582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2948015582
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2940485035
Short name T1633
Test name
Test status
Simulation time 8377726163 ps
CPU time 12 seconds
Started May 16 03:21:36 PM PDT 24
Finished May 16 03:21:58 PM PDT 24
Peak memory 204816 kb
Host smart-8b033d3d-4df1-4a39-b0cc-411e6ba1953a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29404
85035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2940485035
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.2394549419
Short name T228
Test name
Test status
Simulation time 8418858135 ps
CPU time 10.91 seconds
Started May 16 03:21:33 PM PDT 24
Finished May 16 03:21:54 PM PDT 24
Peak memory 204876 kb
Host smart-4f5283cb-4e1a-4dc9-b4f0-2ee1f0937836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23945
49419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.2394549419
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.869315975
Short name T1269
Test name
Test status
Simulation time 8369951102 ps
CPU time 11.15 seconds
Started May 16 03:21:36 PM PDT 24
Finished May 16 03:21:57 PM PDT 24
Peak memory 204896 kb
Host smart-55e9b6b4-ad83-4fc3-9e01-01fd89250c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86931
5975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.869315975
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.744288339
Short name T422
Test name
Test status
Simulation time 8372475396 ps
CPU time 12.13 seconds
Started May 16 03:21:36 PM PDT 24
Finished May 16 03:21:58 PM PDT 24
Peak memory 204860 kb
Host smart-2e2d581e-cc31-464c-8231-8b6c58bdc6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74428
8339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.744288339
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3132266026
Short name T1731
Test name
Test status
Simulation time 19518286428 ps
CPU time 33.86 seconds
Started May 16 03:21:34 PM PDT 24
Finished May 16 03:22:17 PM PDT 24
Peak memory 204876 kb
Host smart-f53f1e1d-8368-4d18-9bc0-b01c9bd2821d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31322
66026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3132266026
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.702475862
Short name T340
Test name
Test status
Simulation time 8382967117 ps
CPU time 14.67 seconds
Started May 16 03:21:37 PM PDT 24
Finished May 16 03:22:02 PM PDT 24
Peak memory 204904 kb
Host smart-db388185-a780-49b1-9b1d-a70461f93d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70247
5862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.702475862
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.888852701
Short name T587
Test name
Test status
Simulation time 8443826783 ps
CPU time 13.93 seconds
Started May 16 03:21:34 PM PDT 24
Finished May 16 03:21:57 PM PDT 24
Peak memory 204828 kb
Host smart-7c33c0e1-a666-479b-8189-9c5397cbe7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88885
2701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.888852701
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.371087136
Short name T347
Test name
Test status
Simulation time 8412552258 ps
CPU time 11.9 seconds
Started May 16 03:21:37 PM PDT 24
Finished May 16 03:21:59 PM PDT 24
Peak memory 204864 kb
Host smart-dc6a0cb2-9bde-47df-bab5-0f63f2460ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37108
7136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.371087136
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.745167651
Short name T725
Test name
Test status
Simulation time 8383173639 ps
CPU time 11.82 seconds
Started May 16 03:21:33 PM PDT 24
Finished May 16 03:21:54 PM PDT 24
Peak memory 204768 kb
Host smart-e470d50f-9d29-4eb2-9cac-d2755775f7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74516
7651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.745167651
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1375203046
Short name T1600
Test name
Test status
Simulation time 8388881745 ps
CPU time 10.97 seconds
Started May 16 03:21:35 PM PDT 24
Finished May 16 03:21:55 PM PDT 24
Peak memory 204852 kb
Host smart-008a7b94-25dc-4da2-8b04-5f8e71f5dc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13752
03046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1375203046
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2942424904
Short name T1265
Test name
Test status
Simulation time 8370587978 ps
CPU time 13.25 seconds
Started May 16 03:21:34 PM PDT 24
Finished May 16 03:21:56 PM PDT 24
Peak memory 204816 kb
Host smart-126ddd25-1ae2-4d9c-bf98-e256fe4b6f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29424
24904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2942424904
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3645285537
Short name T1500
Test name
Test status
Simulation time 8455424081 ps
CPU time 11.34 seconds
Started May 16 03:21:31 PM PDT 24
Finished May 16 03:21:51 PM PDT 24
Peak memory 204824 kb
Host smart-1bf7357f-c31a-47dc-b5b6-acc399658d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36452
85537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3645285537
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.826160692
Short name T1275
Test name
Test status
Simulation time 8400044463 ps
CPU time 10.58 seconds
Started May 16 03:21:33 PM PDT 24
Finished May 16 03:21:53 PM PDT 24
Peak memory 204828 kb
Host smart-9f7a7ce1-5035-43ff-aff2-a152b602473f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82616
0692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.826160692
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1279744112
Short name T1396
Test name
Test status
Simulation time 8391554536 ps
CPU time 13.02 seconds
Started May 16 03:21:34 PM PDT 24
Finished May 16 03:21:57 PM PDT 24
Peak memory 204904 kb
Host smart-961c94fc-bff0-4f58-b34e-a7c4962906e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12797
44112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1279744112
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.1800763124
Short name T1605
Test name
Test status
Simulation time 8472078425 ps
CPU time 11.47 seconds
Started May 16 03:21:39 PM PDT 24
Finished May 16 03:22:00 PM PDT 24
Peak memory 204884 kb
Host smart-1ab50d16-f3fe-4291-b1d1-f9dbb6b97166
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1800763124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.1800763124
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.3919777138
Short name T535
Test name
Test status
Simulation time 8383355237 ps
CPU time 12.19 seconds
Started May 16 03:21:45 PM PDT 24
Finished May 16 03:22:07 PM PDT 24
Peak memory 204872 kb
Host smart-cd6655ca-fe0b-431d-ab96-4b7fa4a1d8b8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3919777138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.3919777138
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.1703631216
Short name T815
Test name
Test status
Simulation time 8414964121 ps
CPU time 10.88 seconds
Started May 16 03:21:44 PM PDT 24
Finished May 16 03:22:06 PM PDT 24
Peak memory 204796 kb
Host smart-f3a75e15-0717-4e81-82f5-f6573b4746e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17036
31216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.1703631216
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.522919358
Short name T563
Test name
Test status
Simulation time 8380572287 ps
CPU time 11.28 seconds
Started May 16 03:21:35 PM PDT 24
Finished May 16 03:21:55 PM PDT 24
Peak memory 204860 kb
Host smart-41f248ee-1ae8-4a4e-8332-ae219487a21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52291
9358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.522919358
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.227338381
Short name T1144
Test name
Test status
Simulation time 9081585311 ps
CPU time 12.9 seconds
Started May 16 03:21:33 PM PDT 24
Finished May 16 03:21:56 PM PDT 24
Peak memory 204916 kb
Host smart-0a042db4-08d7-4eb5-b865-fd8f630b1bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22733
8381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.227338381
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.3382652877
Short name T1208
Test name
Test status
Simulation time 8367336813 ps
CPU time 12.46 seconds
Started May 16 03:21:38 PM PDT 24
Finished May 16 03:22:00 PM PDT 24
Peak memory 204780 kb
Host smart-b38c0dc5-4085-4a8c-ac63-af4a0327419b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33826
52877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.3382652877
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2148701018
Short name T930
Test name
Test status
Simulation time 8398348470 ps
CPU time 11.44 seconds
Started May 16 03:21:36 PM PDT 24
Finished May 16 03:21:58 PM PDT 24
Peak memory 204912 kb
Host smart-3f548dd9-38cf-4991-b389-835d9fec39f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21487
01018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2148701018
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2577368515
Short name T492
Test name
Test status
Simulation time 8392301897 ps
CPU time 13.37 seconds
Started May 16 03:21:36 PM PDT 24
Finished May 16 03:21:59 PM PDT 24
Peak memory 204812 kb
Host smart-439c031e-290c-4e2b-bdfa-49906e412803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25773
68515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2577368515
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3954457326
Short name T1595
Test name
Test status
Simulation time 8419188768 ps
CPU time 11.89 seconds
Started May 16 03:21:42 PM PDT 24
Finished May 16 03:22:04 PM PDT 24
Peak memory 204920 kb
Host smart-4a8d1b1f-a8ab-41f8-b70d-997710dcf812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39544
57326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3954457326
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.596931830
Short name T1019
Test name
Test status
Simulation time 8367649939 ps
CPU time 12.99 seconds
Started May 16 03:21:41 PM PDT 24
Finished May 16 03:22:03 PM PDT 24
Peak memory 204800 kb
Host smart-61ae9d5b-4e7c-4e07-8577-68c0f131606e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59693
1830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.596931830
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.4070567263
Short name T692
Test name
Test status
Simulation time 8452805149 ps
CPU time 12.47 seconds
Started May 16 03:21:37 PM PDT 24
Finished May 16 03:21:59 PM PDT 24
Peak memory 204928 kb
Host smart-2441b618-098e-481d-b584-41fedaeac861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40705
67263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.4070567263
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2007246736
Short name T1382
Test name
Test status
Simulation time 8380733324 ps
CPU time 12.48 seconds
Started May 16 03:21:36 PM PDT 24
Finished May 16 03:21:59 PM PDT 24
Peak memory 204856 kb
Host smart-d9569a7f-531f-46f3-be4a-ef2e08ec3309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20072
46736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2007246736
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.1563149214
Short name T6
Test name
Test status
Simulation time 11541467274 ps
CPU time 15.79 seconds
Started May 16 03:21:40 PM PDT 24
Finished May 16 03:22:05 PM PDT 24
Peak memory 204820 kb
Host smart-9f229912-48ac-4ba7-80ba-485b96b8b558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15631
49214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1563149214
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3418213297
Short name T389
Test name
Test status
Simulation time 8411842689 ps
CPU time 11.87 seconds
Started May 16 03:21:38 PM PDT 24
Finished May 16 03:22:00 PM PDT 24
Peak memory 204828 kb
Host smart-783e763a-44c0-4f24-a4c1-9262ab7cbf02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34182
13297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3418213297
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2786837958
Short name T383
Test name
Test status
Simulation time 8438504609 ps
CPU time 11.94 seconds
Started May 16 03:21:40 PM PDT 24
Finished May 16 03:22:01 PM PDT 24
Peak memory 204748 kb
Host smart-2636288a-a0ff-488a-bf90-555c31e72532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27868
37958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2786837958
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2552421313
Short name T124
Test name
Test status
Simulation time 8410512245 ps
CPU time 12.28 seconds
Started May 16 03:21:43 PM PDT 24
Finished May 16 03:22:05 PM PDT 24
Peak memory 204788 kb
Host smart-22ce0f67-df58-496c-a380-12b744118894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
21313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2552421313
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1050316921
Short name T1256
Test name
Test status
Simulation time 8416302244 ps
CPU time 11.85 seconds
Started May 16 03:21:41 PM PDT 24
Finished May 16 03:22:02 PM PDT 24
Peak memory 204872 kb
Host smart-5432cae7-03b3-4e87-a796-19280a7da06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10503
16921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1050316921
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.826281591
Short name T554
Test name
Test status
Simulation time 8383970115 ps
CPU time 12.22 seconds
Started May 16 03:21:40 PM PDT 24
Finished May 16 03:22:02 PM PDT 24
Peak memory 204892 kb
Host smart-0445f7ab-ac29-4cc8-9ebe-ee02f7ee2464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82628
1591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.826281591
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2235519902
Short name T1209
Test name
Test status
Simulation time 8401089625 ps
CPU time 11.67 seconds
Started May 16 03:21:43 PM PDT 24
Finished May 16 03:22:05 PM PDT 24
Peak memory 204800 kb
Host smart-44c20b17-f1b0-4a7f-9d13-9c010390e921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22355
19902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2235519902
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.1311641347
Short name T766
Test name
Test status
Simulation time 8382672287 ps
CPU time 10.89 seconds
Started May 16 03:21:40 PM PDT 24
Finished May 16 03:22:00 PM PDT 24
Peak memory 204816 kb
Host smart-af04ea97-f783-40f3-a9dc-db257c03da91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13116
41347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.1311641347
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2359041040
Short name T523
Test name
Test status
Simulation time 8368513811 ps
CPU time 13.48 seconds
Started May 16 03:21:43 PM PDT 24
Finished May 16 03:22:07 PM PDT 24
Peak memory 204784 kb
Host smart-e9d883bb-2cac-4b29-8ea7-d5cb74df7e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23590
41040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2359041040
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3896974762
Short name T636
Test name
Test status
Simulation time 8377391685 ps
CPU time 12.06 seconds
Started May 16 03:21:41 PM PDT 24
Finished May 16 03:22:02 PM PDT 24
Peak memory 204864 kb
Host smart-2b1a1336-1c99-4c40-a567-1e1799c0916f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38969
74762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3896974762
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1333601948
Short name T254
Test name
Test status
Simulation time 14360052118 ps
CPU time 28.27 seconds
Started May 16 03:21:39 PM PDT 24
Finished May 16 03:22:17 PM PDT 24
Peak memory 204808 kb
Host smart-f99557fd-bbe1-4efd-b53b-528b05345b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13336
01948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1333601948
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2150092345
Short name T496
Test name
Test status
Simulation time 8397502459 ps
CPU time 11.89 seconds
Started May 16 03:21:43 PM PDT 24
Finished May 16 03:22:05 PM PDT 24
Peak memory 204744 kb
Host smart-01e1fa57-8bc2-49e6-90f1-60ac8e0e7dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21500
92345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2150092345
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1196624307
Short name T1292
Test name
Test status
Simulation time 8413609921 ps
CPU time 10.82 seconds
Started May 16 03:21:44 PM PDT 24
Finished May 16 03:22:05 PM PDT 24
Peak memory 204888 kb
Host smart-cc100242-e9d9-469a-b05b-e2dabf6ce5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11966
24307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1196624307
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.2820982239
Short name T91
Test name
Test status
Simulation time 8400817444 ps
CPU time 12.55 seconds
Started May 16 03:21:41 PM PDT 24
Finished May 16 03:22:03 PM PDT 24
Peak memory 204680 kb
Host smart-ea388a45-33eb-4634-9a9b-f7ce8116a192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28209
82239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.2820982239
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.4174418087
Short name T419
Test name
Test status
Simulation time 8371734251 ps
CPU time 10.55 seconds
Started May 16 03:21:42 PM PDT 24
Finished May 16 03:22:03 PM PDT 24
Peak memory 204872 kb
Host smart-1c7cf0d3-3015-4f27-816a-638a9435a4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41744
18087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.4174418087
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.124180665
Short name T1184
Test name
Test status
Simulation time 8376516987 ps
CPU time 13.13 seconds
Started May 16 03:21:41 PM PDT 24
Finished May 16 03:22:04 PM PDT 24
Peak memory 204836 kb
Host smart-39a48882-a0bc-43ae-8640-a87d9319455f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12418
0665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.124180665
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3231911034
Short name T1384
Test name
Test status
Simulation time 8368587704 ps
CPU time 11.02 seconds
Started May 16 03:21:42 PM PDT 24
Finished May 16 03:22:03 PM PDT 24
Peak memory 204668 kb
Host smart-d8163afa-8c16-433b-9634-31b700175f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32319
11034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3231911034
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.4170918409
Short name T158
Test name
Test status
Simulation time 8470091485 ps
CPU time 10.76 seconds
Started May 16 03:21:34 PM PDT 24
Finished May 16 03:21:54 PM PDT 24
Peak memory 204908 kb
Host smart-df74b8f5-f553-4ffc-986d-8c44ed14d5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41709
18409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.4170918409
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2770616100
Short name T241
Test name
Test status
Simulation time 8411897568 ps
CPU time 12.03 seconds
Started May 16 03:21:44 PM PDT 24
Finished May 16 03:22:07 PM PDT 24
Peak memory 204860 kb
Host smart-a10b9268-5995-4324-9395-cd3752834052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27706
16100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2770616100
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3226486574
Short name T1371
Test name
Test status
Simulation time 8400057378 ps
CPU time 12.76 seconds
Started May 16 03:21:39 PM PDT 24
Finished May 16 03:22:01 PM PDT 24
Peak memory 204796 kb
Host smart-ade58a2c-a1f0-4636-816f-c8f77162105c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32264
86574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3226486574
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.1217077880
Short name T311
Test name
Test status
Simulation time 8468095474 ps
CPU time 12.41 seconds
Started May 16 03:19:06 PM PDT 24
Finished May 16 03:19:24 PM PDT 24
Peak memory 204832 kb
Host smart-0ada3080-924a-445b-841c-9e848975d77f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1217077880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.1217077880
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.1382892964
Short name T709
Test name
Test status
Simulation time 8402730503 ps
CPU time 12.01 seconds
Started May 16 03:19:07 PM PDT 24
Finished May 16 03:19:24 PM PDT 24
Peak memory 204868 kb
Host smart-e2e4fb65-7328-4556-b1b8-6cc047626a63
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1382892964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.1382892964
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.651411699
Short name T344
Test name
Test status
Simulation time 8404891721 ps
CPU time 10.88 seconds
Started May 16 03:19:10 PM PDT 24
Finished May 16 03:19:26 PM PDT 24
Peak memory 204800 kb
Host smart-6b2ced96-b104-412d-a1e6-4cbfb05bad41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65141
1699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.651411699
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2655405871
Short name T401
Test name
Test status
Simulation time 8433363317 ps
CPU time 11.89 seconds
Started May 16 03:18:56 PM PDT 24
Finished May 16 03:19:14 PM PDT 24
Peak memory 204860 kb
Host smart-51464e8e-3d98-4045-839d-0ef20d75d092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26554
05871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2655405871
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2415271153
Short name T1177
Test name
Test status
Simulation time 8773580058 ps
CPU time 13.6 seconds
Started May 16 03:19:03 PM PDT 24
Finished May 16 03:19:21 PM PDT 24
Peak memory 204860 kb
Host smart-30cc9109-e782-4323-bd8c-dd2b5d95b725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24152
71153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2415271153
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2332960590
Short name T978
Test name
Test status
Simulation time 8363187981 ps
CPU time 11.15 seconds
Started May 16 03:18:59 PM PDT 24
Finished May 16 03:19:16 PM PDT 24
Peak memory 204852 kb
Host smart-f3f68db5-0efc-49fb-9b67-efdbe8bc18ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23329
60590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2332960590
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2843518113
Short name T388
Test name
Test status
Simulation time 8388417141 ps
CPU time 12.66 seconds
Started May 16 03:18:58 PM PDT 24
Finished May 16 03:19:16 PM PDT 24
Peak memory 204784 kb
Host smart-5fd4f976-364d-4dc7-a8f7-73cae904b1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28435
18113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2843518113
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1382046369
Short name T355
Test name
Test status
Simulation time 9059199042 ps
CPU time 11.92 seconds
Started May 16 03:18:59 PM PDT 24
Finished May 16 03:19:16 PM PDT 24
Peak memory 204792 kb
Host smart-5ed89de4-135f-46d9-b725-712cebd8ad7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13820
46369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1382046369
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1884147602
Short name T416
Test name
Test status
Simulation time 8445920377 ps
CPU time 12.9 seconds
Started May 16 03:19:04 PM PDT 24
Finished May 16 03:19:20 PM PDT 24
Peak memory 204836 kb
Host smart-d54acfab-ebef-48f2-9a4d-4eb27660e5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18841
47602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1884147602
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2636964718
Short name T457
Test name
Test status
Simulation time 8450264971 ps
CPU time 11.56 seconds
Started May 16 03:19:05 PM PDT 24
Finished May 16 03:19:22 PM PDT 24
Peak memory 204776 kb
Host smart-a9d325ab-9f49-4c3c-a574-b49864acfa8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26369
64718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2636964718
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.711964715
Short name T989
Test name
Test status
Simulation time 8374155091 ps
CPU time 11.07 seconds
Started May 16 03:19:08 PM PDT 24
Finished May 16 03:19:25 PM PDT 24
Peak memory 204892 kb
Host smart-7da2420e-89af-4a6f-bf85-122cc6c4e376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71196
4715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.711964715
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.26536660
Short name T1593
Test name
Test status
Simulation time 8423789313 ps
CPU time 11.96 seconds
Started May 16 03:18:56 PM PDT 24
Finished May 16 03:19:14 PM PDT 24
Peak memory 204856 kb
Host smart-b151794f-c26d-4a24-97e1-f382efd5d262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26536
660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.26536660
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.185496914
Short name T915
Test name
Test status
Simulation time 11549429474 ps
CPU time 14.29 seconds
Started May 16 03:19:01 PM PDT 24
Finished May 16 03:19:20 PM PDT 24
Peak memory 204840 kb
Host smart-da6d0baa-d4d1-4df2-92d1-f3d2bd0dd1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18549
6914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.185496914
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3398996656
Short name T93
Test name
Test status
Simulation time 8455001229 ps
CPU time 11.72 seconds
Started May 16 03:18:57 PM PDT 24
Finished May 16 03:19:15 PM PDT 24
Peak memory 204824 kb
Host smart-628066cd-6289-4711-8311-fb3eca5b5aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33989
96656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3398996656
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2760295308
Short name T1399
Test name
Test status
Simulation time 8381575115 ps
CPU time 13.79 seconds
Started May 16 03:18:58 PM PDT 24
Finished May 16 03:19:17 PM PDT 24
Peak memory 204852 kb
Host smart-7c8c7edc-20f6-47b1-9b89-eafca4a912eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27602
95308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2760295308
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1862414693
Short name T1380
Test name
Test status
Simulation time 8510257982 ps
CPU time 10.94 seconds
Started May 16 03:18:59 PM PDT 24
Finished May 16 03:19:15 PM PDT 24
Peak memory 204924 kb
Host smart-94ff2994-8286-4e17-88ad-61b9cfc4abd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18624
14693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1862414693
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.396061777
Short name T106
Test name
Test status
Simulation time 8460517390 ps
CPU time 11.95 seconds
Started May 16 03:18:58 PM PDT 24
Finished May 16 03:19:16 PM PDT 24
Peak memory 204928 kb
Host smart-6049ea91-bea5-4c4a-80f4-cd6280619b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39606
1777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.396061777
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.543687859
Short name T1658
Test name
Test status
Simulation time 8391114669 ps
CPU time 11.36 seconds
Started May 16 03:18:56 PM PDT 24
Finished May 16 03:19:13 PM PDT 24
Peak memory 204840 kb
Host smart-9f1ee047-2961-4050-a9c6-b5dd95c99c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54368
7859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.543687859
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2062679069
Short name T462
Test name
Test status
Simulation time 8406748570 ps
CPU time 13.98 seconds
Started May 16 03:18:57 PM PDT 24
Finished May 16 03:19:17 PM PDT 24
Peak memory 204820 kb
Host smart-0918c890-4a49-46f8-9dfe-0cdf7fad781c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20626
79069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2062679069
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.4234797418
Short name T595
Test name
Test status
Simulation time 8438884905 ps
CPU time 13.18 seconds
Started May 16 03:19:08 PM PDT 24
Finished May 16 03:19:27 PM PDT 24
Peak memory 204840 kb
Host smart-6a75fcdd-c929-4633-b5b0-00382a753c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42347
97418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.4234797418
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1473059354
Short name T828
Test name
Test status
Simulation time 8376646506 ps
CPU time 10.84 seconds
Started May 16 03:19:08 PM PDT 24
Finished May 16 03:19:25 PM PDT 24
Peak memory 204832 kb
Host smart-f03467ae-a1fc-4489-bdc3-aecbb8a44be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14730
59354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1473059354
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.510052046
Short name T14
Test name
Test status
Simulation time 8373900207 ps
CPU time 11.22 seconds
Started May 16 03:19:09 PM PDT 24
Finished May 16 03:19:26 PM PDT 24
Peak memory 204768 kb
Host smart-925047b9-fa04-44af-82ad-ab4f460ac0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51005
2046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.510052046
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1376442771
Short name T274
Test name
Test status
Simulation time 22720388666 ps
CPU time 48.21 seconds
Started May 16 03:18:57 PM PDT 24
Finished May 16 03:19:51 PM PDT 24
Peak memory 204896 kb
Host smart-f5ae580f-61a0-408a-86e0-fb72bc770958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13764
42771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1376442771
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1964339307
Short name T1211
Test name
Test status
Simulation time 8424851872 ps
CPU time 13.3 seconds
Started May 16 03:19:07 PM PDT 24
Finished May 16 03:19:26 PM PDT 24
Peak memory 204876 kb
Host smart-f68f0156-d3d1-45ca-8227-b529b418d9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19643
39307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1964339307
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3965893163
Short name T149
Test name
Test status
Simulation time 8411780535 ps
CPU time 12.09 seconds
Started May 16 03:19:10 PM PDT 24
Finished May 16 03:19:27 PM PDT 24
Peak memory 204780 kb
Host smart-5245b5d2-d35d-47f2-b3ec-effb75dd2f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39658
93163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3965893163
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.2320149783
Short name T1660
Test name
Test status
Simulation time 8407694338 ps
CPU time 14.23 seconds
Started May 16 03:19:07 PM PDT 24
Finished May 16 03:19:27 PM PDT 24
Peak memory 204732 kb
Host smart-d12ffd16-326f-4474-94df-4c597e81675b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23201
49783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.2320149783
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.2286631185
Short name T1304
Test name
Test status
Simulation time 8436869460 ps
CPU time 12.69 seconds
Started May 16 03:19:08 PM PDT 24
Finished May 16 03:19:26 PM PDT 24
Peak memory 204900 kb
Host smart-28b63bec-a349-4063-aa0d-770272a2bb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22866
31185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.2286631185
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1734847651
Short name T85
Test name
Test status
Simulation time 202806152 ps
CPU time 1.01 seconds
Started May 16 03:19:06 PM PDT 24
Finished May 16 03:19:13 PM PDT 24
Peak memory 220640 kb
Host smart-2cc7cfb7-b01c-4b5d-8406-9860de4a1d7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1734847651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1734847651
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2358861700
Short name T177
Test name
Test status
Simulation time 8379479857 ps
CPU time 11.68 seconds
Started May 16 03:19:09 PM PDT 24
Finished May 16 03:19:26 PM PDT 24
Peak memory 204800 kb
Host smart-5f79a151-5cb2-4659-a357-4c50991028e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23588
61700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2358861700
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2789703875
Short name T1351
Test name
Test status
Simulation time 8376153319 ps
CPU time 11.35 seconds
Started May 16 03:19:06 PM PDT 24
Finished May 16 03:19:23 PM PDT 24
Peak memory 204836 kb
Host smart-a5a4a975-e645-4fe8-85fe-d8000fe95d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27897
03875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2789703875
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.889559170
Short name T1697
Test name
Test status
Simulation time 8450256425 ps
CPU time 13.44 seconds
Started May 16 03:18:59 PM PDT 24
Finished May 16 03:19:18 PM PDT 24
Peak memory 204812 kb
Host smart-c9f9d88d-c684-4e09-aeb5-82ec47d3b638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88955
9170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.889559170
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1716667610
Short name T823
Test name
Test status
Simulation time 8369639149 ps
CPU time 11.04 seconds
Started May 16 03:19:06 PM PDT 24
Finished May 16 03:19:22 PM PDT 24
Peak memory 204936 kb
Host smart-30bb6c1b-c4c8-4071-9b92-842a7c00ee26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17166
67610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1716667610
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.799621946
Short name T1553
Test name
Test status
Simulation time 8429294256 ps
CPU time 13.01 seconds
Started May 16 03:19:05 PM PDT 24
Finished May 16 03:19:23 PM PDT 24
Peak memory 204840 kb
Host smart-dfb22985-27ac-452d-8b2f-d39a8bc4c0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79962
1946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.799621946
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.1674423159
Short name T540
Test name
Test status
Simulation time 8469948720 ps
CPU time 14.04 seconds
Started May 16 03:21:49 PM PDT 24
Finished May 16 03:22:13 PM PDT 24
Peak memory 204872 kb
Host smart-4889d68c-43fe-41e6-b532-5e581e9432f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1674423159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.1674423159
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.2232351294
Short name T988
Test name
Test status
Simulation time 8406164627 ps
CPU time 10.72 seconds
Started May 16 03:21:48 PM PDT 24
Finished May 16 03:22:10 PM PDT 24
Peak memory 204884 kb
Host smart-187f5259-af61-4df7-832a-cd4153579475
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2232351294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.2232351294
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.2310306426
Short name T1241
Test name
Test status
Simulation time 8461443825 ps
CPU time 12 seconds
Started May 16 03:21:49 PM PDT 24
Finished May 16 03:22:11 PM PDT 24
Peak memory 204852 kb
Host smart-f7e99eb1-8b38-4c75-aab8-16170ee6bf80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23103
06426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.2310306426
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.4030085653
Short name T435
Test name
Test status
Simulation time 8376856902 ps
CPU time 11.76 seconds
Started May 16 03:21:40 PM PDT 24
Finished May 16 03:22:02 PM PDT 24
Peak memory 204776 kb
Host smart-f4d61507-3799-4de4-a110-a639ac19f84e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40300
85653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.4030085653
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2454686815
Short name T203
Test name
Test status
Simulation time 8927275028 ps
CPU time 13.14 seconds
Started May 16 03:21:41 PM PDT 24
Finished May 16 03:22:04 PM PDT 24
Peak memory 204928 kb
Host smart-b97ec0e7-b756-44e4-b238-7991afee547b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24546
86815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2454686815
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3196791219
Short name T1548
Test name
Test status
Simulation time 8362341259 ps
CPU time 12.35 seconds
Started May 16 03:21:47 PM PDT 24
Finished May 16 03:22:09 PM PDT 24
Peak memory 204820 kb
Host smart-cf27cb77-5b47-44c8-9822-8277a2385c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31967
91219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3196791219
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3212821836
Short name T1448
Test name
Test status
Simulation time 8385073023 ps
CPU time 11.5 seconds
Started May 16 03:21:40 PM PDT 24
Finished May 16 03:22:01 PM PDT 24
Peak memory 204908 kb
Host smart-d69a1257-1360-49b6-97b0-2d5fde84536f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32128
21836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3212821836
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.782341763
Short name T428
Test name
Test status
Simulation time 9072807825 ps
CPU time 13.89 seconds
Started May 16 03:21:41 PM PDT 24
Finished May 16 03:22:05 PM PDT 24
Peak memory 204784 kb
Host smart-01716eb8-17d8-4ed5-9c7b-9f691a3473f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78234
1763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.782341763
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2268582299
Short name T1466
Test name
Test status
Simulation time 8468638582 ps
CPU time 12.53 seconds
Started May 16 03:21:43 PM PDT 24
Finished May 16 03:22:06 PM PDT 24
Peak memory 204736 kb
Host smart-620ed523-1706-419b-b953-af77dbd6c99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22685
82299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2268582299
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.880466721
Short name T162
Test name
Test status
Simulation time 8469290953 ps
CPU time 12.56 seconds
Started May 16 03:21:49 PM PDT 24
Finished May 16 03:22:13 PM PDT 24
Peak memory 204864 kb
Host smart-1ee6a75d-3ec1-47e6-8f0a-bb7fa5d99446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88046
6721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.880466721
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3857878559
Short name T50
Test name
Test status
Simulation time 8366970678 ps
CPU time 13.17 seconds
Started May 16 03:21:50 PM PDT 24
Finished May 16 03:22:14 PM PDT 24
Peak memory 204856 kb
Host smart-d75a9afe-0b59-49a0-8f81-9ec291b50689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38578
78559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3857878559
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.967965574
Short name T856
Test name
Test status
Simulation time 8455872183 ps
CPU time 10.73 seconds
Started May 16 03:21:42 PM PDT 24
Finished May 16 03:22:03 PM PDT 24
Peak memory 204776 kb
Host smart-14914183-4363-494d-81ab-75bd1b4ddb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96796
5574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.967965574
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3983477547
Short name T223
Test name
Test status
Simulation time 8413665338 ps
CPU time 12.16 seconds
Started May 16 03:21:40 PM PDT 24
Finished May 16 03:22:02 PM PDT 24
Peak memory 204868 kb
Host smart-685da69d-4222-4604-b38b-7783cf91f75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39834
77547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3983477547
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3986817044
Short name T890
Test name
Test status
Simulation time 11516133354 ps
CPU time 13.02 seconds
Started May 16 03:21:43 PM PDT 24
Finished May 16 03:22:07 PM PDT 24
Peak memory 204816 kb
Host smart-a4ea179c-1495-46bf-9f7a-39ac36895815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39868
17044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3986817044
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.4130325092
Short name T1743
Test name
Test status
Simulation time 8441300749 ps
CPU time 11.66 seconds
Started May 16 03:21:40 PM PDT 24
Finished May 16 03:22:01 PM PDT 24
Peak memory 204744 kb
Host smart-3c359818-02b4-4498-a3e1-21a45161529a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41303
25092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.4130325092
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2635349455
Short name T369
Test name
Test status
Simulation time 8400853715 ps
CPU time 13.15 seconds
Started May 16 03:21:40 PM PDT 24
Finished May 16 03:22:03 PM PDT 24
Peak memory 204836 kb
Host smart-98a26b00-0753-4f33-a3fc-095cbbd75968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26353
49455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2635349455
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.164991570
Short name T1461
Test name
Test status
Simulation time 8441662128 ps
CPU time 12.53 seconds
Started May 16 03:21:51 PM PDT 24
Finished May 16 03:22:15 PM PDT 24
Peak memory 204872 kb
Host smart-38651e66-6529-419d-b2d4-5442f05a81b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16499
1570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.164991570
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.4249222488
Short name T343
Test name
Test status
Simulation time 8414615804 ps
CPU time 11.81 seconds
Started May 16 03:21:47 PM PDT 24
Finished May 16 03:22:09 PM PDT 24
Peak memory 204900 kb
Host smart-9adb5dd7-993d-4b7d-8e1a-43a09ee0a7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42492
22488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.4249222488
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2891157123
Short name T495
Test name
Test status
Simulation time 8399254117 ps
CPU time 11.66 seconds
Started May 16 03:21:48 PM PDT 24
Finished May 16 03:22:10 PM PDT 24
Peak memory 204872 kb
Host smart-516b7724-853b-4b80-925c-9f39961fd14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28911
57123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2891157123
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.175160643
Short name T1691
Test name
Test status
Simulation time 8382337847 ps
CPU time 11.38 seconds
Started May 16 03:21:48 PM PDT 24
Finished May 16 03:22:10 PM PDT 24
Peak memory 204824 kb
Host smart-e7b2d23c-f66a-472b-851a-c77666ec39c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17516
0643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.175160643
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.1829358527
Short name T869
Test name
Test status
Simulation time 8434651125 ps
CPU time 10.99 seconds
Started May 16 03:21:52 PM PDT 24
Finished May 16 03:22:14 PM PDT 24
Peak memory 204768 kb
Host smart-d9014f0b-d3ca-435d-9c2c-d2aadcf9b03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18293
58527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.1829358527
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3609966476
Short name T482
Test name
Test status
Simulation time 8370945381 ps
CPU time 11.77 seconds
Started May 16 03:21:49 PM PDT 24
Finished May 16 03:22:11 PM PDT 24
Peak memory 204816 kb
Host smart-bc8ae132-4c0c-44a2-963f-c0301636d4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36099
66476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3609966476
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3762554028
Short name T857
Test name
Test status
Simulation time 8370533077 ps
CPU time 10.59 seconds
Started May 16 03:21:50 PM PDT 24
Finished May 16 03:22:12 PM PDT 24
Peak memory 204852 kb
Host smart-21a1d0b9-2fcb-4346-85ab-ccaf78291db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37625
54028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3762554028
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.4164762686
Short name T15
Test name
Test status
Simulation time 26507734707 ps
CPU time 52.03 seconds
Started May 16 03:21:51 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204848 kb
Host smart-a9a90d95-612c-41b0-b169-cf7fe7542e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41647
62686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.4164762686
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.299425417
Short name T747
Test name
Test status
Simulation time 8399669527 ps
CPU time 12.06 seconds
Started May 16 03:21:50 PM PDT 24
Finished May 16 03:22:13 PM PDT 24
Peak memory 204920 kb
Host smart-f2e98e5e-1dfa-4f3b-b194-12d0f3dd892f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29942
5417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.299425417
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3113219658
Short name T1481
Test name
Test status
Simulation time 8393981803 ps
CPU time 12.17 seconds
Started May 16 03:21:50 PM PDT 24
Finished May 16 03:22:13 PM PDT 24
Peak memory 204816 kb
Host smart-839b7771-36b9-4db7-aebc-5065173bfa0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31132
19658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3113219658
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3857097276
Short name T1193
Test name
Test status
Simulation time 8370148854 ps
CPU time 11.62 seconds
Started May 16 03:21:49 PM PDT 24
Finished May 16 03:22:11 PM PDT 24
Peak memory 204804 kb
Host smart-54921cbb-2fe5-4590-a729-23afe9145d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38570
97276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3857097276
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.934411107
Short name T46
Test name
Test status
Simulation time 8382616316 ps
CPU time 12.41 seconds
Started May 16 03:21:48 PM PDT 24
Finished May 16 03:22:10 PM PDT 24
Peak memory 204840 kb
Host smart-87e1d405-0292-4e93-8bc2-cbb881488147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93441
1107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.934411107
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.846216590
Short name T1338
Test name
Test status
Simulation time 8400802685 ps
CPU time 11.46 seconds
Started May 16 03:21:48 PM PDT 24
Finished May 16 03:22:10 PM PDT 24
Peak memory 204816 kb
Host smart-8c2c808a-c973-4d3c-8a41-b3ea44a8fdcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84621
6590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.846216590
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3464402084
Short name T1725
Test name
Test status
Simulation time 8466940680 ps
CPU time 14.68 seconds
Started May 16 03:21:39 PM PDT 24
Finished May 16 03:22:04 PM PDT 24
Peak memory 204840 kb
Host smart-eb21a7a5-725f-40bd-9fb4-79e6ffbd086a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34644
02084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3464402084
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2773208737
Short name T378
Test name
Test status
Simulation time 8420598332 ps
CPU time 12.12 seconds
Started May 16 03:21:48 PM PDT 24
Finished May 16 03:22:11 PM PDT 24
Peak memory 204896 kb
Host smart-7ac8f42d-f7dc-4287-8ad2-2577ffd43793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27732
08737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2773208737
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2937098713
Short name T1477
Test name
Test status
Simulation time 8448046453 ps
CPU time 11.23 seconds
Started May 16 03:21:47 PM PDT 24
Finished May 16 03:22:08 PM PDT 24
Peak memory 204668 kb
Host smart-d038f987-a7f1-44a2-bef3-1a9b1fa28bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29370
98713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2937098713
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.393733086
Short name T1239
Test name
Test status
Simulation time 8469996704 ps
CPU time 10.85 seconds
Started May 16 03:22:08 PM PDT 24
Finished May 16 03:22:30 PM PDT 24
Peak memory 204844 kb
Host smart-159f6b16-5d1a-436f-9fe5-3158a7371ff2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=393733086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.393733086
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.1114126447
Short name T1358
Test name
Test status
Simulation time 8378162768 ps
CPU time 12.37 seconds
Started May 16 03:22:05 PM PDT 24
Finished May 16 03:22:28 PM PDT 24
Peak memory 204904 kb
Host smart-f47a401e-9e77-497c-92f5-3bc8dda49eb0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1114126447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.1114126447
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.2199692803
Short name T365
Test name
Test status
Simulation time 8445403630 ps
CPU time 13.76 seconds
Started May 16 03:22:03 PM PDT 24
Finished May 16 03:22:27 PM PDT 24
Peak memory 204744 kb
Host smart-9ba95995-3ab2-445d-be7e-969ff94a4f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21996
92803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.2199692803
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2518622969
Short name T1761
Test name
Test status
Simulation time 8372513273 ps
CPU time 13.2 seconds
Started May 16 03:21:47 PM PDT 24
Finished May 16 03:22:10 PM PDT 24
Peak memory 204832 kb
Host smart-d7d3f596-b511-4b9c-8c29-a2b7f650c075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25186
22969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2518622969
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2820245524
Short name T200
Test name
Test status
Simulation time 8960956120 ps
CPU time 12.6 seconds
Started May 16 03:21:52 PM PDT 24
Finished May 16 03:22:16 PM PDT 24
Peak memory 204776 kb
Host smart-9468b2dd-bf52-4b24-93f2-24c7a30fab95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28202
45524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2820245524
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3678498997
Short name T1087
Test name
Test status
Simulation time 8373294536 ps
CPU time 13.68 seconds
Started May 16 03:21:47 PM PDT 24
Finished May 16 03:22:10 PM PDT 24
Peak memory 204820 kb
Host smart-e77bac86-6ab2-47a8-84ab-4de2e687f103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36784
98997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3678498997
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2156781134
Short name T461
Test name
Test status
Simulation time 8409930236 ps
CPU time 13.58 seconds
Started May 16 03:21:49 PM PDT 24
Finished May 16 03:22:13 PM PDT 24
Peak memory 204940 kb
Host smart-ba446bda-bb42-4ffd-bfd3-3df15e500d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21567
81134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2156781134
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1934781883
Short name T1673
Test name
Test status
Simulation time 9242429756 ps
CPU time 12.94 seconds
Started May 16 03:21:52 PM PDT 24
Finished May 16 03:22:16 PM PDT 24
Peak memory 204784 kb
Host smart-2aa4c19d-35fe-4974-82d8-3a3e76556c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19347
81883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1934781883
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3521471817
Short name T564
Test name
Test status
Simulation time 8618344069 ps
CPU time 12.77 seconds
Started May 16 03:21:48 PM PDT 24
Finished May 16 03:22:11 PM PDT 24
Peak memory 204892 kb
Host smart-e466d834-4546-4258-a1a6-4e1fe4070d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35214
71817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3521471817
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3500414687
Short name T1198
Test name
Test status
Simulation time 8408263094 ps
CPU time 11.52 seconds
Started May 16 03:22:05 PM PDT 24
Finished May 16 03:22:28 PM PDT 24
Peak memory 204860 kb
Host smart-5fb513ee-9292-432f-b52a-89f8191d8778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35004
14687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3500414687
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1294461366
Short name T531
Test name
Test status
Simulation time 8370216163 ps
CPU time 11.47 seconds
Started May 16 03:22:03 PM PDT 24
Finished May 16 03:22:25 PM PDT 24
Peak memory 204856 kb
Host smart-7ce4e5d9-524a-4a77-b959-ebda830f4548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12944
61366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1294461366
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.88317198
Short name T1369
Test name
Test status
Simulation time 8463418440 ps
CPU time 10.98 seconds
Started May 16 03:21:48 PM PDT 24
Finished May 16 03:22:10 PM PDT 24
Peak memory 204904 kb
Host smart-4cc36f2f-d970-49fc-af0f-140b1a7c8d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88317
198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.88317198
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.2429871933
Short name T827
Test name
Test status
Simulation time 8413283711 ps
CPU time 11.2 seconds
Started May 16 03:21:53 PM PDT 24
Finished May 16 03:22:15 PM PDT 24
Peak memory 204904 kb
Host smart-55c65c96-3c9a-4464-aa25-49a394321629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24298
71933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.2429871933
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.4226450886
Short name T1764
Test name
Test status
Simulation time 11525546543 ps
CPU time 16.97 seconds
Started May 16 03:21:49 PM PDT 24
Finished May 16 03:22:16 PM PDT 24
Peak memory 204892 kb
Host smart-470e4e35-886f-438a-bbf7-dbadb9356624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42264
50886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.4226450886
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3627256647
Short name T1182
Test name
Test status
Simulation time 8417010547 ps
CPU time 13.36 seconds
Started May 16 03:21:48 PM PDT 24
Finished May 16 03:22:11 PM PDT 24
Peak memory 204816 kb
Host smart-cf89572d-f32e-454f-a45a-254450ff207b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36272
56647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3627256647
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3936218083
Short name T1133
Test name
Test status
Simulation time 8374978509 ps
CPU time 13.91 seconds
Started May 16 03:21:49 PM PDT 24
Finished May 16 03:22:13 PM PDT 24
Peak memory 204836 kb
Host smart-09bd7f85-c9a0-463c-8e93-851878b8b238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39362
18083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3936218083
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3781576061
Short name T123
Test name
Test status
Simulation time 8439198800 ps
CPU time 11.27 seconds
Started May 16 03:21:53 PM PDT 24
Finished May 16 03:22:15 PM PDT 24
Peak memory 204904 kb
Host smart-c06bb084-db59-4dc1-8a6f-93d847d0b9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37815
76061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3781576061
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.716979649
Short name T323
Test name
Test status
Simulation time 8426407843 ps
CPU time 11.58 seconds
Started May 16 03:21:47 PM PDT 24
Finished May 16 03:22:08 PM PDT 24
Peak memory 204892 kb
Host smart-a3a8f530-03e9-402f-955d-a37eed40df2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71697
9649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.716979649
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3591720644
Short name T928
Test name
Test status
Simulation time 8392433052 ps
CPU time 12.38 seconds
Started May 16 03:21:58 PM PDT 24
Finished May 16 03:22:21 PM PDT 24
Peak memory 204804 kb
Host smart-7efceb08-30af-4686-b6b9-27e140ca9f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35917
20644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3591720644
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3944854947
Short name T190
Test name
Test status
Simulation time 8391168386 ps
CPU time 12.35 seconds
Started May 16 03:22:06 PM PDT 24
Finished May 16 03:22:30 PM PDT 24
Peak memory 204600 kb
Host smart-80ecf797-be3b-4663-9e39-9540c3c3a19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39448
54947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3944854947
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2481193703
Short name T10
Test name
Test status
Simulation time 8368232002 ps
CPU time 11.25 seconds
Started May 16 03:22:00 PM PDT 24
Finished May 16 03:22:22 PM PDT 24
Peak memory 204776 kb
Host smart-b3927c41-52a0-42f3-963b-3121237cbfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24811
93703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2481193703
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2142566058
Short name T1584
Test name
Test status
Simulation time 8382703676 ps
CPU time 13.96 seconds
Started May 16 03:22:07 PM PDT 24
Finished May 16 03:22:33 PM PDT 24
Peak memory 204828 kb
Host smart-041b7829-b207-4086-91ef-1090acfd8790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21425
66058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2142566058
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.684861338
Short name T273
Test name
Test status
Simulation time 19298960842 ps
CPU time 33.89 seconds
Started May 16 03:21:56 PM PDT 24
Finished May 16 03:22:41 PM PDT 24
Peak memory 204828 kb
Host smart-62fa9765-5e64-4098-8f9e-c51789860fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68486
1338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.684861338
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3535398688
Short name T650
Test name
Test status
Simulation time 8389835907 ps
CPU time 11.63 seconds
Started May 16 03:21:57 PM PDT 24
Finished May 16 03:22:19 PM PDT 24
Peak memory 204816 kb
Host smart-d21fc736-633b-4b58-8b28-54c64a40afa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35353
98688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3535398688
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2159690344
Short name T1434
Test name
Test status
Simulation time 8429095202 ps
CPU time 11.69 seconds
Started May 16 03:21:57 PM PDT 24
Finished May 16 03:22:19 PM PDT 24
Peak memory 204904 kb
Host smart-7c39769e-ecb5-4cee-84b7-61dd5481846f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21596
90344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2159690344
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.2967757761
Short name T1583
Test name
Test status
Simulation time 8418072105 ps
CPU time 12.5 seconds
Started May 16 03:21:57 PM PDT 24
Finished May 16 03:22:20 PM PDT 24
Peak memory 204808 kb
Host smart-bb5b1839-afdb-4032-b896-add730f2ae8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29677
57761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.2967757761
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2765248190
Short name T1424
Test name
Test status
Simulation time 8386785644 ps
CPU time 10.53 seconds
Started May 16 03:21:59 PM PDT 24
Finished May 16 03:22:20 PM PDT 24
Peak memory 204800 kb
Host smart-933b3a8d-22b3-4044-863d-4a88eb814784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27652
48190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2765248190
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.3091907084
Short name T1149
Test name
Test status
Simulation time 8390999063 ps
CPU time 10.84 seconds
Started May 16 03:21:58 PM PDT 24
Finished May 16 03:22:19 PM PDT 24
Peak memory 204796 kb
Host smart-97cee40f-d092-4fd9-b5bb-9346419c9b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30919
07084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3091907084
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3910636902
Short name T1171
Test name
Test status
Simulation time 8399532003 ps
CPU time 14.32 seconds
Started May 16 03:21:57 PM PDT 24
Finished May 16 03:22:22 PM PDT 24
Peak memory 204856 kb
Host smart-b5d71155-7297-46a4-a68c-e293b581b545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39106
36902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3910636902
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.128399538
Short name T1604
Test name
Test status
Simulation time 8441518557 ps
CPU time 11.69 seconds
Started May 16 03:21:46 PM PDT 24
Finished May 16 03:22:07 PM PDT 24
Peak memory 204844 kb
Host smart-a0ca7395-35c3-4c73-acce-6ea429312905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12839
9538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.128399538
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1459430165
Short name T516
Test name
Test status
Simulation time 8433958582 ps
CPU time 11.43 seconds
Started May 16 03:21:57 PM PDT 24
Finished May 16 03:22:19 PM PDT 24
Peak memory 204780 kb
Host smart-a2a9ea94-23ee-43b4-ab80-2996fb2d628f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14594
30165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1459430165
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3752395926
Short name T1408
Test name
Test status
Simulation time 8402632769 ps
CPU time 11.65 seconds
Started May 16 03:21:58 PM PDT 24
Finished May 16 03:22:20 PM PDT 24
Peak memory 204872 kb
Host smart-0ee02252-d8c3-4c46-a45c-f18ddf35a23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37523
95926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3752395926
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.555927845
Short name T810
Test name
Test status
Simulation time 8463264247 ps
CPU time 10.99 seconds
Started May 16 03:22:05 PM PDT 24
Finished May 16 03:22:28 PM PDT 24
Peak memory 204872 kb
Host smart-dc41a0f6-b084-45bc-ba93-3e80cf8a29ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=555927845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.555927845
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.3317896371
Short name T761
Test name
Test status
Simulation time 8380221601 ps
CPU time 10.75 seconds
Started May 16 03:22:06 PM PDT 24
Finished May 16 03:22:29 PM PDT 24
Peak memory 204796 kb
Host smart-7c680a29-0cda-4ef9-b9fb-af807c053666
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3317896371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.3317896371
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.552293521
Short name T638
Test name
Test status
Simulation time 8426344802 ps
CPU time 12.39 seconds
Started May 16 03:22:04 PM PDT 24
Finished May 16 03:22:27 PM PDT 24
Peak memory 204908 kb
Host smart-053ffd66-ec4f-41e8-bc81-a5cec1632609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55229
3521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.552293521
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1468096854
Short name T1552
Test name
Test status
Simulation time 8383127350 ps
CPU time 11.86 seconds
Started May 16 03:22:07 PM PDT 24
Finished May 16 03:22:31 PM PDT 24
Peak memory 204856 kb
Host smart-8a04cc30-a0b4-41ba-acf8-70839253993c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14680
96854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1468096854
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2679677273
Short name T45
Test name
Test status
Simulation time 9364167948 ps
CPU time 12.62 seconds
Started May 16 03:22:06 PM PDT 24
Finished May 16 03:22:30 PM PDT 24
Peak memory 204928 kb
Host smart-921e32e4-efe5-42b5-b227-3283d22814b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26796
77273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2679677273
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1264257871
Short name T549
Test name
Test status
Simulation time 8367750044 ps
CPU time 11.02 seconds
Started May 16 03:22:07 PM PDT 24
Finished May 16 03:22:30 PM PDT 24
Peak memory 204804 kb
Host smart-2c04d896-fb6f-408c-a288-8918c02a1ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12642
57871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1264257871
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1612946074
Short name T338
Test name
Test status
Simulation time 8382262861 ps
CPU time 11.36 seconds
Started May 16 03:22:07 PM PDT 24
Finished May 16 03:22:31 PM PDT 24
Peak memory 204900 kb
Host smart-f7206657-f4ac-4ece-98e4-894e17d15643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16129
46074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1612946074
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1782832785
Short name T153
Test name
Test status
Simulation time 9182428776 ps
CPU time 12.47 seconds
Started May 16 03:22:05 PM PDT 24
Finished May 16 03:22:28 PM PDT 24
Peak memory 204880 kb
Host smart-9aef90f2-7f9e-4c61-8e2d-c59da31ec43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17828
32785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1782832785
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.681175690
Short name T1159
Test name
Test status
Simulation time 8394718691 ps
CPU time 12.32 seconds
Started May 16 03:22:08 PM PDT 24
Finished May 16 03:22:32 PM PDT 24
Peak memory 204856 kb
Host smart-8a547499-cf72-4678-930c-ced65f311524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68117
5690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.681175690
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3456850223
Short name T1720
Test name
Test status
Simulation time 8416022246 ps
CPU time 11.22 seconds
Started May 16 03:22:05 PM PDT 24
Finished May 16 03:22:27 PM PDT 24
Peak memory 204852 kb
Host smart-24879acc-a2e3-402b-bfb6-5ded683af611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34568
50223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3456850223
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1576226252
Short name T1568
Test name
Test status
Simulation time 8372337500 ps
CPU time 10.8 seconds
Started May 16 03:22:08 PM PDT 24
Finished May 16 03:22:31 PM PDT 24
Peak memory 204828 kb
Host smart-8f707eeb-d4f7-4122-94b8-c00f396ef754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15762
26252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1576226252
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3687118780
Short name T1181
Test name
Test status
Simulation time 8482528218 ps
CPU time 12.49 seconds
Started May 16 03:22:04 PM PDT 24
Finished May 16 03:22:27 PM PDT 24
Peak memory 204792 kb
Host smart-e43a3824-283f-4740-b58b-7382063633bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36871
18780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3687118780
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.921427215
Short name T1507
Test name
Test status
Simulation time 8377707964 ps
CPU time 11.64 seconds
Started May 16 03:22:05 PM PDT 24
Finished May 16 03:22:27 PM PDT 24
Peak memory 204896 kb
Host smart-89e2fa86-e74f-4298-a0ef-fd7df4f4773f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92142
7215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.921427215
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2527816063
Short name T429
Test name
Test status
Simulation time 11499312055 ps
CPU time 15.49 seconds
Started May 16 03:22:07 PM PDT 24
Finished May 16 03:22:34 PM PDT 24
Peak memory 204860 kb
Host smart-f024dd68-9072-4696-b543-33cb2e3c6124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25278
16063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2527816063
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3862800402
Short name T809
Test name
Test status
Simulation time 8454073757 ps
CPU time 11.01 seconds
Started May 16 03:22:06 PM PDT 24
Finished May 16 03:22:29 PM PDT 24
Peak memory 204812 kb
Host smart-3a6a1df5-7798-41f5-ab3f-bfd575a42fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38628
00402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3862800402
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2069466798
Short name T1192
Test name
Test status
Simulation time 8425162263 ps
CPU time 11.2 seconds
Started May 16 03:22:03 PM PDT 24
Finished May 16 03:22:25 PM PDT 24
Peak memory 204812 kb
Host smart-06d4d662-509e-4715-bdaf-26b5ec9da68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20694
66798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2069466798
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.301739584
Short name T710
Test name
Test status
Simulation time 8417929972 ps
CPU time 10.62 seconds
Started May 16 03:22:08 PM PDT 24
Finished May 16 03:22:30 PM PDT 24
Peak memory 204860 kb
Host smart-5feb3328-6e82-44c6-b091-14d79717f595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30173
9584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.301739584
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1068368130
Short name T1511
Test name
Test status
Simulation time 8415223549 ps
CPU time 11.3 seconds
Started May 16 03:22:06 PM PDT 24
Finished May 16 03:22:28 PM PDT 24
Peak memory 204872 kb
Host smart-2bf01cf2-4b69-4f5e-93a0-5660ebbf66f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10683
68130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1068368130
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.954538484
Short name T1504
Test name
Test status
Simulation time 8390120048 ps
CPU time 10.99 seconds
Started May 16 03:22:04 PM PDT 24
Finished May 16 03:22:27 PM PDT 24
Peak memory 204912 kb
Host smart-469ad1d9-6491-4460-b8e1-54f154261770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95453
8484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.954538484
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1297643471
Short name T221
Test name
Test status
Simulation time 8397554488 ps
CPU time 11.43 seconds
Started May 16 03:22:04 PM PDT 24
Finished May 16 03:22:27 PM PDT 24
Peak memory 204836 kb
Host smart-b8dda202-2939-4851-9dec-96a4c30558dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12976
43471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1297643471
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.3656875019
Short name T883
Test name
Test status
Simulation time 8411065709 ps
CPU time 12.15 seconds
Started May 16 03:22:06 PM PDT 24
Finished May 16 03:22:29 PM PDT 24
Peak memory 204820 kb
Host smart-dccfe2b5-ec78-467f-a9c2-2acafdf778b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36568
75019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.3656875019
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2763437357
Short name T1738
Test name
Test status
Simulation time 8368283673 ps
CPU time 10.91 seconds
Started May 16 03:22:07 PM PDT 24
Finished May 16 03:22:30 PM PDT 24
Peak memory 204804 kb
Host smart-6e570479-d6d6-4d62-b292-c5f9ae41ec00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27634
37357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2763437357
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2148363088
Short name T32
Test name
Test status
Simulation time 8360774909 ps
CPU time 10.88 seconds
Started May 16 03:22:06 PM PDT 24
Finished May 16 03:22:29 PM PDT 24
Peak memory 204744 kb
Host smart-239487f1-c1ec-4ad8-92b8-1abe46eb4f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21483
63088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2148363088
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.565007435
Short name T1512
Test name
Test status
Simulation time 21705785182 ps
CPU time 47.79 seconds
Started May 16 03:22:03 PM PDT 24
Finished May 16 03:23:01 PM PDT 24
Peak memory 204816 kb
Host smart-9abe2343-43ae-4d13-bf55-040a545f92f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56500
7435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.565007435
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2672311166
Short name T1006
Test name
Test status
Simulation time 8422848386 ps
CPU time 11.87 seconds
Started May 16 03:22:09 PM PDT 24
Finished May 16 03:22:33 PM PDT 24
Peak memory 204824 kb
Host smart-48e94efd-7d74-4879-8683-bfdc77678562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26723
11166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2672311166
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2007715125
Short name T1348
Test name
Test status
Simulation time 8422515255 ps
CPU time 11.17 seconds
Started May 16 03:22:04 PM PDT 24
Finished May 16 03:22:26 PM PDT 24
Peak memory 204820 kb
Host smart-ed4e2028-fc71-4c89-90f7-8b9d4077ec5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20077
15125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2007715125
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1236305127
Short name T1670
Test name
Test status
Simulation time 8367214848 ps
CPU time 11.22 seconds
Started May 16 03:22:04 PM PDT 24
Finished May 16 03:22:26 PM PDT 24
Peak memory 204808 kb
Host smart-8642a093-d313-4c1a-857e-f40fee7a4c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12363
05127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1236305127
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1795418450
Short name T813
Test name
Test status
Simulation time 8384272296 ps
CPU time 10.55 seconds
Started May 16 03:22:05 PM PDT 24
Finished May 16 03:22:26 PM PDT 24
Peak memory 204908 kb
Host smart-9fb68f11-7cdb-4027-9ae2-d00c050f4e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17954
18450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1795418450
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2002822557
Short name T1341
Test name
Test status
Simulation time 8404234614 ps
CPU time 11.9 seconds
Started May 16 03:22:05 PM PDT 24
Finished May 16 03:22:28 PM PDT 24
Peak memory 204844 kb
Host smart-ec6d0e91-ba0a-4e51-a54a-6b454dc4ba1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20028
22557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2002822557
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.201936696
Short name T1045
Test name
Test status
Simulation time 8431841186 ps
CPU time 14 seconds
Started May 16 03:22:05 PM PDT 24
Finished May 16 03:22:30 PM PDT 24
Peak memory 204772 kb
Host smart-fca999b4-0bfc-4938-84c0-c3040d275b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20193
6696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.201936696
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3239830644
Short name T830
Test name
Test status
Simulation time 8385947785 ps
CPU time 11.56 seconds
Started May 16 03:22:06 PM PDT 24
Finished May 16 03:22:30 PM PDT 24
Peak memory 204876 kb
Host smart-3fe08b29-6365-4b3f-9cb3-ae64417ecfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32398
30644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3239830644
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2308160431
Short name T985
Test name
Test status
Simulation time 8398014558 ps
CPU time 10.98 seconds
Started May 16 03:22:09 PM PDT 24
Finished May 16 03:22:32 PM PDT 24
Peak memory 204916 kb
Host smart-269f119e-87bd-4ae7-bfaf-3d921957f174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23081
60431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2308160431
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.2186883105
Short name T1314
Test name
Test status
Simulation time 8467486712 ps
CPU time 11.54 seconds
Started May 16 03:22:15 PM PDT 24
Finished May 16 03:22:38 PM PDT 24
Peak memory 204272 kb
Host smart-971c6d40-d39a-4026-be16-7718bbeb4422
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2186883105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.2186883105
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.596210785
Short name T1637
Test name
Test status
Simulation time 8377044807 ps
CPU time 13.88 seconds
Started May 16 03:22:13 PM PDT 24
Finished May 16 03:22:38 PM PDT 24
Peak memory 204796 kb
Host smart-cc7e45ac-d7c6-47b7-821a-50638ee3592a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=596210785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.596210785
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.669222284
Short name T321
Test name
Test status
Simulation time 8447933420 ps
CPU time 10.75 seconds
Started May 16 03:22:11 PM PDT 24
Finished May 16 03:22:33 PM PDT 24
Peak memory 204924 kb
Host smart-33ef87a6-749b-4695-8dcb-896908cf2140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66922
2284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.669222284
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1519552695
Short name T1440
Test name
Test status
Simulation time 8392024690 ps
CPU time 11.32 seconds
Started May 16 03:22:05 PM PDT 24
Finished May 16 03:22:27 PM PDT 24
Peak memory 204820 kb
Host smart-6bed4ef7-e889-4aa8-985b-3546728c363a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15195
52695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1519552695
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1457908369
Short name T196
Test name
Test status
Simulation time 9286155319 ps
CPU time 13.27 seconds
Started May 16 03:22:06 PM PDT 24
Finished May 16 03:22:30 PM PDT 24
Peak memory 204888 kb
Host smart-c9fa1a4b-7872-4e32-9dae-ff0e8e62cc0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14579
08369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1457908369
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.3849609187
Short name T628
Test name
Test status
Simulation time 8395746672 ps
CPU time 13.24 seconds
Started May 16 03:22:12 PM PDT 24
Finished May 16 03:22:37 PM PDT 24
Peak memory 204880 kb
Host smart-fe877692-32e4-4ae8-9e52-4f4ce9f49f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38496
09187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.3849609187
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.1141340636
Short name T854
Test name
Test status
Simulation time 8374168130 ps
CPU time 10.63 seconds
Started May 16 03:22:07 PM PDT 24
Finished May 16 03:22:30 PM PDT 24
Peak memory 204832 kb
Host smart-37c510a8-ebd5-4f94-945d-ae182d3a2e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11413
40636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1141340636
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.2535138872
Short name T992
Test name
Test status
Simulation time 9156392629 ps
CPU time 12.84 seconds
Started May 16 03:22:03 PM PDT 24
Finished May 16 03:22:26 PM PDT 24
Peak memory 204928 kb
Host smart-9af5c1fc-f66a-4f62-b99f-1c4512f26763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25351
38872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2535138872
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.984472130
Short name T1272
Test name
Test status
Simulation time 8538571863 ps
CPU time 12.62 seconds
Started May 16 03:22:09 PM PDT 24
Finished May 16 03:22:34 PM PDT 24
Peak memory 204840 kb
Host smart-4b7700c4-02c0-4e2b-96a1-2a690d79c2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98447
2130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.984472130
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.380116092
Short name T791
Test name
Test status
Simulation time 8454201763 ps
CPU time 14.09 seconds
Started May 16 03:22:14 PM PDT 24
Finished May 16 03:22:40 PM PDT 24
Peak memory 204924 kb
Host smart-08f27b9e-6bbf-4da7-96b1-78889677ee85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38011
6092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.380116092
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.452710272
Short name T1266
Test name
Test status
Simulation time 8392356543 ps
CPU time 11.28 seconds
Started May 16 03:22:14 PM PDT 24
Finished May 16 03:22:37 PM PDT 24
Peak memory 204908 kb
Host smart-7546ef38-9df5-447b-ac96-0f5bb14d1911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45271
0272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.452710272
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.4189234372
Short name T156
Test name
Test status
Simulation time 8441586899 ps
CPU time 11.48 seconds
Started May 16 03:22:08 PM PDT 24
Finished May 16 03:22:31 PM PDT 24
Peak memory 204860 kb
Host smart-677f7ee9-a6d8-4f98-ac53-b5dd4fc4ae18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41892
34372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.4189234372
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1096765921
Short name T799
Test name
Test status
Simulation time 8388805128 ps
CPU time 12.53 seconds
Started May 16 03:22:08 PM PDT 24
Finished May 16 03:22:32 PM PDT 24
Peak memory 204832 kb
Host smart-1924ccde-d94a-4a3e-b06c-603513ee7723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10967
65921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1096765921
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1953610148
Short name T976
Test name
Test status
Simulation time 11553969752 ps
CPU time 16.55 seconds
Started May 16 03:22:11 PM PDT 24
Finished May 16 03:22:39 PM PDT 24
Peak memory 204852 kb
Host smart-37984a8c-865c-4fa0-9837-350f205a075f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19536
10148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1953610148
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2402013060
Short name T551
Test name
Test status
Simulation time 8416737591 ps
CPU time 13.7 seconds
Started May 16 03:22:15 PM PDT 24
Finished May 16 03:22:40 PM PDT 24
Peak memory 204828 kb
Host smart-8e0f082e-5d97-4336-af61-f1163e17ea4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24020
13060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2402013060
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.784613213
Short name T1285
Test name
Test status
Simulation time 8369766633 ps
CPU time 11.4 seconds
Started May 16 03:22:15 PM PDT 24
Finished May 16 03:22:38 PM PDT 24
Peak memory 204828 kb
Host smart-75e61f63-bf70-4f92-b123-344c99f622b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78461
3213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.784613213
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2157804001
Short name T1588
Test name
Test status
Simulation time 8418820634 ps
CPU time 12.07 seconds
Started May 16 03:22:14 PM PDT 24
Finished May 16 03:22:37 PM PDT 24
Peak memory 204924 kb
Host smart-f0967746-3f12-4aee-8f4d-3a914eeda41c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21578
04001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2157804001
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.1172679845
Short name T1431
Test name
Test status
Simulation time 8413714746 ps
CPU time 12.43 seconds
Started May 16 03:22:14 PM PDT 24
Finished May 16 03:22:38 PM PDT 24
Peak memory 204836 kb
Host smart-711b7fbf-3cb8-4654-81b1-bb2ce3adf9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11726
79845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.1172679845
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1592173457
Short name T372
Test name
Test status
Simulation time 8409431559 ps
CPU time 11.81 seconds
Started May 16 03:22:12 PM PDT 24
Finished May 16 03:22:36 PM PDT 24
Peak memory 204756 kb
Host smart-09cc7565-d56e-45d3-854b-468f25f89568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15921
73457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1592173457
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2019660527
Short name T1226
Test name
Test status
Simulation time 8413120857 ps
CPU time 11.31 seconds
Started May 16 03:22:11 PM PDT 24
Finished May 16 03:22:35 PM PDT 24
Peak memory 204876 kb
Host smart-b1c52178-c585-4260-aa7f-e0da5ec2f336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20196
60527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2019660527
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.1425971081
Short name T1505
Test name
Test status
Simulation time 8410464830 ps
CPU time 11.54 seconds
Started May 16 03:22:11 PM PDT 24
Finished May 16 03:22:34 PM PDT 24
Peak memory 204856 kb
Host smart-3a07bcb5-e6fb-4252-8c5d-5f88367108bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14259
71081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.1425971081
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2516207825
Short name T1167
Test name
Test status
Simulation time 8378874877 ps
CPU time 11.72 seconds
Started May 16 03:22:10 PM PDT 24
Finished May 16 03:22:34 PM PDT 24
Peak memory 204752 kb
Host smart-632b318d-b057-494a-ad48-20e8070bc990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25162
07825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2516207825
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2400762619
Short name T944
Test name
Test status
Simulation time 8373586998 ps
CPU time 12.61 seconds
Started May 16 03:22:13 PM PDT 24
Finished May 16 03:22:38 PM PDT 24
Peak memory 204860 kb
Host smart-7d650e12-2f27-4794-b2f6-adbd6b866459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24007
62619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2400762619
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3175867367
Short name T1227
Test name
Test status
Simulation time 8412338208 ps
CPU time 12.56 seconds
Started May 16 03:22:14 PM PDT 24
Finished May 16 03:22:38 PM PDT 24
Peak memory 204804 kb
Host smart-17c361ad-c16e-40ff-b00f-86fddce04832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31758
67367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3175867367
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1416679678
Short name T455
Test name
Test status
Simulation time 8468638614 ps
CPU time 12.57 seconds
Started May 16 03:22:14 PM PDT 24
Finished May 16 03:22:38 PM PDT 24
Peak memory 204672 kb
Host smart-4091f98b-461f-4daa-84fe-e3a8a54c5875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14166
79678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1416679678
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.2386534369
Short name T662
Test name
Test status
Simulation time 8385198274 ps
CPU time 10.72 seconds
Started May 16 03:22:13 PM PDT 24
Finished May 16 03:22:36 PM PDT 24
Peak memory 204828 kb
Host smart-59c5f069-13a2-4bb7-b6dc-b461961b25dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23865
34369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.2386534369
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.824413076
Short name T465
Test name
Test status
Simulation time 8368574513 ps
CPU time 12.98 seconds
Started May 16 03:22:14 PM PDT 24
Finished May 16 03:22:39 PM PDT 24
Peak memory 204800 kb
Host smart-76860d97-36bc-4a14-9def-210be981d229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82441
3076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.824413076
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1954123756
Short name T1722
Test name
Test status
Simulation time 8387601796 ps
CPU time 10.41 seconds
Started May 16 03:22:11 PM PDT 24
Finished May 16 03:22:33 PM PDT 24
Peak memory 204792 kb
Host smart-7ae4dbc4-d489-4455-8561-2e9471ee51c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19541
23756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1954123756
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2703848670
Short name T658
Test name
Test status
Simulation time 8389935691 ps
CPU time 12.22 seconds
Started May 16 03:22:12 PM PDT 24
Finished May 16 03:22:36 PM PDT 24
Peak memory 204828 kb
Host smart-bb0a500c-23c7-48ab-aa70-46b0dd1c9fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27038
48670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2703848670
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3877173341
Short name T1413
Test name
Test status
Simulation time 8443919386 ps
CPU time 11.81 seconds
Started May 16 03:22:06 PM PDT 24
Finished May 16 03:22:29 PM PDT 24
Peak memory 204856 kb
Host smart-2d7ec638-b5e0-43ed-a591-595270c3cbbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38771
73341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3877173341
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3358181764
Short name T571
Test name
Test status
Simulation time 8408002581 ps
CPU time 11.02 seconds
Started May 16 03:22:14 PM PDT 24
Finished May 16 03:22:37 PM PDT 24
Peak memory 204792 kb
Host smart-8fde3a83-f39f-4996-a0b9-9eedf8ff9115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33581
81764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3358181764
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.4062041637
Short name T1061
Test name
Test status
Simulation time 8468943805 ps
CPU time 12.13 seconds
Started May 16 03:22:30 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204860 kb
Host smart-e9640c2a-a755-45c3-933c-9f2e959dbc9a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4062041637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.4062041637
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.1810902305
Short name T1762
Test name
Test status
Simulation time 8409401855 ps
CPU time 11.87 seconds
Started May 16 03:22:30 PM PDT 24
Finished May 16 03:22:55 PM PDT 24
Peak memory 204856 kb
Host smart-3b4d60a6-0491-41c3-8580-b35fa27e3e09
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1810902305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.1810902305
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.623024346
Short name T371
Test name
Test status
Simulation time 8417950449 ps
CPU time 11.86 seconds
Started May 16 03:22:28 PM PDT 24
Finished May 16 03:22:51 PM PDT 24
Peak memory 204856 kb
Host smart-9d900bf2-a163-40cd-a89b-d77201d24cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62302
4346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.623024346
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.870242239
Short name T966
Test name
Test status
Simulation time 8385751475 ps
CPU time 13.66 seconds
Started May 16 03:22:11 PM PDT 24
Finished May 16 03:22:36 PM PDT 24
Peak memory 204840 kb
Host smart-579d17e3-b5bb-45cb-964f-7da93ab9979b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87024
2239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.870242239
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3822662148
Short name T363
Test name
Test status
Simulation time 8367514290 ps
CPU time 10.94 seconds
Started May 16 03:22:12 PM PDT 24
Finished May 16 03:22:35 PM PDT 24
Peak memory 204832 kb
Host smart-3add87ba-22fb-4ecf-bd6d-33655f104d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38226
62148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3822662148
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.3955362560
Short name T305
Test name
Test status
Simulation time 8380329403 ps
CPU time 13.42 seconds
Started May 16 03:22:15 PM PDT 24
Finished May 16 03:22:40 PM PDT 24
Peak memory 204880 kb
Host smart-30180ac4-c473-4074-b183-eb89dc37c1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39553
62560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3955362560
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2338135786
Short name T943
Test name
Test status
Simulation time 8403945535 ps
CPU time 12.92 seconds
Started May 16 03:22:14 PM PDT 24
Finished May 16 03:22:38 PM PDT 24
Peak memory 204804 kb
Host smart-7e59bf7d-9fa2-428d-b817-cf40c984f025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23381
35786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2338135786
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3644687416
Short name T1092
Test name
Test status
Simulation time 8418880732 ps
CPU time 10.65 seconds
Started May 16 03:22:31 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204796 kb
Host smart-56251782-db91-497d-b114-840a03a0c0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36446
87416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3644687416
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3420899271
Short name T1694
Test name
Test status
Simulation time 8370307133 ps
CPU time 10.37 seconds
Started May 16 03:22:29 PM PDT 24
Finished May 16 03:22:51 PM PDT 24
Peak memory 204836 kb
Host smart-abd72d17-1314-4add-a8f5-a12e1229717b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34208
99271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3420899271
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1786132842
Short name T1668
Test name
Test status
Simulation time 8470213182 ps
CPU time 11.01 seconds
Started May 16 03:22:13 PM PDT 24
Finished May 16 03:22:36 PM PDT 24
Peak memory 204888 kb
Host smart-87fab40e-f3a3-4419-8194-fde92e20cfa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17861
32842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1786132842
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3494570621
Short name T991
Test name
Test status
Simulation time 8385813375 ps
CPU time 12.28 seconds
Started May 16 03:22:11 PM PDT 24
Finished May 16 03:22:34 PM PDT 24
Peak memory 204932 kb
Host smart-24ed97dc-bde8-4898-aac8-c5e6e38cfb1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34945
70621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3494570621
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1220881364
Short name T608
Test name
Test status
Simulation time 11508638505 ps
CPU time 13.47 seconds
Started May 16 03:22:14 PM PDT 24
Finished May 16 03:22:39 PM PDT 24
Peak memory 204816 kb
Host smart-53074a61-c985-4c8d-b0db-63cfbda1cd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12208
81364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1220881364
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3528674635
Short name T1763
Test name
Test status
Simulation time 8458496454 ps
CPU time 11.94 seconds
Started May 16 03:22:12 PM PDT 24
Finished May 16 03:22:36 PM PDT 24
Peak memory 204816 kb
Host smart-57577d95-0959-450a-b743-3ecd513cb106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35286
74635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3528674635
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1297155344
Short name T309
Test name
Test status
Simulation time 8373095370 ps
CPU time 13.1 seconds
Started May 16 03:22:12 PM PDT 24
Finished May 16 03:22:36 PM PDT 24
Peak memory 204844 kb
Host smart-6f178b3c-8e1d-43a8-bff0-b27141465845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12971
55344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1297155344
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2368590232
Short name T932
Test name
Test status
Simulation time 8416977872 ps
CPU time 11.44 seconds
Started May 16 03:22:11 PM PDT 24
Finished May 16 03:22:34 PM PDT 24
Peak memory 204824 kb
Host smart-ee40027e-862e-48ad-a9c4-6856e5a79299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23685
90232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2368590232
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.334013741
Short name T334
Test name
Test status
Simulation time 8405707100 ps
CPU time 11.41 seconds
Started May 16 03:22:20 PM PDT 24
Finished May 16 03:22:40 PM PDT 24
Peak memory 204816 kb
Host smart-cef68034-4744-450e-9179-c9e60c17e019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33401
3741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.334013741
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1973844565
Short name T1173
Test name
Test status
Simulation time 8410706725 ps
CPU time 10.43 seconds
Started May 16 03:22:29 PM PDT 24
Finished May 16 03:22:51 PM PDT 24
Peak memory 204852 kb
Host smart-6a87f8e7-2921-42f1-a47b-403c276d1dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19738
44565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1973844565
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2815113888
Short name T600
Test name
Test status
Simulation time 8426880964 ps
CPU time 13.84 seconds
Started May 16 03:22:26 PM PDT 24
Finished May 16 03:22:50 PM PDT 24
Peak memory 204820 kb
Host smart-6bbcd6d5-657f-4c8e-a487-35c89b7bc1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28151
13888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2815113888
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.3967285062
Short name T689
Test name
Test status
Simulation time 8391909550 ps
CPU time 11.2 seconds
Started May 16 03:22:21 PM PDT 24
Finished May 16 03:22:43 PM PDT 24
Peak memory 204808 kb
Host smart-969e33aa-9445-405b-8f14-50bbc77850b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39672
85062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.3967285062
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3487913230
Short name T963
Test name
Test status
Simulation time 8363889520 ps
CPU time 10.68 seconds
Started May 16 03:22:28 PM PDT 24
Finished May 16 03:22:50 PM PDT 24
Peak memory 204768 kb
Host smart-b656bf42-bf30-4121-88ce-5022c1516d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34879
13230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3487913230
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.863213470
Short name T716
Test name
Test status
Simulation time 20714381724 ps
CPU time 34.87 seconds
Started May 16 03:22:28 PM PDT 24
Finished May 16 03:23:15 PM PDT 24
Peak memory 204804 kb
Host smart-923411d1-e43b-49c2-88cc-0505c65013a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86321
3470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.863213470
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2766444056
Short name T1705
Test name
Test status
Simulation time 8400068128 ps
CPU time 12.92 seconds
Started May 16 03:22:21 PM PDT 24
Finished May 16 03:22:44 PM PDT 24
Peak memory 204824 kb
Host smart-f2ab4dce-2149-4b18-ad18-a2ecfada5895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27664
44056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2766444056
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2170066243
Short name T154
Test name
Test status
Simulation time 8405200176 ps
CPU time 10.42 seconds
Started May 16 03:22:22 PM PDT 24
Finished May 16 03:22:43 PM PDT 24
Peak memory 204840 kb
Host smart-75efcfe4-0058-4334-abbb-bb56e27b576c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21700
66243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2170066243
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.1324769291
Short name T1756
Test name
Test status
Simulation time 8385826637 ps
CPU time 11.44 seconds
Started May 16 03:22:25 PM PDT 24
Finished May 16 03:22:48 PM PDT 24
Peak memory 204804 kb
Host smart-011f3881-4335-4ae1-89ed-02f2df9c5277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13247
69291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.1324769291
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.68123055
Short name T615
Test name
Test status
Simulation time 8373055470 ps
CPU time 12.69 seconds
Started May 16 03:22:26 PM PDT 24
Finished May 16 03:22:49 PM PDT 24
Peak memory 204788 kb
Host smart-bcdc79dd-5df0-40a9-aa98-3140eb5e4f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68123
055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.68123055
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1163347178
Short name T1132
Test name
Test status
Simulation time 8374013998 ps
CPU time 12.1 seconds
Started May 16 03:22:22 PM PDT 24
Finished May 16 03:22:43 PM PDT 24
Peak memory 204864 kb
Host smart-8fcbfa48-cfd0-4d4f-b43e-2264a504b997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11633
47178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1163347178
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1131475187
Short name T1067
Test name
Test status
Simulation time 8370923524 ps
CPU time 11.64 seconds
Started May 16 03:22:29 PM PDT 24
Finished May 16 03:22:52 PM PDT 24
Peak memory 204820 kb
Host smart-27d5758f-e588-4eea-8256-261d05ca4ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11314
75187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1131475187
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3429144785
Short name T173
Test name
Test status
Simulation time 8463723991 ps
CPU time 12.16 seconds
Started May 16 03:22:13 PM PDT 24
Finished May 16 03:22:36 PM PDT 24
Peak memory 204804 kb
Host smart-8b3761ec-bec5-4b4a-82e5-d67219b48469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34291
44785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3429144785
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2870594207
Short name T1361
Test name
Test status
Simulation time 8407604548 ps
CPU time 10.75 seconds
Started May 16 03:22:28 PM PDT 24
Finished May 16 03:22:50 PM PDT 24
Peak memory 204800 kb
Host smart-9f627db3-6c22-4768-bc4d-c03a3e19b6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28705
94207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2870594207
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.704459751
Short name T527
Test name
Test status
Simulation time 8393093478 ps
CPU time 13.08 seconds
Started May 16 03:22:25 PM PDT 24
Finished May 16 03:22:49 PM PDT 24
Peak memory 204892 kb
Host smart-7b28f33e-bf59-40a9-8335-e746a379a106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70445
9751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.704459751
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.2919391709
Short name T1359
Test name
Test status
Simulation time 8469344829 ps
CPU time 11.83 seconds
Started May 16 03:22:35 PM PDT 24
Finished May 16 03:22:58 PM PDT 24
Peak memory 204904 kb
Host smart-54f1dd74-a374-43bd-8930-45afeb569df5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2919391709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.2919391709
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.1580677479
Short name T439
Test name
Test status
Simulation time 8385508745 ps
CPU time 11.4 seconds
Started May 16 03:22:38 PM PDT 24
Finished May 16 03:23:00 PM PDT 24
Peak memory 204900 kb
Host smart-f1d6c4c5-c07e-4693-aafe-6800d6e20ffc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1580677479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.1580677479
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.483822916
Short name T1760
Test name
Test status
Simulation time 8404714333 ps
CPU time 13.51 seconds
Started May 16 03:22:37 PM PDT 24
Finished May 16 03:23:01 PM PDT 24
Peak memory 204924 kb
Host smart-8df511cf-697f-4414-9135-31c7a5b849a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48382
2916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.483822916
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3189435153
Short name T548
Test name
Test status
Simulation time 8378846288 ps
CPU time 12.71 seconds
Started May 16 03:22:31 PM PDT 24
Finished May 16 03:22:57 PM PDT 24
Peak memory 204852 kb
Host smart-cdec8906-e251-403c-ac32-c9e8a40361f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31894
35153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3189435153
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.3468866637
Short name T54
Test name
Test status
Simulation time 8373978802 ps
CPU time 10.96 seconds
Started May 16 03:22:31 PM PDT 24
Finished May 16 03:22:55 PM PDT 24
Peak memory 204744 kb
Host smart-00ade89b-8a9d-46f8-a757-247c2315b22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34688
66637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.3468866637
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2280108477
Short name T1083
Test name
Test status
Simulation time 8897897613 ps
CPU time 12.24 seconds
Started May 16 03:22:27 PM PDT 24
Finished May 16 03:22:51 PM PDT 24
Peak memory 204928 kb
Host smart-0045509b-ee50-4db3-b110-91c80bec109b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22801
08477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2280108477
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1962115470
Short name T1724
Test name
Test status
Simulation time 8369459127 ps
CPU time 11.82 seconds
Started May 16 03:22:32 PM PDT 24
Finished May 16 03:22:56 PM PDT 24
Peak memory 204828 kb
Host smart-5133f3ef-c2ed-4ce7-aeba-6628b152cc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19621
15470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1962115470
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1498624437
Short name T485
Test name
Test status
Simulation time 8432255707 ps
CPU time 11.87 seconds
Started May 16 03:22:30 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204824 kb
Host smart-9d157aa1-4a64-465d-9f16-bf12a2df4e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14986
24437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1498624437
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.708735582
Short name T1164
Test name
Test status
Simulation time 8387320896 ps
CPU time 11.87 seconds
Started May 16 03:22:30 PM PDT 24
Finished May 16 03:22:55 PM PDT 24
Peak memory 204808 kb
Host smart-664bfb59-1225-4a19-86b5-fc4a2c592434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70873
5582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.708735582
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.4046939389
Short name T1075
Test name
Test status
Simulation time 8425596124 ps
CPU time 12.58 seconds
Started May 16 03:22:29 PM PDT 24
Finished May 16 03:22:53 PM PDT 24
Peak memory 204856 kb
Host smart-a79ba178-36a1-41fc-ab4a-aeb886595165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40469
39389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.4046939389
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3796598767
Short name T1392
Test name
Test status
Simulation time 8365196219 ps
CPU time 11.73 seconds
Started May 16 03:22:30 PM PDT 24
Finished May 16 03:22:55 PM PDT 24
Peak memory 204864 kb
Host smart-6d66662b-9c79-4a6c-bbd6-be3dc130bb66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37965
98767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3796598767
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3112822620
Short name T1418
Test name
Test status
Simulation time 8434792339 ps
CPU time 11.18 seconds
Started May 16 03:22:30 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204812 kb
Host smart-366613db-53b7-48c9-ba9d-c2ff22b2a72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31128
22620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3112822620
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.597132280
Short name T1755
Test name
Test status
Simulation time 8414049435 ps
CPU time 10.58 seconds
Started May 16 03:22:30 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204836 kb
Host smart-61ec8fd9-7c6d-4f1a-a035-daccfd4b1c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59713
2280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.597132280
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.3883465007
Short name T1224
Test name
Test status
Simulation time 11558922249 ps
CPU time 16.93 seconds
Started May 16 03:22:27 PM PDT 24
Finished May 16 03:22:56 PM PDT 24
Peak memory 204772 kb
Host smart-a205c28b-9418-4d8b-9d89-e9d5c9b20c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38834
65007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.3883465007
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1925363061
Short name T610
Test name
Test status
Simulation time 8438689395 ps
CPU time 11.2 seconds
Started May 16 03:22:30 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204820 kb
Host smart-c1d7d9f5-3e21-44d1-adba-af4c3cf84350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19253
63061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1925363061
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1033404308
Short name T1300
Test name
Test status
Simulation time 8376509079 ps
CPU time 12.15 seconds
Started May 16 03:22:29 PM PDT 24
Finished May 16 03:22:53 PM PDT 24
Peak memory 204796 kb
Host smart-ee57ec1c-7797-400e-87e4-2f56d9dae59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10334
04308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1033404308
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.3712641746
Short name T1102
Test name
Test status
Simulation time 8517205306 ps
CPU time 10.68 seconds
Started May 16 03:22:29 PM PDT 24
Finished May 16 03:22:52 PM PDT 24
Peak memory 204840 kb
Host smart-0dfca926-c5e5-4798-8be4-94a0c952bba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37126
41746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3712641746
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1431261817
Short name T1666
Test name
Test status
Simulation time 8370748506 ps
CPU time 12.98 seconds
Started May 16 03:22:29 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204932 kb
Host smart-074b430e-53c9-413f-8fa1-54bdb3005c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14312
61817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1431261817
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.649281683
Short name T384
Test name
Test status
Simulation time 8393095034 ps
CPU time 11.49 seconds
Started May 16 03:22:29 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204876 kb
Host smart-70e6e069-0573-4878-b332-433ac900caf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64928
1683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.649281683
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2612338006
Short name T194
Test name
Test status
Simulation time 8408587873 ps
CPU time 11.5 seconds
Started May 16 03:22:29 PM PDT 24
Finished May 16 03:22:53 PM PDT 24
Peak memory 204740 kb
Host smart-20a430f3-c64d-41b5-afec-477efd000f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26123
38006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2612338006
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.2058870803
Short name T1316
Test name
Test status
Simulation time 8389827656 ps
CPU time 10.5 seconds
Started May 16 03:22:31 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204676 kb
Host smart-b1d0084d-3afb-4c57-848f-27edfedf92f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20588
70803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.2058870803
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1400727837
Short name T907
Test name
Test status
Simulation time 8377202982 ps
CPU time 12.13 seconds
Started May 16 03:22:27 PM PDT 24
Finished May 16 03:22:51 PM PDT 24
Peak memory 204796 kb
Host smart-91620905-b255-4e9d-b5e2-6f25b81e606e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14007
27837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1400727837
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.178898451
Short name T842
Test name
Test status
Simulation time 8361209320 ps
CPU time 12.07 seconds
Started May 16 03:22:28 PM PDT 24
Finished May 16 03:22:52 PM PDT 24
Peak memory 204832 kb
Host smart-76c50e86-f306-49e0-93f9-62c50071c3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17889
8451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.178898451
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1120863734
Short name T275
Test name
Test status
Simulation time 20640810540 ps
CPU time 37.48 seconds
Started May 16 03:22:28 PM PDT 24
Finished May 16 03:23:16 PM PDT 24
Peak memory 204832 kb
Host smart-4be107e1-d26b-4291-96df-ddc9881330fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11208
63734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1120863734
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2771652467
Short name T752
Test name
Test status
Simulation time 8375317720 ps
CPU time 13.79 seconds
Started May 16 03:22:28 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204820 kb
Host smart-28203fc7-44d8-4436-8657-d0612024c579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27716
52467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2771652467
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1023644574
Short name T754
Test name
Test status
Simulation time 8463810053 ps
CPU time 11.67 seconds
Started May 16 03:22:33 PM PDT 24
Finished May 16 03:22:56 PM PDT 24
Peak memory 204888 kb
Host smart-2aeb88c8-7617-44c0-b6ff-4c7ef411ecc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10236
44574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1023644574
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.518938147
Short name T420
Test name
Test status
Simulation time 8388690598 ps
CPU time 11.16 seconds
Started May 16 03:22:29 PM PDT 24
Finished May 16 03:22:52 PM PDT 24
Peak memory 204812 kb
Host smart-b62a3f74-8d89-4120-bf6e-15eb91394908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51893
8147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.518938147
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.783430031
Short name T353
Test name
Test status
Simulation time 8364372904 ps
CPU time 11.89 seconds
Started May 16 03:22:29 PM PDT 24
Finished May 16 03:22:53 PM PDT 24
Peak memory 204900 kb
Host smart-4d9c18ad-baa1-4a86-8c9c-378641ebcc3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78343
0031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.783430031
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.448584974
Short name T1121
Test name
Test status
Simulation time 8377236781 ps
CPU time 11.33 seconds
Started May 16 03:22:26 PM PDT 24
Finished May 16 03:22:48 PM PDT 24
Peak memory 204860 kb
Host smart-09772b93-2a7b-433d-a054-dc919fc0cf80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44858
4974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.448584974
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2942639173
Short name T1153
Test name
Test status
Simulation time 8362057368 ps
CPU time 11.19 seconds
Started May 16 03:22:31 PM PDT 24
Finished May 16 03:22:55 PM PDT 24
Peak memory 204724 kb
Host smart-3ca0d2bb-a6d3-4ded-9883-a41723c85aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29426
39173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2942639173
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1100143404
Short name T1427
Test name
Test status
Simulation time 8522319020 ps
CPU time 11.98 seconds
Started May 16 03:22:30 PM PDT 24
Finished May 16 03:22:54 PM PDT 24
Peak memory 204820 kb
Host smart-579c2b6e-0944-400e-999c-66ba568ae542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11001
43404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1100143404
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.605903524
Short name T1437
Test name
Test status
Simulation time 8397538044 ps
CPU time 13.21 seconds
Started May 16 03:22:32 PM PDT 24
Finished May 16 03:22:57 PM PDT 24
Peak memory 204872 kb
Host smart-b01ecdc2-76af-4838-8078-f9fd3f2b77f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60590
3524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.605903524
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.772440154
Short name T1744
Test name
Test status
Simulation time 8393042778 ps
CPU time 11.72 seconds
Started May 16 03:22:30 PM PDT 24
Finished May 16 03:22:55 PM PDT 24
Peak memory 204904 kb
Host smart-ae05e5a4-b9f1-441f-86fb-87c7bbb5a8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77244
0154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.772440154
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.3681011599
Short name T699
Test name
Test status
Simulation time 8487487117 ps
CPU time 12.74 seconds
Started May 16 03:22:46 PM PDT 24
Finished May 16 03:23:08 PM PDT 24
Peak memory 204888 kb
Host smart-604b43cc-76e8-47d9-bce7-4c824eebad14
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3681011599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.3681011599
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.3760533738
Short name T580
Test name
Test status
Simulation time 8466034440 ps
CPU time 11.91 seconds
Started May 16 03:22:44 PM PDT 24
Finished May 16 03:23:05 PM PDT 24
Peak memory 204832 kb
Host smart-97948a43-65ea-4692-b72d-b88e4d4ad3c0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3760533738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.3760533738
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.462978876
Short name T1730
Test name
Test status
Simulation time 8434907028 ps
CPU time 12.59 seconds
Started May 16 03:22:43 PM PDT 24
Finished May 16 03:23:05 PM PDT 24
Peak memory 204836 kb
Host smart-66835f35-1429-4be3-9f77-391a6c1f5014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46297
8876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.462978876
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.336968653
Short name T1575
Test name
Test status
Simulation time 8376968850 ps
CPU time 11.73 seconds
Started May 16 03:22:36 PM PDT 24
Finished May 16 03:22:58 PM PDT 24
Peak memory 204808 kb
Host smart-77ceb981-3f76-485a-b09a-2719e3b0148c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33696
8653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.336968653
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.897577351
Short name T1707
Test name
Test status
Simulation time 8377229502 ps
CPU time 11.02 seconds
Started May 16 03:22:39 PM PDT 24
Finished May 16 03:23:01 PM PDT 24
Peak memory 204876 kb
Host smart-019f46a0-2219-4a48-b1be-30d3f53e9e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89757
7351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.897577351
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.3206224884
Short name T892
Test name
Test status
Simulation time 8365819008 ps
CPU time 10.87 seconds
Started May 16 03:22:37 PM PDT 24
Finished May 16 03:23:00 PM PDT 24
Peak memory 204864 kb
Host smart-31fc1b17-b4e5-467c-831c-cb6321aaf62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32062
24884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3206224884
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.185891257
Short name T850
Test name
Test status
Simulation time 8378507399 ps
CPU time 12.39 seconds
Started May 16 03:22:40 PM PDT 24
Finished May 16 03:23:03 PM PDT 24
Peak memory 204888 kb
Host smart-c611d4d4-8f97-44ee-9fff-82d9169624ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18589
1257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.185891257
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2695065539
Short name T938
Test name
Test status
Simulation time 9194414810 ps
CPU time 12.32 seconds
Started May 16 03:22:36 PM PDT 24
Finished May 16 03:22:59 PM PDT 24
Peak memory 204856 kb
Host smart-70b0f819-db35-46fd-9d3a-5a9778c11b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26950
65539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2695065539
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1801465476
Short name T1576
Test name
Test status
Simulation time 8395752038 ps
CPU time 12.4 seconds
Started May 16 03:22:37 PM PDT 24
Finished May 16 03:23:01 PM PDT 24
Peak memory 204760 kb
Host smart-31806284-3bba-4ed2-9c5c-8de4d8de1068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18014
65476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1801465476
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2006890476
Short name T795
Test name
Test status
Simulation time 8404608952 ps
CPU time 12.78 seconds
Started May 16 03:22:46 PM PDT 24
Finished May 16 03:23:09 PM PDT 24
Peak memory 204760 kb
Host smart-5b9c0af0-fee4-4c04-af4a-79d1ff5d1a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
90476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2006890476
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2200606312
Short name T1311
Test name
Test status
Simulation time 8363996336 ps
CPU time 13.08 seconds
Started May 16 03:22:46 PM PDT 24
Finished May 16 03:23:08 PM PDT 24
Peak memory 204736 kb
Host smart-ed69d168-8df2-4a00-b2ba-5ad731e85185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22006
06312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2200606312
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3605843256
Short name T969
Test name
Test status
Simulation time 8404265794 ps
CPU time 11.45 seconds
Started May 16 03:22:40 PM PDT 24
Finished May 16 03:23:02 PM PDT 24
Peak memory 204852 kb
Host smart-ab7952a1-e5a5-44dd-b230-c737bc0dd360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36058
43256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3605843256
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3005870263
Short name T1528
Test name
Test status
Simulation time 8412467028 ps
CPU time 12.63 seconds
Started May 16 03:22:36 PM PDT 24
Finished May 16 03:22:59 PM PDT 24
Peak memory 204808 kb
Host smart-e43fd6ed-aed7-4c79-a99a-08ae47f5a621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30058
70263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3005870263
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2863584423
Short name T1325
Test name
Test status
Simulation time 11511720036 ps
CPU time 13.98 seconds
Started May 16 03:22:36 PM PDT 24
Finished May 16 03:23:00 PM PDT 24
Peak memory 204760 kb
Host smart-eb315ef7-39fa-4bde-bbc8-2a1d9c010464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28635
84423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2863584423
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1244441980
Short name T483
Test name
Test status
Simulation time 8419102671 ps
CPU time 13.04 seconds
Started May 16 03:22:36 PM PDT 24
Finished May 16 03:23:00 PM PDT 24
Peak memory 204808 kb
Host smart-255fc46d-bbea-4816-b7c6-394fc92ebbe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12444
41980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1244441980
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1439421539
Short name T1414
Test name
Test status
Simulation time 8372228872 ps
CPU time 11.51 seconds
Started May 16 03:22:37 PM PDT 24
Finished May 16 03:22:59 PM PDT 24
Peak memory 204864 kb
Host smart-273edc92-10e5-405a-96dc-d750654c4363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14394
21539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1439421539
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.709028819
Short name T578
Test name
Test status
Simulation time 8423165901 ps
CPU time 11.24 seconds
Started May 16 03:22:37 PM PDT 24
Finished May 16 03:22:59 PM PDT 24
Peak memory 204796 kb
Host smart-e518b9f5-c5c9-430b-8db9-97d3a0f29130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70902
8819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.709028819
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.570702943
Short name T319
Test name
Test status
Simulation time 8418303224 ps
CPU time 11.1 seconds
Started May 16 03:22:36 PM PDT 24
Finished May 16 03:22:58 PM PDT 24
Peak memory 204908 kb
Host smart-c8453f84-1316-4cc0-9dd7-c59fb3f9080a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57070
2943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.570702943
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.31364470
Short name T356
Test name
Test status
Simulation time 8414679234 ps
CPU time 13.68 seconds
Started May 16 03:22:39 PM PDT 24
Finished May 16 03:23:04 PM PDT 24
Peak memory 204824 kb
Host smart-313bf424-e6a8-44e8-92a2-0910d4a60745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31364
470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.31364470
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3333053418
Short name T444
Test name
Test status
Simulation time 8387464387 ps
CPU time 11.71 seconds
Started May 16 03:22:37 PM PDT 24
Finished May 16 03:22:59 PM PDT 24
Peak memory 204896 kb
Host smart-dbffb341-8c76-4dfa-86ee-a85abdd1d572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33330
53418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3333053418
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3202033776
Short name T170
Test name
Test status
Simulation time 8411620335 ps
CPU time 12 seconds
Started May 16 03:22:35 PM PDT 24
Finished May 16 03:22:58 PM PDT 24
Peak memory 204888 kb
Host smart-f5b056c2-f43f-4a49-9e6b-5dc631ae4aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32020
33776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3202033776
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.2175740215
Short name T670
Test name
Test status
Simulation time 8368396407 ps
CPU time 12.81 seconds
Started May 16 03:22:36 PM PDT 24
Finished May 16 03:22:59 PM PDT 24
Peak memory 204768 kb
Host smart-2bba0427-3e48-486e-83f0-b1164046e550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21757
40215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.2175740215
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1620575625
Short name T440
Test name
Test status
Simulation time 8376576509 ps
CPU time 12 seconds
Started May 16 03:22:41 PM PDT 24
Finished May 16 03:23:03 PM PDT 24
Peak memory 204820 kb
Host smart-52f0f4f1-4e36-4167-a070-96db6abf7c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16205
75625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1620575625
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1629014860
Short name T1099
Test name
Test status
Simulation time 8369203303 ps
CPU time 13.12 seconds
Started May 16 03:22:40 PM PDT 24
Finished May 16 03:23:03 PM PDT 24
Peak memory 204888 kb
Host smart-6b25b26e-2c56-4824-8bc9-e0e363928056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16290
14860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1629014860
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3615952591
Short name T822
Test name
Test status
Simulation time 26112418055 ps
CPU time 52.26 seconds
Started May 16 03:22:38 PM PDT 24
Finished May 16 03:23:41 PM PDT 24
Peak memory 204932 kb
Host smart-4a5f3c5d-4d1c-4aa8-8530-dad4aa5ed475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36159
52591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3615952591
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.4105004988
Short name T1524
Test name
Test status
Simulation time 8405117533 ps
CPU time 12.06 seconds
Started May 16 03:22:36 PM PDT 24
Finished May 16 03:22:58 PM PDT 24
Peak memory 204812 kb
Host smart-95115d02-335d-4a59-8d89-afb9bc19726d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41050
04988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.4105004988
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3032296330
Short name T1501
Test name
Test status
Simulation time 8415198152 ps
CPU time 10.51 seconds
Started May 16 03:22:34 PM PDT 24
Finished May 16 03:22:56 PM PDT 24
Peak memory 204848 kb
Host smart-acddbbbb-5d74-4ce6-87fc-db3c92d71135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30322
96330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3032296330
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.629562882
Short name T889
Test name
Test status
Simulation time 8406275578 ps
CPU time 11.38 seconds
Started May 16 03:22:37 PM PDT 24
Finished May 16 03:23:00 PM PDT 24
Peak memory 204864 kb
Host smart-bdaa5fdb-5a12-4fe9-976b-2b0449cf4d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62956
2882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.629562882
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1523759970
Short name T1449
Test name
Test status
Simulation time 8362131990 ps
CPU time 10.45 seconds
Started May 16 03:22:36 PM PDT 24
Finished May 16 03:22:57 PM PDT 24
Peak memory 204856 kb
Host smart-5ec25d34-8f03-449d-b07f-eb74c835c072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15237
59970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1523759970
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1973353706
Short name T1253
Test name
Test status
Simulation time 8384060365 ps
CPU time 12.57 seconds
Started May 16 03:22:40 PM PDT 24
Finished May 16 03:23:03 PM PDT 24
Peak memory 204896 kb
Host smart-eaaca05c-1e2f-47ec-be95-bc369fe98d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19733
53706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1973353706
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3040962972
Short name T1525
Test name
Test status
Simulation time 8393501261 ps
CPU time 10.84 seconds
Started May 16 03:22:36 PM PDT 24
Finished May 16 03:22:58 PM PDT 24
Peak memory 204868 kb
Host smart-0560ed51-6989-45df-8e15-f4dd2f55e1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30409
62972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3040962972
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.240963362
Short name T1336
Test name
Test status
Simulation time 8423248190 ps
CPU time 12.65 seconds
Started May 16 03:22:36 PM PDT 24
Finished May 16 03:22:59 PM PDT 24
Peak memory 204904 kb
Host smart-738bdc42-bf87-44e2-b65b-109498a65bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24096
3362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.240963362
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.219401414
Short name T1646
Test name
Test status
Simulation time 8419374694 ps
CPU time 10.79 seconds
Started May 16 03:22:39 PM PDT 24
Finished May 16 03:23:00 PM PDT 24
Peak memory 204872 kb
Host smart-72865681-1888-4401-a26e-2837b19028e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21940
1414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.219401414
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.27304481
Short name T364
Test name
Test status
Simulation time 8403180022 ps
CPU time 11.3 seconds
Started May 16 03:22:37 PM PDT 24
Finished May 16 03:23:00 PM PDT 24
Peak memory 204992 kb
Host smart-62f526be-9595-401f-b7f2-58ba37ba5b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27304
481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.27304481
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.1169820155
Short name T526
Test name
Test status
Simulation time 8481849243 ps
CPU time 12.23 seconds
Started May 16 03:22:46 PM PDT 24
Finished May 16 03:23:07 PM PDT 24
Peak memory 204892 kb
Host smart-dcf2841c-f59a-47de-83ed-8bf6b34e103b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1169820155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.1169820155
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.1796102649
Short name T322
Test name
Test status
Simulation time 8389030031 ps
CPU time 12.66 seconds
Started May 16 03:22:51 PM PDT 24
Finished May 16 03:23:13 PM PDT 24
Peak memory 204836 kb
Host smart-fee6271f-cec7-4bd1-998a-5a10d6b7d8fe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1796102649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.1796102649
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.4175674609
Short name T1643
Test name
Test status
Simulation time 8458128127 ps
CPU time 10.61 seconds
Started May 16 03:22:47 PM PDT 24
Finished May 16 03:23:07 PM PDT 24
Peak memory 204916 kb
Host smart-ca1a7186-057c-4513-8ae1-c9656abf45b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41756
74609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.4175674609
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1565661607
Short name T1486
Test name
Test status
Simulation time 8374836529 ps
CPU time 11.36 seconds
Started May 16 03:22:45 PM PDT 24
Finished May 16 03:23:05 PM PDT 24
Peak memory 204924 kb
Host smart-507f3dc3-22c9-4aa7-b26f-a31d4f6fe0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15656
61607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1565661607
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.4242298153
Short name T1488
Test name
Test status
Simulation time 8402898256 ps
CPU time 12.66 seconds
Started May 16 03:22:45 PM PDT 24
Finished May 16 03:23:06 PM PDT 24
Peak memory 204832 kb
Host smart-97619e6f-ed9d-4743-a88a-d70822fbbd0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42422
98153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.4242298153
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3641291687
Short name T208
Test name
Test status
Simulation time 9035653492 ps
CPU time 13.25 seconds
Started May 16 03:22:45 PM PDT 24
Finished May 16 03:23:07 PM PDT 24
Peak memory 204752 kb
Host smart-9962b82f-1ab4-4fa9-8a94-759a40828786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36412
91687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3641291687
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.816602009
Short name T432
Test name
Test status
Simulation time 8375649714 ps
CPU time 12.2 seconds
Started May 16 03:22:47 PM PDT 24
Finished May 16 03:23:08 PM PDT 24
Peak memory 204800 kb
Host smart-acc1527f-d013-4dad-a786-bbaaf221dbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81660
2009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.816602009
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1335549464
Short name T1757
Test name
Test status
Simulation time 8376767050 ps
CPU time 12.92 seconds
Started May 16 03:22:45 PM PDT 24
Finished May 16 03:23:07 PM PDT 24
Peak memory 204744 kb
Host smart-a1551427-0f67-437e-a52e-8e2480a45098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13355
49464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1335549464
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.4243639941
Short name T924
Test name
Test status
Simulation time 8399283610 ps
CPU time 12.03 seconds
Started May 16 03:22:51 PM PDT 24
Finished May 16 03:23:12 PM PDT 24
Peak memory 204744 kb
Host smart-e49870da-7176-462a-9062-1f14d210fbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42436
39941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.4243639941
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.726312215
Short name T1254
Test name
Test status
Simulation time 8454217972 ps
CPU time 11.1 seconds
Started May 16 03:22:46 PM PDT 24
Finished May 16 03:23:07 PM PDT 24
Peak memory 204888 kb
Host smart-e4986d20-314c-47d2-97c9-5cddaa10320a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72631
2215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.726312215
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1471459646
Short name T584
Test name
Test status
Simulation time 8367116443 ps
CPU time 11.9 seconds
Started May 16 03:22:44 PM PDT 24
Finished May 16 03:23:05 PM PDT 24
Peak memory 204848 kb
Host smart-12ceb081-f20d-4bf9-b393-ac8eb076f3a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14714
59646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1471459646
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1646724904
Short name T88
Test name
Test status
Simulation time 8444364279 ps
CPU time 12.43 seconds
Started May 16 03:22:46 PM PDT 24
Finished May 16 03:23:07 PM PDT 24
Peak memory 204740 kb
Host smart-1f36083e-3f81-4d7a-b1a8-2974c39e310e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16467
24904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1646724904
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.1278473764
Short name T339
Test name
Test status
Simulation time 8449070870 ps
CPU time 10.99 seconds
Started May 16 03:22:44 PM PDT 24
Finished May 16 03:23:04 PM PDT 24
Peak memory 204872 kb
Host smart-ebbb3c10-4cee-4e0c-a587-0f2120d730f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12784
73764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.1278473764
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1493728217
Short name T861
Test name
Test status
Simulation time 11542488682 ps
CPU time 14.09 seconds
Started May 16 03:22:47 PM PDT 24
Finished May 16 03:23:10 PM PDT 24
Peak memory 204832 kb
Host smart-14e15c8d-c1a7-4d98-ae8d-ad65d333d9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14937
28217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1493728217
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1250032060
Short name T816
Test name
Test status
Simulation time 8441550037 ps
CPU time 11.08 seconds
Started May 16 03:22:45 PM PDT 24
Finished May 16 03:23:05 PM PDT 24
Peak memory 204856 kb
Host smart-a1158935-821f-41f0-b2ec-92839c24e4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12500
32060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1250032060
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2920530401
Short name T468
Test name
Test status
Simulation time 8368541249 ps
CPU time 12.14 seconds
Started May 16 03:22:48 PM PDT 24
Finished May 16 03:23:09 PM PDT 24
Peak memory 204800 kb
Host smart-578fb5c3-246f-49f0-a767-3b9453092e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29205
30401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2920530401
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2283166758
Short name T1212
Test name
Test status
Simulation time 8444611287 ps
CPU time 13.17 seconds
Started May 16 03:22:44 PM PDT 24
Finished May 16 03:23:06 PM PDT 24
Peak memory 204856 kb
Host smart-d6043bc7-2aba-4414-a39e-32554b3ae6bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22831
66758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2283166758
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.4151216204
Short name T844
Test name
Test status
Simulation time 8415513217 ps
CPU time 12.64 seconds
Started May 16 03:22:48 PM PDT 24
Finished May 16 03:23:10 PM PDT 24
Peak memory 204848 kb
Host smart-da307c12-62c7-4660-a3ae-a51ca63808d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41512
16204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.4151216204
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.620892815
Short name T1683
Test name
Test status
Simulation time 8390408575 ps
CPU time 13.39 seconds
Started May 16 03:22:44 PM PDT 24
Finished May 16 03:23:06 PM PDT 24
Peak memory 204904 kb
Host smart-c20f2273-ab58-4fdc-a00e-7d190f31e517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62089
2815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.620892815
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3562401353
Short name T342
Test name
Test status
Simulation time 8390527377 ps
CPU time 12.52 seconds
Started May 16 03:22:47 PM PDT 24
Finished May 16 03:23:09 PM PDT 24
Peak memory 204812 kb
Host smart-0d80ac95-e19c-4b6e-8d5a-4905f923bb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35624
01353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3562401353
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3156402920
Short name T933
Test name
Test status
Simulation time 8461927956 ps
CPU time 11.42 seconds
Started May 16 03:22:44 PM PDT 24
Finished May 16 03:23:04 PM PDT 24
Peak memory 204896 kb
Host smart-d525c001-3931-43a9-a224-8db1a1489aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31564
02920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3156402920
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.3801059972
Short name T400
Test name
Test status
Simulation time 8424450550 ps
CPU time 11.75 seconds
Started May 16 03:22:46 PM PDT 24
Finished May 16 03:23:07 PM PDT 24
Peak memory 204820 kb
Host smart-0ca5c10f-9c09-47e3-9883-2fef75e0c8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38010
59972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.3801059972
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.106655605
Short name T61
Test name
Test status
Simulation time 8367789325 ps
CPU time 11.72 seconds
Started May 16 03:22:43 PM PDT 24
Finished May 16 03:23:04 PM PDT 24
Peak memory 204772 kb
Host smart-03117539-6a92-4bc1-9881-2e60ac732db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10665
5605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.106655605
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.433873975
Short name T814
Test name
Test status
Simulation time 8366724891 ps
CPU time 11.34 seconds
Started May 16 03:22:45 PM PDT 24
Finished May 16 03:23:06 PM PDT 24
Peak memory 204856 kb
Host smart-2748f2b2-97b6-49e4-b193-dec2700e22ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43387
3975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.433873975
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2112427752
Short name T230
Test name
Test status
Simulation time 26769384300 ps
CPU time 51.61 seconds
Started May 16 03:22:46 PM PDT 24
Finished May 16 03:23:47 PM PDT 24
Peak memory 204796 kb
Host smart-339bcb43-1d0a-42bc-a70e-baf240bdb770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21124
27752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2112427752
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1239052040
Short name T1506
Test name
Test status
Simulation time 8384377960 ps
CPU time 13.66 seconds
Started May 16 03:22:44 PM PDT 24
Finished May 16 03:23:06 PM PDT 24
Peak memory 204820 kb
Host smart-14047f54-15fa-43f5-8ee4-8040ea31ec8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12390
52040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1239052040
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1198678297
Short name T954
Test name
Test status
Simulation time 8437752719 ps
CPU time 11.49 seconds
Started May 16 03:22:46 PM PDT 24
Finished May 16 03:23:07 PM PDT 24
Peak memory 204796 kb
Host smart-36133d2a-f284-4a71-8153-866095ff21b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986
78297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1198678297
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.2015599945
Short name T568
Test name
Test status
Simulation time 8401166952 ps
CPU time 12.78 seconds
Started May 16 03:22:44 PM PDT 24
Finished May 16 03:23:05 PM PDT 24
Peak memory 204824 kb
Host smart-3721edd7-d522-4f9b-9c96-05930b66b1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20155
99945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.2015599945
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.979859490
Short name T36
Test name
Test status
Simulation time 8371406580 ps
CPU time 11.22 seconds
Started May 16 03:22:45 PM PDT 24
Finished May 16 03:23:05 PM PDT 24
Peak memory 204796 kb
Host smart-f419f580-3e48-4605-b038-1010cdc39019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97985
9490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.979859490
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.527023251
Short name T174
Test name
Test status
Simulation time 8395895915 ps
CPU time 13.25 seconds
Started May 16 03:22:44 PM PDT 24
Finished May 16 03:23:06 PM PDT 24
Peak memory 204836 kb
Host smart-5fa8f46b-df6a-4f39-99e4-f1ae7b134d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52702
3251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.527023251
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1374194507
Short name T1267
Test name
Test status
Simulation time 8367179677 ps
CPU time 10.65 seconds
Started May 16 03:22:46 PM PDT 24
Finished May 16 03:23:06 PM PDT 24
Peak memory 204840 kb
Host smart-7eed8747-efdd-4448-af2a-253caa859904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13741
94507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1374194507
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3874950874
Short name T1542
Test name
Test status
Simulation time 8447189224 ps
CPU time 13.71 seconds
Started May 16 03:22:51 PM PDT 24
Finished May 16 03:23:14 PM PDT 24
Peak memory 204784 kb
Host smart-a1bdc469-f807-48d5-8aee-44e4a2206308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38749
50874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3874950874
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.654038319
Short name T803
Test name
Test status
Simulation time 8392507243 ps
CPU time 13.77 seconds
Started May 16 03:22:45 PM PDT 24
Finished May 16 03:23:08 PM PDT 24
Peak memory 204832 kb
Host smart-2ba794f5-9b65-401e-aac2-204b00c1da64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65403
8319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.654038319
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2019152745
Short name T602
Test name
Test status
Simulation time 8396445809 ps
CPU time 10.82 seconds
Started May 16 03:22:43 PM PDT 24
Finished May 16 03:23:03 PM PDT 24
Peak memory 204860 kb
Host smart-904b2a54-9f33-483c-a806-d962b512b0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20191
52745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2019152745
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.906338278
Short name T1446
Test name
Test status
Simulation time 8508048480 ps
CPU time 11.49 seconds
Started May 16 03:23:01 PM PDT 24
Finished May 16 03:23:20 PM PDT 24
Peak memory 204808 kb
Host smart-eb87b995-872f-4ef2-b384-13b85b4e20cb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=906338278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.906338278
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.4113296882
Short name T1303
Test name
Test status
Simulation time 8384856321 ps
CPU time 12.56 seconds
Started May 16 03:23:00 PM PDT 24
Finished May 16 03:23:21 PM PDT 24
Peak memory 204860 kb
Host smart-1a2ff761-4a1d-48dd-874a-d16f840ffbab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4113296882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.4113296882
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.4059625336
Short name T1518
Test name
Test status
Simulation time 8446388287 ps
CPU time 11.53 seconds
Started May 16 03:22:52 PM PDT 24
Finished May 16 03:23:14 PM PDT 24
Peak memory 204860 kb
Host smart-52b0a2d3-8dbb-4e5f-8eed-a1c3bf6b16cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40596
25336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.4059625336
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1091597917
Short name T354
Test name
Test status
Simulation time 8387526643 ps
CPU time 12.22 seconds
Started May 16 03:22:55 PM PDT 24
Finished May 16 03:23:16 PM PDT 24
Peak memory 204848 kb
Host smart-d7603f1c-506a-4fc9-89dd-0b0063a7b851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10915
97917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1091597917
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.3818873095
Short name T193
Test name
Test status
Simulation time 8972161363 ps
CPU time 12.04 seconds
Started May 16 03:23:01 PM PDT 24
Finished May 16 03:23:21 PM PDT 24
Peak memory 204876 kb
Host smart-330ac1dd-9144-47ef-a6c5-ee70a4a95c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38188
73095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3818873095
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.432906995
Short name T1264
Test name
Test status
Simulation time 8368884654 ps
CPU time 11.29 seconds
Started May 16 03:22:52 PM PDT 24
Finished May 16 03:23:13 PM PDT 24
Peak memory 204880 kb
Host smart-6a82cb1f-639f-4a18-b06f-07db91f245f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43290
6995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.432906995
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2264938727
Short name T1315
Test name
Test status
Simulation time 8377072312 ps
CPU time 11.55 seconds
Started May 16 03:22:51 PM PDT 24
Finished May 16 03:23:12 PM PDT 24
Peak memory 204864 kb
Host smart-431bcd52-bb8c-4d4f-b4c0-12561c04f27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22649
38727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2264938727
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.466206818
Short name T1201
Test name
Test status
Simulation time 8975394846 ps
CPU time 12.45 seconds
Started May 16 03:22:52 PM PDT 24
Finished May 16 03:23:14 PM PDT 24
Peak memory 204776 kb
Host smart-264beb95-0809-4ff4-af05-13119dfe84e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46620
6818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.466206818
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.968390508
Short name T1020
Test name
Test status
Simulation time 8649170270 ps
CPU time 13.68 seconds
Started May 16 03:23:01 PM PDT 24
Finished May 16 03:23:22 PM PDT 24
Peak memory 204840 kb
Host smart-ab6db210-74df-4ca7-8002-82074be9f6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96839
0508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.968390508
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3098618673
Short name T148
Test name
Test status
Simulation time 8492087160 ps
CPU time 14.64 seconds
Started May 16 03:22:54 PM PDT 24
Finished May 16 03:23:18 PM PDT 24
Peak memory 204860 kb
Host smart-d4f77644-0134-48b2-992b-358ca136fac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30986
18673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3098618673
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1759833447
Short name T1223
Test name
Test status
Simulation time 8423619257 ps
CPU time 10.95 seconds
Started May 16 03:22:54 PM PDT 24
Finished May 16 03:23:14 PM PDT 24
Peak memory 204824 kb
Host smart-6c932bc3-2874-4919-a1cb-c43fc62a2b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17598
33447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1759833447
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.359571867
Short name T1468
Test name
Test status
Simulation time 8414026872 ps
CPU time 11.37 seconds
Started May 16 03:22:53 PM PDT 24
Finished May 16 03:23:14 PM PDT 24
Peak memory 204784 kb
Host smart-7ea44522-95e2-4fcf-88a1-c341bce48224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35957
1867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.359571867
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3192094220
Short name T681
Test name
Test status
Simulation time 8415853855 ps
CPU time 11.16 seconds
Started May 16 03:22:52 PM PDT 24
Finished May 16 03:23:12 PM PDT 24
Peak memory 204868 kb
Host smart-68b4cd43-fd30-4e00-807b-077e1d948baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31920
94220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3192094220
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1024326783
Short name T425
Test name
Test status
Simulation time 11559859158 ps
CPU time 14.31 seconds
Started May 16 03:22:53 PM PDT 24
Finished May 16 03:23:17 PM PDT 24
Peak memory 204852 kb
Host smart-7865f70d-a626-4100-832f-fd401165b187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10243
26783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1024326783
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1173137604
Short name T1328
Test name
Test status
Simulation time 8423196313 ps
CPU time 13.22 seconds
Started May 16 03:22:52 PM PDT 24
Finished May 16 03:23:14 PM PDT 24
Peak memory 204852 kb
Host smart-603df6c8-df2d-4fe5-8865-f7f56755b374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11731
37604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1173137604
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1878056469
Short name T1438
Test name
Test status
Simulation time 8373371458 ps
CPU time 13.04 seconds
Started May 16 03:23:01 PM PDT 24
Finished May 16 03:23:22 PM PDT 24
Peak memory 204804 kb
Host smart-32a2ed78-217c-4c27-99f9-7a45fbcffc01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18780
56469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1878056469
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3184044732
Short name T137
Test name
Test status
Simulation time 8410772450 ps
CPU time 11.57 seconds
Started May 16 03:22:55 PM PDT 24
Finished May 16 03:23:16 PM PDT 24
Peak memory 204904 kb
Host smart-bae3208a-7a4d-4dc9-946b-ab60a2f46ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31840
44732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3184044732
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1740549148
Short name T625
Test name
Test status
Simulation time 8423388670 ps
CPU time 10.99 seconds
Started May 16 03:22:57 PM PDT 24
Finished May 16 03:23:17 PM PDT 24
Peak memory 204752 kb
Host smart-80daa3b9-1873-4db9-a34d-e9e9064498ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17405
49148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1740549148
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.661707092
Short name T983
Test name
Test status
Simulation time 8404010796 ps
CPU time 11.25 seconds
Started May 16 03:23:01 PM PDT 24
Finished May 16 03:23:20 PM PDT 24
Peak memory 204848 kb
Host smart-0207d3e3-8153-4d19-a508-3fcd55fcad45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66170
7092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.661707092
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2162564786
Short name T647
Test name
Test status
Simulation time 8412921748 ps
CPU time 11.76 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:21 PM PDT 24
Peak memory 204828 kb
Host smart-f00f80d7-0492-44b4-b238-28ad16b40686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21625
64786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2162564786
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.948009951
Short name T905
Test name
Test status
Simulation time 8405662496 ps
CPU time 12.72 seconds
Started May 16 03:22:52 PM PDT 24
Finished May 16 03:23:14 PM PDT 24
Peak memory 204828 kb
Host smart-50b523ae-4f59-4709-9e08-471c135696c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94800
9951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.948009951
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.1903840507
Short name T947
Test name
Test status
Simulation time 8391486778 ps
CPU time 12.38 seconds
Started May 16 03:22:53 PM PDT 24
Finished May 16 03:23:15 PM PDT 24
Peak memory 204788 kb
Host smart-6a01d54b-9095-4780-90b3-044c93f10481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19038
40507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.1903840507
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1985642542
Short name T1393
Test name
Test status
Simulation time 8376273922 ps
CPU time 11.01 seconds
Started May 16 03:22:53 PM PDT 24
Finished May 16 03:23:14 PM PDT 24
Peak memory 204808 kb
Host smart-6bc88e0c-5ba3-4cc8-abb7-ea1bad59afc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19856
42542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1985642542
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1240890587
Short name T1711
Test name
Test status
Simulation time 8370629120 ps
CPU time 11.24 seconds
Started May 16 03:22:56 PM PDT 24
Finished May 16 03:23:16 PM PDT 24
Peak memory 204864 kb
Host smart-089c8c57-abe8-4e60-be13-7652e7ff3b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12408
90587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1240890587
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3030312188
Short name T272
Test name
Test status
Simulation time 19776799450 ps
CPU time 41.89 seconds
Started May 16 03:22:52 PM PDT 24
Finished May 16 03:23:44 PM PDT 24
Peak memory 204872 kb
Host smart-33590b68-4c9b-4956-8258-91473a797852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30303
12188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3030312188
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.4287543016
Short name T1190
Test name
Test status
Simulation time 8370439685 ps
CPU time 12.84 seconds
Started May 16 03:22:53 PM PDT 24
Finished May 16 03:23:15 PM PDT 24
Peak memory 204820 kb
Host smart-84b483d6-770e-4f7a-978a-c52349c341ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42875
43016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.4287543016
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.88846148
Short name T1681
Test name
Test status
Simulation time 8534951201 ps
CPU time 12.16 seconds
Started May 16 03:22:52 PM PDT 24
Finished May 16 03:23:14 PM PDT 24
Peak memory 204932 kb
Host smart-d9c52ff1-27a7-4a02-bf7b-432fae98b385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88846
148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.88846148
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2355740386
Short name T987
Test name
Test status
Simulation time 8396813225 ps
CPU time 11.8 seconds
Started May 16 03:22:53 PM PDT 24
Finished May 16 03:23:14 PM PDT 24
Peak memory 204840 kb
Host smart-f33d4485-3d31-4d89-bc01-af019acd09ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23557
40386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2355740386
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3809555480
Short name T1093
Test name
Test status
Simulation time 8362759076 ps
CPU time 11.76 seconds
Started May 16 03:22:54 PM PDT 24
Finished May 16 03:23:15 PM PDT 24
Peak memory 204916 kb
Host smart-2286ac4b-f488-4690-a27b-37da1711f35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38095
55480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3809555480
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1979228305
Short name T1621
Test name
Test status
Simulation time 8381288873 ps
CPU time 11.76 seconds
Started May 16 03:22:51 PM PDT 24
Finished May 16 03:23:13 PM PDT 24
Peak memory 204812 kb
Host smart-196c6536-d775-4126-a780-1a8ed32496b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19792
28305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1979228305
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1709854148
Short name T622
Test name
Test status
Simulation time 8375056771 ps
CPU time 11.26 seconds
Started May 16 03:22:56 PM PDT 24
Finished May 16 03:23:16 PM PDT 24
Peak memory 204812 kb
Host smart-ef7da83d-7f14-433a-84d7-5ff2cba9086c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17098
54148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1709854148
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3708068884
Short name T1337
Test name
Test status
Simulation time 8422831691 ps
CPU time 13.84 seconds
Started May 16 03:22:45 PM PDT 24
Finished May 16 03:23:07 PM PDT 24
Peak memory 204844 kb
Host smart-e78f5d16-bdc0-465d-b40e-05785bd43cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37080
68884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3708068884
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1999261208
Short name T1713
Test name
Test status
Simulation time 8476067217 ps
CPU time 11.25 seconds
Started May 16 03:22:51 PM PDT 24
Finished May 16 03:23:12 PM PDT 24
Peak memory 204744 kb
Host smart-96fa23c0-53df-4577-95f4-79e5059c6799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19992
61208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1999261208
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.4166198598
Short name T926
Test name
Test status
Simulation time 8419904916 ps
CPU time 13.35 seconds
Started May 16 03:22:55 PM PDT 24
Finished May 16 03:23:18 PM PDT 24
Peak memory 204816 kb
Host smart-bb12f694-38a3-4d5a-a97b-cdb7298bc286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41661
98598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.4166198598
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.3106722644
Short name T1411
Test name
Test status
Simulation time 8464488676 ps
CPU time 10.86 seconds
Started May 16 03:23:08 PM PDT 24
Finished May 16 03:23:25 PM PDT 24
Peak memory 204808 kb
Host smart-649723e3-9874-4db0-8be1-c6282e172bc9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3106722644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.3106722644
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.1105794029
Short name T1391
Test name
Test status
Simulation time 8376235396 ps
CPU time 13.69 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204880 kb
Host smart-0b1cec91-6b46-424e-877b-54641a73555d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1105794029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.1105794029
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.2657017148
Short name T1129
Test name
Test status
Simulation time 8396624121 ps
CPU time 11.11 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:27 PM PDT 24
Peak memory 204896 kb
Host smart-bf52469f-c286-4308-9ed8-e6469a01f1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26570
17148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.2657017148
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1258206036
Short name T886
Test name
Test status
Simulation time 8405632936 ps
CPU time 13.21 seconds
Started May 16 03:22:53 PM PDT 24
Finished May 16 03:23:16 PM PDT 24
Peak memory 204860 kb
Host smart-cd78910a-0745-49a0-9c96-73994aa8c7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
06036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1258206036
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2333638193
Short name T108
Test name
Test status
Simulation time 8397502419 ps
CPU time 12.76 seconds
Started May 16 03:22:57 PM PDT 24
Finished May 16 03:23:18 PM PDT 24
Peak memory 204688 kb
Host smart-323163c5-9158-4c3a-94d2-8526d67ba3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23336
38193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2333638193
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.67978307
Short name T1472
Test name
Test status
Simulation time 9270731623 ps
CPU time 13.78 seconds
Started May 16 03:22:54 PM PDT 24
Finished May 16 03:23:17 PM PDT 24
Peak memory 204824 kb
Host smart-59b804e3-c712-48a9-a71e-5c9195deb2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67978
307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.67978307
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2724701081
Short name T532
Test name
Test status
Simulation time 8380276311 ps
CPU time 12.21 seconds
Started May 16 03:23:05 PM PDT 24
Finished May 16 03:23:23 PM PDT 24
Peak memory 204796 kb
Host smart-7ae25aea-14f5-47e9-b2b2-f53d8a7dcbbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27247
01081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2724701081
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.23162443
Short name T1388
Test name
Test status
Simulation time 8373387971 ps
CPU time 10.99 seconds
Started May 16 03:22:53 PM PDT 24
Finished May 16 03:23:13 PM PDT 24
Peak memory 204852 kb
Host smart-f99add48-4fd4-4aa9-a34e-3a58bff8c5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23162
443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.23162443
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3550465430
Short name T357
Test name
Test status
Simulation time 8418121249 ps
CPU time 12.8 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:22 PM PDT 24
Peak memory 204892 kb
Host smart-4bd85c23-a67f-43f2-8336-f4f19fd06ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35504
65430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3550465430
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.764854867
Short name T777
Test name
Test status
Simulation time 8395573721 ps
CPU time 11.33 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:28 PM PDT 24
Peak memory 204884 kb
Host smart-89aa1ab7-5b5e-4bf0-a6ff-99a7feab6f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76485
4867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.764854867
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2666018513
Short name T936
Test name
Test status
Simulation time 8412357231 ps
CPU time 12.42 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204872 kb
Host smart-c1e7df36-86a2-440e-baf6-32cef40f57c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26660
18513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2666018513
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1440476791
Short name T627
Test name
Test status
Simulation time 8468394789 ps
CPU time 10.9 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:21 PM PDT 24
Peak memory 204876 kb
Host smart-65359243-7d12-42a4-b61b-b2f2b3700fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14404
76791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1440476791
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.3699196455
Short name T1442
Test name
Test status
Simulation time 8397755377 ps
CPU time 10.44 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:20 PM PDT 24
Peak memory 204892 kb
Host smart-d256e3b4-9d82-40e4-a8d5-1cd3ba8f8b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36991
96455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3699196455
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3338484989
Short name T1473
Test name
Test status
Simulation time 11560224244 ps
CPU time 15.07 seconds
Started May 16 03:23:09 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204776 kb
Host smart-9791f9f9-693a-4e8e-846e-bfab1c38fbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33384
84989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3338484989
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.986299721
Short name T780
Test name
Test status
Simulation time 8414369434 ps
CPU time 12.33 seconds
Started May 16 03:23:01 PM PDT 24
Finished May 16 03:23:21 PM PDT 24
Peak memory 204824 kb
Host smart-39139950-4690-42c5-b6a3-41fc72655128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98629
9721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.986299721
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3174418316
Short name T373
Test name
Test status
Simulation time 8370910226 ps
CPU time 12.82 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:22 PM PDT 24
Peak memory 204864 kb
Host smart-f6b88c83-39f3-4c35-b3cb-44fa0c746eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31744
18316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3174418316
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.371257969
Short name T1654
Test name
Test status
Simulation time 8452628973 ps
CPU time 11.97 seconds
Started May 16 03:23:03 PM PDT 24
Finished May 16 03:23:22 PM PDT 24
Peak memory 204776 kb
Host smart-6d07fb54-1748-43f9-a49c-c86f5c9cf4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37125
7969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.371257969
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2177463400
Short name T788
Test name
Test status
Simulation time 8426277504 ps
CPU time 10.61 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:20 PM PDT 24
Peak memory 204844 kb
Host smart-2a1bbebe-ed2a-4298-9cab-e6ed180d943c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21774
63400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2177463400
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2444929548
Short name T1287
Test name
Test status
Simulation time 8417366684 ps
CPU time 12.23 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:21 PM PDT 24
Peak memory 204868 kb
Host smart-e7705744-6429-4919-aa1e-ea674b55dbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24449
29548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2444929548
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2139982518
Short name T437
Test name
Test status
Simulation time 8400836026 ps
CPU time 10.86 seconds
Started May 16 03:23:04 PM PDT 24
Finished May 16 03:23:21 PM PDT 24
Peak memory 204864 kb
Host smart-e9d09467-8ad2-4aa2-abe2-580715671254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21399
82518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2139982518
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.731098838
Short name T1321
Test name
Test status
Simulation time 8400244052 ps
CPU time 13.55 seconds
Started May 16 03:23:03 PM PDT 24
Finished May 16 03:23:24 PM PDT 24
Peak memory 204896 kb
Host smart-41be4121-110a-4770-8324-b34b0152284e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73109
8838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.731098838
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.4019125713
Short name T1059
Test name
Test status
Simulation time 8390702348 ps
CPU time 14.24 seconds
Started May 16 03:23:03 PM PDT 24
Finished May 16 03:23:25 PM PDT 24
Peak memory 204824 kb
Host smart-748053f8-e275-4cae-9982-3c3b512b18d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40191
25713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.4019125713
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.4138224176
Short name T536
Test name
Test status
Simulation time 8382436493 ps
CPU time 11.23 seconds
Started May 16 03:23:05 PM PDT 24
Finished May 16 03:23:22 PM PDT 24
Peak memory 204748 kb
Host smart-6368c4bc-79c3-4214-97d0-713a962eda8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41382
24176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.4138224176
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.420008406
Short name T1170
Test name
Test status
Simulation time 8369682932 ps
CPU time 14.09 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:24 PM PDT 24
Peak memory 204864 kb
Host smart-ef250f99-ae22-4e2e-8dad-926956ca9cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42000
8406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.420008406
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2744863785
Short name T834
Test name
Test status
Simulation time 21613546508 ps
CPU time 39.02 seconds
Started May 16 03:23:01 PM PDT 24
Finished May 16 03:23:48 PM PDT 24
Peak memory 204828 kb
Host smart-1515e15c-cb7a-40e7-9033-63d83a40f175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27448
63785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2744863785
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1011735887
Short name T1243
Test name
Test status
Simulation time 8407930666 ps
CPU time 11.5 seconds
Started May 16 03:23:01 PM PDT 24
Finished May 16 03:23:20 PM PDT 24
Peak memory 204920 kb
Host smart-d408355c-98b5-4908-b791-344d4a004beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10117
35887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1011735887
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1881929359
Short name T1689
Test name
Test status
Simulation time 8446872238 ps
CPU time 11.63 seconds
Started May 16 03:23:00 PM PDT 24
Finished May 16 03:23:20 PM PDT 24
Peak memory 204864 kb
Host smart-799c932f-457f-46b1-8e9f-edd71d66f422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18819
29359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1881929359
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.1245083399
Short name T1749
Test name
Test status
Simulation time 8388953857 ps
CPU time 12.27 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:22 PM PDT 24
Peak memory 204840 kb
Host smart-f1d84388-33ea-4a86-b938-b69afff193cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12450
83399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.1245083399
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2377366482
Short name T764
Test name
Test status
Simulation time 8367648661 ps
CPU time 11.87 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:22 PM PDT 24
Peak memory 204776 kb
Host smart-9b975f05-7273-40d4-9a51-a678c26bc7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23773
66482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2377366482
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3077448695
Short name T1326
Test name
Test status
Simulation time 8380194376 ps
CPU time 12.12 seconds
Started May 16 03:23:05 PM PDT 24
Finished May 16 03:23:23 PM PDT 24
Peak memory 204868 kb
Host smart-f63eaf31-2ce2-4ed5-a6d1-e824c8b241b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30774
48695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3077448695
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1954979090
Short name T637
Test name
Test status
Simulation time 8364090662 ps
CPU time 11.05 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:20 PM PDT 24
Peak memory 204784 kb
Host smart-20aa69d0-62dd-4c50-8ca4-c0bd440b07eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19549
79090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1954979090
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.745660319
Short name T1401
Test name
Test status
Simulation time 8412414932 ps
CPU time 13.35 seconds
Started May 16 03:22:53 PM PDT 24
Finished May 16 03:23:16 PM PDT 24
Peak memory 204800 kb
Host smart-7a84a51f-0cc9-4183-98bb-ffcd5eddbab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74566
0319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.745660319
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3506693997
Short name T1033
Test name
Test status
Simulation time 8383987439 ps
CPU time 11.03 seconds
Started May 16 03:23:07 PM PDT 24
Finished May 16 03:23:24 PM PDT 24
Peak memory 204692 kb
Host smart-44d5e5a0-d526-402d-a949-334291e577c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35066
93997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3506693997
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2570611987
Short name T1234
Test name
Test status
Simulation time 8388173233 ps
CPU time 10.92 seconds
Started May 16 03:23:02 PM PDT 24
Finished May 16 03:23:20 PM PDT 24
Peak memory 204864 kb
Host smart-71c6f23a-0a7c-4cd4-be07-5e8dd0ef03da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25706
11987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2570611987
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.37916184
Short name T1444
Test name
Test status
Simulation time 8536613093 ps
CPU time 14.42 seconds
Started May 16 03:19:24 PM PDT 24
Finished May 16 03:19:44 PM PDT 24
Peak memory 204788 kb
Host smart-44f167df-3455-4659-be7d-2016e8253e6e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=37916184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.37916184
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.1038286403
Short name T746
Test name
Test status
Simulation time 8380976271 ps
CPU time 11.52 seconds
Started May 16 03:19:15 PM PDT 24
Finished May 16 03:19:32 PM PDT 24
Peak memory 204792 kb
Host smart-a1300fca-34a4-4df1-aeab-242cd8f0de33
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1038286403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.1038286403
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.3799252536
Short name T1307
Test name
Test status
Simulation time 8423058382 ps
CPU time 12.56 seconds
Started May 16 03:19:14 PM PDT 24
Finished May 16 03:19:31 PM PDT 24
Peak memory 204836 kb
Host smart-4d00a5aa-cc3f-43ea-a9ad-eb80353b8e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37992
52536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.3799252536
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.567603787
Short name T1495
Test name
Test status
Simulation time 8383495163 ps
CPU time 11.23 seconds
Started May 16 03:19:10 PM PDT 24
Finished May 16 03:19:26 PM PDT 24
Peak memory 204728 kb
Host smart-03847f9e-6cab-414a-96e0-3b1f9935d8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56760
3787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.567603787
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.2972117721
Short name T1566
Test name
Test status
Simulation time 9247773461 ps
CPU time 14.35 seconds
Started May 16 03:19:07 PM PDT 24
Finished May 16 03:19:26 PM PDT 24
Peak memory 204864 kb
Host smart-2b6a03fb-dcb7-466d-8a24-c54642f1ed1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29721
17721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.2972117721
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.767328994
Short name T1747
Test name
Test status
Simulation time 8363017572 ps
CPU time 11.3 seconds
Started May 16 03:19:17 PM PDT 24
Finished May 16 03:19:33 PM PDT 24
Peak memory 204872 kb
Host smart-f599996f-b93b-41dc-b3d8-99bb796baa44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76732
8994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.767328994
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.801160271
Short name T917
Test name
Test status
Simulation time 8382923987 ps
CPU time 10.72 seconds
Started May 16 03:19:07 PM PDT 24
Finished May 16 03:19:23 PM PDT 24
Peak memory 204868 kb
Host smart-a0e058d0-5858-43a2-a097-4cdc0607e98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80116
0271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.801160271
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.545386232
Short name T438
Test name
Test status
Simulation time 8391847113 ps
CPU time 12.85 seconds
Started May 16 03:19:18 PM PDT 24
Finished May 16 03:19:35 PM PDT 24
Peak memory 204812 kb
Host smart-42c7fd28-42bc-4427-ae27-863e4ed8896e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54538
6232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.545386232
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.189882792
Short name T906
Test name
Test status
Simulation time 8441163325 ps
CPU time 11.31 seconds
Started May 16 03:19:16 PM PDT 24
Finished May 16 03:19:32 PM PDT 24
Peak memory 204800 kb
Host smart-0e94647c-6600-4537-91fe-e591bf19896e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18988
2792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.189882792
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2940007138
Short name T1610
Test name
Test status
Simulation time 8411410005 ps
CPU time 11.86 seconds
Started May 16 03:19:15 PM PDT 24
Finished May 16 03:19:32 PM PDT 24
Peak memory 204876 kb
Host smart-06289042-8fde-4ef4-9541-eb1a68efc19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29400
07138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2940007138
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.790910154
Short name T674
Test name
Test status
Simulation time 8439063795 ps
CPU time 12.89 seconds
Started May 16 03:19:15 PM PDT 24
Finished May 16 03:19:33 PM PDT 24
Peak memory 204844 kb
Host smart-9a8fdbcd-f515-4648-868f-14f9063690d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79091
0154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.790910154
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3121685487
Short name T1572
Test name
Test status
Simulation time 8403457102 ps
CPU time 10.58 seconds
Started May 16 03:19:15 PM PDT 24
Finished May 16 03:19:31 PM PDT 24
Peak memory 204836 kb
Host smart-48ddd6b0-f6f3-455f-bdf3-827a26b45104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31216
85487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3121685487
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2540225559
Short name T557
Test name
Test status
Simulation time 11500399407 ps
CPU time 14.79 seconds
Started May 16 03:19:14 PM PDT 24
Finished May 16 03:19:34 PM PDT 24
Peak memory 204856 kb
Host smart-a2bbe671-0709-43f6-a1e1-c4c04a3da469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25402
25559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2540225559
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.4224196983
Short name T700
Test name
Test status
Simulation time 8421276768 ps
CPU time 11.61 seconds
Started May 16 03:19:13 PM PDT 24
Finished May 16 03:19:30 PM PDT 24
Peak memory 204860 kb
Host smart-81ea2364-b9e4-4e24-8116-8d7ee9ab9811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42241
96983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.4224196983
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3848394245
Short name T1688
Test name
Test status
Simulation time 8379540813 ps
CPU time 11.55 seconds
Started May 16 03:19:15 PM PDT 24
Finished May 16 03:19:32 PM PDT 24
Peak memory 204856 kb
Host smart-54da4866-7ef0-4f7e-8495-06dd34200f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38483
94245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3848394245
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.986931671
Short name T1704
Test name
Test status
Simulation time 8395756353 ps
CPU time 11.86 seconds
Started May 16 03:19:15 PM PDT 24
Finished May 16 03:19:32 PM PDT 24
Peak memory 204724 kb
Host smart-215f4fa8-80c9-4c75-8fa2-156eb2fb1399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98693
1671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.986931671
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.4097451527
Short name T1080
Test name
Test status
Simulation time 8445108016 ps
CPU time 11.89 seconds
Started May 16 03:19:15 PM PDT 24
Finished May 16 03:19:32 PM PDT 24
Peak memory 204896 kb
Host smart-6b082f11-2d3d-410c-93a4-e9c53e9c530a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40974
51527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.4097451527
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2323400370
Short name T789
Test name
Test status
Simulation time 8427563654 ps
CPU time 11.37 seconds
Started May 16 03:19:14 PM PDT 24
Finished May 16 03:19:30 PM PDT 24
Peak memory 204860 kb
Host smart-a4c7f691-0ba0-4857-b4d7-0a92312471d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23234
00370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2323400370
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3914700580
Short name T1758
Test name
Test status
Simulation time 8408081411 ps
CPU time 11.91 seconds
Started May 16 03:19:14 PM PDT 24
Finished May 16 03:19:31 PM PDT 24
Peak memory 204812 kb
Host smart-9f134726-566e-40e6-81c4-bd5917b16c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39147
00580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3914700580
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.169442212
Short name T990
Test name
Test status
Simulation time 8441891374 ps
CPU time 10.96 seconds
Started May 16 03:19:16 PM PDT 24
Finished May 16 03:19:31 PM PDT 24
Peak memory 204864 kb
Host smart-b59844c1-eea7-4b1f-80fe-b8f5792681ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16944
2212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.169442212
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.865372917
Short name T1101
Test name
Test status
Simulation time 8400568580 ps
CPU time 14.47 seconds
Started May 16 03:19:16 PM PDT 24
Finished May 16 03:19:35 PM PDT 24
Peak memory 204320 kb
Host smart-35a35ce9-0733-4ad6-a83d-0172cb7288f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86537
2917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.865372917
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.326056622
Short name T542
Test name
Test status
Simulation time 8373784611 ps
CPU time 11.8 seconds
Started May 16 03:19:15 PM PDT 24
Finished May 16 03:19:32 PM PDT 24
Peak memory 204772 kb
Host smart-c7419b8f-eb77-478b-a5d9-8d5e9a5f2e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32605
6622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.326056622
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.832446403
Short name T696
Test name
Test status
Simulation time 8371705911 ps
CPU time 10.87 seconds
Started May 16 03:19:15 PM PDT 24
Finished May 16 03:19:31 PM PDT 24
Peak memory 204768 kb
Host smart-ed609a94-20e5-416c-a5fe-ebf7b943204e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83244
6403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.832446403
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3128328218
Short name T1562
Test name
Test status
Simulation time 31027627892 ps
CPU time 63.34 seconds
Started May 16 03:19:16 PM PDT 24
Finished May 16 03:20:24 PM PDT 24
Peak memory 204268 kb
Host smart-b8a325c9-6022-4d37-a94d-9cb7ecf644d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31283
28218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3128328218
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1342313549
Short name T1532
Test name
Test status
Simulation time 8385345270 ps
CPU time 11.58 seconds
Started May 16 03:19:14 PM PDT 24
Finished May 16 03:19:31 PM PDT 24
Peak memory 204844 kb
Host smart-1d224e6e-97c2-4454-90bb-9fc033b76707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13423
13549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1342313549
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2396414542
Short name T512
Test name
Test status
Simulation time 8390138096 ps
CPU time 11.04 seconds
Started May 16 03:19:13 PM PDT 24
Finished May 16 03:19:30 PM PDT 24
Peak memory 204776 kb
Host smart-099568ac-64b2-40db-a247-1360b2131c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23964
14542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2396414542
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.3061595003
Short name T824
Test name
Test status
Simulation time 8396201137 ps
CPU time 11.07 seconds
Started May 16 03:19:18 PM PDT 24
Finished May 16 03:19:33 PM PDT 24
Peak memory 204848 kb
Host smart-41b7a6dd-e7f9-4904-970a-8f560750b3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30615
95003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.3061595003
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3450418266
Short name T775
Test name
Test status
Simulation time 8368966281 ps
CPU time 12.89 seconds
Started May 16 03:19:16 PM PDT 24
Finished May 16 03:19:33 PM PDT 24
Peak memory 204848 kb
Host smart-353488f0-4373-499a-bb28-9db2b934a82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34504
18266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3450418266
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1965483255
Short name T86
Test name
Test status
Simulation time 287716674 ps
CPU time 1.08 seconds
Started May 16 03:19:25 PM PDT 24
Finished May 16 03:19:31 PM PDT 24
Peak memory 220476 kb
Host smart-d93bdda1-3d85-408a-b3dc-a21cbb786b9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1965483255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1965483255
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.380388749
Short name T184
Test name
Test status
Simulation time 8385268399 ps
CPU time 10.88 seconds
Started May 16 03:19:17 PM PDT 24
Finished May 16 03:19:32 PM PDT 24
Peak memory 204824 kb
Host smart-021ec93b-6548-4a57-9d50-2364bfc5794b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38038
8749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.380388749
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.628457107
Short name T1509
Test name
Test status
Simulation time 8374506172 ps
CPU time 11.83 seconds
Started May 16 03:19:15 PM PDT 24
Finished May 16 03:19:32 PM PDT 24
Peak memory 204848 kb
Host smart-1d6d0300-f4f3-41b1-ad8e-cab18e3ea776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62845
7107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.628457107
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3533236313
Short name T1523
Test name
Test status
Simulation time 8455182643 ps
CPU time 11.52 seconds
Started May 16 03:19:10 PM PDT 24
Finished May 16 03:19:27 PM PDT 24
Peak memory 204804 kb
Host smart-9aee0065-95aa-4572-b919-8f0b0217d6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35332
36313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3533236313
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2892481488
Short name T585
Test name
Test status
Simulation time 8408768810 ps
CPU time 11.67 seconds
Started May 16 03:19:15 PM PDT 24
Finished May 16 03:19:32 PM PDT 24
Peak memory 204880 kb
Host smart-75f3ff67-f7a9-4323-9cbe-ad0151d72d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28924
81488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2892481488
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.551823286
Short name T589
Test name
Test status
Simulation time 8389434628 ps
CPU time 11.46 seconds
Started May 16 03:19:16 PM PDT 24
Finished May 16 03:19:32 PM PDT 24
Peak memory 204880 kb
Host smart-688999ef-2216-44b2-8735-a05e469d827f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55182
3286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.551823286
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.4228356429
Short name T349
Test name
Test status
Simulation time 8486319055 ps
CPU time 11.73 seconds
Started May 16 03:23:09 PM PDT 24
Finished May 16 03:23:27 PM PDT 24
Peak memory 204904 kb
Host smart-62747977-95d7-451a-aa86-6c113ddd2c73
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4228356429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.4228356429
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.2316221781
Short name T1063
Test name
Test status
Simulation time 8380137673 ps
CPU time 13.64 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:31 PM PDT 24
Peak memory 204912 kb
Host smart-427c95de-981e-4fa9-9b1c-fa6d499438b5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2316221781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.2316221781
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.3578899349
Short name T733
Test name
Test status
Simulation time 8456192872 ps
CPU time 11.34 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:29 PM PDT 24
Peak memory 204812 kb
Host smart-23bf3a5d-3e75-479a-8ea4-5bde42c87ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35788
99349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.3578899349
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.4075858577
Short name T1186
Test name
Test status
Simulation time 8399814942 ps
CPU time 12.32 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204880 kb
Host smart-e58720b7-0514-437b-a543-aaa14e64bbc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40758
58577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.4075858577
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.3483820411
Short name T1435
Test name
Test status
Simulation time 8371486864 ps
CPU time 12.23 seconds
Started May 16 03:23:08 PM PDT 24
Finished May 16 03:23:26 PM PDT 24
Peak memory 204764 kb
Host smart-8d8eb081-5c97-4fb5-84d8-5bcbc3b5368f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34838
20411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.3483820411
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.98341976
Short name T1737
Test name
Test status
Simulation time 9501573854 ps
CPU time 14.35 seconds
Started May 16 03:23:13 PM PDT 24
Finished May 16 03:23:33 PM PDT 24
Peak memory 204868 kb
Host smart-ab8dfb2c-4d3e-40b6-9760-86b1e9b81131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98341
976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.98341976
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2396396839
Short name T1106
Test name
Test status
Simulation time 8360480089 ps
CPU time 11.24 seconds
Started May 16 03:23:12 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204764 kb
Host smart-45c7e82b-fb09-45cd-aaeb-091e8b129f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23963
96839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2396396839
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.4104742810
Short name T720
Test name
Test status
Simulation time 8379857108 ps
CPU time 11.34 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:29 PM PDT 24
Peak memory 204800 kb
Host smart-15db51cf-f5e1-473a-8a79-2b520e56685d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41047
42810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.4104742810
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3486581546
Short name T1136
Test name
Test status
Simulation time 9031626010 ps
CPU time 13.45 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:31 PM PDT 24
Peak memory 204952 kb
Host smart-58ec4c36-302d-4905-8555-36b320b059bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34865
81546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3486581546
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2097192457
Short name T708
Test name
Test status
Simulation time 8464010023 ps
CPU time 14.04 seconds
Started May 16 03:23:13 PM PDT 24
Finished May 16 03:23:33 PM PDT 24
Peak memory 204872 kb
Host smart-236f6df2-cdff-4133-91d2-581624fc1ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20971
92457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2097192457
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.965674942
Short name T53
Test name
Test status
Simulation time 8450095960 ps
CPU time 11.68 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:29 PM PDT 24
Peak memory 204912 kb
Host smart-0e652cfa-272d-4a96-9624-aa883b403913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96567
4942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.965674942
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.4092870017
Short name T829
Test name
Test status
Simulation time 8368618059 ps
CPU time 10.84 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:29 PM PDT 24
Peak memory 204808 kb
Host smart-3b6f6044-bbdb-4a27-8af4-b21e2bfb1790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40928
70017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.4092870017
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1779959471
Short name T1657
Test name
Test status
Simulation time 8453483081 ps
CPU time 11.45 seconds
Started May 16 03:23:13 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204804 kb
Host smart-1f0f1f4d-56cd-4331-8c5b-b85b49841c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17799
59471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1779959471
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.3746626993
Short name T635
Test name
Test status
Simulation time 8381694456 ps
CPU time 11.16 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:28 PM PDT 24
Peak memory 204864 kb
Host smart-87a4d916-785b-40a3-a02a-3b4b283cfd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37466
26993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.3746626993
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.512574918
Short name T1306
Test name
Test status
Simulation time 11540430205 ps
CPU time 13.09 seconds
Started May 16 03:23:09 PM PDT 24
Finished May 16 03:23:28 PM PDT 24
Peak memory 204836 kb
Host smart-9b850b59-3296-4a33-b61e-5728aebb54e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51257
4918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.512574918
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3959843283
Short name T497
Test name
Test status
Simulation time 8424833392 ps
CPU time 11.42 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:28 PM PDT 24
Peak memory 204848 kb
Host smart-7b9056ef-6c38-47c4-a75b-1e699bacac70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39598
43283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3959843283
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.400459606
Short name T955
Test name
Test status
Simulation time 8453010347 ps
CPU time 13.25 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:29 PM PDT 24
Peak memory 204804 kb
Host smart-bf8e9525-d638-43ca-83f8-bddb07ef4cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40045
9606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.400459606
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1311505739
Short name T1233
Test name
Test status
Simulation time 8472346539 ps
CPU time 11.8 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:28 PM PDT 24
Peak memory 204836 kb
Host smart-5d59109e-4750-43ff-b24b-3d3cf899fd33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13115
05739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1311505739
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.2608488401
Short name T107
Test name
Test status
Simulation time 8414042565 ps
CPU time 12.13 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204864 kb
Host smart-405a07a3-72ce-4ea6-849b-d2822e3544ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26084
88401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.2608488401
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.372700870
Short name T1433
Test name
Test status
Simulation time 8395485099 ps
CPU time 14.28 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204928 kb
Host smart-de9a08c2-c921-40ba-8c97-6f5e77ce5d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37270
0870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.372700870
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.267776480
Short name T1651
Test name
Test status
Simulation time 8408281043 ps
CPU time 11.92 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:29 PM PDT 24
Peak memory 204868 kb
Host smart-264cc468-e478-4a34-b0b2-1aa5109e679c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26777
6480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.267776480
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.1771175620
Short name T407
Test name
Test status
Simulation time 8409599546 ps
CPU time 11.05 seconds
Started May 16 03:23:13 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204824 kb
Host smart-d7d6d522-3af8-42cd-b64b-de3c4fedde7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17711
75620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.1771175620
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2490919753
Short name T713
Test name
Test status
Simulation time 8369382254 ps
CPU time 11.65 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:27 PM PDT 24
Peak memory 204816 kb
Host smart-2a987861-317e-4459-b5f6-4267e40876e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24909
19753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2490919753
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2268423997
Short name T1632
Test name
Test status
Simulation time 23292961248 ps
CPU time 46.3 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:24:04 PM PDT 24
Peak memory 204832 kb
Host smart-9b472025-0694-46d1-af5b-c716520c2618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22684
23997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2268423997
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.816473475
Short name T1213
Test name
Test status
Simulation time 8396234364 ps
CPU time 13.38 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204876 kb
Host smart-f360b007-5f59-46b9-af4d-bb9232c9022a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81647
3475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.816473475
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3373061266
Short name T345
Test name
Test status
Simulation time 8475181440 ps
CPU time 11.46 seconds
Started May 16 03:23:09 PM PDT 24
Finished May 16 03:23:27 PM PDT 24
Peak memory 204872 kb
Host smart-9adb84e1-a2d4-4bc2-af61-aff6dee64ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33730
61266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3373061266
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.998795907
Short name T1645
Test name
Test status
Simulation time 8402791591 ps
CPU time 10.96 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:29 PM PDT 24
Peak memory 204812 kb
Host smart-970c92ba-e0cb-435f-b6a5-574e41d25e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99879
5907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.998795907
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.4123834786
Short name T487
Test name
Test status
Simulation time 8365206702 ps
CPU time 11.85 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:28 PM PDT 24
Peak memory 204800 kb
Host smart-9e1be54f-a320-493b-988c-ee307204c371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41238
34786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.4123834786
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3244019506
Short name T181
Test name
Test status
Simulation time 8388932402 ps
CPU time 11.27 seconds
Started May 16 03:23:09 PM PDT 24
Finished May 16 03:23:27 PM PDT 24
Peak memory 204784 kb
Host smart-4ee4f96e-32f6-4649-af57-fe0aff515cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32440
19506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3244019506
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.294174231
Short name T853
Test name
Test status
Simulation time 8409350450 ps
CPU time 13.79 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204952 kb
Host smart-ed844048-5eaa-4034-8348-3b531c5f5430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29417
4231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.294174231
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2581755677
Short name T1280
Test name
Test status
Simulation time 8449438825 ps
CPU time 10.97 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:28 PM PDT 24
Peak memory 204864 kb
Host smart-8f805af2-3bfd-444e-ac12-8fe85b2b9341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25817
55677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2581755677
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1152796151
Short name T1453
Test name
Test status
Simulation time 8390680029 ps
CPU time 11.16 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:27 PM PDT 24
Peak memory 204888 kb
Host smart-e2c2c6b1-4e97-4e8f-bf7c-3b64d7cb5cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11527
96151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1152796151
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.531877086
Short name T821
Test name
Test status
Simulation time 8381996988 ps
CPU time 13.02 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:31 PM PDT 24
Peak memory 204832 kb
Host smart-48611a33-4381-4f41-bfb7-a13440b5da9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53187
7086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.531877086
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.4092360193
Short name T977
Test name
Test status
Simulation time 8467559794 ps
CPU time 11.59 seconds
Started May 16 03:23:23 PM PDT 24
Finished May 16 03:23:44 PM PDT 24
Peak memory 204884 kb
Host smart-0b061179-5dc3-416a-9589-87f4d9b9a998
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4092360193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.4092360193
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.4047164319
Short name T982
Test name
Test status
Simulation time 8379488548 ps
CPU time 10.87 seconds
Started May 16 03:23:18 PM PDT 24
Finished May 16 03:23:35 PM PDT 24
Peak memory 204836 kb
Host smart-71d397e8-1fac-4f5e-ad38-e344a0a9b856
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4047164319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.4047164319
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.3884216932
Short name T835
Test name
Test status
Simulation time 8472996764 ps
CPU time 15.11 seconds
Started May 16 03:23:26 PM PDT 24
Finished May 16 03:23:50 PM PDT 24
Peak memory 204876 kb
Host smart-51c3283d-8274-4992-aeac-464456a5a900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38842
16932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.3884216932
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2050916060
Short name T1603
Test name
Test status
Simulation time 8378206848 ps
CPU time 11.23 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:29 PM PDT 24
Peak memory 204856 kb
Host smart-8c829618-c52a-4ef6-a9ec-eefb5985ecfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20509
16060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2050916060
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2812805840
Short name T1069
Test name
Test status
Simulation time 8479591112 ps
CPU time 13.87 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204828 kb
Host smart-638f47ad-7fab-44a4-a54f-42b9f6b9a4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28128
05840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2812805840
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.4140290450
Short name T1745
Test name
Test status
Simulation time 8388125422 ps
CPU time 11.26 seconds
Started May 16 03:23:19 PM PDT 24
Finished May 16 03:23:37 PM PDT 24
Peak memory 204844 kb
Host smart-bb8a97c7-ea92-4294-a240-fc5e143741f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41402
90450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.4140290450
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.4113872684
Short name T467
Test name
Test status
Simulation time 8390180560 ps
CPU time 11.74 seconds
Started May 16 03:23:16 PM PDT 24
Finished May 16 03:23:33 PM PDT 24
Peak memory 204756 kb
Host smart-194b81fd-e570-4d85-aadc-52013f5e4f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41138
72684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.4113872684
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.842179861
Short name T1675
Test name
Test status
Simulation time 9043724079 ps
CPU time 12.38 seconds
Started May 16 03:23:11 PM PDT 24
Finished May 16 03:23:30 PM PDT 24
Peak memory 204872 kb
Host smart-1ff8e158-8f37-4f7c-a753-3a52046c551d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84217
9861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.842179861
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.4125489749
Short name T1000
Test name
Test status
Simulation time 8514398522 ps
CPU time 13.35 seconds
Started May 16 03:23:16 PM PDT 24
Finished May 16 03:23:36 PM PDT 24
Peak memory 204904 kb
Host smart-bfe1c7cd-d07a-4ed2-b73a-2b1f0383f619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41254
89749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.4125489749
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.33110192
Short name T588
Test name
Test status
Simulation time 8439090584 ps
CPU time 10.5 seconds
Started May 16 03:23:17 PM PDT 24
Finished May 16 03:23:34 PM PDT 24
Peak memory 204804 kb
Host smart-14ce10f5-f70a-4ec9-abcf-0124092ca342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33110
192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.33110192
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2669654265
Short name T1706
Test name
Test status
Simulation time 8369170786 ps
CPU time 11.06 seconds
Started May 16 03:23:23 PM PDT 24
Finished May 16 03:23:43 PM PDT 24
Peak memory 204840 kb
Host smart-bb6e5981-c123-4e58-9fc5-6cffeec65637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26696
54265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2669654265
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.674299014
Short name T1678
Test name
Test status
Simulation time 8429476843 ps
CPU time 12.47 seconds
Started May 16 03:23:18 PM PDT 24
Finished May 16 03:23:36 PM PDT 24
Peak memory 204908 kb
Host smart-fdd1ccff-ec68-473b-b861-30a53622040f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67429
9014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.674299014
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.940298168
Short name T1215
Test name
Test status
Simulation time 8448207634 ps
CPU time 11.96 seconds
Started May 16 03:23:19 PM PDT 24
Finished May 16 03:23:38 PM PDT 24
Peak memory 204832 kb
Host smart-efa9bc77-4b04-446b-b94c-7b86681df0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94029
8168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.940298168
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.512783164
Short name T424
Test name
Test status
Simulation time 11548478368 ps
CPU time 15.12 seconds
Started May 16 03:23:20 PM PDT 24
Finished May 16 03:23:43 PM PDT 24
Peak memory 204828 kb
Host smart-3c75ca61-59a5-4f27-ba3b-84677bc3a871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51278
3164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.512783164
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3541423412
Short name T640
Test name
Test status
Simulation time 8417587683 ps
CPU time 13.92 seconds
Started May 16 03:23:15 PM PDT 24
Finished May 16 03:23:35 PM PDT 24
Peak memory 204772 kb
Host smart-05b6ea34-5dc2-49c5-b4b6-56c9531c55c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35414
23412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3541423412
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2323967776
Short name T1082
Test name
Test status
Simulation time 8366338554 ps
CPU time 13.25 seconds
Started May 16 03:23:18 PM PDT 24
Finished May 16 03:23:38 PM PDT 24
Peak memory 204844 kb
Host smart-ca3fc2a5-e3d7-44e1-91e0-62ef7ad78df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23239
67776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2323967776
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2461362343
Short name T120
Test name
Test status
Simulation time 8503732919 ps
CPU time 12.66 seconds
Started May 16 03:23:20 PM PDT 24
Finished May 16 03:23:40 PM PDT 24
Peak memory 204816 kb
Host smart-8c434996-4855-4f33-9b0a-bde14923eab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24613
62343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2461362343
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.4263811271
Short name T1206
Test name
Test status
Simulation time 8420360874 ps
CPU time 10.56 seconds
Started May 16 03:23:19 PM PDT 24
Finished May 16 03:23:36 PM PDT 24
Peak memory 204820 kb
Host smart-69fee6ba-6f87-4d36-8190-53dec84bbb19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42638
11271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.4263811271
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.282057891
Short name T1065
Test name
Test status
Simulation time 8409434016 ps
CPU time 11.61 seconds
Started May 16 03:23:17 PM PDT 24
Finished May 16 03:23:35 PM PDT 24
Peak memory 204868 kb
Host smart-cecbfc34-20e4-4b79-9543-5e3ec3a48443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28205
7891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.282057891
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1467549195
Short name T1244
Test name
Test status
Simulation time 8394981155 ps
CPU time 12.08 seconds
Started May 16 03:23:18 PM PDT 24
Finished May 16 03:23:36 PM PDT 24
Peak memory 204828 kb
Host smart-4383ae48-6b57-4024-9221-06f7c371de6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14675
49195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1467549195
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.2220012864
Short name T1278
Test name
Test status
Simulation time 8400367343 ps
CPU time 13.36 seconds
Started May 16 03:23:18 PM PDT 24
Finished May 16 03:23:38 PM PDT 24
Peak memory 204840 kb
Host smart-794eee6c-4ec4-47b8-b14f-ec93babc99ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22200
12864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.2220012864
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.4258299183
Short name T538
Test name
Test status
Simulation time 8388219746 ps
CPU time 11.2 seconds
Started May 16 03:23:21 PM PDT 24
Finished May 16 03:23:40 PM PDT 24
Peak memory 204820 kb
Host smart-10267226-c3a6-4210-bcbb-be02731cb715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42582
99183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.4258299183
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.760965237
Short name T864
Test name
Test status
Simulation time 8362408599 ps
CPU time 11.57 seconds
Started May 16 03:23:21 PM PDT 24
Finished May 16 03:23:41 PM PDT 24
Peak memory 204844 kb
Host smart-87094af8-9cc8-48e7-9e6f-a82f85b63742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76096
5237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.760965237
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1699890176
Short name T1346
Test name
Test status
Simulation time 30948618939 ps
CPU time 59.28 seconds
Started May 16 03:23:20 PM PDT 24
Finished May 16 03:24:27 PM PDT 24
Peak memory 204824 kb
Host smart-0165d20f-dede-4e2c-bca9-9951d9379da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16998
90176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1699890176
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.4050513953
Short name T1498
Test name
Test status
Simulation time 8386091420 ps
CPU time 11.28 seconds
Started May 16 03:23:23 PM PDT 24
Finished May 16 03:23:43 PM PDT 24
Peak memory 204868 kb
Host smart-ae9eaf01-f356-41f4-a8fd-7664506611d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40505
13953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.4050513953
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2620361205
Short name T967
Test name
Test status
Simulation time 8381542081 ps
CPU time 12.8 seconds
Started May 16 03:23:26 PM PDT 24
Finished May 16 03:23:47 PM PDT 24
Peak memory 204868 kb
Host smart-b6eb654f-94f0-43f8-b450-c6da899362df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26203
61205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2620361205
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.3771157799
Short name T1365
Test name
Test status
Simulation time 8374010762 ps
CPU time 11.58 seconds
Started May 16 03:23:19 PM PDT 24
Finished May 16 03:23:37 PM PDT 24
Peak memory 204832 kb
Host smart-064c6016-0c66-4abf-8fcf-76e45702cd64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37711
57799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.3771157799
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.169485858
Short name T94
Test name
Test status
Simulation time 8368896377 ps
CPU time 11.5 seconds
Started May 16 03:23:18 PM PDT 24
Finished May 16 03:23:35 PM PDT 24
Peak memory 204844 kb
Host smart-06d0ec2e-3fff-4116-876d-980af032b8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16948
5858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.169485858
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.4174570067
Short name T604
Test name
Test status
Simulation time 8382854488 ps
CPU time 12.17 seconds
Started May 16 03:23:20 PM PDT 24
Finished May 16 03:23:40 PM PDT 24
Peak memory 204760 kb
Host smart-dbf8e5b0-0114-4d14-a3b4-a0f738289a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41745
70067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.4174570067
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4039698438
Short name T756
Test name
Test status
Simulation time 8360265972 ps
CPU time 10.89 seconds
Started May 16 03:23:21 PM PDT 24
Finished May 16 03:23:41 PM PDT 24
Peak memory 204792 kb
Host smart-94f3ea68-851c-4eb6-acdd-7caee16e4bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
98438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4039698438
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.778735702
Short name T1366
Test name
Test status
Simulation time 8415977188 ps
CPU time 10.72 seconds
Started May 16 03:23:10 PM PDT 24
Finished May 16 03:23:27 PM PDT 24
Peak memory 204832 kb
Host smart-21e05aa4-5b8c-437d-bbc4-75ad9fb81809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77873
5702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.778735702
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3644680916
Short name T965
Test name
Test status
Simulation time 8429994755 ps
CPU time 11.11 seconds
Started May 16 03:23:19 PM PDT 24
Finished May 16 03:23:37 PM PDT 24
Peak memory 204812 kb
Host smart-06980a30-e2f4-423e-a9ca-3cb158f6f7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36446
80916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3644680916
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2795881138
Short name T1517
Test name
Test status
Simulation time 8422396010 ps
CPU time 11.48 seconds
Started May 16 03:23:19 PM PDT 24
Finished May 16 03:23:37 PM PDT 24
Peak memory 204876 kb
Host smart-8ebc800a-5602-4d40-a1c6-af9709af18da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27958
81138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2795881138
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.2461592972
Short name T1002
Test name
Test status
Simulation time 8466213829 ps
CPU time 10.67 seconds
Started May 16 03:23:39 PM PDT 24
Finished May 16 03:23:56 PM PDT 24
Peak memory 204364 kb
Host smart-e292c25c-a41e-4064-a33d-e6a0312275c4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2461592972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.2461592972
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.753906422
Short name T1118
Test name
Test status
Simulation time 8395086745 ps
CPU time 10.64 seconds
Started May 16 03:23:38 PM PDT 24
Finished May 16 03:23:54 PM PDT 24
Peak memory 204888 kb
Host smart-0fbc2cf2-af2d-49a3-bd9b-35fedddd7a13
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=753906422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.753906422
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.1484625503
Short name T1360
Test name
Test status
Simulation time 8396379602 ps
CPU time 11.33 seconds
Started May 16 03:23:39 PM PDT 24
Finished May 16 03:23:56 PM PDT 24
Peak memory 204916 kb
Host smart-b7ee05e5-0e9f-46b2-a702-61c9c3890601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14846
25503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.1484625503
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2134271431
Short name T1195
Test name
Test status
Simulation time 8383966524 ps
CPU time 10.36 seconds
Started May 16 03:23:26 PM PDT 24
Finished May 16 03:23:45 PM PDT 24
Peak memory 204596 kb
Host smart-f5428c1b-d978-47d3-ab27-2cccff2190ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21342
71431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2134271431
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.756632854
Short name T973
Test name
Test status
Simulation time 8365287533 ps
CPU time 10.91 seconds
Started May 16 03:23:23 PM PDT 24
Finished May 16 03:23:43 PM PDT 24
Peak memory 204832 kb
Host smart-676bc500-f6d1-4d4d-9e30-c1de85e48f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75663
2854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.756632854
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2754058258
Short name T714
Test name
Test status
Simulation time 8399603768 ps
CPU time 12.2 seconds
Started May 16 03:23:17 PM PDT 24
Finished May 16 03:23:35 PM PDT 24
Peak memory 204900 kb
Host smart-c654c3bf-4e86-4b07-9080-355dca94a181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27540
58258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2754058258
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.4046791507
Short name T707
Test name
Test status
Simulation time 9073520440 ps
CPU time 12.47 seconds
Started May 16 03:23:19 PM PDT 24
Finished May 16 03:23:38 PM PDT 24
Peak memory 204816 kb
Host smart-0e9a5aae-7acb-48c4-9982-7629c4132d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40467
91507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.4046791507
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2223965894
Short name T1751
Test name
Test status
Simulation time 8414401245 ps
CPU time 12.98 seconds
Started May 16 03:23:20 PM PDT 24
Finished May 16 03:23:41 PM PDT 24
Peak memory 204832 kb
Host smart-b8a91dfb-52d6-4a9b-ad90-34cb30234cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22239
65894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2223965894
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1937349762
Short name T879
Test name
Test status
Simulation time 8407503938 ps
CPU time 11.58 seconds
Started May 16 03:23:37 PM PDT 24
Finished May 16 03:23:53 PM PDT 24
Peak memory 204860 kb
Host smart-39435355-073b-4fea-b308-17f5c10b5cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19373
49762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1937349762
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2831160689
Short name T675
Test name
Test status
Simulation time 8364189899 ps
CPU time 11.4 seconds
Started May 16 03:23:28 PM PDT 24
Finished May 16 03:23:47 PM PDT 24
Peak memory 204848 kb
Host smart-10401c9b-5c60-40c4-b3ea-1541315837ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28311
60689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2831160689
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3986918127
Short name T1617
Test name
Test status
Simulation time 8383088570 ps
CPU time 11.36 seconds
Started May 16 03:23:18 PM PDT 24
Finished May 16 03:23:36 PM PDT 24
Peak memory 204700 kb
Host smart-91a9fcb4-a75a-4147-964f-9ef3dadf49a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39869
18127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3986918127
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2982425827
Short name T224
Test name
Test status
Simulation time 8420680248 ps
CPU time 11 seconds
Started May 16 03:23:18 PM PDT 24
Finished May 16 03:23:35 PM PDT 24
Peak memory 204756 kb
Host smart-ec2a1767-cfef-4d89-b436-aab97d0a66f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29824
25827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2982425827
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.4273847287
Short name T900
Test name
Test status
Simulation time 11528806370 ps
CPU time 18.18 seconds
Started May 16 03:23:19 PM PDT 24
Finished May 16 03:23:45 PM PDT 24
Peak memory 204796 kb
Host smart-45e8b8c0-d275-4b16-b068-088e4a6c4335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42738
47287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.4273847287
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2922858098
Short name T308
Test name
Test status
Simulation time 8422632683 ps
CPU time 10.57 seconds
Started May 16 03:23:23 PM PDT 24
Finished May 16 03:23:42 PM PDT 24
Peak memory 204800 kb
Host smart-bfdfc40d-9880-45c4-a92c-a6297be1f03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29228
58098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2922858098
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3938943831
Short name T453
Test name
Test status
Simulation time 8374024936 ps
CPU time 14.05 seconds
Started May 16 03:23:27 PM PDT 24
Finished May 16 03:23:49 PM PDT 24
Peak memory 204868 kb
Host smart-5de8db0c-d978-438e-a805-31c3f8758624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39389
43831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3938943831
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2834408691
Short name T134
Test name
Test status
Simulation time 8413953473 ps
CPU time 12.69 seconds
Started May 16 03:23:18 PM PDT 24
Finished May 16 03:23:36 PM PDT 24
Peak memory 204760 kb
Host smart-bc49cc0a-fa10-4b94-8e54-39fe5ea1c49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28344
08691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2834408691
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3501698221
Short name T1284
Test name
Test status
Simulation time 8409696361 ps
CPU time 11.43 seconds
Started May 16 03:23:23 PM PDT 24
Finished May 16 03:23:44 PM PDT 24
Peak memory 204868 kb
Host smart-23f72479-5eb8-48d9-aedc-5383ef7797dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35016
98221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3501698221
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1843025760
Short name T1302
Test name
Test status
Simulation time 8387306897 ps
CPU time 13.2 seconds
Started May 16 03:23:20 PM PDT 24
Finished May 16 03:23:41 PM PDT 24
Peak memory 204780 kb
Host smart-7d355eb8-bcca-4a2c-b84c-a89f60b0888c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18430
25760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1843025760
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1221046720
Short name T702
Test name
Test status
Simulation time 8413140447 ps
CPU time 12.53 seconds
Started May 16 03:23:26 PM PDT 24
Finished May 16 03:23:47 PM PDT 24
Peak memory 204448 kb
Host smart-df6090f3-941b-4c1b-8f2e-f3990dda3404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12210
46720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1221046720
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3505446613
Short name T168
Test name
Test status
Simulation time 8423934730 ps
CPU time 12.69 seconds
Started May 16 03:23:27 PM PDT 24
Finished May 16 03:23:48 PM PDT 24
Peak memory 204800 kb
Host smart-d9df6e5b-ad45-4869-9dd4-e20309a6bbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35054
46613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3505446613
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.605430651
Short name T1155
Test name
Test status
Simulation time 8406385237 ps
CPU time 12.5 seconds
Started May 16 03:23:28 PM PDT 24
Finished May 16 03:23:48 PM PDT 24
Peak memory 204864 kb
Host smart-93afd128-59a6-45b2-b599-fb9ef88c1e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60543
0651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.605430651
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3310120110
Short name T95
Test name
Test status
Simulation time 8366772178 ps
CPU time 10.81 seconds
Started May 16 03:23:29 PM PDT 24
Finished May 16 03:23:47 PM PDT 24
Peak memory 204808 kb
Host smart-fe51a7d3-d172-47ae-9f84-11d92da9479b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33101
20110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3310120110
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.894510552
Short name T948
Test name
Test status
Simulation time 8373815590 ps
CPU time 12.88 seconds
Started May 16 03:23:28 PM PDT 24
Finished May 16 03:23:49 PM PDT 24
Peak memory 204820 kb
Host smart-03f5e514-a940-4e11-b213-c1cb694b3f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89451
0552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.894510552
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1711991081
Short name T1715
Test name
Test status
Simulation time 18926434808 ps
CPU time 32.82 seconds
Started May 16 03:23:21 PM PDT 24
Finished May 16 03:24:02 PM PDT 24
Peak memory 204788 kb
Host smart-a6208dd6-6f33-4a36-b409-825526e29faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17119
91081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1711991081
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3876224800
Short name T935
Test name
Test status
Simulation time 8413576481 ps
CPU time 11.12 seconds
Started May 16 03:23:20 PM PDT 24
Finished May 16 03:23:38 PM PDT 24
Peak memory 204872 kb
Host smart-597332ac-dccd-40d2-9a0d-f6b564797795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38762
24800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3876224800
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1344266734
Short name T1541
Test name
Test status
Simulation time 8462770803 ps
CPU time 12.3 seconds
Started May 16 03:23:29 PM PDT 24
Finished May 16 03:23:48 PM PDT 24
Peak memory 204880 kb
Host smart-060f41ea-a750-4138-9e85-13c63e0980d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13442
66734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1344266734
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.1794929898
Short name T1503
Test name
Test status
Simulation time 8409302778 ps
CPU time 10.77 seconds
Started May 16 03:23:31 PM PDT 24
Finished May 16 03:23:47 PM PDT 24
Peak memory 204808 kb
Host smart-94188a43-4bf7-4a77-835f-1898a303098a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17949
29898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.1794929898
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3899899057
Short name T472
Test name
Test status
Simulation time 8369982015 ps
CPU time 11.02 seconds
Started May 16 03:23:32 PM PDT 24
Finished May 16 03:23:48 PM PDT 24
Peak memory 204872 kb
Host smart-d8fc325d-f527-408a-9df0-c249b2b093a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38998
99057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3899899057
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2459485569
Short name T1591
Test name
Test status
Simulation time 8384210298 ps
CPU time 13.18 seconds
Started May 16 03:23:28 PM PDT 24
Finished May 16 03:23:49 PM PDT 24
Peak memory 204876 kb
Host smart-72b86fb9-f78a-4b3b-b6d6-cfef221cea38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24594
85569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2459485569
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3759446761
Short name T792
Test name
Test status
Simulation time 8364682122 ps
CPU time 11.24 seconds
Started May 16 03:23:30 PM PDT 24
Finished May 16 03:23:48 PM PDT 24
Peak memory 204840 kb
Host smart-845bd160-b3c9-4413-8045-0a75bcb5bc0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37594
46761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3759446761
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3275999978
Short name T1249
Test name
Test status
Simulation time 8445864864 ps
CPU time 13.09 seconds
Started May 16 03:23:21 PM PDT 24
Finished May 16 03:23:42 PM PDT 24
Peak memory 204904 kb
Host smart-677d6b77-aad4-47b3-a35a-66dbcbe31ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32759
99978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3275999978
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1198047538
Short name T1262
Test name
Test status
Simulation time 8412768214 ps
CPU time 11.69 seconds
Started May 16 03:23:28 PM PDT 24
Finished May 16 03:23:47 PM PDT 24
Peak memory 204860 kb
Host smart-11becee7-88de-4d72-8032-0b77ca765ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11980
47538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1198047538
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1308811307
Short name T1510
Test name
Test status
Simulation time 8417188423 ps
CPU time 10.68 seconds
Started May 16 03:23:30 PM PDT 24
Finished May 16 03:23:47 PM PDT 24
Peak memory 204840 kb
Host smart-abf8cd07-7446-4e6f-b130-c30cebd42674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13088
11307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1308811307
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.1181524466
Short name T325
Test name
Test status
Simulation time 8472710841 ps
CPU time 12.14 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:04 PM PDT 24
Peak memory 204848 kb
Host smart-91dcad90-285d-4242-8cd3-daf4459a7839
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1181524466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.1181524466
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.3776193927
Short name T1445
Test name
Test status
Simulation time 8413165838 ps
CPU time 13.5 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204872 kb
Host smart-641fef98-3d80-448e-ac05-87d1b9ddfec5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3776193927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.3776193927
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.3265038384
Short name T697
Test name
Test status
Simulation time 8448488670 ps
CPU time 11.32 seconds
Started May 16 03:23:39 PM PDT 24
Finished May 16 03:23:56 PM PDT 24
Peak memory 204856 kb
Host smart-242f4ffc-220a-48ba-bdde-a9c773a074c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32650
38384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.3265038384
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3229963958
Short name T1362
Test name
Test status
Simulation time 8383574439 ps
CPU time 11.22 seconds
Started May 16 03:23:39 PM PDT 24
Finished May 16 03:23:56 PM PDT 24
Peak memory 204944 kb
Host smart-724d9841-1890-4a56-9103-e3d9d9a4cf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32299
63958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3229963958
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3744835457
Short name T888
Test name
Test status
Simulation time 8374843844 ps
CPU time 10.89 seconds
Started May 16 03:23:38 PM PDT 24
Finished May 16 03:23:54 PM PDT 24
Peak memory 204664 kb
Host smart-38062c60-2966-4f2d-9fc7-2ce063032c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37448
35457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3744835457
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1975023406
Short name T1672
Test name
Test status
Simulation time 8453740216 ps
CPU time 14.55 seconds
Started May 16 03:23:40 PM PDT 24
Finished May 16 03:24:03 PM PDT 24
Peak memory 204856 kb
Host smart-3056560b-3b21-4a6b-8d3a-b0ea3a659fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19750
23406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1975023406
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2220003361
Short name T572
Test name
Test status
Simulation time 8374178284 ps
CPU time 10.89 seconds
Started May 16 03:23:39 PM PDT 24
Finished May 16 03:23:56 PM PDT 24
Peak memory 204336 kb
Host smart-2e88b793-b879-4282-a6bb-f7b8a85d31cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22200
03361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2220003361
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2772549167
Short name T1194
Test name
Test status
Simulation time 8387962577 ps
CPU time 14.1 seconds
Started May 16 03:23:40 PM PDT 24
Finished May 16 03:24:01 PM PDT 24
Peak memory 204924 kb
Host smart-7c88f5c5-10e8-4024-92e5-4babaa444c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27725
49167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2772549167
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2595618770
Short name T567
Test name
Test status
Simulation time 8923153220 ps
CPU time 11.38 seconds
Started May 16 03:23:39 PM PDT 24
Finished May 16 03:23:56 PM PDT 24
Peak memory 204900 kb
Host smart-6d4eca7c-a99a-482b-93ad-200488fac41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25956
18770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2595618770
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2470402588
Short name T1001
Test name
Test status
Simulation time 8452274722 ps
CPU time 11.27 seconds
Started May 16 03:23:40 PM PDT 24
Finished May 16 03:23:59 PM PDT 24
Peak memory 204868 kb
Host smart-555ea365-40ed-443d-ad68-c236df8c82f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24704
02588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2470402588
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1923424770
Short name T653
Test name
Test status
Simulation time 8378806067 ps
CPU time 11.55 seconds
Started May 16 03:23:39 PM PDT 24
Finished May 16 03:23:57 PM PDT 24
Peak memory 204948 kb
Host smart-947fd6b3-180a-4804-92fd-66a7dea37c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19234
24770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1923424770
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3536485054
Short name T1716
Test name
Test status
Simulation time 8431447066 ps
CPU time 11.62 seconds
Started May 16 03:23:37 PM PDT 24
Finished May 16 03:23:53 PM PDT 24
Peak memory 204832 kb
Host smart-5c9495c4-52a4-4c17-a4a0-8d08d363f86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35364
85054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3536485054
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2576138180
Short name T543
Test name
Test status
Simulation time 8402899632 ps
CPU time 12.07 seconds
Started May 16 03:23:37 PM PDT 24
Finished May 16 03:23:53 PM PDT 24
Peak memory 204808 kb
Host smart-028bbd3a-8f49-4f8e-b2e4-c7ddc7cc2e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25761
38180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2576138180
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1747376521
Short name T1293
Test name
Test status
Simulation time 11510100677 ps
CPU time 17.13 seconds
Started May 16 03:23:38 PM PDT 24
Finished May 16 03:24:01 PM PDT 24
Peak memory 204864 kb
Host smart-c55f6da7-a58f-4ae0-acea-67c632e8d573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17473
76521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1747376521
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2641950562
Short name T1508
Test name
Test status
Simulation time 8417501581 ps
CPU time 13.34 seconds
Started May 16 03:23:38 PM PDT 24
Finished May 16 03:23:57 PM PDT 24
Peak memory 204824 kb
Host smart-3df3b98d-6985-40e2-9a91-4bf64dec4cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26419
50562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2641950562
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.624502782
Short name T1515
Test name
Test status
Simulation time 8388229760 ps
CPU time 12.89 seconds
Started May 16 03:23:40 PM PDT 24
Finished May 16 03:24:01 PM PDT 24
Peak memory 204800 kb
Host smart-d6193c21-d2c5-42da-be91-8f592372f7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62450
2782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.624502782
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3949760371
Short name T145
Test name
Test status
Simulation time 8431597822 ps
CPU time 11.76 seconds
Started May 16 03:23:40 PM PDT 24
Finished May 16 03:23:58 PM PDT 24
Peak memory 204876 kb
Host smart-aefe80dd-a7ad-43aa-a3c3-440d269eb3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39497
60371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3949760371
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.3651293849
Short name T509
Test name
Test status
Simulation time 8424340108 ps
CPU time 10.56 seconds
Started May 16 03:23:39 PM PDT 24
Finished May 16 03:23:56 PM PDT 24
Peak memory 204872 kb
Host smart-ca845827-f4b4-4798-95a8-b8a3b4944060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36512
93849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.3651293849
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.259644366
Short name T730
Test name
Test status
Simulation time 8414892687 ps
CPU time 11.18 seconds
Started May 16 03:23:42 PM PDT 24
Finished May 16 03:24:02 PM PDT 24
Peak memory 204848 kb
Host smart-4dbdb2de-3806-4ba1-abc1-974738bb96a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25964
4366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.259644366
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3825665290
Short name T517
Test name
Test status
Simulation time 8437935491 ps
CPU time 12.85 seconds
Started May 16 03:23:40 PM PDT 24
Finished May 16 03:24:00 PM PDT 24
Peak memory 204828 kb
Host smart-482137a1-89b4-4021-bc8d-8924959836db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38256
65290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3825665290
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2318679905
Short name T1450
Test name
Test status
Simulation time 8417840440 ps
CPU time 11.59 seconds
Started May 16 03:23:40 PM PDT 24
Finished May 16 03:23:59 PM PDT 24
Peak memory 204888 kb
Host smart-e9c5fd48-3b6b-43af-9603-e0fe2a57b17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23186
79905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2318679905
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.371715148
Short name T341
Test name
Test status
Simulation time 8490417394 ps
CPU time 14.39 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:07 PM PDT 24
Peak memory 204812 kb
Host smart-f3ac012a-2c41-4f77-9a2c-e842a2f4af2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37171
5148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.371715148
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3990263826
Short name T101
Test name
Test status
Simulation time 8379242488 ps
CPU time 11.42 seconds
Started May 16 03:23:40 PM PDT 24
Finished May 16 03:23:59 PM PDT 24
Peak memory 204820 kb
Host smart-aeae734a-38af-4075-aa1a-d1cb0baf5900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39902
63826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3990263826
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.526668586
Short name T1381
Test name
Test status
Simulation time 8366664284 ps
CPU time 11.07 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:03 PM PDT 24
Peak memory 204844 kb
Host smart-8b9de306-7173-48bd-a307-55fa74b8801e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52666
8586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.526668586
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.111360505
Short name T1403
Test name
Test status
Simulation time 27358442283 ps
CPU time 52.75 seconds
Started May 16 03:23:40 PM PDT 24
Finished May 16 03:24:40 PM PDT 24
Peak memory 204820 kb
Host smart-515eb1c3-39e0-4286-8977-4b22cb7377fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11136
0505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.111360505
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1103314526
Short name T1179
Test name
Test status
Simulation time 8416143802 ps
CPU time 11.49 seconds
Started May 16 03:23:41 PM PDT 24
Finished May 16 03:24:01 PM PDT 24
Peak memory 204812 kb
Host smart-bb211ab7-de63-41c1-b610-fed0de9d0ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11033
14526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1103314526
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.626477433
Short name T411
Test name
Test status
Simulation time 8450925620 ps
CPU time 12.37 seconds
Started May 16 03:23:38 PM PDT 24
Finished May 16 03:23:56 PM PDT 24
Peak memory 204860 kb
Host smart-523b308f-fbdd-4e77-8ac2-3019c134e5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62647
7433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.626477433
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.3793632894
Short name T1022
Test name
Test status
Simulation time 8401766085 ps
CPU time 11.2 seconds
Started May 16 03:23:41 PM PDT 24
Finished May 16 03:24:01 PM PDT 24
Peak memory 204748 kb
Host smart-cc769983-2b03-4f30-9342-affd4a6d5db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37936
32894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.3793632894
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2350656232
Short name T1288
Test name
Test status
Simulation time 8365699903 ps
CPU time 11.26 seconds
Started May 16 03:23:39 PM PDT 24
Finished May 16 03:23:56 PM PDT 24
Peak memory 204776 kb
Host smart-2ec8ba26-62f2-4ef3-bcf8-4fa7eb88490d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23506
56232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2350656232
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.4067001931
Short name T1356
Test name
Test status
Simulation time 8363498051 ps
CPU time 12.08 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:04 PM PDT 24
Peak memory 204600 kb
Host smart-7b411ccd-c5d4-4e09-9700-dc917a444114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40670
01931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.4067001931
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3069726972
Short name T677
Test name
Test status
Simulation time 8474606920 ps
CPU time 12.19 seconds
Started May 16 03:23:37 PM PDT 24
Finished May 16 03:23:53 PM PDT 24
Peak memory 204896 kb
Host smart-723cd8fb-c1b0-4990-91c1-d0a57923408d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30697
26972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3069726972
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.4291772624
Short name T1120
Test name
Test status
Simulation time 8441164958 ps
CPU time 10.79 seconds
Started May 16 03:23:41 PM PDT 24
Finished May 16 03:24:00 PM PDT 24
Peak memory 204904 kb
Host smart-a207f388-d420-444e-a61f-37e1d65f1af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42917
72624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.4291772624
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2060706810
Short name T583
Test name
Test status
Simulation time 8389114468 ps
CPU time 11.77 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:03 PM PDT 24
Peak memory 204888 kb
Host smart-94c265d5-db09-4734-a3ee-2e3f738a77f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20607
06810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2060706810
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.946883089
Short name T738
Test name
Test status
Simulation time 8472099795 ps
CPU time 10.96 seconds
Started May 16 03:23:48 PM PDT 24
Finished May 16 03:24:10 PM PDT 24
Peak memory 204720 kb
Host smart-e69a4f27-479f-4288-ba09-3aa5be43ff85
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=946883089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.946883089
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.224038589
Short name T556
Test name
Test status
Simulation time 8440393019 ps
CPU time 12.01 seconds
Started May 16 03:23:47 PM PDT 24
Finished May 16 03:24:09 PM PDT 24
Peak memory 204800 kb
Host smart-877410c4-2aa2-45a9-ba82-35e0c267a3b4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=224038589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.224038589
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.274258757
Short name T18
Test name
Test status
Simulation time 8505621138 ps
CPU time 11.75 seconds
Started May 16 03:23:47 PM PDT 24
Finished May 16 03:24:09 PM PDT 24
Peak memory 204912 kb
Host smart-38e8bf0c-6cff-4de9-aefb-e95202d800f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27425
8757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.274258757
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3293123444
Short name T916
Test name
Test status
Simulation time 8380539094 ps
CPU time 11.28 seconds
Started May 16 03:23:42 PM PDT 24
Finished May 16 03:24:02 PM PDT 24
Peak memory 204916 kb
Host smart-ed8ec6d1-6010-424f-aa09-183d156e9082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32931
23444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3293123444
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1628152471
Short name T1175
Test name
Test status
Simulation time 8669092868 ps
CPU time 12.63 seconds
Started May 16 03:23:38 PM PDT 24
Finished May 16 03:23:55 PM PDT 24
Peak memory 204876 kb
Host smart-aaac6cf0-cf63-4dc6-b4dd-825e4d5accac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16281
52471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1628152471
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.3579691918
Short name T633
Test name
Test status
Simulation time 8372448143 ps
CPU time 13.69 seconds
Started May 16 03:23:46 PM PDT 24
Finished May 16 03:24:09 PM PDT 24
Peak memory 204808 kb
Host smart-bcf7409d-a075-4bf0-8445-83af8b758c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35796
91918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.3579691918
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.4280116576
Short name T676
Test name
Test status
Simulation time 8371538357 ps
CPU time 11.61 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:03 PM PDT 24
Peak memory 204884 kb
Host smart-4b7892b0-c8ab-4ea2-a1db-028041461c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42801
16576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.4280116576
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3471833497
Short name T418
Test name
Test status
Simulation time 9029467543 ps
CPU time 12.22 seconds
Started May 16 03:23:40 PM PDT 24
Finished May 16 03:23:59 PM PDT 24
Peak memory 204728 kb
Host smart-df558b6f-cd71-4860-bafa-52e60815b451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34718
33497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3471833497
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.4153485179
Short name T1044
Test name
Test status
Simulation time 8450862390 ps
CPU time 11.34 seconds
Started May 16 03:23:41 PM PDT 24
Finished May 16 03:24:01 PM PDT 24
Peak memory 204892 kb
Host smart-b69e0409-3f75-470f-861e-5bd3e5f139b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41534
85179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.4153485179
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3389945415
Short name T1114
Test name
Test status
Simulation time 8379135145 ps
CPU time 11 seconds
Started May 16 03:23:44 PM PDT 24
Finished May 16 03:24:03 PM PDT 24
Peak memory 204764 kb
Host smart-320f042f-379b-407f-9238-f1b20385745b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33899
45415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3389945415
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3203080978
Short name T741
Test name
Test status
Simulation time 8366522331 ps
CPU time 11.4 seconds
Started May 16 03:23:45 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204860 kb
Host smart-bd5f1667-2b1e-46d6-b6ab-205b00a7d127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32030
80978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3203080978
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.301883233
Short name T489
Test name
Test status
Simulation time 8463737434 ps
CPU time 12.32 seconds
Started May 16 03:23:42 PM PDT 24
Finished May 16 03:24:03 PM PDT 24
Peak memory 204880 kb
Host smart-013a763c-f619-4c2c-b267-3358a4bf1c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30188
3233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.301883233
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3982238178
Short name T654
Test name
Test status
Simulation time 8478372874 ps
CPU time 12.28 seconds
Started May 16 03:23:40 PM PDT 24
Finished May 16 03:24:00 PM PDT 24
Peak memory 204884 kb
Host smart-f00ae15d-bc03-49f5-aa58-b33ba96ca33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39822
38178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3982238178
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3121117230
Short name T862
Test name
Test status
Simulation time 11504371648 ps
CPU time 14.33 seconds
Started May 16 03:23:42 PM PDT 24
Finished May 16 03:24:05 PM PDT 24
Peak memory 204824 kb
Host smart-71c24a2f-c5fc-4d86-9714-8c94ede49355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31211
17230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3121117230
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2375902187
Short name T1142
Test name
Test status
Simulation time 8422474642 ps
CPU time 12.02 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:04 PM PDT 24
Peak memory 204836 kb
Host smart-e81141ad-1e89-42fc-b9e5-2311035c4d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23759
02187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2375902187
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.69093845
Short name T1531
Test name
Test status
Simulation time 8372275348 ps
CPU time 13.55 seconds
Started May 16 03:23:39 PM PDT 24
Finished May 16 03:24:00 PM PDT 24
Peak memory 204848 kb
Host smart-163c2518-2933-46fb-9b18-fa528c49d8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69093
845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.69093845
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2891156447
Short name T129
Test name
Test status
Simulation time 8407574393 ps
CPU time 13.82 seconds
Started May 16 03:23:46 PM PDT 24
Finished May 16 03:24:10 PM PDT 24
Peak memory 204916 kb
Host smart-51f65269-b56f-4ca2-8307-0d4ab74aaa56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28911
56447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2891156447
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.4028676499
Short name T413
Test name
Test status
Simulation time 8411305577 ps
CPU time 11.4 seconds
Started May 16 03:23:47 PM PDT 24
Finished May 16 03:24:09 PM PDT 24
Peak memory 204860 kb
Host smart-0d99ef20-3b3d-46f7-b8bb-c0a6b2c57f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40286
76499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.4028676499
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.25362227
Short name T679
Test name
Test status
Simulation time 8386733221 ps
CPU time 11.56 seconds
Started May 16 03:23:41 PM PDT 24
Finished May 16 03:24:01 PM PDT 24
Peak memory 204768 kb
Host smart-63c92fe4-a31e-4a17-99b3-f149cbb25c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25362
227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.25362227
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.735861135
Short name T1585
Test name
Test status
Simulation time 8414951433 ps
CPU time 11.55 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:03 PM PDT 24
Peak memory 204696 kb
Host smart-2079299e-79ea-4bbc-8de8-21faf4f66319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73586
1135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.735861135
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.3845689784
Short name T768
Test name
Test status
Simulation time 8398482374 ps
CPU time 11.84 seconds
Started May 16 03:23:44 PM PDT 24
Finished May 16 03:24:05 PM PDT 24
Peak memory 204892 kb
Host smart-67d6f9e0-31f3-4e4d-8c53-93c973ce7c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38456
89784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3845689784
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.2376632610
Short name T931
Test name
Test status
Simulation time 8436855556 ps
CPU time 12.34 seconds
Started May 16 03:23:45 PM PDT 24
Finished May 16 03:24:07 PM PDT 24
Peak memory 204800 kb
Host smart-68c311d2-0c6b-47b3-9dd4-9fb486b93b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23766
32610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.2376632610
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3106669496
Short name T434
Test name
Test status
Simulation time 8372880037 ps
CPU time 11.36 seconds
Started May 16 03:23:45 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204816 kb
Host smart-6c2e4d09-3625-4abc-be50-a6d61cd80b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31066
69496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3106669496
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3743622162
Short name T569
Test name
Test status
Simulation time 8368330479 ps
CPU time 10.83 seconds
Started May 16 03:23:46 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204840 kb
Host smart-3c2fc7e8-80c4-449b-8a38-6ef4a61751ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37436
22162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3743622162
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2410157869
Short name T250
Test name
Test status
Simulation time 22566319653 ps
CPU time 44.71 seconds
Started May 16 03:23:47 PM PDT 24
Finished May 16 03:24:42 PM PDT 24
Peak memory 204860 kb
Host smart-28efb912-14b6-444f-b884-8fabb76429db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24101
57869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2410157869
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1374869915
Short name T1282
Test name
Test status
Simulation time 8387279965 ps
CPU time 12.72 seconds
Started May 16 03:23:42 PM PDT 24
Finished May 16 03:24:04 PM PDT 24
Peak memory 204848 kb
Host smart-bb1e4a62-3fc6-4ae8-baf4-db2b0c5b5852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13748
69915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1374869915
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1483588707
Short name T486
Test name
Test status
Simulation time 8433192639 ps
CPU time 10.89 seconds
Started May 16 03:23:42 PM PDT 24
Finished May 16 03:24:02 PM PDT 24
Peak memory 204816 kb
Host smart-6f8c5aa7-6275-4bac-a55f-55585dbe2c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14835
88707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1483588707
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.3238406135
Short name T1295
Test name
Test status
Simulation time 8492042807 ps
CPU time 11.11 seconds
Started May 16 03:23:41 PM PDT 24
Finished May 16 03:24:01 PM PDT 24
Peak memory 204852 kb
Host smart-4ddf8ecf-d13b-4419-8986-14ba84a96c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32384
06135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.3238406135
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3541257456
Short name T1163
Test name
Test status
Simulation time 8365997506 ps
CPU time 11.66 seconds
Started May 16 03:23:42 PM PDT 24
Finished May 16 03:24:02 PM PDT 24
Peak memory 204836 kb
Host smart-5f3b7780-a41a-416a-bd03-c1365e603194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35412
57456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3541257456
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.878805895
Short name T825
Test name
Test status
Simulation time 8370196197 ps
CPU time 12.32 seconds
Started May 16 03:23:44 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204832 kb
Host smart-df4bbfa8-0efe-4ef8-9f1a-ec57f1bfc3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87880
5895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.878805895
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2465100096
Short name T958
Test name
Test status
Simulation time 8391607096 ps
CPU time 14.18 seconds
Started May 16 03:23:46 PM PDT 24
Finished May 16 03:24:10 PM PDT 24
Peak memory 204880 kb
Host smart-989820d6-f099-406c-bdd8-0547b8cec94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24651
00096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2465100096
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2076962127
Short name T1624
Test name
Test status
Simulation time 8464604731 ps
CPU time 12.39 seconds
Started May 16 03:23:42 PM PDT 24
Finished May 16 03:24:03 PM PDT 24
Peak memory 204884 kb
Host smart-4ae1497b-3e8f-4332-b581-0941c31cda24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20769
62127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2076962127
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2841005008
Short name T1494
Test name
Test status
Simulation time 8406238281 ps
CPU time 10.72 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:03 PM PDT 24
Peak memory 204840 kb
Host smart-41b09262-81dd-4e59-a813-ef6cbcfe10f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28410
05008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2841005008
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2723491719
Short name T894
Test name
Test status
Simulation time 8376442377 ps
CPU time 11.45 seconds
Started May 16 03:23:47 PM PDT 24
Finished May 16 03:24:09 PM PDT 24
Peak memory 204916 kb
Host smart-42934670-8f98-41c2-b772-d6fd9fecb572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27234
91719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2723491719
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2522571626
Short name T953
Test name
Test status
Simulation time 8475003351 ps
CPU time 12.4 seconds
Started May 16 03:23:50 PM PDT 24
Finished May 16 03:24:14 PM PDT 24
Peak memory 204880 kb
Host smart-92161c33-7d2e-429f-b888-b79d56fde7fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2522571626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2522571626
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.3331591176
Short name T878
Test name
Test status
Simulation time 8384732415 ps
CPU time 11.22 seconds
Started May 16 03:23:49 PM PDT 24
Finished May 16 03:24:11 PM PDT 24
Peak memory 204880 kb
Host smart-53989833-1cb5-4d4a-a47e-4d4420fab5fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3331591176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.3331591176
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.1650277076
Short name T1137
Test name
Test status
Simulation time 8410566028 ps
CPU time 13.76 seconds
Started May 16 03:23:47 PM PDT 24
Finished May 16 03:24:11 PM PDT 24
Peak memory 204916 kb
Host smart-4fa72c31-8882-4a99-82d1-69fc23740d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16502
77076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.1650277076
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2369852504
Short name T1709
Test name
Test status
Simulation time 8378135017 ps
CPU time 14.04 seconds
Started May 16 03:23:43 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204656 kb
Host smart-e51fb8ba-fbfe-4b39-a150-f64c3876eb5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23698
52504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2369852504
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.981254946
Short name T937
Test name
Test status
Simulation time 8469847884 ps
CPU time 11.72 seconds
Started May 16 03:23:48 PM PDT 24
Finished May 16 03:24:11 PM PDT 24
Peak memory 204872 kb
Host smart-9cab8a59-e21d-4a8f-a2f8-c0d435e9e593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98125
4946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.981254946
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1946055583
Short name T634
Test name
Test status
Simulation time 8368217424 ps
CPU time 13.2 seconds
Started May 16 03:23:46 PM PDT 24
Finished May 16 03:24:09 PM PDT 24
Peak memory 204764 kb
Host smart-54537339-7c42-40e2-95c6-610b4ebdcc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19460
55583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1946055583
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.2971971431
Short name T951
Test name
Test status
Simulation time 8389455414 ps
CPU time 11.73 seconds
Started May 16 03:23:45 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204876 kb
Host smart-8839fb3a-0f61-4ee3-8aba-88816f9a4bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29719
71431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2971971431
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.278643441
Short name T1526
Test name
Test status
Simulation time 9139720902 ps
CPU time 11.53 seconds
Started May 16 03:23:46 PM PDT 24
Finished May 16 03:24:08 PM PDT 24
Peak memory 204732 kb
Host smart-8cddca88-7bd0-4fa7-b500-1c41954d79f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27864
3441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.278643441
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3518992548
Short name T1692
Test name
Test status
Simulation time 8399307231 ps
CPU time 13.39 seconds
Started May 16 03:23:46 PM PDT 24
Finished May 16 03:24:09 PM PDT 24
Peak memory 204788 kb
Host smart-60adc32b-2ebc-4978-bd3c-ef5b27d531fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35189
92548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3518992548
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1370430640
Short name T1620
Test name
Test status
Simulation time 8413145961 ps
CPU time 11.51 seconds
Started May 16 03:23:49 PM PDT 24
Finished May 16 03:24:11 PM PDT 24
Peak memory 204936 kb
Host smart-f6541b9c-c57f-40b8-9a89-6052ea2da153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13704
30640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1370430640
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.4157071359
Short name T897
Test name
Test status
Simulation time 8370059040 ps
CPU time 10.71 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:19 PM PDT 24
Peak memory 204800 kb
Host smart-c24b65de-6dd9-4279-8088-94e97110affa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41570
71359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.4157071359
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.568656669
Short name T868
Test name
Test status
Simulation time 8430903183 ps
CPU time 13.63 seconds
Started May 16 03:23:45 PM PDT 24
Finished May 16 03:24:08 PM PDT 24
Peak memory 204844 kb
Host smart-1e30eb68-d230-4ce5-ac4b-6b3f49622c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56865
6669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.568656669
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.733326319
Short name T1091
Test name
Test status
Simulation time 8400658438 ps
CPU time 13.37 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:22 PM PDT 24
Peak memory 204860 kb
Host smart-aa9a7b50-3205-40ec-8dc7-bc98569189fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73332
6319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.733326319
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2478338111
Short name T1076
Test name
Test status
Simulation time 11541312678 ps
CPU time 14.21 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:22 PM PDT 24
Peak memory 204872 kb
Host smart-a8a76b68-87e0-46c4-9074-c34039a05785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24783
38111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2478338111
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3712220592
Short name T1625
Test name
Test status
Simulation time 8411741531 ps
CPU time 10.99 seconds
Started May 16 03:23:44 PM PDT 24
Finished May 16 03:24:04 PM PDT 24
Peak memory 204824 kb
Host smart-91480e00-9f39-4f94-89d8-1d63aa8e0b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37122
20592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3712220592
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.334700855
Short name T891
Test name
Test status
Simulation time 8377437787 ps
CPU time 13.45 seconds
Started May 16 03:23:45 PM PDT 24
Finished May 16 03:24:08 PM PDT 24
Peak memory 204864 kb
Host smart-9ef6df05-542d-4428-836e-ef9bf4d1cf3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33470
0855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.334700855
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.4094324724
Short name T1238
Test name
Test status
Simulation time 8428013806 ps
CPU time 11.7 seconds
Started May 16 03:23:48 PM PDT 24
Finished May 16 03:24:11 PM PDT 24
Peak memory 204900 kb
Host smart-cb918b6c-34ea-4f42-a336-d000ed100442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40943
24724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.4094324724
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3860644554
Short name T1514
Test name
Test status
Simulation time 8414735499 ps
CPU time 12.01 seconds
Started May 16 03:23:44 PM PDT 24
Finished May 16 03:24:05 PM PDT 24
Peak memory 204776 kb
Host smart-be9ba02f-48f4-49c3-a31b-b99d8a6ea7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38606
44554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3860644554
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3026597524
Short name T836
Test name
Test status
Simulation time 8406220271 ps
CPU time 11.8 seconds
Started May 16 03:23:46 PM PDT 24
Finished May 16 03:24:08 PM PDT 24
Peak memory 204908 kb
Host smart-1c10a0eb-9e93-4bb8-85c3-25cc4a0b40a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30265
97524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3026597524
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3211232413
Short name T1270
Test name
Test status
Simulation time 8394556803 ps
CPU time 11.19 seconds
Started May 16 03:23:49 PM PDT 24
Finished May 16 03:24:11 PM PDT 24
Peak memory 204880 kb
Host smart-990aad25-6c27-4508-a642-c8f6a28b5d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32112
32413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3211232413
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.977048487
Short name T1684
Test name
Test status
Simulation time 8450597347 ps
CPU time 11.76 seconds
Started May 16 03:23:49 PM PDT 24
Finished May 16 03:24:11 PM PDT 24
Peak memory 204880 kb
Host smart-70aa8de3-8edc-4e42-97d6-3870851675cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97704
8487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.977048487
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.667767195
Short name T858
Test name
Test status
Simulation time 8406626360 ps
CPU time 12.66 seconds
Started May 16 03:23:49 PM PDT 24
Finished May 16 03:24:12 PM PDT 24
Peak memory 204856 kb
Host smart-7defe5ff-8c84-40b9-bb6e-d52d57ad484c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66776
7195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.667767195
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.4009073447
Short name T673
Test name
Test status
Simulation time 8380625251 ps
CPU time 10.88 seconds
Started May 16 03:23:50 PM PDT 24
Finished May 16 03:24:13 PM PDT 24
Peak memory 204804 kb
Host smart-5fc93488-aead-44c5-90ca-ad7c60e1f6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40090
73447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.4009073447
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2151077765
Short name T508
Test name
Test status
Simulation time 8379591019 ps
CPU time 11.13 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:19 PM PDT 24
Peak memory 204788 kb
Host smart-ed213be8-479f-444d-9aa1-bf720a8565c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21510
77765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2151077765
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2354132584
Short name T1665
Test name
Test status
Simulation time 24031017946 ps
CPU time 52.45 seconds
Started May 16 03:23:45 PM PDT 24
Finished May 16 03:24:47 PM PDT 24
Peak memory 204848 kb
Host smart-c8b86007-7340-4fff-93fc-0c7549dc5a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23541
32584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2354132584
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.4050944319
Short name T1098
Test name
Test status
Simulation time 8404686490 ps
CPU time 11.14 seconds
Started May 16 03:23:48 PM PDT 24
Finished May 16 03:24:10 PM PDT 24
Peak memory 204724 kb
Host smart-db3fb0ec-2b63-4a2c-8b2c-bbdaf0029f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40509
44319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.4050944319
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.512483816
Short name T1023
Test name
Test status
Simulation time 8434678524 ps
CPU time 12.55 seconds
Started May 16 03:23:44 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204732 kb
Host smart-dbbd66c2-b79e-4bfe-b245-db845b4be48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51248
3816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.512483816
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.3678036939
Short name T1013
Test name
Test status
Simulation time 8475834404 ps
CPU time 12.02 seconds
Started May 16 03:23:44 PM PDT 24
Finished May 16 03:24:05 PM PDT 24
Peak memory 204808 kb
Host smart-79bbe888-c048-4633-be5f-35cc9edbbe26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36780
36939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.3678036939
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2523933179
Short name T335
Test name
Test status
Simulation time 8438307246 ps
CPU time 12.06 seconds
Started May 16 03:23:45 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204876 kb
Host smart-90796cfa-78fd-411f-a465-3a7594873f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25239
33179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2523933179
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.779253445
Short name T459
Test name
Test status
Simulation time 8371021458 ps
CPU time 11.21 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:20 PM PDT 24
Peak memory 204792 kb
Host smart-13d86cf0-d445-4c82-aaf8-3702c67b98de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77925
3445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.779253445
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.645079288
Short name T686
Test name
Test status
Simulation time 8364033288 ps
CPU time 10.64 seconds
Started May 16 03:23:46 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204668 kb
Host smart-3e97f00e-520c-4150-8100-7c3ee36ffa6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64507
9288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.645079288
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.120044969
Short name T166
Test name
Test status
Simulation time 8450429661 ps
CPU time 12.16 seconds
Started May 16 03:23:44 PM PDT 24
Finished May 16 03:24:05 PM PDT 24
Peak memory 204796 kb
Host smart-9f583b25-1bd7-4f42-892a-dbc7e9194671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12004
4969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.120044969
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3271595773
Short name T826
Test name
Test status
Simulation time 8401832707 ps
CPU time 11.94 seconds
Started May 16 03:23:47 PM PDT 24
Finished May 16 03:24:10 PM PDT 24
Peak memory 204904 kb
Host smart-adebd8e9-7a1a-4f55-86ce-9dbde8ca6858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32715
95773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3271595773
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.2324545666
Short name T1200
Test name
Test status
Simulation time 8408088694 ps
CPU time 11.58 seconds
Started May 16 03:23:45 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204904 kb
Host smart-eb53655b-0212-4668-b0c3-309046357edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23245
45666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2324545666
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.559219357
Short name T1334
Test name
Test status
Simulation time 8493308340 ps
CPU time 11.25 seconds
Started May 16 03:23:57 PM PDT 24
Finished May 16 03:24:23 PM PDT 24
Peak memory 204744 kb
Host smart-f8ba0217-5d49-43bd-9f18-ef13aa5147f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=559219357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.559219357
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.128623851
Short name T871
Test name
Test status
Simulation time 8395140225 ps
CPU time 11.95 seconds
Started May 16 03:23:57 PM PDT 24
Finished May 16 03:24:23 PM PDT 24
Peak memory 204744 kb
Host smart-a2fd512d-06a2-4515-a37f-0dd8ff5c42cb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=128623851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.128623851
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.3598506374
Short name T1052
Test name
Test status
Simulation time 8422254756 ps
CPU time 14.17 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:22 PM PDT 24
Peak memory 204928 kb
Host smart-a52399f6-eb34-4b21-85a8-3e04d34a4099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35985
06374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.3598506374
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.955562296
Short name T1608
Test name
Test status
Simulation time 8385241660 ps
CPU time 11.14 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:20 PM PDT 24
Peak memory 204856 kb
Host smart-89f147fd-2637-4314-83e8-b16e764beb22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95556
2296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.955562296
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.4201229792
Short name T1036
Test name
Test status
Simulation time 8391134551 ps
CPU time 11.46 seconds
Started May 16 03:23:46 PM PDT 24
Finished May 16 03:24:07 PM PDT 24
Peak memory 204880 kb
Host smart-d1851093-6bb0-443b-89f3-226dae48d842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42012
29792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.4201229792
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2318455704
Short name T9
Test name
Test status
Simulation time 8364101251 ps
CPU time 11.2 seconds
Started May 16 03:23:53 PM PDT 24
Finished May 16 03:24:18 PM PDT 24
Peak memory 204796 kb
Host smart-377d733c-2241-4261-8af9-611319462f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23184
55704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2318455704
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.271839625
Short name T460
Test name
Test status
Simulation time 8379529634 ps
CPU time 11.84 seconds
Started May 16 03:23:52 PM PDT 24
Finished May 16 03:24:17 PM PDT 24
Peak memory 204924 kb
Host smart-871a7893-f753-4b68-bacf-e77ae1079205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27183
9625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.271839625
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2606882699
Short name T1011
Test name
Test status
Simulation time 9142616773 ps
CPU time 12.89 seconds
Started May 16 03:23:53 PM PDT 24
Finished May 16 03:24:20 PM PDT 24
Peak memory 204840 kb
Host smart-82f01611-3072-49e2-bdd3-eabbdb3a021b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26068
82699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2606882699
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1631630100
Short name T59
Test name
Test status
Simulation time 8537633226 ps
CPU time 12.9 seconds
Started May 16 03:23:53 PM PDT 24
Finished May 16 03:24:20 PM PDT 24
Peak memory 204808 kb
Host smart-9762f217-ab30-4afb-b280-eb3fab47e867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16316
30100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1631630100
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.4280986647
Short name T52
Test name
Test status
Simulation time 8431598491 ps
CPU time 11.12 seconds
Started May 16 03:23:58 PM PDT 24
Finished May 16 03:24:24 PM PDT 24
Peak memory 204768 kb
Host smart-354af8dd-16fd-4e30-bfa8-0e30bb65c2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42809
86647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.4280986647
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3793634782
Short name T818
Test name
Test status
Simulation time 8386358408 ps
CPU time 11.02 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:19 PM PDT 24
Peak memory 204900 kb
Host smart-edc7a20e-bf9b-44a8-8696-764b00c7717c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37936
34782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3793634782
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.407542380
Short name T1581
Test name
Test status
Simulation time 8425741516 ps
CPU time 11.05 seconds
Started May 16 03:23:53 PM PDT 24
Finished May 16 03:24:18 PM PDT 24
Peak memory 204900 kb
Host smart-d804c5da-b055-417d-abf7-e601109deda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40754
2380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.407542380
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1134258756
Short name T1471
Test name
Test status
Simulation time 8420788351 ps
CPU time 10.9 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:19 PM PDT 24
Peak memory 204832 kb
Host smart-a1173b1b-e398-4791-92b2-9fa2005dc6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11342
58756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1134258756
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3797044545
Short name T918
Test name
Test status
Simulation time 11541505360 ps
CPU time 14.18 seconds
Started May 16 03:23:55 PM PDT 24
Finished May 16 03:24:24 PM PDT 24
Peak memory 204888 kb
Host smart-abb85206-a1e7-46d2-a6b8-bf11ec0cbe71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37970
44545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3797044545
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2292032181
Short name T1251
Test name
Test status
Simulation time 8441316993 ps
CPU time 10.4 seconds
Started May 16 03:23:53 PM PDT 24
Finished May 16 03:24:18 PM PDT 24
Peak memory 204832 kb
Host smart-d289a6bd-ed6e-4bd9-b6fa-302f04941272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22920
32181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2292032181
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.929238305
Short name T1710
Test name
Test status
Simulation time 8383520969 ps
CPU time 11.29 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:19 PM PDT 24
Peak memory 204852 kb
Host smart-0eb886cb-8c49-4e48-89b7-b70951b87128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92923
8305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.929238305
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3372591018
Short name T790
Test name
Test status
Simulation time 8417962855 ps
CPU time 11.55 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:20 PM PDT 24
Peak memory 204940 kb
Host smart-fb824ba6-0d62-4d65-aa54-0e36837627cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33725
91018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3372591018
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3354462469
Short name T695
Test name
Test status
Simulation time 8449260329 ps
CPU time 12.43 seconds
Started May 16 03:23:57 PM PDT 24
Finished May 16 03:24:25 PM PDT 24
Peak memory 204820 kb
Host smart-d7a62493-cb77-46e6-9a7a-ac5d560876bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33544
62469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3354462469
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3875961284
Short name T611
Test name
Test status
Simulation time 8402261341 ps
CPU time 10.96 seconds
Started May 16 03:23:58 PM PDT 24
Finished May 16 03:24:24 PM PDT 24
Peak memory 204760 kb
Host smart-e3740d8d-8113-430a-b91e-ef8db9248ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38759
61284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3875961284
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.915700636
Short name T48
Test name
Test status
Simulation time 8383380819 ps
CPU time 13.79 seconds
Started May 16 03:23:55 PM PDT 24
Finished May 16 03:24:23 PM PDT 24
Peak memory 204840 kb
Host smart-4cc02ed7-e0b3-4f86-8e2e-03286c911d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91570
0636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.915700636
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.1625750716
Short name T520
Test name
Test status
Simulation time 8393386747 ps
CPU time 10.57 seconds
Started May 16 03:23:56 PM PDT 24
Finished May 16 03:24:21 PM PDT 24
Peak memory 204856 kb
Host smart-693052fe-60bf-4fa3-a4d5-cb238a84e1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16257
50716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.1625750716
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.515134892
Short name T846
Test name
Test status
Simulation time 8368320396 ps
CPU time 12.49 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:21 PM PDT 24
Peak memory 204840 kb
Host smart-c0622a8a-6fea-482a-9864-ab789b4e8e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51513
4892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.515134892
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.120328145
Short name T865
Test name
Test status
Simulation time 8365506654 ps
CPU time 10.96 seconds
Started May 16 03:23:55 PM PDT 24
Finished May 16 03:24:21 PM PDT 24
Peak memory 204796 kb
Host smart-66091ccd-ed8e-4e40-92e1-a6f79960a156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12032
8145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.120328145
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.712768579
Short name T253
Test name
Test status
Simulation time 26059727539 ps
CPU time 46.96 seconds
Started May 16 03:23:55 PM PDT 24
Finished May 16 03:24:56 PM PDT 24
Peak memory 204816 kb
Host smart-cc85d423-64d2-4d9d-a89b-83b866a99317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71276
8579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.712768579
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3432101738
Short name T721
Test name
Test status
Simulation time 8376350908 ps
CPU time 11.28 seconds
Started May 16 03:23:55 PM PDT 24
Finished May 16 03:24:21 PM PDT 24
Peak memory 204840 kb
Host smart-d7a2b297-f290-4e7f-89d0-f5ae3957e651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34321
01738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3432101738
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2212954207
Short name T1037
Test name
Test status
Simulation time 8448774221 ps
CPU time 11.81 seconds
Started May 16 03:23:57 PM PDT 24
Finished May 16 03:24:25 PM PDT 24
Peak memory 204808 kb
Host smart-760d3efc-e66e-4b61-a84f-c82346d9e41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22129
54207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2212954207
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.1908264194
Short name T998
Test name
Test status
Simulation time 8381283080 ps
CPU time 11.31 seconds
Started May 16 03:23:54 PM PDT 24
Finished May 16 03:24:20 PM PDT 24
Peak memory 204816 kb
Host smart-4aa5abb3-cc85-4ef5-b73f-f136a81a5230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19082
64194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.1908264194
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2118387401
Short name T525
Test name
Test status
Simulation time 8366710796 ps
CPU time 12.16 seconds
Started May 16 03:23:53 PM PDT 24
Finished May 16 03:24:19 PM PDT 24
Peak memory 204852 kb
Host smart-517856c9-8950-40e3-81a6-c30c533d093c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21183
87401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2118387401
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1081283105
Short name T605
Test name
Test status
Simulation time 8380988811 ps
CPU time 10.86 seconds
Started May 16 03:23:55 PM PDT 24
Finished May 16 03:24:20 PM PDT 24
Peak memory 204876 kb
Host smart-ecdb26d7-5fb2-4f8d-be74-3e841b1091dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10812
83105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1081283105
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1340080771
Short name T873
Test name
Test status
Simulation time 8380524445 ps
CPU time 10.7 seconds
Started May 16 03:23:55 PM PDT 24
Finished May 16 03:24:20 PM PDT 24
Peak memory 204868 kb
Host smart-4ffdac9c-cf3b-40f6-97aa-bb6826267baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13400
80771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1340080771
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3252573861
Short name T1242
Test name
Test status
Simulation time 8447231499 ps
CPU time 11.53 seconds
Started May 16 03:23:45 PM PDT 24
Finished May 16 03:24:06 PM PDT 24
Peak memory 204832 kb
Host smart-f4a605a6-c00b-43f7-aa0e-c2714526c45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32525
73861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3252573861
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.4074917111
Short name T1187
Test name
Test status
Simulation time 8396216415 ps
CPU time 11.29 seconds
Started May 16 03:24:01 PM PDT 24
Finished May 16 03:24:27 PM PDT 24
Peak memory 204808 kb
Host smart-7fcd5f48-e6b4-48e3-bb61-6ec031088479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40749
17111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.4074917111
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.384241233
Short name T1555
Test name
Test status
Simulation time 8400508849 ps
CPU time 11.54 seconds
Started May 16 03:23:53 PM PDT 24
Finished May 16 03:24:19 PM PDT 24
Peak memory 204872 kb
Host smart-2fba0b20-8475-42d1-b975-61b7ac440df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38424
1233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.384241233
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.1437466669
Short name T1339
Test name
Test status
Simulation time 8476155063 ps
CPU time 10.85 seconds
Started May 16 03:24:06 PM PDT 24
Finished May 16 03:24:32 PM PDT 24
Peak memory 204888 kb
Host smart-67f0236c-9756-4412-ab69-ae3b51f27c1d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1437466669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.1437466669
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.718270922
Short name T1134
Test name
Test status
Simulation time 8409951114 ps
CPU time 10.92 seconds
Started May 16 03:24:09 PM PDT 24
Finished May 16 03:24:34 PM PDT 24
Peak memory 204832 kb
Host smart-a359fe82-186f-48ed-b3e6-ddf00b47b7ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=718270922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.718270922
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.2033098553
Short name T972
Test name
Test status
Simulation time 8482676177 ps
CPU time 12.18 seconds
Started May 16 03:24:03 PM PDT 24
Finished May 16 03:24:30 PM PDT 24
Peak memory 204876 kb
Host smart-db0a3ae7-00be-4632-9b85-d19c1b1479d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20330
98553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.2033098553
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3584995385
Short name T427
Test name
Test status
Simulation time 8376557887 ps
CPU time 11.92 seconds
Started May 16 03:24:01 PM PDT 24
Finished May 16 03:24:29 PM PDT 24
Peak memory 204836 kb
Host smart-a8d70ed8-1149-4ff4-a8cc-3e8f4fa1f85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35849
95385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3584995385
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3871918819
Short name T774
Test name
Test status
Simulation time 8608121458 ps
CPU time 13.19 seconds
Started May 16 03:23:57 PM PDT 24
Finished May 16 03:24:26 PM PDT 24
Peak memory 204768 kb
Host smart-0012d658-9351-4e8f-8b94-4dec98690048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38719
18819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3871918819
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1819271021
Short name T102
Test name
Test status
Simulation time 8372984113 ps
CPU time 13.79 seconds
Started May 16 03:24:02 PM PDT 24
Finished May 16 03:24:30 PM PDT 24
Peak memory 204868 kb
Host smart-34fc937c-152b-4992-9371-8b5617ea796e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18192
71021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1819271021
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2816622091
Short name T1240
Test name
Test status
Simulation time 8371301869 ps
CPU time 12.28 seconds
Started May 16 03:23:57 PM PDT 24
Finished May 16 03:24:25 PM PDT 24
Peak memory 204848 kb
Host smart-43a1283a-2378-46d8-a77a-ff68eb5e4199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28166
22091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2816622091
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2476529296
Short name T975
Test name
Test status
Simulation time 8405067754 ps
CPU time 12.3 seconds
Started May 16 03:24:01 PM PDT 24
Finished May 16 03:24:29 PM PDT 24
Peak memory 204800 kb
Host smart-1fd6547b-6097-4f24-a425-567d867d1533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24765
29296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2476529296
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2508100667
Short name T1218
Test name
Test status
Simulation time 8455877285 ps
CPU time 12.4 seconds
Started May 16 03:24:07 PM PDT 24
Finished May 16 03:24:34 PM PDT 24
Peak memory 204892 kb
Host smart-faaf0cc4-f970-4d5f-8deb-abad13d1a943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25081
00667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2508100667
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3516703927
Short name T1029
Test name
Test status
Simulation time 8397276109 ps
CPU time 12.11 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204860 kb
Host smart-9d85a916-4fc7-4cc5-8871-cb1bcad7f4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35167
03927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3516703927
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3342051653
Short name T1397
Test name
Test status
Simulation time 8411158962 ps
CPU time 10.62 seconds
Started May 16 03:24:01 PM PDT 24
Finished May 16 03:24:27 PM PDT 24
Peak memory 204892 kb
Host smart-78377307-a803-4748-87c9-e676333728fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33420
51653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3342051653
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1636095372
Short name T1693
Test name
Test status
Simulation time 8399747607 ps
CPU time 12.2 seconds
Started May 16 03:24:01 PM PDT 24
Finished May 16 03:24:28 PM PDT 24
Peak memory 204860 kb
Host smart-51612343-b74a-45f1-9d25-37f3c050b71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16360
95372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1636095372
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3584688276
Short name T396
Test name
Test status
Simulation time 11542797547 ps
CPU time 13.75 seconds
Started May 16 03:23:55 PM PDT 24
Finished May 16 03:24:23 PM PDT 24
Peak memory 204884 kb
Host smart-efc78fbd-2190-4721-970f-980450a7c1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35846
88276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3584688276
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1913986734
Short name T731
Test name
Test status
Simulation time 8425330503 ps
CPU time 13.1 seconds
Started May 16 03:24:08 PM PDT 24
Finished May 16 03:24:35 PM PDT 24
Peak memory 204816 kb
Host smart-2cf70283-72d8-4118-ab66-cbe8dc71eb94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19139
86734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1913986734
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.754408855
Short name T1107
Test name
Test status
Simulation time 8370370076 ps
CPU time 11.64 seconds
Started May 16 03:24:02 PM PDT 24
Finished May 16 03:24:29 PM PDT 24
Peak memory 204832 kb
Host smart-c0b8979c-5e64-4452-ae06-b2c3575fc326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75440
8855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.754408855
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.586069847
Short name T132
Test name
Test status
Simulation time 8419377941 ps
CPU time 12.67 seconds
Started May 16 03:24:02 PM PDT 24
Finished May 16 03:24:30 PM PDT 24
Peak memory 204800 kb
Host smart-418a6ed8-5e48-4bdd-9e3b-a145f47ab321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58606
9847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.586069847
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3554724779
Short name T751
Test name
Test status
Simulation time 8410470344 ps
CPU time 13.13 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204780 kb
Host smart-2d93ed06-acb8-45e2-9695-906344576547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35547
24779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3554724779
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2503214756
Short name T1502
Test name
Test status
Simulation time 8392578973 ps
CPU time 11.77 seconds
Started May 16 03:24:02 PM PDT 24
Finished May 16 03:24:29 PM PDT 24
Peak memory 204936 kb
Host smart-92297fe8-6cf7-489c-9b8e-0b9028df1813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25032
14756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2503214756
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.214944717
Short name T773
Test name
Test status
Simulation time 8406941980 ps
CPU time 13.72 seconds
Started May 16 03:24:07 PM PDT 24
Finished May 16 03:24:36 PM PDT 24
Peak memory 204872 kb
Host smart-56be9dac-d5f1-43e6-a74b-8fdf657a8e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21494
4717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.214944717
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2508376504
Short name T1236
Test name
Test status
Simulation time 8413539135 ps
CPU time 12.01 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204848 kb
Host smart-9bfad38f-fd3e-4cf2-b58f-73d37f4c9aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25083
76504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2508376504
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.3610321267
Short name T1012
Test name
Test status
Simulation time 8445533838 ps
CPU time 11.85 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204800 kb
Host smart-afb90f3d-0dd7-488d-ba78-bb566931bbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36103
21267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.3610321267
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.281512169
Short name T1126
Test name
Test status
Simulation time 8374742987 ps
CPU time 11.38 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:36 PM PDT 24
Peak memory 204856 kb
Host smart-c4e51316-7de8-41fc-9915-42bbd621a702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28151
2169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.281512169
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.510909768
Short name T1003
Test name
Test status
Simulation time 8403407104 ps
CPU time 12.46 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204868 kb
Host smart-7579f3bb-98c4-4e48-bd40-85282a0727a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51090
9768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.510909768
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.4089384942
Short name T945
Test name
Test status
Simulation time 29200730527 ps
CPU time 61.95 seconds
Started May 16 03:24:01 PM PDT 24
Finished May 16 03:25:19 PM PDT 24
Peak memory 204808 kb
Host smart-159474ee-ee43-48dc-9e04-25d729ec6aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40893
84942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.4089384942
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.84217176
Short name T1404
Test name
Test status
Simulation time 8393296625 ps
CPU time 11.03 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:36 PM PDT 24
Peak memory 204904 kb
Host smart-7a02d4bb-e4f6-4e30-83d1-b24ff83e18be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84217
176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.84217176
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.380427036
Short name T1702
Test name
Test status
Simulation time 8424672411 ps
CPU time 11.21 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:35 PM PDT 24
Peak memory 204776 kb
Host smart-23eadeef-96e7-4bfc-a7a6-814764557f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38042
7036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.380427036
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.3239943221
Short name T1291
Test name
Test status
Simulation time 8416829475 ps
CPU time 12.91 seconds
Started May 16 03:24:08 PM PDT 24
Finished May 16 03:24:36 PM PDT 24
Peak memory 204784 kb
Host smart-6160ce40-98f8-43c2-a0d9-6a71e67910cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32399
43221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.3239943221
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1737840915
Short name T426
Test name
Test status
Simulation time 8365836178 ps
CPU time 13.32 seconds
Started May 16 03:24:08 PM PDT 24
Finished May 16 03:24:36 PM PDT 24
Peak memory 204832 kb
Host smart-a17bec04-7b21-4bb1-b7a0-618442badfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17378
40915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1737840915
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.4284144759
Short name T607
Test name
Test status
Simulation time 8378709768 ps
CPU time 11.74 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204820 kb
Host smart-b29e8654-55cb-4c9c-b46a-42ec84234462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42841
44759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.4284144759
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1267480599
Short name T1634
Test name
Test status
Simulation time 8403227078 ps
CPU time 11.25 seconds
Started May 16 03:24:03 PM PDT 24
Finished May 16 03:24:29 PM PDT 24
Peak memory 204816 kb
Host smart-679e6390-b67d-4fdb-9ac2-a3a7e8680b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12674
80599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1267480599
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2244404335
Short name T182
Test name
Test status
Simulation time 8469337430 ps
CPU time 10.89 seconds
Started May 16 03:23:56 PM PDT 24
Finished May 16 03:24:21 PM PDT 24
Peak memory 204908 kb
Host smart-d386f127-2165-4954-862c-233ec77ede36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22444
04335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2244404335
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2801575414
Short name T3
Test name
Test status
Simulation time 8392924958 ps
CPU time 11.21 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:36 PM PDT 24
Peak memory 204860 kb
Host smart-f5baa24d-8fd1-44f6-a305-788603d359d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28015
75414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2801575414
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.193325325
Short name T1648
Test name
Test status
Simulation time 8415954910 ps
CPU time 12.66 seconds
Started May 16 03:24:01 PM PDT 24
Finished May 16 03:24:29 PM PDT 24
Peak memory 204872 kb
Host smart-ad043f17-ba18-4c5e-8c11-94c099e47152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19332
5325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.193325325
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.1056460733
Short name T403
Test name
Test status
Simulation time 8470107297 ps
CPU time 12.82 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204824 kb
Host smart-da165b4b-96b5-4103-8c02-45778c04d9d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1056460733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.1056460733
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.648133592
Short name T1309
Test name
Test status
Simulation time 8382176042 ps
CPU time 11.18 seconds
Started May 16 03:24:14 PM PDT 24
Finished May 16 03:24:39 PM PDT 24
Peak memory 204828 kb
Host smart-592aef23-5b7f-419d-bb0e-6305ea5fafd6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=648133592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.648133592
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.1116154816
Short name T1421
Test name
Test status
Simulation time 8465762593 ps
CPU time 12.8 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204860 kb
Host smart-24db6426-874e-4c88-af3f-cf24bae2c2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11161
54816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.1116154816
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3996948662
Short name T1544
Test name
Test status
Simulation time 8387480381 ps
CPU time 12.05 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204908 kb
Host smart-8c9d5ac2-75b7-42f4-9b46-48b9821b0e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39969
48662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3996948662
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1749306790
Short name T92
Test name
Test status
Simulation time 9512720819 ps
CPU time 15.36 seconds
Started May 16 03:24:03 PM PDT 24
Finished May 16 03:24:33 PM PDT 24
Peak memory 204880 kb
Host smart-96939772-a1ac-4cf0-a167-0d0e8ec09e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17493
06790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1749306790
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3519435501
Short name T1345
Test name
Test status
Simulation time 8434733808 ps
CPU time 12.69 seconds
Started May 16 03:24:14 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204876 kb
Host smart-3894777b-48ca-4bc6-91d3-37938f1829b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35194
35501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3519435501
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3959267914
Short name T652
Test name
Test status
Simulation time 8374839110 ps
CPU time 11.51 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204912 kb
Host smart-9944c10d-0f8c-4aa3-8e6e-12af987ad402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39592
67914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3959267914
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.728833578
Short name T1452
Test name
Test status
Simulation time 9047205057 ps
CPU time 12.75 seconds
Started May 16 03:24:07 PM PDT 24
Finished May 16 03:24:35 PM PDT 24
Peak memory 204708 kb
Host smart-e3d5c0ec-1f7b-4fd9-96f3-1b277638f4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72883
3578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.728833578
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.371792193
Short name T875
Test name
Test status
Simulation time 8661671747 ps
CPU time 13 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204824 kb
Host smart-df7b2a7d-bdec-4767-8ef1-02a73360a192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37179
2193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.371792193
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2463347739
Short name T729
Test name
Test status
Simulation time 8501210253 ps
CPU time 11.27 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:36 PM PDT 24
Peak memory 204928 kb
Host smart-4ec51f2f-cb81-4461-8c3a-b9cab0d10361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24633
47739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2463347739
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1549966886
Short name T1301
Test name
Test status
Simulation time 8365583217 ps
CPU time 12.44 seconds
Started May 16 03:24:15 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204872 kb
Host smart-22adc173-79ae-4aca-b171-3cdbefe14344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15499
66886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1549966886
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2024510205
Short name T475
Test name
Test status
Simulation time 8469254369 ps
CPU time 10.92 seconds
Started May 16 03:24:07 PM PDT 24
Finished May 16 03:24:33 PM PDT 24
Peak memory 204796 kb
Host smart-369eff03-d5bd-4734-801c-43320e82e1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20245
10205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2024510205
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.2166209486
Short name T1653
Test name
Test status
Simulation time 8403223966 ps
CPU time 13.33 seconds
Started May 16 03:24:03 PM PDT 24
Finished May 16 03:24:31 PM PDT 24
Peak memory 204948 kb
Host smart-0d5ba102-04e0-4f28-93fa-7c84e35311d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21662
09486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.2166209486
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.505233516
Short name T1100
Test name
Test status
Simulation time 11505259131 ps
CPU time 14.24 seconds
Started May 16 03:24:09 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204752 kb
Host smart-cab4cfe7-47a8-4ea6-94d9-226a51a5bcde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50523
3516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.505233516
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2157835855
Short name T2
Test name
Test status
Simulation time 8413220530 ps
CPU time 10.84 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:36 PM PDT 24
Peak memory 204764 kb
Host smart-a64fea26-717e-43a3-8b37-e87b35a663e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21578
35855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2157835855
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2326515962
Short name T1021
Test name
Test status
Simulation time 8400100492 ps
CPU time 11.08 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:36 PM PDT 24
Peak memory 204776 kb
Host smart-41f035c1-bcba-4f53-940a-6fddb4965b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23265
15962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2326515962
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.387926013
Short name T1308
Test name
Test status
Simulation time 8417377883 ps
CPU time 12.35 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204800 kb
Host smart-a743e99e-a38a-4d0f-aef7-a0db3d2c889a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38792
6013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.387926013
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.809746781
Short name T849
Test name
Test status
Simulation time 8417721725 ps
CPU time 14.28 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204880 kb
Host smart-20c3b405-c873-4df4-83e5-e0a4e25526de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80974
6781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.809746781
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1822081432
Short name T1686
Test name
Test status
Simulation time 8398690675 ps
CPU time 11.61 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204776 kb
Host smart-c58359db-3260-4e35-8712-a861b6fa1a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18220
81432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1822081432
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3290915955
Short name T855
Test name
Test status
Simulation time 8463977138 ps
CPU time 11.12 seconds
Started May 16 03:24:13 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204804 kb
Host smart-7817eeb8-3caa-4b3b-87fb-80f577d3b250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32909
15955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3290915955
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.821573229
Short name T213
Test name
Test status
Simulation time 8419148972 ps
CPU time 11.23 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204920 kb
Host smart-f3c42600-6497-40c5-9be1-c9f66dfdca13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82157
3229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.821573229
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.2456239840
Short name T1055
Test name
Test status
Simulation time 8373044374 ps
CPU time 11.5 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204816 kb
Host smart-0b728b7f-4729-447e-bb7f-bd8144ee934c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24562
39840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.2456239840
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.217818646
Short name T500
Test name
Test status
Simulation time 8371904000 ps
CPU time 10.77 seconds
Started May 16 03:24:16 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204804 kb
Host smart-aedbe5ec-56bf-4061-800c-fc93140a2d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21781
8646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.217818646
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.324635824
Short name T1370
Test name
Test status
Simulation time 8396237660 ps
CPU time 11.18 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204744 kb
Host smart-65a5c283-9ef6-4f2d-a6ed-fd309cd116df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32463
5824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.324635824
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1586782085
Short name T1425
Test name
Test status
Simulation time 19993885110 ps
CPU time 35.63 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:25:01 PM PDT 24
Peak memory 204808 kb
Host smart-9f93b451-ad9c-468c-b6db-0e9e18310025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15867
82085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1586782085
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3015381823
Short name T1587
Test name
Test status
Simulation time 8393973198 ps
CPU time 11.45 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204928 kb
Host smart-a2638f67-dfcb-42af-9a1c-e2d1d3e94e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30153
81823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3015381823
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2460470042
Short name T693
Test name
Test status
Simulation time 8450874454 ps
CPU time 11.16 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204856 kb
Host smart-1dc7f0d5-2463-4e1b-9306-24ca7b679cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24604
70042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2460470042
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3014459966
Short name T1016
Test name
Test status
Simulation time 8378613771 ps
CPU time 12.32 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204848 kb
Host smart-bacdf7ff-ca7b-4900-8fcc-cef4e7b25223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30144
59966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3014459966
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3077654266
Short name T1663
Test name
Test status
Simulation time 8379164848 ps
CPU time 11.97 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204776 kb
Host smart-ec5852d4-c7dd-46be-af58-f33d0b75735c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30776
54266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3077654266
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2720569306
Short name T180
Test name
Test status
Simulation time 8380640672 ps
CPU time 13.33 seconds
Started May 16 03:24:17 PM PDT 24
Finished May 16 03:24:44 PM PDT 24
Peak memory 204860 kb
Host smart-ca53cb00-ddc6-4efe-a913-8188e5fc5077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27205
69306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2720569306
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.784162079
Short name T89
Test name
Test status
Simulation time 8364963663 ps
CPU time 13.03 seconds
Started May 16 03:24:14 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204840 kb
Host smart-bf5f54b9-9af7-48b9-a8cb-b7f79d1498d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78416
2079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.784162079
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3438218504
Short name T601
Test name
Test status
Simulation time 8432486154 ps
CPU time 12.13 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204884 kb
Host smart-97cd1018-1126-4542-8097-1f79353e6825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34382
18504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3438218504
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1106496139
Short name T1165
Test name
Test status
Simulation time 8383848413 ps
CPU time 11.33 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204820 kb
Host smart-e2a736f3-6d0a-4646-9f2d-7b1d148ec6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11064
96139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1106496139
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1265100397
Short name T1493
Test name
Test status
Simulation time 8405149193 ps
CPU time 10.35 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204832 kb
Host smart-099e0b46-0905-4b05-a836-2bd65f0aae03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12651
00397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1265100397
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.2689775848
Short name T43
Test name
Test status
Simulation time 8473239158 ps
CPU time 10.68 seconds
Started May 16 03:24:17 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204756 kb
Host smart-3ca7bdf5-9dea-4fb4-909e-83ba5dbba9d5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2689775848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.2689775848
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.3926075525
Short name T447
Test name
Test status
Simulation time 8384773730 ps
CPU time 11.44 seconds
Started May 16 03:24:19 PM PDT 24
Finished May 16 03:24:44 PM PDT 24
Peak memory 204956 kb
Host smart-346105e3-033d-4530-b82a-ab4a0cd064c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3926075525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.3926075525
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.2520112814
Short name T328
Test name
Test status
Simulation time 8464467591 ps
CPU time 11.96 seconds
Started May 16 03:24:17 PM PDT 24
Finished May 16 03:24:42 PM PDT 24
Peak memory 204712 kb
Host smart-a026d8c1-a308-4ece-ad0f-7a212037e9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
12814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.2520112814
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.4272121391
Short name T362
Test name
Test status
Simulation time 8376276062 ps
CPU time 10.77 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:35 PM PDT 24
Peak memory 204956 kb
Host smart-673aa026-0b82-4f76-9ddc-dbccb9bf108d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42721
21391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.4272121391
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2269149407
Short name T56
Test name
Test status
Simulation time 8410622046 ps
CPU time 10.93 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204772 kb
Host smart-ffa9172f-02ce-4666-9a68-9febf772fcf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22691
49407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2269149407
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.178828190
Short name T1708
Test name
Test status
Simulation time 8943675320 ps
CPU time 12.67 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204924 kb
Host smart-c6bdc589-1f34-48c5-9270-2c313236c815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17882
8190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.178828190
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2585448763
Short name T1357
Test name
Test status
Simulation time 8367974794 ps
CPU time 12.3 seconds
Started May 16 03:24:14 PM PDT 24
Finished May 16 03:24:40 PM PDT 24
Peak memory 204852 kb
Host smart-798701e4-4567-437a-95bf-7712b67cfd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25854
48763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2585448763
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.757390468
Short name T1158
Test name
Test status
Simulation time 8394532421 ps
CPU time 11.09 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204824 kb
Host smart-439601ae-3275-496a-80b0-f82161e59d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75739
0468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.757390468
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2618862948
Short name T1372
Test name
Test status
Simulation time 8468844985 ps
CPU time 11.5 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204856 kb
Host smart-dbbaf643-493f-470f-b8af-896d9b9f910f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26188
62948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2618862948
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2194600664
Short name T1546
Test name
Test status
Simulation time 8463435020 ps
CPU time 10.97 seconds
Started May 16 03:24:24 PM PDT 24
Finished May 16 03:24:47 PM PDT 24
Peak memory 204872 kb
Host smart-2d6a0c1c-04aa-481d-a10d-28eaf39eda3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21946
00664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2194600664
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1727192945
Short name T712
Test name
Test status
Simulation time 8379564759 ps
CPU time 11.75 seconds
Started May 16 03:24:19 PM PDT 24
Finished May 16 03:24:45 PM PDT 24
Peak memory 204880 kb
Host smart-61076440-2366-4aa2-bd15-a55f909064a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17271
92945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1727192945
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.943118271
Short name T405
Test name
Test status
Simulation time 8429320847 ps
CPU time 11.77 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204436 kb
Host smart-cbcdba76-5fda-4f45-b018-71b55cc84160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94311
8271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.943118271
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.1824227927
Short name T1533
Test name
Test status
Simulation time 8425627845 ps
CPU time 11.31 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204844 kb
Host smart-896ab99d-9886-4950-a91c-ae0880845737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18242
27927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.1824227927
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2448864720
Short name T446
Test name
Test status
Simulation time 8457476119 ps
CPU time 11.31 seconds
Started May 16 03:24:15 PM PDT 24
Finished May 16 03:24:40 PM PDT 24
Peak memory 204828 kb
Host smart-3393e872-47e2-4941-bd52-991b6ede8b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24488
64720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2448864720
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3449968397
Short name T927
Test name
Test status
Simulation time 8384616840 ps
CPU time 11.06 seconds
Started May 16 03:24:10 PM PDT 24
Finished May 16 03:24:36 PM PDT 24
Peak memory 204544 kb
Host smart-e78adc82-0360-47b8-addc-f4496bd90138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34499
68397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3449968397
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1927505630
Short name T141
Test name
Test status
Simulation time 8426899610 ps
CPU time 12.89 seconds
Started May 16 03:24:14 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204928 kb
Host smart-09304605-64b2-4c11-bfad-53f1f8f8d198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19275
05630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1927505630
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1601380274
Short name T1216
Test name
Test status
Simulation time 8474092819 ps
CPU time 10.98 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204912 kb
Host smart-b66eca4c-d61f-4fff-915d-98593f530581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16013
80274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1601380274
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1749596543
Short name T1616
Test name
Test status
Simulation time 8399695917 ps
CPU time 10.94 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:36 PM PDT 24
Peak memory 204876 kb
Host smart-a8564c6d-4516-4176-ad84-d42eba416d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17495
96543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1749596543
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.240760262
Short name T1732
Test name
Test status
Simulation time 8395263212 ps
CPU time 11.31 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204820 kb
Host smart-6bc2f658-3ee0-4bb9-87f8-ee272f115a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24076
0262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.240760262
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3489740927
Short name T206
Test name
Test status
Simulation time 8393048461 ps
CPU time 11.1 seconds
Started May 16 03:24:16 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204808 kb
Host smart-c11a5cff-1b4e-45c1-8966-49bc9d5eb3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34897
40927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3489740927
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.1564625871
Short name T1089
Test name
Test status
Simulation time 8370172034 ps
CPU time 13.6 seconds
Started May 16 03:24:18 PM PDT 24
Finished May 16 03:24:44 PM PDT 24
Peak memory 204828 kb
Host smart-69c01c69-bdac-42f9-8915-66496190e2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15646
25871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.1564625871
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3738878278
Short name T914
Test name
Test status
Simulation time 8372571540 ps
CPU time 11.2 seconds
Started May 16 03:24:17 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204804 kb
Host smart-45352c42-b2fb-491c-95d5-7d0e4a9062b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37388
78278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3738878278
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3179341197
Short name T1661
Test name
Test status
Simulation time 8440911468 ps
CPU time 12.53 seconds
Started May 16 03:24:16 PM PDT 24
Finished May 16 03:24:42 PM PDT 24
Peak memory 204892 kb
Host smart-62216b3c-df24-4dc2-8d83-5625b7b9a7a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31793
41197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3179341197
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1423380375
Short name T1759
Test name
Test status
Simulation time 28094880878 ps
CPU time 54.15 seconds
Started May 16 03:24:13 PM PDT 24
Finished May 16 03:25:21 PM PDT 24
Peak memory 204736 kb
Host smart-1b219422-619e-4f9c-a905-183b48eb6ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14233
80375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1423380375
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2195251749
Short name T1368
Test name
Test status
Simulation time 8383484321 ps
CPU time 11.49 seconds
Started May 16 03:24:14 PM PDT 24
Finished May 16 03:24:40 PM PDT 24
Peak memory 204828 kb
Host smart-819a63da-2697-491d-bef2-cd7dbeb18ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21952
51749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2195251749
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2527246419
Short name T1247
Test name
Test status
Simulation time 8419857572 ps
CPU time 11.58 seconds
Started May 16 03:24:14 PM PDT 24
Finished May 16 03:24:40 PM PDT 24
Peak memory 204852 kb
Host smart-b5752ca1-7d29-4b55-97ab-843a4f62009c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25272
46419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2527246419
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3233292037
Short name T361
Test name
Test status
Simulation time 8388959760 ps
CPU time 11.92 seconds
Started May 16 03:24:11 PM PDT 24
Finished May 16 03:24:38 PM PDT 24
Peak memory 204872 kb
Host smart-e3b9b410-622d-48f4-9fb4-24a130331e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32332
92037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3233292037
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2361379047
Short name T1455
Test name
Test status
Simulation time 8370427616 ps
CPU time 10.94 seconds
Started May 16 03:24:12 PM PDT 24
Finished May 16 03:24:37 PM PDT 24
Peak memory 204704 kb
Host smart-3441714f-e46f-4a28-8ecc-545ce8a78442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23613
79047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2361379047
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1093085553
Short name T37
Test name
Test status
Simulation time 8392827953 ps
CPU time 13.01 seconds
Started May 16 03:24:17 PM PDT 24
Finished May 16 03:24:43 PM PDT 24
Peak memory 204888 kb
Host smart-79c35b7b-8e0d-4f55-849a-e8b2bab03b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10930
85553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1093085553
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2169397300
Short name T1377
Test name
Test status
Simulation time 8375821768 ps
CPU time 12.3 seconds
Started May 16 03:24:16 PM PDT 24
Finished May 16 03:24:42 PM PDT 24
Peak memory 204780 kb
Host smart-ee0b0e50-0ae5-456c-b2ce-b826567e1703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21693
97300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2169397300
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3987952982
Short name T1563
Test name
Test status
Simulation time 8439021505 ps
CPU time 11.5 seconds
Started May 16 03:24:16 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204868 kb
Host smart-96da6aa2-b0cb-44a5-8732-bf78736d76c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39879
52982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3987952982
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1561827089
Short name T449
Test name
Test status
Simulation time 8404397706 ps
CPU time 11.06 seconds
Started May 16 03:24:16 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204932 kb
Host smart-dd8cfb4b-a126-40cb-ad30-b838206c16b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15618
27089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1561827089
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3392308527
Short name T1068
Test name
Test status
Simulation time 8399788486 ps
CPU time 12.52 seconds
Started May 16 03:24:16 PM PDT 24
Finished May 16 03:24:42 PM PDT 24
Peak memory 204892 kb
Host smart-27ad29b7-95a0-47a2-a822-9018c3aed120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33923
08527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3392308527
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.3261219788
Short name T759
Test name
Test status
Simulation time 8467219663 ps
CPU time 10.79 seconds
Started May 16 03:19:35 PM PDT 24
Finished May 16 03:19:51 PM PDT 24
Peak memory 204856 kb
Host smart-a758f3d1-b718-46df-886b-fcd6238e08d9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3261219788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.3261219788
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.1858384578
Short name T1008
Test name
Test status
Simulation time 8383478358 ps
CPU time 11.63 seconds
Started May 16 03:19:36 PM PDT 24
Finished May 16 03:19:53 PM PDT 24
Peak memory 204864 kb
Host smart-aac8dc1f-4fdd-47a6-a8da-fdd5dfde601f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1858384578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.1858384578
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.3382565495
Short name T1483
Test name
Test status
Simulation time 8442767567 ps
CPU time 11.2 seconds
Started May 16 03:19:33 PM PDT 24
Finished May 16 03:19:48 PM PDT 24
Peak memory 204880 kb
Host smart-d9696fdb-0442-4246-b391-d7e6cfd56090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33825
65495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.3382565495
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.378094496
Short name T801
Test name
Test status
Simulation time 8383831756 ps
CPU time 12.04 seconds
Started May 16 03:19:26 PM PDT 24
Finished May 16 03:19:44 PM PDT 24
Peak memory 204772 kb
Host smart-d49179a2-d662-439b-ac34-18a47ae20a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
4496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.378094496
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1201584340
Short name T1631
Test name
Test status
Simulation time 8376625077 ps
CPU time 10.46 seconds
Started May 16 03:19:26 PM PDT 24
Finished May 16 03:19:42 PM PDT 24
Peak memory 204848 kb
Host smart-22497249-87f6-48ff-adf8-5b2f72d4be85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12015
84340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1201584340
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.763835163
Short name T735
Test name
Test status
Simulation time 8386310312 ps
CPU time 11.65 seconds
Started May 16 03:19:24 PM PDT 24
Finished May 16 03:19:40 PM PDT 24
Peak memory 204852 kb
Host smart-17245393-b9c4-4d1a-a766-a4551a3257c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76383
5163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.763835163
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3807431033
Short name T1116
Test name
Test status
Simulation time 9101628385 ps
CPU time 11.96 seconds
Started May 16 03:19:26 PM PDT 24
Finished May 16 03:19:43 PM PDT 24
Peak memory 204884 kb
Host smart-431846b2-13c6-4372-92fc-6c9e171e35eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38074
31033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3807431033
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.139954926
Short name T544
Test name
Test status
Simulation time 8407983451 ps
CPU time 14.66 seconds
Started May 16 03:19:23 PM PDT 24
Finished May 16 03:19:42 PM PDT 24
Peak memory 204852 kb
Host smart-b6f35b1d-befa-4784-af94-1a02e4f81245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13995
4926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.139954926
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1613240384
Short name T161
Test name
Test status
Simulation time 8418660223 ps
CPU time 11.83 seconds
Started May 16 03:19:34 PM PDT 24
Finished May 16 03:19:50 PM PDT 24
Peak memory 204904 kb
Host smart-56bd9569-65a2-4bf1-b490-c175825e1f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16132
40384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1613240384
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3388662539
Short name T1147
Test name
Test status
Simulation time 8374736468 ps
CPU time 13.89 seconds
Started May 16 03:19:29 PM PDT 24
Finished May 16 03:19:48 PM PDT 24
Peak memory 204884 kb
Host smart-084bf8f1-5404-488f-bb6d-491efd1fa26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33886
62539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3388662539
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.709460913
Short name T960
Test name
Test status
Simulation time 8429472137 ps
CPU time 14.35 seconds
Started May 16 03:19:26 PM PDT 24
Finished May 16 03:19:46 PM PDT 24
Peak memory 204872 kb
Host smart-382967fb-128c-4b93-b4e2-85c4432add0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70946
0913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.709460913
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3768123402
Short name T302
Test name
Test status
Simulation time 8394174002 ps
CPU time 11.51 seconds
Started May 16 03:19:26 PM PDT 24
Finished May 16 03:19:43 PM PDT 24
Peak memory 204828 kb
Host smart-4d2d2488-f418-4114-b938-f7ba048e8c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37681
23402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3768123402
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1607674394
Short name T404
Test name
Test status
Simulation time 11558331150 ps
CPU time 13.81 seconds
Started May 16 03:19:28 PM PDT 24
Finished May 16 03:19:47 PM PDT 24
Peak memory 204792 kb
Host smart-135480c5-c796-446f-be79-82f34e78d4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16076
74394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1607674394
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.811141831
Short name T1257
Test name
Test status
Simulation time 8415597361 ps
CPU time 12.15 seconds
Started May 16 03:19:24 PM PDT 24
Finished May 16 03:19:41 PM PDT 24
Peak memory 204760 kb
Host smart-1c96786e-c643-4e17-8a82-9528757f6689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81114
1831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.811141831
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1504446754
Short name T1649
Test name
Test status
Simulation time 8390437383 ps
CPU time 10.97 seconds
Started May 16 03:19:27 PM PDT 24
Finished May 16 03:19:44 PM PDT 24
Peak memory 204796 kb
Host smart-febafcc1-c559-4c32-a385-a1b28808dc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15044
46754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1504446754
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3233153882
Short name T1072
Test name
Test status
Simulation time 8449048144 ps
CPU time 11.4 seconds
Started May 16 03:19:23 PM PDT 24
Finished May 16 03:19:38 PM PDT 24
Peak memory 204928 kb
Host smart-c5fea187-f77a-40a1-a59b-73932dca5ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
53882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3233153882
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.536984788
Short name T1426
Test name
Test status
Simulation time 8429418182 ps
CPU time 13.28 seconds
Started May 16 03:19:24 PM PDT 24
Finished May 16 03:19:42 PM PDT 24
Peak memory 204876 kb
Host smart-fb88f1b9-a515-4044-bb5f-c1c45e04942a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53698
4788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.536984788
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.806027823
Short name T1741
Test name
Test status
Simulation time 8413204429 ps
CPU time 12.31 seconds
Started May 16 03:19:27 PM PDT 24
Finished May 16 03:19:45 PM PDT 24
Peak memory 204904 kb
Host smart-8f2adf51-a133-415e-bb2c-e68b78d86cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80602
7823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.806027823
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1610675825
Short name T655
Test name
Test status
Simulation time 8409951758 ps
CPU time 13.61 seconds
Started May 16 03:19:27 PM PDT 24
Finished May 16 03:19:46 PM PDT 24
Peak memory 204756 kb
Host smart-5994a5ec-b696-4668-b8b2-bb3a4c039d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16106
75825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1610675825
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1366350380
Short name T570
Test name
Test status
Simulation time 8401972805 ps
CPU time 11.96 seconds
Started May 16 03:19:26 PM PDT 24
Finished May 16 03:19:44 PM PDT 24
Peak memory 204928 kb
Host smart-0f46e106-4e6b-4d23-9c1b-f14a09548e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13663
50380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1366350380
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.2995723378
Short name T1714
Test name
Test status
Simulation time 8409198239 ps
CPU time 11.2 seconds
Started May 16 03:19:25 PM PDT 24
Finished May 16 03:19:41 PM PDT 24
Peak memory 204728 kb
Host smart-42414a98-b195-4c48-9fc4-17e8010eea85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29957
23378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.2995723378
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2143930054
Short name T643
Test name
Test status
Simulation time 8367000442 ps
CPU time 11.91 seconds
Started May 16 03:19:23 PM PDT 24
Finished May 16 03:19:40 PM PDT 24
Peak memory 204832 kb
Host smart-305f13ee-67fe-4b71-a804-fc87e4520efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21439
30054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2143930054
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.211249814
Short name T617
Test name
Test status
Simulation time 8365824521 ps
CPU time 11.95 seconds
Started May 16 03:19:27 PM PDT 24
Finished May 16 03:19:44 PM PDT 24
Peak memory 204824 kb
Host smart-b9fef961-cea9-4158-8dea-f8c0465cd67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21124
9814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.211249814
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.2351342767
Short name T1447
Test name
Test status
Simulation time 28498322014 ps
CPU time 56.12 seconds
Started May 16 03:19:27 PM PDT 24
Finished May 16 03:20:29 PM PDT 24
Peak memory 204856 kb
Host smart-24fafa13-4023-408e-900f-2d0d3ba9aa42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23513
42767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.2351342767
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3523247324
Short name T1169
Test name
Test status
Simulation time 8405328705 ps
CPU time 11.23 seconds
Started May 16 03:19:26 PM PDT 24
Finished May 16 03:19:42 PM PDT 24
Peak memory 204828 kb
Host smart-a01987ad-bb70-48ce-8b0a-f58cddffc791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35232
47324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3523247324
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2098042987
Short name T77
Test name
Test status
Simulation time 8384258347 ps
CPU time 11.87 seconds
Started May 16 03:19:25 PM PDT 24
Finished May 16 03:19:42 PM PDT 24
Peak memory 204880 kb
Host smart-870aad6c-bc41-4d93-9332-22872bd0268a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20980
42987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2098042987
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.3805343602
Short name T316
Test name
Test status
Simulation time 8398568066 ps
CPU time 11.58 seconds
Started May 16 03:19:29 PM PDT 24
Finished May 16 03:19:46 PM PDT 24
Peak memory 204860 kb
Host smart-d7afd128-dcf8-4ce6-9756-0e2bff933fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38053
43602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.3805343602
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2513157086
Short name T1766
Test name
Test status
Simulation time 8372149223 ps
CPU time 11.3 seconds
Started May 16 03:19:29 PM PDT 24
Finished May 16 03:19:46 PM PDT 24
Peak memory 204836 kb
Host smart-d18fd49e-c042-48d3-89c6-82f65b55ca78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25131
57086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2513157086
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3532870959
Short name T63
Test name
Test status
Simulation time 1307120956 ps
CPU time 2.09 seconds
Started May 16 03:19:33 PM PDT 24
Finished May 16 03:19:40 PM PDT 24
Peak memory 221568 kb
Host smart-7d0c069c-f4ac-418e-b549-2d85bc94a2d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3532870959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3532870959
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.109987651
Short name T1119
Test name
Test status
Simulation time 8377658932 ps
CPU time 11.65 seconds
Started May 16 03:19:26 PM PDT 24
Finished May 16 03:19:44 PM PDT 24
Peak memory 204752 kb
Host smart-3843919d-2969-4b47-be2e-90c880afa5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10998
7651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.109987651
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2836154812
Short name T1154
Test name
Test status
Simulation time 8370370696 ps
CPU time 12.39 seconds
Started May 16 03:19:25 PM PDT 24
Finished May 16 03:19:43 PM PDT 24
Peak memory 204852 kb
Host smart-aeee4cac-849d-4282-a15c-7c8005b7bc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28361
54812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2836154812
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3200421256
Short name T1123
Test name
Test status
Simulation time 8531398808 ps
CPU time 11.26 seconds
Started May 16 03:19:27 PM PDT 24
Finished May 16 03:19:44 PM PDT 24
Peak memory 204880 kb
Host smart-0fa98614-9061-4953-a79f-c8b23d138d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32004
21256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3200421256
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3668204662
Short name T1492
Test name
Test status
Simulation time 8411304454 ps
CPU time 11.76 seconds
Started May 16 03:19:24 PM PDT 24
Finished May 16 03:19:40 PM PDT 24
Peak memory 204876 kb
Host smart-a3136706-97cd-444a-8e2d-d75fee990abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36682
04662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3668204662
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2966057562
Short name T1255
Test name
Test status
Simulation time 8392974807 ps
CPU time 11.94 seconds
Started May 16 03:19:24 PM PDT 24
Finished May 16 03:19:41 PM PDT 24
Peak memory 204700 kb
Host smart-702c2a9a-abde-4bf4-b9af-9bf041dabe02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29660
57562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2966057562
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.3939049285
Short name T1024
Test name
Test status
Simulation time 8470114175 ps
CPU time 11.61 seconds
Started May 16 03:24:26 PM PDT 24
Finished May 16 03:24:49 PM PDT 24
Peak memory 204888 kb
Host smart-85f3e954-6b14-4fb9-80f2-4b71ddedadbf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3939049285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.3939049285
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.1577584862
Short name T150
Test name
Test status
Simulation time 8393076079 ps
CPU time 10.84 seconds
Started May 16 03:24:25 PM PDT 24
Finished May 16 03:24:47 PM PDT 24
Peak memory 204912 kb
Host smart-f65e721e-c007-4115-89a2-98dd2c9adbaa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1577584862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.1577584862
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.1641933126
Short name T1350
Test name
Test status
Simulation time 8386561468 ps
CPU time 10.9 seconds
Started May 16 03:24:27 PM PDT 24
Finished May 16 03:24:50 PM PDT 24
Peak memory 204916 kb
Host smart-a5e3cc1d-2a4a-4d58-9612-ac7656c54bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16419
33126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.1641933126
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1485991083
Short name T1527
Test name
Test status
Simulation time 8395963681 ps
CPU time 11.02 seconds
Started May 16 03:24:20 PM PDT 24
Finished May 16 03:24:45 PM PDT 24
Peak memory 204792 kb
Host smart-86e8747f-f228-474f-9371-6b3b8bea4fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14859
91083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1485991083
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2316395707
Short name T1038
Test name
Test status
Simulation time 8970500624 ps
CPU time 14.45 seconds
Started May 16 03:24:16 PM PDT 24
Finished May 16 03:24:44 PM PDT 24
Peak memory 204832 kb
Host smart-5705e1d2-8d0e-48d9-a537-895befdb73d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
95707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2316395707
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2090213829
Short name T839
Test name
Test status
Simulation time 8371160587 ps
CPU time 12.87 seconds
Started May 16 03:24:25 PM PDT 24
Finished May 16 03:24:49 PM PDT 24
Peak memory 204824 kb
Host smart-50f86886-b17d-432d-8ea4-a1853559ba8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20902
13829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2090213829
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.479320008
Short name T1162
Test name
Test status
Simulation time 8376981598 ps
CPU time 11.56 seconds
Started May 16 03:24:17 PM PDT 24
Finished May 16 03:24:42 PM PDT 24
Peak memory 204872 kb
Host smart-42deab37-ad39-4871-8f7f-f1a4372977b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47932
0008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.479320008
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3114813181
Short name T1467
Test name
Test status
Simulation time 8999004300 ps
CPU time 14.03 seconds
Started May 16 03:24:24 PM PDT 24
Finished May 16 03:24:50 PM PDT 24
Peak memory 204884 kb
Host smart-53ac6eeb-86d5-4469-8de6-395d93fa2c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31148
13181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3114813181
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1960256525
Short name T946
Test name
Test status
Simulation time 8423172001 ps
CPU time 11.98 seconds
Started May 16 03:24:18 PM PDT 24
Finished May 16 03:24:43 PM PDT 24
Peak memory 204856 kb
Host smart-43c4b863-c8dc-4685-959f-e14adb75eb5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19602
56525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1960256525
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.763338362
Short name T618
Test name
Test status
Simulation time 8436388074 ps
CPU time 11.39 seconds
Started May 16 03:24:28 PM PDT 24
Finished May 16 03:24:52 PM PDT 24
Peak memory 204896 kb
Host smart-948c765d-2e74-457b-9903-b6658accd387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76333
8362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.763338362
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1506542914
Short name T573
Test name
Test status
Simulation time 8396316643 ps
CPU time 11.14 seconds
Started May 16 03:24:27 PM PDT 24
Finished May 16 03:24:51 PM PDT 24
Peak memory 204812 kb
Host smart-417eef29-1031-42f0-9d52-f068a09ef73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15065
42914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1506542914
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2484696118
Short name T1463
Test name
Test status
Simulation time 8451874346 ps
CPU time 11.22 seconds
Started May 16 03:24:17 PM PDT 24
Finished May 16 03:24:42 PM PDT 24
Peak memory 204896 kb
Host smart-84a26656-67ff-49e1-b57d-b42087aab15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24846
96118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2484696118
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1512564505
Short name T767
Test name
Test status
Simulation time 8419165546 ps
CPU time 11.5 seconds
Started May 16 03:24:17 PM PDT 24
Finished May 16 03:24:42 PM PDT 24
Peak memory 204832 kb
Host smart-d2b4d037-52b1-469a-b6c3-0f670da14a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15125
64505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1512564505
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3747448601
Short name T811
Test name
Test status
Simulation time 11528032240 ps
CPU time 14.28 seconds
Started May 16 03:24:18 PM PDT 24
Finished May 16 03:24:46 PM PDT 24
Peak memory 204804 kb
Host smart-fe7b3abf-f32c-4c12-852c-6f29992cac10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37474
48601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3747448601
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3995114687
Short name T1070
Test name
Test status
Simulation time 8397232184 ps
CPU time 12.13 seconds
Started May 16 03:24:18 PM PDT 24
Finished May 16 03:24:43 PM PDT 24
Peak memory 204788 kb
Host smart-bd6272a9-aef3-468f-b868-639d52c0f2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39951
14687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3995114687
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3350810220
Short name T391
Test name
Test status
Simulation time 8413668189 ps
CPU time 11.04 seconds
Started May 16 03:24:20 PM PDT 24
Finished May 16 03:24:45 PM PDT 24
Peak memory 204816 kb
Host smart-06b0339e-7db1-43ab-bfb9-16e821f3736c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33508
10220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3350810220
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.4099478929
Short name T431
Test name
Test status
Simulation time 8424765729 ps
CPU time 11.49 seconds
Started May 16 03:24:16 PM PDT 24
Finished May 16 03:24:41 PM PDT 24
Peak memory 204704 kb
Host smart-52ed0511-32b4-40ef-adc0-55cdb1ccb39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40994
78929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.4099478929
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.562709779
Short name T1609
Test name
Test status
Simulation time 8405326011 ps
CPU time 12.25 seconds
Started May 16 03:24:18 PM PDT 24
Finished May 16 03:24:43 PM PDT 24
Peak memory 204760 kb
Host smart-5faba231-926e-49e9-946f-2de426f2b5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56270
9779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.562709779
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.2219419553
Short name T60
Test name
Test status
Simulation time 8398607138 ps
CPU time 12.33 seconds
Started May 16 03:24:29 PM PDT 24
Finished May 16 03:24:53 PM PDT 24
Peak memory 204896 kb
Host smart-8213e6c3-c2b0-4924-8887-cfc79e22105f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22194
19553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.2219419553
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.3381609393
Short name T1443
Test name
Test status
Simulation time 8375659130 ps
CPU time 11.57 seconds
Started May 16 03:24:26 PM PDT 24
Finished May 16 03:24:49 PM PDT 24
Peak memory 204828 kb
Host smart-61149728-a426-475e-a199-577ba2a90ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33816
09393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.3381609393
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1430254925
Short name T646
Test name
Test status
Simulation time 8368342399 ps
CPU time 11.31 seconds
Started May 16 03:24:26 PM PDT 24
Finished May 16 03:24:49 PM PDT 24
Peak memory 204820 kb
Host smart-270ac4ee-3aad-4bc7-a66b-fb4762b44448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14302
54925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1430254925
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1741450872
Short name T1650
Test name
Test status
Simulation time 8379327294 ps
CPU time 10.64 seconds
Started May 16 03:24:25 PM PDT 24
Finished May 16 03:24:48 PM PDT 24
Peak memory 204692 kb
Host smart-86bc124e-be57-4980-a603-de091d585e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17414
50872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1741450872
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2265048000
Short name T16
Test name
Test status
Simulation time 25191373169 ps
CPU time 50.37 seconds
Started May 16 03:24:24 PM PDT 24
Finished May 16 03:25:26 PM PDT 24
Peak memory 204876 kb
Host smart-9372c918-2924-4e91-b2c7-69aa755b9aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22650
48000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2265048000
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1355285893
Short name T406
Test name
Test status
Simulation time 8406779425 ps
CPU time 11.42 seconds
Started May 16 03:24:18 PM PDT 24
Finished May 16 03:24:42 PM PDT 24
Peak memory 204808 kb
Host smart-8657e90c-594e-4d17-9ee1-98c95516474a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13552
85893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1355285893
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.708181668
Short name T160
Test name
Test status
Simulation time 8443775054 ps
CPU time 11.4 seconds
Started May 16 03:24:25 PM PDT 24
Finished May 16 03:24:48 PM PDT 24
Peak memory 204840 kb
Host smart-9e5d995d-faf6-4aed-91c1-efd5f8b2610e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70818
1668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.708181668
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.239184870
Short name T672
Test name
Test status
Simulation time 8411628502 ps
CPU time 10.95 seconds
Started May 16 03:24:28 PM PDT 24
Finished May 16 03:24:51 PM PDT 24
Peak memory 204836 kb
Host smart-497622e5-15da-48a9-8ecf-41b2c040a389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23918
4870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.239184870
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.4090176218
Short name T1550
Test name
Test status
Simulation time 8375664720 ps
CPU time 11.34 seconds
Started May 16 03:24:31 PM PDT 24
Finished May 16 03:24:54 PM PDT 24
Peak memory 204784 kb
Host smart-069891e3-5638-42d8-855e-57593c426421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40901
76218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.4090176218
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.602374016
Short name T656
Test name
Test status
Simulation time 8407696488 ps
CPU time 10.71 seconds
Started May 16 03:24:26 PM PDT 24
Finished May 16 03:24:48 PM PDT 24
Peak memory 204952 kb
Host smart-c9cf1f31-8eed-4cd8-9d85-498f26ac2d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60237
4016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.602374016
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1780189518
Short name T105
Test name
Test status
Simulation time 8403483446 ps
CPU time 10.76 seconds
Started May 16 03:24:26 PM PDT 24
Finished May 16 03:24:48 PM PDT 24
Peak memory 204836 kb
Host smart-57d419cf-5d21-450c-832d-2fc0e9423c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17801
89518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1780189518
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3545013579
Short name T187
Test name
Test status
Simulation time 8431251259 ps
CPU time 12.21 seconds
Started May 16 03:24:17 PM PDT 24
Finished May 16 03:24:42 PM PDT 24
Peak memory 204832 kb
Host smart-6cf764a5-1efa-483d-8b5f-bd5904adceba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35450
13579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3545013579
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2988644108
Short name T327
Test name
Test status
Simulation time 8381940852 ps
CPU time 11.06 seconds
Started May 16 03:24:25 PM PDT 24
Finished May 16 03:24:48 PM PDT 24
Peak memory 204836 kb
Host smart-1dcd5b69-1dac-4e12-bc7d-406ee8b7c8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29886
44108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2988644108
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.4048049286
Short name T1571
Test name
Test status
Simulation time 8412659774 ps
CPU time 13.2 seconds
Started May 16 03:24:27 PM PDT 24
Finished May 16 03:24:53 PM PDT 24
Peak memory 204888 kb
Host smart-fa0efc23-aea6-40ad-9a08-6919591fb585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40480
49286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.4048049286
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.2353546926
Short name T379
Test name
Test status
Simulation time 8463134042 ps
CPU time 11.24 seconds
Started May 16 03:24:37 PM PDT 24
Finished May 16 03:24:59 PM PDT 24
Peak memory 204884 kb
Host smart-90c4c9a2-765f-4ed1-8a2a-ebff2744fb1c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2353546926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.2353546926
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.3654806503
Short name T313
Test name
Test status
Simulation time 8385230595 ps
CPU time 11.41 seconds
Started May 16 03:24:35 PM PDT 24
Finished May 16 03:24:58 PM PDT 24
Peak memory 204844 kb
Host smart-f04cd603-77ed-476e-9935-6c0e47708a9e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3654806503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.3654806503
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.1651757747
Short name T898
Test name
Test status
Simulation time 8435460046 ps
CPU time 13.58 seconds
Started May 16 03:24:34 PM PDT 24
Finished May 16 03:24:59 PM PDT 24
Peak memory 204824 kb
Host smart-49f99f96-3320-41c8-a535-c89640f0d725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16517
57747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.1651757747
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1122724842
Short name T513
Test name
Test status
Simulation time 8408209614 ps
CPU time 11.62 seconds
Started May 16 03:24:26 PM PDT 24
Finished May 16 03:24:49 PM PDT 24
Peak memory 204892 kb
Host smart-ca3b2291-572a-456c-a216-a64a9bc5fe3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11227
24842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1122724842
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.833401775
Short name T215
Test name
Test status
Simulation time 8908977498 ps
CPU time 14.3 seconds
Started May 16 03:24:28 PM PDT 24
Finished May 16 03:24:55 PM PDT 24
Peak memory 204880 kb
Host smart-f8c2d031-7c7c-404c-82dc-8d26cac29bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83340
1775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.833401775
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.384340555
Short name T11
Test name
Test status
Simulation time 8403971236 ps
CPU time 10.69 seconds
Started May 16 03:24:26 PM PDT 24
Finished May 16 03:24:48 PM PDT 24
Peak memory 204832 kb
Host smart-7e73a466-64ea-4376-8fd9-60dbf2e69b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38434
0555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.384340555
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2901208198
Short name T717
Test name
Test status
Simulation time 8401711452 ps
CPU time 11.52 seconds
Started May 16 03:24:26 PM PDT 24
Finished May 16 03:24:49 PM PDT 24
Peak memory 204844 kb
Host smart-a7e7834a-5afa-4a04-93ed-96f010b7378b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29012
08198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2901208198
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.82811443
Short name T1140
Test name
Test status
Simulation time 9107670141 ps
CPU time 13 seconds
Started May 16 03:24:31 PM PDT 24
Finished May 16 03:24:56 PM PDT 24
Peak memory 204808 kb
Host smart-4651ae29-da6d-4577-aea7-c38e21103863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82811
443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.82811443
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3279197656
Short name T113
Test name
Test status
Simulation time 8411017413 ps
CPU time 12.93 seconds
Started May 16 03:24:27 PM PDT 24
Finished May 16 03:24:52 PM PDT 24
Peak memory 204852 kb
Host smart-32da8b72-debd-4adc-80c1-4e0586c6fa07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32791
97656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3279197656
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1417139498
Short name T1594
Test name
Test status
Simulation time 8456765124 ps
CPU time 13.33 seconds
Started May 16 03:24:36 PM PDT 24
Finished May 16 03:25:01 PM PDT 24
Peak memory 204872 kb
Host smart-ff1183e7-e5ff-48f7-8419-ecdbc7043e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14171
39498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1417139498
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1630952225
Short name T1428
Test name
Test status
Simulation time 8388241299 ps
CPU time 11.81 seconds
Started May 16 03:24:35 PM PDT 24
Finished May 16 03:24:59 PM PDT 24
Peak memory 204840 kb
Host smart-c59eee31-31c4-4738-9ade-d325d62e7a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16309
52225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1630952225
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2744746998
Short name T1549
Test name
Test status
Simulation time 8489916398 ps
CPU time 12.03 seconds
Started May 16 03:24:26 PM PDT 24
Finished May 16 03:24:49 PM PDT 24
Peak memory 204876 kb
Host smart-ce6cdae8-3e02-41e2-b62e-6cd210acbb9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27447
46998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2744746998
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.812765888
Short name T910
Test name
Test status
Simulation time 8393225923 ps
CPU time 11.67 seconds
Started May 16 03:24:29 PM PDT 24
Finished May 16 03:24:52 PM PDT 24
Peak memory 204840 kb
Host smart-c48cdd52-9d64-4461-bf18-6ac8e4263605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81276
5888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.812765888
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1840597446
Short name T715
Test name
Test status
Simulation time 11500346664 ps
CPU time 14.67 seconds
Started May 16 03:24:27 PM PDT 24
Finished May 16 03:24:54 PM PDT 24
Peak memory 204804 kb
Host smart-2b73d3fd-e84d-47be-97f3-5d20b69eab6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18405
97446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1840597446
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3831250342
Short name T351
Test name
Test status
Simulation time 8428299568 ps
CPU time 10.65 seconds
Started May 16 03:24:26 PM PDT 24
Finished May 16 03:24:48 PM PDT 24
Peak memory 204792 kb
Host smart-98e329be-abad-4660-894c-9c89963de273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38312
50342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3831250342
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2874270851
Short name T1079
Test name
Test status
Simulation time 8374901385 ps
CPU time 11.59 seconds
Started May 16 03:24:27 PM PDT 24
Finished May 16 03:24:51 PM PDT 24
Peak memory 204836 kb
Host smart-b81fb19d-6b2c-4fdc-8081-4b8986afdc55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28742
70851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2874270851
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1758115740
Short name T1701
Test name
Test status
Simulation time 8433920159 ps
CPU time 12.2 seconds
Started May 16 03:24:36 PM PDT 24
Finished May 16 03:25:00 PM PDT 24
Peak memory 204872 kb
Host smart-ed4be3b2-5eb2-4ccc-9556-e9eb700ebbf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17581
15740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1758115740
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1623866568
Short name T546
Test name
Test status
Simulation time 8423198345 ps
CPU time 13.04 seconds
Started May 16 03:24:33 PM PDT 24
Finished May 16 03:24:56 PM PDT 24
Peak memory 204816 kb
Host smart-78a6ed1e-6040-4251-bb83-f9fb1889c28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16238
66568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1623866568
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.4127706875
Short name T382
Test name
Test status
Simulation time 8402120257 ps
CPU time 10.94 seconds
Started May 16 03:24:35 PM PDT 24
Finished May 16 03:24:58 PM PDT 24
Peak memory 204808 kb
Host smart-5c5143d0-5af0-485d-8e71-d5921aea0c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41277
06875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.4127706875
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1258145746
Short name T1520
Test name
Test status
Simulation time 8396280563 ps
CPU time 12.09 seconds
Started May 16 03:24:37 PM PDT 24
Finished May 16 03:25:01 PM PDT 24
Peak memory 204872 kb
Host smart-5ef6e3c2-da97-4c20-ad77-9bf8b000e920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12581
45746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1258145746
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3306807285
Short name T778
Test name
Test status
Simulation time 8377416480 ps
CPU time 11.44 seconds
Started May 16 03:24:37 PM PDT 24
Finished May 16 03:25:00 PM PDT 24
Peak memory 204912 kb
Host smart-6890cd06-1ea3-40e6-8009-0bf69f25f569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33068
07285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3306807285
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.867158303
Short name T410
Test name
Test status
Simulation time 8402378147 ps
CPU time 13.4 seconds
Started May 16 03:24:37 PM PDT 24
Finished May 16 03:25:02 PM PDT 24
Peak memory 204792 kb
Host smart-14089df4-f20c-4723-99d5-8cccb9f7b674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86715
8303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.867158303
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2597070306
Short name T750
Test name
Test status
Simulation time 8370983835 ps
CPU time 11.1 seconds
Started May 16 03:24:34 PM PDT 24
Finished May 16 03:24:57 PM PDT 24
Peak memory 204776 kb
Host smart-f7036a05-aa87-46ab-bbd2-8c65c3f450a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25970
70306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2597070306
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.1866988376
Short name T1451
Test name
Test status
Simulation time 8368106983 ps
CPU time 11.34 seconds
Started May 16 03:24:37 PM PDT 24
Finished May 16 03:24:59 PM PDT 24
Peak memory 204776 kb
Host smart-aa92b271-0c8d-447b-a071-fec2f86f911e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18669
88376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.1866988376
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1049254650
Short name T718
Test name
Test status
Simulation time 23862314839 ps
CPU time 48.26 seconds
Started May 16 03:24:34 PM PDT 24
Finished May 16 03:25:34 PM PDT 24
Peak memory 204932 kb
Host smart-6b2e1e0c-2e33-4499-a37e-dd8702a3bf1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10492
54650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1049254650
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.4132389456
Short name T698
Test name
Test status
Simulation time 8400789308 ps
CPU time 10.96 seconds
Started May 16 03:24:34 PM PDT 24
Finished May 16 03:24:56 PM PDT 24
Peak memory 204868 kb
Host smart-e97ad8bb-707c-447e-94d6-0889ea6dd91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41323
89456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.4132389456
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3979756929
Short name T745
Test name
Test status
Simulation time 8412581844 ps
CPU time 11.74 seconds
Started May 16 03:24:35 PM PDT 24
Finished May 16 03:24:58 PM PDT 24
Peak memory 204836 kb
Host smart-d6c8cf85-bcd6-41f5-8605-a4b5eab039e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39797
56929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3979756929
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2616063372
Short name T1374
Test name
Test status
Simulation time 8394993011 ps
CPU time 11.14 seconds
Started May 16 03:24:37 PM PDT 24
Finished May 16 03:24:59 PM PDT 24
Peak memory 204848 kb
Host smart-cdcfacdc-3a33-4aca-a387-11f966a4fbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26160
63372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2616063372
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1625565982
Short name T332
Test name
Test status
Simulation time 8359443929 ps
CPU time 12.23 seconds
Started May 16 03:24:36 PM PDT 24
Finished May 16 03:25:00 PM PDT 24
Peak memory 204680 kb
Host smart-2e92aaec-e36f-430c-91d4-ef6024f5a996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16255
65982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1625565982
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2392493898
Short name T1482
Test name
Test status
Simulation time 8383506571 ps
CPU time 12.32 seconds
Started May 16 03:24:37 PM PDT 24
Finished May 16 03:25:01 PM PDT 24
Peak memory 204856 kb
Host smart-0e250d13-86de-4928-a9ee-175ff8f62967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23924
93898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2392493898
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.36281863
Short name T1596
Test name
Test status
Simulation time 8369916226 ps
CPU time 11.64 seconds
Started May 16 03:24:33 PM PDT 24
Finished May 16 03:24:55 PM PDT 24
Peak memory 204760 kb
Host smart-c33533dd-4af2-4b77-aff7-f340cb330db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36281
863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.36281863
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2159161612
Short name T682
Test name
Test status
Simulation time 8472283396 ps
CPU time 11.33 seconds
Started May 16 03:24:27 PM PDT 24
Finished May 16 03:24:51 PM PDT 24
Peak memory 204896 kb
Host smart-0a1951eb-f415-4b1f-90d8-9555adb26db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21591
61612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2159161612
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1104129602
Short name T1456
Test name
Test status
Simulation time 8382834116 ps
CPU time 13.33 seconds
Started May 16 03:24:35 PM PDT 24
Finished May 16 03:25:00 PM PDT 24
Peak memory 204844 kb
Host smart-a87d93aa-af94-4e36-89a2-dd25936b1300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11041
29602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1104129602
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3013466998
Short name T1032
Test name
Test status
Simulation time 8466991587 ps
CPU time 10.51 seconds
Started May 16 03:24:33 PM PDT 24
Finished May 16 03:24:54 PM PDT 24
Peak memory 204776 kb
Host smart-da57b49a-8b74-4db9-aa70-e759107013e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30134
66998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3013466998
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.1533917913
Short name T1556
Test name
Test status
Simulation time 8464575810 ps
CPU time 11.05 seconds
Started May 16 03:24:43 PM PDT 24
Finished May 16 03:25:05 PM PDT 24
Peak memory 204772 kb
Host smart-00a7f322-a7a2-4058-beb6-8fea79be56c0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1533917913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.1533917913
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.2243587878
Short name T1739
Test name
Test status
Simulation time 8383428089 ps
CPU time 12.22 seconds
Started May 16 03:24:44 PM PDT 24
Finished May 16 03:25:07 PM PDT 24
Peak memory 204888 kb
Host smart-708729f9-5279-493d-af53-8ad34bc4b560
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2243587878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.2243587878
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.2439934690
Short name T1630
Test name
Test status
Simulation time 8411015873 ps
CPU time 15.07 seconds
Started May 16 03:24:42 PM PDT 24
Finished May 16 03:25:08 PM PDT 24
Peak memory 204768 kb
Host smart-d5111e08-b8f9-4655-b265-a1a60b38bfe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24399
34690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.2439934690
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1493134661
Short name T402
Test name
Test status
Simulation time 8375188549 ps
CPU time 11.13 seconds
Started May 16 03:24:46 PM PDT 24
Finished May 16 03:25:07 PM PDT 24
Peak memory 204860 kb
Host smart-149c9051-8862-42d3-b775-164574b978d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14931
34661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1493134661
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.1262718659
Short name T687
Test name
Test status
Simulation time 8374041585 ps
CPU time 12.18 seconds
Started May 16 03:24:40 PM PDT 24
Finished May 16 03:25:02 PM PDT 24
Peak memory 204840 kb
Host smart-d134388b-27df-4422-bc2b-7082d0c1c80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12627
18659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.1262718659
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1208266123
Short name T207
Test name
Test status
Simulation time 8949534103 ps
CPU time 13.22 seconds
Started May 16 03:24:43 PM PDT 24
Finished May 16 03:25:06 PM PDT 24
Peak memory 204828 kb
Host smart-5b079cb6-e6a3-4040-83cc-b74b6ad4e2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12082
66123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1208266123
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1296367603
Short name T1606
Test name
Test status
Simulation time 8372375629 ps
CPU time 11.55 seconds
Started May 16 03:24:45 PM PDT 24
Finished May 16 03:25:07 PM PDT 24
Peak memory 204792 kb
Host smart-2c7b6b95-3ad8-498f-8ff1-da59c87648a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12963
67603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1296367603
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1052017167
Short name T317
Test name
Test status
Simulation time 8401175760 ps
CPU time 11.32 seconds
Started May 16 03:24:43 PM PDT 24
Finished May 16 03:25:04 PM PDT 24
Peak memory 204900 kb
Host smart-f717b6f3-f56e-4cf9-b676-a81777eff1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10520
17167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1052017167
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3979153309
Short name T1635
Test name
Test status
Simulation time 9107802000 ps
CPU time 12.54 seconds
Started May 16 03:24:45 PM PDT 24
Finished May 16 03:25:07 PM PDT 24
Peak memory 204864 kb
Host smart-816930cd-9784-40f5-b12c-30489e121e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39791
53309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3979153309
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.867448695
Short name T1753
Test name
Test status
Simulation time 8395836735 ps
CPU time 13.9 seconds
Started May 16 03:24:45 PM PDT 24
Finished May 16 03:25:09 PM PDT 24
Peak memory 204792 kb
Host smart-234a5bff-599b-43a9-aa78-8ecd484c62bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86744
8695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.867448695
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3704137054
Short name T847
Test name
Test status
Simulation time 8373496939 ps
CPU time 12.39 seconds
Started May 16 03:24:45 PM PDT 24
Finished May 16 03:25:08 PM PDT 24
Peak memory 204864 kb
Host smart-edd82d8e-8e09-4192-bf7e-238264e5b724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37041
37054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3704137054
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1932531903
Short name T732
Test name
Test status
Simulation time 8399903318 ps
CPU time 10.97 seconds
Started May 16 03:24:42 PM PDT 24
Finished May 16 03:25:03 PM PDT 24
Peak memory 204904 kb
Host smart-a1a83db5-a84f-4640-b18f-2ed6c1cfbc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19325
31903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1932531903
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.1207980972
Short name T1373
Test name
Test status
Simulation time 8412783476 ps
CPU time 11.39 seconds
Started May 16 03:24:43 PM PDT 24
Finished May 16 03:25:05 PM PDT 24
Peak memory 204892 kb
Host smart-77520aae-4210-4303-a86e-9479f0b80ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12079
80972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1207980972
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1183993530
Short name T728
Test name
Test status
Simulation time 11569357891 ps
CPU time 15.01 seconds
Started May 16 03:24:41 PM PDT 24
Finished May 16 03:25:07 PM PDT 24
Peak memory 204848 kb
Host smart-b35a6e43-71eb-487a-af0b-57847df65cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11839
93530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1183993530
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2554202914
Short name T1561
Test name
Test status
Simulation time 8491417445 ps
CPU time 10.67 seconds
Started May 16 03:24:46 PM PDT 24
Finished May 16 03:25:07 PM PDT 24
Peak memory 204828 kb
Host smart-28e6cce6-1488-43bc-9954-365caae86cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25542
02914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2554202914
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.654013512
Short name T412
Test name
Test status
Simulation time 8393385716 ps
CPU time 12.93 seconds
Started May 16 03:24:41 PM PDT 24
Finished May 16 03:25:04 PM PDT 24
Peak memory 204796 kb
Host smart-305ca7b7-3761-4824-b2ef-fa54f3a520ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65401
3512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.654013512
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2034599671
Short name T1538
Test name
Test status
Simulation time 8459044794 ps
CPU time 13.1 seconds
Started May 16 03:24:42 PM PDT 24
Finished May 16 03:25:05 PM PDT 24
Peak memory 204892 kb
Host smart-5d847dd1-bf03-4b47-b082-723611a50f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20345
99671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2034599671
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.3069036959
Short name T324
Test name
Test status
Simulation time 8411194435 ps
CPU time 10.79 seconds
Started May 16 03:24:40 PM PDT 24
Finished May 16 03:25:01 PM PDT 24
Peak memory 204816 kb
Host smart-15e6a8f9-36a3-4cf4-a9d2-06312a2dc37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30690
36959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.3069036959
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1591104503
Short name T1327
Test name
Test status
Simulation time 8418732224 ps
CPU time 11.94 seconds
Started May 16 03:24:45 PM PDT 24
Finished May 16 03:25:07 PM PDT 24
Peak memory 204884 kb
Host smart-29c158a2-c805-4495-95cb-e8f02db22382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15911
04503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1591104503
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.773296895
Short name T97
Test name
Test status
Simulation time 8395492593 ps
CPU time 11.14 seconds
Started May 16 03:24:43 PM PDT 24
Finished May 16 03:25:04 PM PDT 24
Peak memory 204772 kb
Host smart-6f60d0df-dd1a-4b85-81d9-29edb3543fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77329
6895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.773296895
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.987211467
Short name T227
Test name
Test status
Simulation time 8437920653 ps
CPU time 11.42 seconds
Started May 16 03:24:44 PM PDT 24
Finished May 16 03:25:05 PM PDT 24
Peak memory 204824 kb
Host smart-f6490980-90ad-4ff8-a970-ca6c4ee70f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98721
1467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.987211467
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.611753609
Short name T1619
Test name
Test status
Simulation time 8373810952 ps
CPU time 11.17 seconds
Started May 16 03:24:41 PM PDT 24
Finished May 16 03:25:02 PM PDT 24
Peak memory 204848 kb
Host smart-06216ec7-375c-45ec-a6bb-a9855541025e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61175
3609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.611753609
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2702778428
Short name T885
Test name
Test status
Simulation time 8362460602 ps
CPU time 11.03 seconds
Started May 16 03:24:46 PM PDT 24
Finished May 16 03:25:07 PM PDT 24
Peak memory 204772 kb
Host smart-1b53928e-0f5e-477c-a88d-b09437bb55d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27027
78428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2702778428
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.236752144
Short name T1320
Test name
Test status
Simulation time 8396778728 ps
CPU time 11.11 seconds
Started May 16 03:24:42 PM PDT 24
Finished May 16 03:25:03 PM PDT 24
Peak memory 204744 kb
Host smart-f2886f2a-e4ca-40da-9677-93d98661f120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
2144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.236752144
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2963173819
Short name T1143
Test name
Test status
Simulation time 8443109794 ps
CPU time 12.71 seconds
Started May 16 03:24:43 PM PDT 24
Finished May 16 03:25:06 PM PDT 24
Peak memory 204904 kb
Host smart-a1c8ad41-7cbe-4b1d-9229-f1a609e48a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29631
73819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2963173819
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.379196053
Short name T1031
Test name
Test status
Simulation time 8400264644 ps
CPU time 12.36 seconds
Started May 16 03:24:46 PM PDT 24
Finished May 16 03:25:08 PM PDT 24
Peak memory 204816 kb
Host smart-30795d11-187c-4ea7-bc8c-ce931d49a308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37919
6053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.379196053
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1235934466
Short name T481
Test name
Test status
Simulation time 8364432959 ps
CPU time 11.2 seconds
Started May 16 03:24:41 PM PDT 24
Finished May 16 03:25:02 PM PDT 24
Peak memory 204876 kb
Host smart-9ed3b422-35b2-4edc-86d1-bc494f2863ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12359
34466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1235934466
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1475043456
Short name T550
Test name
Test status
Simulation time 8383788962 ps
CPU time 11.29 seconds
Started May 16 03:24:42 PM PDT 24
Finished May 16 03:25:04 PM PDT 24
Peak memory 204816 kb
Host smart-3d3cf31b-4e64-47b9-91d0-3a73552428d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14750
43456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1475043456
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1126615118
Short name T1429
Test name
Test status
Simulation time 8370033161 ps
CPU time 11.56 seconds
Started May 16 03:24:46 PM PDT 24
Finished May 16 03:25:08 PM PDT 24
Peak memory 204816 kb
Host smart-93f52afb-9045-463a-a6c1-af9434052b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11266
15118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1126615118
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1947593465
Short name T1580
Test name
Test status
Simulation time 8432849738 ps
CPU time 12.06 seconds
Started May 16 03:24:42 PM PDT 24
Finished May 16 03:25:04 PM PDT 24
Peak memory 204872 kb
Host smart-dd31407a-e1ac-4925-8821-69ce7a6de92e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19475
93465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1947593465
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3445670399
Short name T1135
Test name
Test status
Simulation time 8426664629 ps
CPU time 12.64 seconds
Started May 16 03:24:44 PM PDT 24
Finished May 16 03:25:06 PM PDT 24
Peak memory 204912 kb
Host smart-504a3f7a-eace-4019-b524-d1c36bf2c24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34456
70399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3445670399
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3941451853
Short name T417
Test name
Test status
Simulation time 8435490339 ps
CPU time 13.34 seconds
Started May 16 03:24:41 PM PDT 24
Finished May 16 03:25:04 PM PDT 24
Peak memory 204884 kb
Host smart-d0d05903-d9c0-4fd2-95de-8f3119b4e088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39414
51853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3941451853
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.150364396
Short name T762
Test name
Test status
Simulation time 8465349148 ps
CPU time 10.96 seconds
Started May 16 03:24:55 PM PDT 24
Finished May 16 03:25:14 PM PDT 24
Peak memory 204876 kb
Host smart-bfd0f172-e9d8-42c8-a4b4-e4e963d1dfae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=150364396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.150364396
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.3689943408
Short name T506
Test name
Test status
Simulation time 8402406089 ps
CPU time 11.04 seconds
Started May 16 03:24:53 PM PDT 24
Finished May 16 03:25:12 PM PDT 24
Peak memory 204856 kb
Host smart-25c6632d-90f7-44e4-b11f-0ae5c2e81759
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3689943408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.3689943408
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.614855192
Short name T848
Test name
Test status
Simulation time 8412551052 ps
CPU time 12.44 seconds
Started May 16 03:24:53 PM PDT 24
Finished May 16 03:25:14 PM PDT 24
Peak memory 204868 kb
Host smart-851bebf1-b388-4644-bf0d-f15b4f6b2964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61485
5192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.614855192
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1837850511
Short name T1026
Test name
Test status
Simulation time 8379377778 ps
CPU time 11.65 seconds
Started May 16 03:24:46 PM PDT 24
Finished May 16 03:25:07 PM PDT 24
Peak memory 204884 kb
Host smart-79681e5d-f654-4ec5-9715-21d5c31707be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18378
50511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1837850511
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2334549498
Short name T882
Test name
Test status
Simulation time 8367885475 ps
CPU time 11.33 seconds
Started May 16 03:24:42 PM PDT 24
Finished May 16 03:25:04 PM PDT 24
Peak memory 204836 kb
Host smart-b75dc23e-4216-4cf9-9d5a-83b3c4497e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23345
49498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2334549498
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3715456060
Short name T225
Test name
Test status
Simulation time 9049939172 ps
CPU time 12.62 seconds
Started May 16 03:24:43 PM PDT 24
Finished May 16 03:25:06 PM PDT 24
Peak memory 204724 kb
Host smart-cb0029b3-2201-4055-80e8-fa4a56574672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37154
56060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3715456060
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.280909477
Short name T577
Test name
Test status
Simulation time 8396063493 ps
CPU time 13.93 seconds
Started May 16 03:24:49 PM PDT 24
Finished May 16 03:25:12 PM PDT 24
Peak memory 204804 kb
Host smart-2b032c62-52f4-4c66-9a59-b4edf6971851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28090
9477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.280909477
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.193611961
Short name T592
Test name
Test status
Simulation time 8379225787 ps
CPU time 11.81 seconds
Started May 16 03:24:52 PM PDT 24
Finished May 16 03:25:13 PM PDT 24
Peak memory 204880 kb
Host smart-efd5bece-4972-47ed-afb9-0699756b1b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19361
1961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.193611961
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.2845025138
Short name T510
Test name
Test status
Simulation time 9192143396 ps
CPU time 15.36 seconds
Started May 16 03:24:46 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204800 kb
Host smart-be694d91-dac4-41c4-a2b1-52abd85fb0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28450
25138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.2845025138
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3386774732
Short name T1728
Test name
Test status
Simulation time 8474675939 ps
CPU time 12.33 seconds
Started May 16 03:24:52 PM PDT 24
Finished May 16 03:25:13 PM PDT 24
Peak memory 204856 kb
Host smart-893172f0-7412-4e31-82a3-c53faf1743e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33867
74732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3386774732
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.1302241929
Short name T1148
Test name
Test status
Simulation time 8398924327 ps
CPU time 10.74 seconds
Started May 16 03:24:51 PM PDT 24
Finished May 16 03:25:12 PM PDT 24
Peak memory 204760 kb
Host smart-73a0f65d-3b7e-404f-a760-ddefc18f298b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13022
41929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.1302241929
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.4037548491
Short name T1489
Test name
Test status
Simulation time 8379190949 ps
CPU time 12.98 seconds
Started May 16 03:24:49 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204724 kb
Host smart-7c02bc09-eb54-4cfa-8d89-3f51d8ed3092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40375
48491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.4037548491
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3723901433
Short name T769
Test name
Test status
Simulation time 8428774835 ps
CPU time 11.15 seconds
Started May 16 03:24:51 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204876 kb
Host smart-19d0800b-6e0b-4b6b-8377-d504c8594c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37239
01433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3723901433
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.1017495984
Short name T1406
Test name
Test status
Simulation time 8385523663 ps
CPU time 11.95 seconds
Started May 16 03:24:50 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204844 kb
Host smart-89ab1936-23cd-40f6-a417-3e142cfbef54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10174
95984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.1017495984
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3971209016
Short name T7
Test name
Test status
Simulation time 11506493219 ps
CPU time 16.37 seconds
Started May 16 03:24:52 PM PDT 24
Finished May 16 03:25:17 PM PDT 24
Peak memory 204784 kb
Host smart-377cc936-3461-4ecd-90c1-94ff727a5503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39712
09016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3971209016
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1317407466
Short name T337
Test name
Test status
Simulation time 8429308418 ps
CPU time 11.93 seconds
Started May 16 03:24:48 PM PDT 24
Finished May 16 03:25:10 PM PDT 24
Peak memory 204824 kb
Host smart-81575ef1-0ef1-49d2-ac8c-d40ddb56e3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13174
07466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1317407466
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3584248286
Short name T1333
Test name
Test status
Simulation time 8369436441 ps
CPU time 11.09 seconds
Started May 16 03:24:51 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204832 kb
Host smart-873a0dd6-6b76-4374-835b-9583484c020b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35842
48286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3584248286
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2034213665
Short name T913
Test name
Test status
Simulation time 8438241913 ps
CPU time 10.82 seconds
Started May 16 03:24:50 PM PDT 24
Finished May 16 03:25:10 PM PDT 24
Peak memory 204836 kb
Host smart-285be939-a750-48a3-bf32-bc1e1d2f4575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20342
13665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2034213665
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.1224925491
Short name T1685
Test name
Test status
Simulation time 8415731396 ps
CPU time 11.3 seconds
Started May 16 03:24:52 PM PDT 24
Finished May 16 03:25:12 PM PDT 24
Peak memory 204828 kb
Host smart-d17fc561-6a0b-4986-9d95-b206cc0efdc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12249
25491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1224925491
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.618120425
Short name T1458
Test name
Test status
Simulation time 8399638124 ps
CPU time 10.94 seconds
Started May 16 03:24:52 PM PDT 24
Finished May 16 03:25:12 PM PDT 24
Peak memory 204848 kb
Host smart-359f70f3-e415-4b6d-956b-c9fdb30ddd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61812
0425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.618120425
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1754442298
Short name T1085
Test name
Test status
Simulation time 8423276705 ps
CPU time 11.41 seconds
Started May 16 03:24:51 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204780 kb
Host smart-1df4725e-6903-49f9-a748-585da410306c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17544
42298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1754442298
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2605774981
Short name T1476
Test name
Test status
Simulation time 8369419704 ps
CPU time 10.85 seconds
Started May 16 03:24:53 PM PDT 24
Finished May 16 03:25:12 PM PDT 24
Peak memory 204892 kb
Host smart-841bc05f-9c3f-4750-8966-43d1193802ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26057
74981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2605774981
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.516630374
Short name T1097
Test name
Test status
Simulation time 8420083445 ps
CPU time 12.4 seconds
Started May 16 03:24:52 PM PDT 24
Finished May 16 03:25:13 PM PDT 24
Peak memory 204876 kb
Host smart-fe7a9649-5ecc-495c-84ae-5fdefe321f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51663
0374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.516630374
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.29111310
Short name T1168
Test name
Test status
Simulation time 8384068993 ps
CPU time 11.17 seconds
Started May 16 03:24:51 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204828 kb
Host smart-38def069-bbd4-4cd8-b89d-a18e446c0ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29111
310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.29111310
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3571842374
Short name T31
Test name
Test status
Simulation time 8383227465 ps
CPU time 13.84 seconds
Started May 16 03:24:51 PM PDT 24
Finished May 16 03:25:14 PM PDT 24
Peak memory 204900 kb
Host smart-024de56f-982e-43f8-aaa6-aead36ab8d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35718
42374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3571842374
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3147146315
Short name T476
Test name
Test status
Simulation time 8501442863 ps
CPU time 11.38 seconds
Started May 16 03:24:49 PM PDT 24
Finished May 16 03:25:09 PM PDT 24
Peak memory 204804 kb
Host smart-e045e82d-20a6-43cb-8f77-91137c9aef1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31471
46315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3147146315
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2367914930
Short name T1558
Test name
Test status
Simulation time 8411140381 ps
CPU time 11.17 seconds
Started May 16 03:24:53 PM PDT 24
Finished May 16 03:25:13 PM PDT 24
Peak memory 204892 kb
Host smart-726bfa97-ac83-40fd-9eed-9ca7d3854a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23679
14930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2367914930
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.3917479073
Short name T753
Test name
Test status
Simulation time 8407727469 ps
CPU time 12.71 seconds
Started May 16 03:24:53 PM PDT 24
Finished May 16 03:25:14 PM PDT 24
Peak memory 204856 kb
Host smart-3566756e-a806-49a1-b3e6-86d80758da3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39174
79073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.3917479073
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1095817559
Short name T593
Test name
Test status
Simulation time 8382007825 ps
CPU time 12.73 seconds
Started May 16 03:24:49 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204908 kb
Host smart-5e85b449-ac41-4f89-b0ee-c69028515b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10958
17559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1095817559
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2965730616
Short name T1283
Test name
Test status
Simulation time 8397197519 ps
CPU time 12.96 seconds
Started May 16 03:24:56 PM PDT 24
Finished May 16 03:25:16 PM PDT 24
Peak memory 204792 kb
Host smart-49ca09c9-4634-4206-9f52-5b243780f004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29657
30616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2965730616
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3041226878
Short name T582
Test name
Test status
Simulation time 8368372247 ps
CPU time 10.79 seconds
Started May 16 03:24:50 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204720 kb
Host smart-1c493cf6-849e-43b1-9098-01eb2a8120b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30412
26878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3041226878
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.81802986
Short name T442
Test name
Test status
Simulation time 8377712820 ps
CPU time 13.79 seconds
Started May 16 03:24:51 PM PDT 24
Finished May 16 03:25:14 PM PDT 24
Peak memory 204884 kb
Host smart-b530aa59-67d7-41a4-af17-94c6cf5556c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81802
986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.81802986
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2813330971
Short name T1599
Test name
Test status
Simulation time 8473353423 ps
CPU time 11.36 seconds
Started May 16 03:24:48 PM PDT 24
Finished May 16 03:25:09 PM PDT 24
Peak memory 204792 kb
Host smart-1a4b4b9a-ac51-44bc-8dba-91fe8fc7e492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28133
30971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2813330971
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.886992431
Short name T1161
Test name
Test status
Simulation time 8495703991 ps
CPU time 10.77 seconds
Started May 16 03:24:59 PM PDT 24
Finished May 16 03:25:15 PM PDT 24
Peak memory 204808 kb
Host smart-de2ebcfa-e92a-4010-a5b9-da728b2bbb68
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=886992431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.886992431
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.43017981
Short name T724
Test name
Test status
Simulation time 8389358199 ps
CPU time 11.68 seconds
Started May 16 03:24:57 PM PDT 24
Finished May 16 03:25:16 PM PDT 24
Peak memory 204848 kb
Host smart-e4637189-7122-4bac-9898-da1e123a794d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=43017981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.43017981
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.3945384679
Short name T964
Test name
Test status
Simulation time 8435772331 ps
CPU time 11.3 seconds
Started May 16 03:24:57 PM PDT 24
Finished May 16 03:25:15 PM PDT 24
Peak memory 204860 kb
Host smart-11e38bf8-432e-4f69-9b28-10d8235e40cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39453
84679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.3945384679
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3529676749
Short name T887
Test name
Test status
Simulation time 8390555901 ps
CPU time 12.19 seconds
Started May 16 03:24:52 PM PDT 24
Finished May 16 03:25:13 PM PDT 24
Peak memory 204728 kb
Host smart-8ec45d96-337b-4d64-9469-65038d4603c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35296
76749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3529676749
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.2393627505
Short name T1317
Test name
Test status
Simulation time 8410776221 ps
CPU time 12.26 seconds
Started May 16 03:24:49 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204764 kb
Host smart-eb79e101-55c6-4e51-b055-51d8a9c6ab9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23936
27505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2393627505
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.491974717
Short name T195
Test name
Test status
Simulation time 9330358432 ps
CPU time 12.96 seconds
Started May 16 03:24:49 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204800 kb
Host smart-d2179da1-4cb3-4f30-aa44-0db313701492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49197
4717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.491974717
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.2494664757
Short name T683
Test name
Test status
Simulation time 8389807557 ps
CPU time 11.96 seconds
Started May 16 03:24:53 PM PDT 24
Finished May 16 03:25:14 PM PDT 24
Peak memory 204816 kb
Host smart-a88c5ef4-38ba-4727-bcb4-b0e5c9c0d97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24946
64757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.2494664757
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3284236953
Short name T597
Test name
Test status
Simulation time 8415510997 ps
CPU time 12.59 seconds
Started May 16 03:24:47 PM PDT 24
Finished May 16 03:25:10 PM PDT 24
Peak memory 204908 kb
Host smart-34345cba-0386-4ab0-bea2-a1ae7b03bb40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32842
36953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3284236953
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.793533918
Short name T1457
Test name
Test status
Simulation time 8976766073 ps
CPU time 12.02 seconds
Started May 16 03:24:51 PM PDT 24
Finished May 16 03:25:13 PM PDT 24
Peak memory 204932 kb
Host smart-a2122bd6-5f7a-45f1-ba93-9a5bfb471f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79353
3918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.793533918
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2097592940
Short name T452
Test name
Test status
Simulation time 8505817991 ps
CPU time 14.81 seconds
Started May 16 03:24:56 PM PDT 24
Finished May 16 03:25:18 PM PDT 24
Peak memory 204844 kb
Host smart-43c3e16c-b127-4674-a246-67098d29ce2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20975
92940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2097592940
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.423548817
Short name T421
Test name
Test status
Simulation time 8440167177 ps
CPU time 14.09 seconds
Started May 16 03:24:55 PM PDT 24
Finished May 16 03:25:17 PM PDT 24
Peak memory 204884 kb
Host smart-cc6fecca-0eca-414d-a20c-308e5b4ad2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42354
8817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.423548817
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2344435939
Short name T1323
Test name
Test status
Simulation time 8371948271 ps
CPU time 11.79 seconds
Started May 16 03:25:07 PM PDT 24
Finished May 16 03:25:24 PM PDT 24
Peak memory 204832 kb
Host smart-4a7e5411-a5b0-4232-8d02-af472f15dd53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444
35939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2344435939
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1460813849
Short name T904
Test name
Test status
Simulation time 8387368006 ps
CPU time 14 seconds
Started May 16 03:24:48 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204852 kb
Host smart-e5768e69-8530-46e7-ad07-8fb5cd7db9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14608
13849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1460813849
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2732972579
Short name T1268
Test name
Test status
Simulation time 8419311631 ps
CPU time 11 seconds
Started May 16 03:24:49 PM PDT 24
Finished May 16 03:25:09 PM PDT 24
Peak memory 204904 kb
Host smart-5741fc29-9ac0-4a25-9086-ef657aaf52c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27329
72579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2732972579
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3062425031
Short name T1718
Test name
Test status
Simulation time 11533937604 ps
CPU time 18.4 seconds
Started May 16 03:24:52 PM PDT 24
Finished May 16 03:25:19 PM PDT 24
Peak memory 204912 kb
Host smart-e9500a5f-ba21-4067-9398-b0b18166e064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30624
25031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3062425031
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3498682255
Short name T450
Test name
Test status
Simulation time 8440926937 ps
CPU time 11 seconds
Started May 16 03:24:51 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204800 kb
Host smart-e7f5ac6e-08f1-4a9f-b5a7-64fc9c16bfee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34986
82255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3498682255
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.344858101
Short name T845
Test name
Test status
Simulation time 8372793494 ps
CPU time 11.9 seconds
Started May 16 03:24:49 PM PDT 24
Finished May 16 03:25:10 PM PDT 24
Peak memory 204804 kb
Host smart-7f61b0d7-ecb9-4b61-b480-78d76413f110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34485
8101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.344858101
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3424888160
Short name T133
Test name
Test status
Simulation time 8436195623 ps
CPU time 12.66 seconds
Started May 16 03:24:48 PM PDT 24
Finished May 16 03:25:10 PM PDT 24
Peak memory 204800 kb
Host smart-d3d929a6-380f-4e6c-bce6-587c547ca9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34248
88160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3424888160
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.843746624
Short name T352
Test name
Test status
Simulation time 8428541984 ps
CPU time 14.06 seconds
Started May 16 03:24:52 PM PDT 24
Finished May 16 03:25:15 PM PDT 24
Peak memory 204848 kb
Host smart-bfd0985b-231a-4b70-af58-dec2b4154d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84374
6624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.843746624
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.643332732
Short name T929
Test name
Test status
Simulation time 8410197308 ps
CPU time 11.6 seconds
Started May 16 03:24:56 PM PDT 24
Finished May 16 03:25:15 PM PDT 24
Peak memory 204876 kb
Host smart-02fb1731-b5be-412b-bb7b-9651096c2229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64333
2732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.643332732
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1891807570
Short name T98
Test name
Test status
Simulation time 8377794421 ps
CPU time 11.49 seconds
Started May 16 03:24:57 PM PDT 24
Finished May 16 03:25:15 PM PDT 24
Peak memory 204772 kb
Host smart-4cd8fb00-7891-4cd7-ad43-4e23ec4fabcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18918
07570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1891807570
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.3594585972
Short name T368
Test name
Test status
Simulation time 8418653904 ps
CPU time 12.7 seconds
Started May 16 03:24:57 PM PDT 24
Finished May 16 03:25:17 PM PDT 24
Peak memory 204880 kb
Host smart-8d99c7b0-ed4a-49fb-9155-5aba9786fe3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35945
85972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.3594585972
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.2170875655
Short name T968
Test name
Test status
Simulation time 8382172844 ps
CPU time 11.82 seconds
Started May 16 03:25:10 PM PDT 24
Finished May 16 03:25:27 PM PDT 24
Peak memory 204780 kb
Host smart-c93220c6-3aa8-49b3-bcae-1181705bec31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21708
75655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2170875655
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.4267962614
Short name T545
Test name
Test status
Simulation time 8361239363 ps
CPU time 13.19 seconds
Started May 16 03:24:57 PM PDT 24
Finished May 16 03:25:17 PM PDT 24
Peak memory 204852 kb
Host smart-c7f343cf-395d-4ef7-8d57-5be17407d973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42679
62614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.4267962614
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.4206700084
Short name T1615
Test name
Test status
Simulation time 31225407548 ps
CPU time 62 seconds
Started May 16 03:24:53 PM PDT 24
Finished May 16 03:26:04 PM PDT 24
Peak memory 204868 kb
Host smart-8dd4a278-bc0e-4a0d-981d-a55c28295162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42067
00084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.4206700084
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2135850155
Short name T242
Test name
Test status
Simulation time 8380701678 ps
CPU time 11.04 seconds
Started May 16 03:24:56 PM PDT 24
Finished May 16 03:25:14 PM PDT 24
Peak memory 204860 kb
Host smart-606ea485-6417-472f-9393-3efe1b178f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21358
50155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2135850155
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2402432779
Short name T742
Test name
Test status
Simulation time 8453114552 ps
CPU time 11.34 seconds
Started May 16 03:24:58 PM PDT 24
Finished May 16 03:25:16 PM PDT 24
Peak memory 204904 kb
Host smart-780b4bf6-ffcc-405f-8878-d39ca96f0a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24024
32779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2402432779
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.441721124
Short name T779
Test name
Test status
Simulation time 8381264671 ps
CPU time 11.06 seconds
Started May 16 03:25:07 PM PDT 24
Finished May 16 03:25:23 PM PDT 24
Peak memory 204796 kb
Host smart-56f083fd-3d6f-407b-8dd5-35ff34689d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44172
1124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.441721124
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.745297816
Short name T191
Test name
Test status
Simulation time 8393619885 ps
CPU time 11.38 seconds
Started May 16 03:25:07 PM PDT 24
Finished May 16 03:25:24 PM PDT 24
Peak memory 204776 kb
Host smart-074130a2-0664-4e14-99f3-29ac2ae7db0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74529
7816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.745297816
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.990349872
Short name T1202
Test name
Test status
Simulation time 8366916458 ps
CPU time 13.79 seconds
Started May 16 03:24:56 PM PDT 24
Finished May 16 03:25:17 PM PDT 24
Peak memory 204852 kb
Host smart-98f9becc-9b48-4ec6-b76f-a65a7aa296e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99034
9872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.990349872
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2204770697
Short name T163
Test name
Test status
Simulation time 8459566420 ps
CPU time 10.94 seconds
Started May 16 03:24:51 PM PDT 24
Finished May 16 03:25:11 PM PDT 24
Peak memory 204692 kb
Host smart-5a251ba1-9c63-478d-825e-5bf4e9d458ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22047
70697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2204770697
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3308929432
Short name T804
Test name
Test status
Simulation time 8412808790 ps
CPU time 11.28 seconds
Started May 16 03:24:56 PM PDT 24
Finished May 16 03:25:15 PM PDT 24
Peak memory 204824 kb
Host smart-7f3e4538-d7a3-40ef-98ec-ed39d2d24d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33089
29432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3308929432
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3305552585
Short name T1618
Test name
Test status
Simulation time 8404943884 ps
CPU time 13.28 seconds
Started May 16 03:24:57 PM PDT 24
Finished May 16 03:25:17 PM PDT 24
Peak memory 204848 kb
Host smart-7bd6d6b8-720f-42e4-8e91-bd2a089db9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33055
52585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3305552585
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.1514509390
Short name T939
Test name
Test status
Simulation time 8489142156 ps
CPU time 11.16 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:32 PM PDT 24
Peak memory 204908 kb
Host smart-a6593b44-7600-4549-9857-9c40c373acd8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1514509390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.1514509390
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.1886531755
Short name T1669
Test name
Test status
Simulation time 8378704517 ps
CPU time 12.18 seconds
Started May 16 03:25:16 PM PDT 24
Finished May 16 03:25:35 PM PDT 24
Peak memory 204904 kb
Host smart-216504cf-b02a-4bce-b345-6dff99c19d7a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1886531755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.1886531755
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.4132501455
Short name T763
Test name
Test status
Simulation time 8439124461 ps
CPU time 12.46 seconds
Started May 16 03:25:07 PM PDT 24
Finished May 16 03:25:25 PM PDT 24
Peak memory 204916 kb
Host smart-5228ab7f-e1de-4315-a573-64a05f9257d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41325
01455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.4132501455
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.840384839
Short name T1141
Test name
Test status
Simulation time 8378671850 ps
CPU time 10.46 seconds
Started May 16 03:25:09 PM PDT 24
Finished May 16 03:25:25 PM PDT 24
Peak memory 204780 kb
Host smart-c8f2b257-985e-430c-9cef-059503afc276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84038
4839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.840384839
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3797636565
Short name T1389
Test name
Test status
Simulation time 9315463735 ps
CPU time 12.05 seconds
Started May 16 03:25:06 PM PDT 24
Finished May 16 03:25:23 PM PDT 24
Peak memory 204868 kb
Host smart-7aa98747-943d-4677-a1a0-f571744e33c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37976
36565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3797636565
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2866482652
Short name T974
Test name
Test status
Simulation time 8368312967 ps
CPU time 10.99 seconds
Started May 16 03:25:06 PM PDT 24
Finished May 16 03:25:22 PM PDT 24
Peak memory 204792 kb
Host smart-229f4611-578f-4d89-8c6d-710f300f0507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28664
82652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2866482652
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2485331446
Short name T870
Test name
Test status
Simulation time 8396381293 ps
CPU time 11.87 seconds
Started May 16 03:25:09 PM PDT 24
Finished May 16 03:25:26 PM PDT 24
Peak memory 204848 kb
Host smart-6b700ca7-7195-4171-bb62-a499aeeffdbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24853
31446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2485331446
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.2817266322
Short name T480
Test name
Test status
Simulation time 9006498985 ps
CPU time 11.88 seconds
Started May 16 03:25:06 PM PDT 24
Finished May 16 03:25:23 PM PDT 24
Peak memory 204836 kb
Host smart-5b4ec80f-222c-43b9-bc15-2ea607881b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28172
66322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2817266322
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.202182093
Short name T1318
Test name
Test status
Simulation time 8459566944 ps
CPU time 13.59 seconds
Started May 16 03:25:04 PM PDT 24
Finished May 16 03:25:23 PM PDT 24
Peak memory 204864 kb
Host smart-ff238d38-d5a3-47d2-89b0-311d5916e684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20218
2093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.202182093
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.982698206
Short name T660
Test name
Test status
Simulation time 8434561725 ps
CPU time 13.42 seconds
Started May 16 03:25:08 PM PDT 24
Finished May 16 03:25:27 PM PDT 24
Peak memory 204828 kb
Host smart-58ae5ea9-73bb-4356-8212-7b6d4e39b55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98269
8206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.982698206
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1788832314
Short name T837
Test name
Test status
Simulation time 8380070916 ps
CPU time 13.6 seconds
Started May 16 03:25:06 PM PDT 24
Finished May 16 03:25:25 PM PDT 24
Peak memory 204836 kb
Host smart-25f3e6ac-de1d-4a67-b38a-68e2fccf57b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17888
32314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1788832314
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.4258308820
Short name T896
Test name
Test status
Simulation time 8411339683 ps
CPU time 10.71 seconds
Started May 16 03:25:07 PM PDT 24
Finished May 16 03:25:23 PM PDT 24
Peak memory 204904 kb
Host smart-9e5b9962-b908-486a-a014-5cf160b0fc84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42583
08820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.4258308820
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2812276188
Short name T530
Test name
Test status
Simulation time 8426173036 ps
CPU time 11.4 seconds
Started May 16 03:25:09 PM PDT 24
Finished May 16 03:25:25 PM PDT 24
Peak memory 204868 kb
Host smart-7c4c9272-9a20-4a03-aa5d-4e1f4d1fe20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28122
76188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2812276188
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.185742763
Short name T466
Test name
Test status
Simulation time 11529013861 ps
CPU time 14.2 seconds
Started May 16 03:25:10 PM PDT 24
Finished May 16 03:25:29 PM PDT 24
Peak memory 204852 kb
Host smart-d390e146-e411-40d4-a209-2642d025741e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18574
2763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.185742763
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.60953115
Short name T318
Test name
Test status
Simulation time 8413614774 ps
CPU time 12.23 seconds
Started May 16 03:25:09 PM PDT 24
Finished May 16 03:25:27 PM PDT 24
Peak memory 204776 kb
Host smart-68c14eab-34c9-4ab2-a7ae-26d08fd3fbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60953
115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.60953115
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1564217149
Short name T502
Test name
Test status
Simulation time 8402912940 ps
CPU time 12.11 seconds
Started May 16 03:25:03 PM PDT 24
Finished May 16 03:25:21 PM PDT 24
Peak memory 204792 kb
Host smart-aac4974f-0764-422b-96a4-a117b265f31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15642
17149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1564217149
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.773480437
Short name T122
Test name
Test status
Simulation time 8418852412 ps
CPU time 11.41 seconds
Started May 16 03:25:06 PM PDT 24
Finished May 16 03:25:22 PM PDT 24
Peak memory 204784 kb
Host smart-d468aae8-a4aa-4bba-877a-1ba4876194dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77348
0437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.773480437
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.1234430290
Short name T1536
Test name
Test status
Simulation time 8417209786 ps
CPU time 11.93 seconds
Started May 16 03:25:05 PM PDT 24
Finished May 16 03:25:22 PM PDT 24
Peak memory 204840 kb
Host smart-7d843dc4-1250-4c54-805e-277b74cbdffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12344
30290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.1234430290
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1357557767
Short name T1578
Test name
Test status
Simulation time 8416338543 ps
CPU time 10.82 seconds
Started May 16 03:25:05 PM PDT 24
Finished May 16 03:25:21 PM PDT 24
Peak memory 204860 kb
Host smart-66af8191-8387-4b5f-80ce-a974eed134ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13575
57767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1357557767
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2406298132
Short name T680
Test name
Test status
Simulation time 8413717701 ps
CPU time 11.69 seconds
Started May 16 03:25:04 PM PDT 24
Finished May 16 03:25:21 PM PDT 24
Peak memory 204872 kb
Host smart-8d6c7e79-d437-4a93-9e19-9027bb6e16e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24062
98132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2406298132
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.3814303546
Short name T201
Test name
Test status
Simulation time 8371782977 ps
CPU time 11.2 seconds
Started May 16 03:25:05 PM PDT 24
Finished May 16 03:25:21 PM PDT 24
Peak memory 204836 kb
Host smart-edc3baae-cbc6-4fe5-b971-7ddc3c0ec8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38143
03546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.3814303546
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.3983055885
Short name T596
Test name
Test status
Simulation time 8426466614 ps
CPU time 12.89 seconds
Started May 16 03:25:05 PM PDT 24
Finished May 16 03:25:23 PM PDT 24
Peak memory 204824 kb
Host smart-540e0599-2f67-4cf5-8055-cd5760ee0492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39830
55885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.3983055885
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2906086711
Short name T456
Test name
Test status
Simulation time 8383125894 ps
CPU time 12.22 seconds
Started May 16 03:25:08 PM PDT 24
Finished May 16 03:25:25 PM PDT 24
Peak memory 204764 kb
Host smart-989def0f-9b0f-4b63-bcc8-0f87593e6e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29060
86711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2906086711
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2068091242
Short name T1131
Test name
Test status
Simulation time 8364878514 ps
CPU time 11.07 seconds
Started May 16 03:25:08 PM PDT 24
Finished May 16 03:25:24 PM PDT 24
Peak memory 204748 kb
Host smart-cc8be716-60c2-4847-a345-fbfe47bb4f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20680
91242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2068091242
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3853345259
Short name T901
Test name
Test status
Simulation time 30186546228 ps
CPU time 68 seconds
Started May 16 03:25:09 PM PDT 24
Finished May 16 03:26:22 PM PDT 24
Peak memory 204796 kb
Host smart-e82402de-7f85-4150-900c-234a3d13b26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38533
45259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3853345259
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3182747795
Short name T632
Test name
Test status
Simulation time 8376290122 ps
CPU time 11.56 seconds
Started May 16 03:25:05 PM PDT 24
Finished May 16 03:25:22 PM PDT 24
Peak memory 204744 kb
Host smart-81025d09-86cc-423a-8311-04da39abaf7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31827
47795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3182747795
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.1387695420
Short name T112
Test name
Test status
Simulation time 8404226113 ps
CPU time 10.83 seconds
Started May 16 03:25:06 PM PDT 24
Finished May 16 03:25:22 PM PDT 24
Peak memory 204788 kb
Host smart-eea2590e-fe20-4a94-bbab-806afd366e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13876
95420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.1387695420
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2457823421
Short name T1252
Test name
Test status
Simulation time 8362688362 ps
CPU time 13.08 seconds
Started May 16 03:25:09 PM PDT 24
Finished May 16 03:25:27 PM PDT 24
Peak memory 204836 kb
Host smart-30a002f8-3910-4225-b46f-6eaf729f7077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24578
23421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2457823421
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3811691505
Short name T1250
Test name
Test status
Simulation time 8387855136 ps
CPU time 11.35 seconds
Started May 16 03:25:08 PM PDT 24
Finished May 16 03:25:25 PM PDT 24
Peak memory 204804 kb
Host smart-69ba8325-e04b-4e28-87e1-107b56c08316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38116
91505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3811691505
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2282063913
Short name T744
Test name
Test status
Simulation time 8389826556 ps
CPU time 10.73 seconds
Started May 16 03:25:06 PM PDT 24
Finished May 16 03:25:22 PM PDT 24
Peak memory 204872 kb
Host smart-4fb3c7f2-79a1-40d4-9e3a-890702eaedcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22820
63913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2282063913
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.620589446
Short name T1416
Test name
Test status
Simulation time 8432012075 ps
CPU time 11.64 seconds
Started May 16 03:24:57 PM PDT 24
Finished May 16 03:25:15 PM PDT 24
Peak memory 204860 kb
Host smart-1df04c4e-8a67-4106-9340-edaa1a5dc859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62058
9446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.620589446
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.443362828
Short name T539
Test name
Test status
Simulation time 8405026008 ps
CPU time 11.17 seconds
Started May 16 03:25:05 PM PDT 24
Finished May 16 03:25:21 PM PDT 24
Peak memory 204908 kb
Host smart-c9b8f0d1-d577-49e0-9bfc-d7e34554c5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44336
2828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.443362828
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2169328570
Short name T1480
Test name
Test status
Simulation time 8410436605 ps
CPU time 10.91 seconds
Started May 16 03:25:08 PM PDT 24
Finished May 16 03:25:24 PM PDT 24
Peak memory 204836 kb
Host smart-bc20580f-422a-4450-af6d-791436b2975c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21693
28570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2169328570
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.1779562174
Short name T808
Test name
Test status
Simulation time 8489829209 ps
CPU time 11.24 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:32 PM PDT 24
Peak memory 204860 kb
Host smart-09f9fbc4-653a-44b0-bb5e-d73e0f65cf1a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1779562174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.1779562174
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.3476665723
Short name T1230
Test name
Test status
Simulation time 8428450844 ps
CPU time 11.49 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:33 PM PDT 24
Peak memory 204892 kb
Host smart-943ce5b3-0256-4697-828f-0b5faa339a9a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3476665723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.3476665723
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.1415686278
Short name T348
Test name
Test status
Simulation time 8444533065 ps
CPU time 11.93 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:33 PM PDT 24
Peak memory 204824 kb
Host smart-1507a25f-56e3-4b5a-baae-fe7a5d6939c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14156
86278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.1415686278
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1742303841
Short name T307
Test name
Test status
Simulation time 8371119567 ps
CPU time 10.9 seconds
Started May 16 03:25:16 PM PDT 24
Finished May 16 03:25:34 PM PDT 24
Peak memory 204868 kb
Host smart-655f35f1-a470-4696-9bf3-6e251de282fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17423
03841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1742303841
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2316682029
Short name T204
Test name
Test status
Simulation time 8657790825 ps
CPU time 12.6 seconds
Started May 16 03:25:13 PM PDT 24
Finished May 16 03:25:32 PM PDT 24
Peak memory 204816 kb
Host smart-f1e09107-3d4f-4461-995e-ac064ddb8f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23166
82029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2316682029
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.2513542162
Short name T1157
Test name
Test status
Simulation time 8374452432 ps
CPU time 11.21 seconds
Started May 16 03:25:13 PM PDT 24
Finished May 16 03:25:31 PM PDT 24
Peak memory 204776 kb
Host smart-4bc7d60a-4967-4ec2-981c-6e02a304a3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25135
42162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.2513542162
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.450635440
Short name T1611
Test name
Test status
Simulation time 8408577987 ps
CPU time 11 seconds
Started May 16 03:25:13 PM PDT 24
Finished May 16 03:25:31 PM PDT 24
Peak memory 204868 kb
Host smart-e8094ee9-5a28-427a-8d95-cede6f75c53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45063
5440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.450635440
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3807256032
Short name T1717
Test name
Test status
Simulation time 9135233838 ps
CPU time 13.66 seconds
Started May 16 03:25:16 PM PDT 24
Finished May 16 03:25:36 PM PDT 24
Peak memory 204900 kb
Host smart-afa6963f-dd91-4beb-9224-53652e18c47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38072
56032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3807256032
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1885513926
Short name T832
Test name
Test status
Simulation time 8441101964 ps
CPU time 12.51 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:33 PM PDT 24
Peak memory 204828 kb
Host smart-c64f52a4-ed24-4ba9-b548-79414e01309a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18855
13926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1885513926
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3889515843
Short name T1109
Test name
Test status
Simulation time 8408584934 ps
CPU time 12.92 seconds
Started May 16 03:25:15 PM PDT 24
Finished May 16 03:25:35 PM PDT 24
Peak memory 204908 kb
Host smart-77503c45-274b-49d8-bdd4-0e90e306be5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38895
15843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3889515843
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.646512171
Short name T1415
Test name
Test status
Simulation time 8391053458 ps
CPU time 11.94 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:32 PM PDT 24
Peak memory 204732 kb
Host smart-71af0c95-97df-43a4-a078-a6e018467b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64651
2171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.646512171
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1753242288
Short name T688
Test name
Test status
Simulation time 8384084248 ps
CPU time 10.39 seconds
Started May 16 03:25:15 PM PDT 24
Finished May 16 03:25:32 PM PDT 24
Peak memory 204840 kb
Host smart-4eaa564f-b7f0-4f08-a319-45cad4d4084a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17532
42288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1753242288
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1521736428
Short name T310
Test name
Test status
Simulation time 8409060265 ps
CPU time 12.08 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:33 PM PDT 24
Peak memory 204776 kb
Host smart-2de12a9f-8019-43e9-ab98-570e3bec5aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15217
36428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1521736428
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2728925399
Short name T565
Test name
Test status
Simulation time 11539145750 ps
CPU time 17.33 seconds
Started May 16 03:25:13 PM PDT 24
Finished May 16 03:25:37 PM PDT 24
Peak memory 204760 kb
Host smart-273721f4-1caa-4e86-8adb-c5cdf2576a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27289
25399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2728925399
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.509227607
Short name T760
Test name
Test status
Simulation time 8442954480 ps
CPU time 11.03 seconds
Started May 16 03:25:13 PM PDT 24
Finished May 16 03:25:30 PM PDT 24
Peak memory 204716 kb
Host smart-2997c22c-22be-448b-8c7d-76f4feff3dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50922
7607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.509227607
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2635399955
Short name T668
Test name
Test status
Simulation time 8372623325 ps
CPU time 11.94 seconds
Started May 16 03:25:15 PM PDT 24
Finished May 16 03:25:34 PM PDT 24
Peak memory 204852 kb
Host smart-c4425fba-88de-4776-9e02-639a22a2e4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26353
99955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2635399955
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2021683413
Short name T1183
Test name
Test status
Simulation time 8416717983 ps
CPU time 10.66 seconds
Started May 16 03:25:16 PM PDT 24
Finished May 16 03:25:33 PM PDT 24
Peak memory 204892 kb
Host smart-175a124c-7668-454a-9eb2-1a501c7834dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20216
83413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2021683413
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.181397094
Short name T494
Test name
Test status
Simulation time 8426514712 ps
CPU time 13.89 seconds
Started May 16 03:25:12 PM PDT 24
Finished May 16 03:25:33 PM PDT 24
Peak memory 204864 kb
Host smart-845fb67c-205b-40b7-a94a-4999ee16a0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18139
7094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.181397094
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.452302950
Short name T1441
Test name
Test status
Simulation time 8378514949 ps
CPU time 13.08 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:34 PM PDT 24
Peak memory 204852 kb
Host smart-08b27e06-c5ce-4627-a39e-158dc9655128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45230
2950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.452302950
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1279809249
Short name T903
Test name
Test status
Simulation time 8387829018 ps
CPU time 11.1 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:33 PM PDT 24
Peak memory 204872 kb
Host smart-fa51ed40-29e8-434e-8ecc-919975259797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12798
09249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1279809249
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3751309094
Short name T38
Test name
Test status
Simulation time 8393290514 ps
CPU time 11.49 seconds
Started May 16 03:25:16 PM PDT 24
Finished May 16 03:25:34 PM PDT 24
Peak memory 204932 kb
Host smart-9f1b84eb-83f0-464c-9b77-9abcfdc7af9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37513
09094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3751309094
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.990835397
Short name T1394
Test name
Test status
Simulation time 8423681601 ps
CPU time 11.22 seconds
Started May 16 03:25:16 PM PDT 24
Finished May 16 03:25:35 PM PDT 24
Peak memory 204808 kb
Host smart-abac6d60-530e-4269-b5a7-560ca3431715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99083
5397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.990835397
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.1150422488
Short name T979
Test name
Test status
Simulation time 8452738397 ps
CPU time 11.42 seconds
Started May 16 03:25:13 PM PDT 24
Finished May 16 03:25:32 PM PDT 24
Peak memory 204784 kb
Host smart-71bdcdf8-34d1-4547-8f95-224911af0a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11504
22488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.1150422488
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3539062524
Short name T1589
Test name
Test status
Simulation time 8363933076 ps
CPU time 10.31 seconds
Started May 16 03:25:13 PM PDT 24
Finished May 16 03:25:30 PM PDT 24
Peak memory 204808 kb
Host smart-d46baded-156c-410a-a448-90fc6b98b5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35390
62524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3539062524
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.390895273
Short name T986
Test name
Test status
Simulation time 25723702512 ps
CPU time 50.32 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:26:12 PM PDT 24
Peak memory 204780 kb
Host smart-55840a7d-80e1-40e7-984c-ca173c25b642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39089
5273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.390895273
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2820116250
Short name T304
Test name
Test status
Simulation time 8409775549 ps
CPU time 10.94 seconds
Started May 16 03:25:16 PM PDT 24
Finished May 16 03:25:34 PM PDT 24
Peak memory 204824 kb
Host smart-de2eff29-8548-4b4e-80c9-7f76f96086f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28201
16250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2820116250
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2234802486
Short name T1205
Test name
Test status
Simulation time 8458083826 ps
CPU time 13.57 seconds
Started May 16 03:25:17 PM PDT 24
Finished May 16 03:25:38 PM PDT 24
Peak memory 204836 kb
Host smart-ddf6604c-3f52-4132-bb1f-a7faa404f4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22348
02486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2234802486
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.356333593
Short name T802
Test name
Test status
Simulation time 8416444923 ps
CPU time 11.06 seconds
Started May 16 03:25:15 PM PDT 24
Finished May 16 03:25:33 PM PDT 24
Peak memory 204848 kb
Host smart-c95dde6a-4b1f-49f7-aa45-0524969567f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35633
3593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.356333593
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3841152784
Short name T1112
Test name
Test status
Simulation time 8392874096 ps
CPU time 12.04 seconds
Started May 16 03:25:13 PM PDT 24
Finished May 16 03:25:32 PM PDT 24
Peak memory 204900 kb
Host smart-03adf12b-8950-424a-a484-4cf504042829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38411
52784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3841152784
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.79701468
Short name T1375
Test name
Test status
Simulation time 8375576335 ps
CPU time 12.25 seconds
Started May 16 03:25:13 PM PDT 24
Finished May 16 03:25:32 PM PDT 24
Peak memory 204888 kb
Host smart-95d1b359-b47f-467e-bfad-c736bb960cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79701
468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.79701468
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.4154180225
Short name T1330
Test name
Test status
Simulation time 8366181440 ps
CPU time 12.18 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:34 PM PDT 24
Peak memory 204816 kb
Host smart-b1607264-d38e-4617-a51e-bd20ee153192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41541
80225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.4154180225
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.30425089
Short name T1642
Test name
Test status
Simulation time 8463332715 ps
CPU time 10.83 seconds
Started May 16 03:25:13 PM PDT 24
Finished May 16 03:25:30 PM PDT 24
Peak memory 204832 kb
Host smart-9b2bac8f-7ac7-4e08-848e-7af42a121e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30425
089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.30425089
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3858214539
Short name T1703
Test name
Test status
Simulation time 8412593825 ps
CPU time 13 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:34 PM PDT 24
Peak memory 204840 kb
Host smart-1491a546-9040-4fc1-8b24-3ae0fef934c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38582
14539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3858214539
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2904402097
Short name T1078
Test name
Test status
Simulation time 8425118404 ps
CPU time 11.39 seconds
Started May 16 03:25:15 PM PDT 24
Finished May 16 03:25:33 PM PDT 24
Peak memory 204784 kb
Host smart-98acb6f7-ad91-4343-885a-b096c4f44b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29044
02097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2904402097
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.3677936178
Short name T303
Test name
Test status
Simulation time 8482524206 ps
CPU time 11.39 seconds
Started May 16 03:25:22 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204892 kb
Host smart-6f68e424-c889-4416-b710-e2ff715dc535
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3677936178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.3677936178
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.1385380909
Short name T1277
Test name
Test status
Simulation time 8392133499 ps
CPU time 11.22 seconds
Started May 16 03:25:23 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204840 kb
Host smart-c440c687-4c24-4c50-a09b-096d825ded80
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1385380909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.1385380909
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.1872677661
Short name T994
Test name
Test status
Simulation time 8477197681 ps
CPU time 11.66 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:41 PM PDT 24
Peak memory 204836 kb
Host smart-79dcf579-9387-4677-80b0-252836835336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18726
77661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.1872677661
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1516722605
Short name T359
Test name
Test status
Simulation time 8380626720 ps
CPU time 12.99 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:34 PM PDT 24
Peak memory 204920 kb
Host smart-d40b55b5-3283-4c9b-ad6e-f87e17c4d17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15167
22605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1516722605
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.1914859830
Short name T980
Test name
Test status
Simulation time 8375521174 ps
CPU time 11.75 seconds
Started May 16 03:25:13 PM PDT 24
Finished May 16 03:25:31 PM PDT 24
Peak memory 204812 kb
Host smart-29b72e5d-7249-4825-bf64-418258b8d4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19148
59830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.1914859830
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.23626454
Short name T1010
Test name
Test status
Simulation time 8530843361 ps
CPU time 10.84 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:32 PM PDT 24
Peak memory 204872 kb
Host smart-bc78ce7a-4bf1-4e10-85e4-c7b7f92f25c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23626
454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.23626454
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1662254235
Short name T1410
Test name
Test status
Simulation time 8367823087 ps
CPU time 11.69 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:41 PM PDT 24
Peak memory 204780 kb
Host smart-6b35b04d-d611-4884-b3b5-9f8fce265bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16622
54235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1662254235
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3782245108
Short name T333
Test name
Test status
Simulation time 8380899371 ps
CPU time 11.35 seconds
Started May 16 03:25:16 PM PDT 24
Finished May 16 03:25:34 PM PDT 24
Peak memory 204984 kb
Host smart-d7aa6383-887e-4da6-9302-6f6d4591da9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37822
45108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3782245108
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.108593134
Short name T1569
Test name
Test status
Simulation time 8962789263 ps
CPU time 12.26 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:33 PM PDT 24
Peak memory 204816 kb
Host smart-e93ab652-a753-490c-8830-29ed4184af22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10859
3134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.108593134
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3057645088
Short name T1719
Test name
Test status
Simulation time 8407452249 ps
CPU time 14.63 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204796 kb
Host smart-558714f9-898d-4321-b32b-c97296e105af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30576
45088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3057645088
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2287874470
Short name T503
Test name
Test status
Simulation time 8462259517 ps
CPU time 11.25 seconds
Started May 16 03:25:20 PM PDT 24
Finished May 16 03:25:40 PM PDT 24
Peak memory 204836 kb
Host smart-96320e3f-2afc-491a-9e9a-44375dabd3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22878
74470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2287874470
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3285533996
Short name T51
Test name
Test status
Simulation time 8397422750 ps
CPU time 13.14 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:43 PM PDT 24
Peak memory 204844 kb
Host smart-58243d11-4414-4af4-94a1-4a44d84975c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32855
33996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3285533996
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.475963148
Short name T840
Test name
Test status
Simulation time 8406676990 ps
CPU time 11.42 seconds
Started May 16 03:25:25 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204900 kb
Host smart-914ff662-88bd-48ba-a0ed-b9ff8f885991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47596
3148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.475963148
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.2705202639
Short name T1545
Test name
Test status
Simulation time 8411884739 ps
CPU time 11.09 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:41 PM PDT 24
Peak memory 204668 kb
Host smart-aff14743-d612-4423-b954-41a237c2b927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27052
02639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.2705202639
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1688365524
Short name T1298
Test name
Test status
Simulation time 11492273212 ps
CPU time 16 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204772 kb
Host smart-8059c0be-81c1-4450-bda7-852ad02a47bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16883
65524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1688365524
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.4051273371
Short name T1454
Test name
Test status
Simulation time 8413711649 ps
CPU time 11.53 seconds
Started May 16 03:25:26 PM PDT 24
Finished May 16 03:25:47 PM PDT 24
Peak memory 204820 kb
Host smart-223f0dc2-abfb-440e-9676-67942ddcd606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40512
73371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.4051273371
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2603206357
Short name T1367
Test name
Test status
Simulation time 8369373774 ps
CPU time 12.56 seconds
Started May 16 03:25:20 PM PDT 24
Finished May 16 03:25:41 PM PDT 24
Peak memory 204848 kb
Host smart-748140d9-0eb4-4549-94d9-d9c21c0d41c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26032
06357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2603206357
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.984919186
Short name T306
Test name
Test status
Simulation time 8423588564 ps
CPU time 11.39 seconds
Started May 16 03:25:22 PM PDT 24
Finished May 16 03:25:43 PM PDT 24
Peak memory 204868 kb
Host smart-76d3a5d0-2a1f-4496-822c-1ec2b9d0e26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98491
9186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.984919186
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2639459141
Short name T1146
Test name
Test status
Simulation time 8387567629 ps
CPU time 11.21 seconds
Started May 16 03:25:20 PM PDT 24
Finished May 16 03:25:40 PM PDT 24
Peak memory 204832 kb
Host smart-71e79f84-7acd-480c-b429-b756d5018a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26394
59141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2639459141
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.230571464
Short name T96
Test name
Test status
Simulation time 8381977505 ps
CPU time 13.51 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:43 PM PDT 24
Peak memory 204836 kb
Host smart-1096860d-5f42-44f1-ba32-e213f9e6a157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23057
1464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.230571464
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2674262414
Short name T197
Test name
Test status
Simulation time 8404791498 ps
CPU time 14.01 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204896 kb
Host smart-96227623-d637-4136-89be-040f01ffa315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26742
62414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2674262414
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.1475413132
Short name T956
Test name
Test status
Simulation time 8412797894 ps
CPU time 11.13 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204768 kb
Host smart-13445a4e-eaa3-4803-9866-45dcec363698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14754
13132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.1475413132
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1062909288
Short name T529
Test name
Test status
Simulation time 8366566402 ps
CPU time 10.57 seconds
Started May 16 03:25:22 PM PDT 24
Finished May 16 03:25:42 PM PDT 24
Peak memory 204812 kb
Host smart-7e4c42e4-7003-4cd2-b4fd-40d2ec54be49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10629
09288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1062909288
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2971215473
Short name T30
Test name
Test status
Simulation time 8369916882 ps
CPU time 10.96 seconds
Started May 16 03:25:25 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204840 kb
Host smart-94dba678-08e5-4f7c-a592-1d058c67d432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29712
15473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2971215473
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2843872964
Short name T1050
Test name
Test status
Simulation time 18881295651 ps
CPU time 37.55 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:26:11 PM PDT 24
Peak memory 204892 kb
Host smart-d39fa981-aa31-42ca-859e-78debc074de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28438
72964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2843872964
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.359653861
Short name T380
Test name
Test status
Simulation time 8375077679 ps
CPU time 13.96 seconds
Started May 16 03:25:23 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204720 kb
Host smart-45758068-ee1b-4ed9-9d11-d1d70829a110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35965
3861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.359653861
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3036722247
Short name T157
Test name
Test status
Simulation time 8427831997 ps
CPU time 10.52 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204804 kb
Host smart-4b4f240a-19ce-47f6-91fb-8f5ced0500f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30367
22247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3036722247
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.4195298719
Short name T899
Test name
Test status
Simulation time 8418746871 ps
CPU time 12.45 seconds
Started May 16 03:25:23 PM PDT 24
Finished May 16 03:25:45 PM PDT 24
Peak memory 204712 kb
Host smart-8dc7c66c-6e8a-4944-a027-5ca6908dd008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41952
98719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.4195298719
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.467542447
Short name T1005
Test name
Test status
Simulation time 8394459471 ps
CPU time 11.74 seconds
Started May 16 03:25:22 PM PDT 24
Finished May 16 03:25:42 PM PDT 24
Peak memory 204904 kb
Host smart-df4f8413-d275-44dc-a438-86c2f17f3816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46754
2447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.467542447
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2171458180
Short name T1383
Test name
Test status
Simulation time 8375227094 ps
CPU time 11.83 seconds
Started May 16 03:25:25 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204852 kb
Host smart-0977855a-841a-459c-9264-df8c9f4c6d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21714
58180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2171458180
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.532684606
Short name T1228
Test name
Test status
Simulation time 8392055333 ps
CPU time 10.81 seconds
Started May 16 03:25:25 PM PDT 24
Finished May 16 03:25:45 PM PDT 24
Peak memory 204784 kb
Host smart-fc4b2df4-6d5d-4820-a6b9-7917a5449512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53268
4606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.532684606
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.839978412
Short name T1274
Test name
Test status
Simulation time 8465167372 ps
CPU time 13.81 seconds
Started May 16 03:25:14 PM PDT 24
Finished May 16 03:25:35 PM PDT 24
Peak memory 204844 kb
Host smart-97829a37-57b4-4c0c-92e0-489e8bd94a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83997
8412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.839978412
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4243058453
Short name T330
Test name
Test status
Simulation time 8389574017 ps
CPU time 12.09 seconds
Started May 16 03:25:20 PM PDT 24
Finished May 16 03:25:41 PM PDT 24
Peak memory 204876 kb
Host smart-e58a11bb-7691-41ec-9668-e8e7929d2073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42430
58453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4243058453
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3926816832
Short name T1592
Test name
Test status
Simulation time 8426189753 ps
CPU time 10.98 seconds
Started May 16 03:25:26 PM PDT 24
Finished May 16 03:25:47 PM PDT 24
Peak memory 204828 kb
Host smart-49e22015-7b33-40dd-9617-0e97033a9a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39268
16832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3926816832
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.382956119
Short name T441
Test name
Test status
Simulation time 8472052713 ps
CPU time 12.83 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204860 kb
Host smart-94548b44-7dc4-4072-bf24-393bd102cae6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=382956119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.382956119
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.1576487712
Short name T478
Test name
Test status
Simulation time 8378864389 ps
CPU time 11.67 seconds
Started May 16 03:25:22 PM PDT 24
Finished May 16 03:25:43 PM PDT 24
Peak memory 204892 kb
Host smart-fa750f36-29a4-4d73-8c02-c22a258370ba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1576487712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.1576487712
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.1361015948
Short name T984
Test name
Test status
Simulation time 8415543917 ps
CPU time 12.84 seconds
Started May 16 03:25:23 PM PDT 24
Finished May 16 03:25:45 PM PDT 24
Peak memory 204860 kb
Host smart-88a4973d-9ede-4895-9d15-39071394ba1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13610
15948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.1361015948
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1527633573
Short name T1214
Test name
Test status
Simulation time 8373589930 ps
CPU time 10.87 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204876 kb
Host smart-ec923e18-1e98-4348-84d6-9521ac76d5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15276
33573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1527633573
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.4161243410
Short name T229
Test name
Test status
Simulation time 8402134958 ps
CPU time 13.44 seconds
Started May 16 03:25:20 PM PDT 24
Finished May 16 03:25:42 PM PDT 24
Peak memory 204856 kb
Host smart-5a8de5e0-eba1-4080-8aab-c6961e5860cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41612
43410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.4161243410
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1960264796
Short name T205
Test name
Test status
Simulation time 9332765338 ps
CPU time 12.88 seconds
Started May 16 03:25:20 PM PDT 24
Finished May 16 03:25:42 PM PDT 24
Peak memory 204756 kb
Host smart-a0bc0a0c-08ff-4ac2-92bb-79c0a794025e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19602
64796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1960264796
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1150572425
Short name T1537
Test name
Test status
Simulation time 8371628048 ps
CPU time 11.52 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204896 kb
Host smart-548fc9f0-19e1-415f-8075-a2fd49b26791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11505
72425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1150572425
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.2358472355
Short name T629
Test name
Test status
Simulation time 8386988024 ps
CPU time 11.22 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:41 PM PDT 24
Peak memory 204744 kb
Host smart-1e24be32-59d5-4740-b277-8c207df4cf3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23584
72355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2358472355
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1012350630
Short name T941
Test name
Test status
Simulation time 9271170775 ps
CPU time 13.02 seconds
Started May 16 03:25:23 PM PDT 24
Finished May 16 03:25:45 PM PDT 24
Peak memory 204832 kb
Host smart-df941b81-9ace-4e25-bf43-c723faf7f454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10123
50630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1012350630
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.788033458
Short name T620
Test name
Test status
Simulation time 8414724650 ps
CPU time 12.58 seconds
Started May 16 03:25:25 PM PDT 24
Finished May 16 03:25:47 PM PDT 24
Peak memory 204852 kb
Host smart-e93837f0-75bb-4813-b208-9a17913b1218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78803
3458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.788033458
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3418532193
Short name T1559
Test name
Test status
Simulation time 8389447058 ps
CPU time 11.28 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:25:45 PM PDT 24
Peak memory 204900 kb
Host smart-631a492f-36dd-4baa-abd1-21b95039a398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34185
32193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3418532193
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2432893594
Short name T1110
Test name
Test status
Simulation time 8397881894 ps
CPU time 11.1 seconds
Started May 16 03:25:25 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204796 kb
Host smart-322bdd00-e55e-4c6f-9c0e-0e5ec78ba973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24328
93594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2432893594
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3239610465
Short name T703
Test name
Test status
Simulation time 8465543105 ps
CPU time 12.74 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:43 PM PDT 24
Peak memory 204852 kb
Host smart-bbafeeff-f7f1-4a0a-90d7-4d98af7b139b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396
10465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3239610465
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.4198147617
Short name T23
Test name
Test status
Simulation time 8382687699 ps
CPU time 10.8 seconds
Started May 16 03:25:22 PM PDT 24
Finished May 16 03:25:42 PM PDT 24
Peak memory 204816 kb
Host smart-1f7770ac-117b-49d2-9d10-04c09eead87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41981
47617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.4198147617
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1583784628
Short name T1048
Test name
Test status
Simulation time 11550599223 ps
CPU time 15.24 seconds
Started May 16 03:25:22 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204920 kb
Host smart-b0d5e492-0f92-4fb2-8a27-6931ed17b287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15837
84628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1583784628
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3216669793
Short name T1727
Test name
Test status
Simulation time 8417791908 ps
CPU time 13.72 seconds
Started May 16 03:25:22 PM PDT 24
Finished May 16 03:25:45 PM PDT 24
Peak memory 204772 kb
Host smart-f510f32c-1dc6-432d-bf14-a0cffa147da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32166
69793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3216669793
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2426061801
Short name T776
Test name
Test status
Simulation time 8375559184 ps
CPU time 13.53 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204792 kb
Host smart-68ab20fd-6f05-4461-a513-faaa5d188406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24260
61801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2426061801
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.223599116
Short name T136
Test name
Test status
Simulation time 8452340644 ps
CPU time 10.66 seconds
Started May 16 03:25:25 PM PDT 24
Finished May 16 03:25:45 PM PDT 24
Peak memory 204816 kb
Host smart-ea599f2e-6162-4d7d-898a-3eed32dac156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22359
9116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.223599116
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2930441437
Short name T1622
Test name
Test status
Simulation time 8409582687 ps
CPU time 10.77 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204860 kb
Host smart-6209c281-eb4c-4533-9d33-d33fb4fb4c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29304
41437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2930441437
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1465845414
Short name T488
Test name
Test status
Simulation time 8409394393 ps
CPU time 11.25 seconds
Started May 16 03:25:22 PM PDT 24
Finished May 16 03:25:43 PM PDT 24
Peak memory 204892 kb
Host smart-6d32c4b2-0b10-4374-a962-2957e2e6a969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14658
45414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1465845414
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2086012864
Short name T1676
Test name
Test status
Simulation time 8473075698 ps
CPU time 10.99 seconds
Started May 16 03:25:26 PM PDT 24
Finished May 16 03:25:47 PM PDT 24
Peak memory 204888 kb
Host smart-a46e99d7-54a2-497e-8cf9-0d172e881d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20860
12864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2086012864
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.3124280565
Short name T1412
Test name
Test status
Simulation time 8421461197 ps
CPU time 11.65 seconds
Started May 16 03:25:23 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204800 kb
Host smart-2a019947-a6f2-4c4b-ba43-5eb64e2c012b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31242
80565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.3124280565
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1492690724
Short name T1733
Test name
Test status
Simulation time 8385948060 ps
CPU time 11.29 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:41 PM PDT 24
Peak memory 204752 kb
Host smart-259f7454-ca02-49f8-b24d-55526795dd8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14926
90724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1492690724
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1957000151
Short name T1220
Test name
Test status
Simulation time 8414727842 ps
CPU time 13.52 seconds
Started May 16 03:25:23 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204892 kb
Host smart-590f7c74-aa57-4eb0-b81e-1f5726c67108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19570
00151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1957000151
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.21983619
Short name T114
Test name
Test status
Simulation time 20040405579 ps
CPU time 37.89 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:26:11 PM PDT 24
Peak memory 204780 kb
Host smart-faa70c0f-5c30-4f88-8027-84b583f761e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21983
619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.21983619
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.1922642342
Short name T1484
Test name
Test status
Simulation time 8408845256 ps
CPU time 12.11 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:42 PM PDT 24
Peak memory 204816 kb
Host smart-44d0bf4a-70de-4e5a-af08-d22a875c3ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19226
42342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1922642342
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3600599167
Short name T1305
Test name
Test status
Simulation time 8446969672 ps
CPU time 11.99 seconds
Started May 16 03:25:22 PM PDT 24
Finished May 16 03:25:43 PM PDT 24
Peak memory 204884 kb
Host smart-00dc87a6-3d02-4239-abbd-4f9476d04f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36005
99167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3600599167
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.2296524332
Short name T1039
Test name
Test status
Simulation time 8454651231 ps
CPU time 11.54 seconds
Started May 16 03:25:25 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204828 kb
Host smart-d319eb23-9a34-4f43-a410-01447e972c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22965
24332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.2296524332
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.3763597844
Short name T470
Test name
Test status
Simulation time 8403217923 ps
CPU time 14 seconds
Started May 16 03:25:25 PM PDT 24
Finished May 16 03:25:48 PM PDT 24
Peak memory 204864 kb
Host smart-175eba59-a4f8-4987-9bd0-8a19ceb7710f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37635
97844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.3763597844
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.4103296844
Short name T1248
Test name
Test status
Simulation time 8402543657 ps
CPU time 12.96 seconds
Started May 16 03:25:22 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204760 kb
Host smart-8e714d67-7701-438e-9797-91a91d4a8bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41032
96844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.4103296844
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1242324711
Short name T1554
Test name
Test status
Simulation time 8367509641 ps
CPU time 11.5 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:25:45 PM PDT 24
Peak memory 204856 kb
Host smart-335b1b89-bbe8-4610-8e79-751775d5d465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12423
24711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1242324711
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.133821053
Short name T1627
Test name
Test status
Simulation time 8517867917 ps
CPU time 11.53 seconds
Started May 16 03:25:21 PM PDT 24
Finished May 16 03:25:42 PM PDT 24
Peak memory 204892 kb
Host smart-32984569-e169-4bc8-8bcf-4f18cc4dd45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13382
1053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.133821053
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2661550278
Short name T1041
Test name
Test status
Simulation time 8393500195 ps
CPU time 11.2 seconds
Started May 16 03:25:25 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204884 kb
Host smart-685f41c8-6a5a-4920-be67-54fc07912020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26615
50278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2661550278
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.536084727
Short name T1310
Test name
Test status
Simulation time 8401200210 ps
CPU time 10.64 seconds
Started May 16 03:25:24 PM PDT 24
Finished May 16 03:25:44 PM PDT 24
Peak memory 204856 kb
Host smart-83af9aa7-82b8-461d-8ed7-62ab22df1791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53608
4727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.536084727
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.3101614251
Short name T436
Test name
Test status
Simulation time 8475842188 ps
CPU time 12.34 seconds
Started May 16 03:25:27 PM PDT 24
Finished May 16 03:25:49 PM PDT 24
Peak memory 204844 kb
Host smart-50711f59-cbd6-4bcd-b81d-d3aadc4de890
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3101614251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.3101614251
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.2045667770
Short name T685
Test name
Test status
Simulation time 8394444393 ps
CPU time 10.71 seconds
Started May 16 03:25:29 PM PDT 24
Finished May 16 03:25:48 PM PDT 24
Peak memory 204816 kb
Host smart-91cd5c72-4aa9-4d2e-a415-426a534a5a3c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2045667770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.2045667770
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.3973691220
Short name T1271
Test name
Test status
Simulation time 8460077982 ps
CPU time 12.69 seconds
Started May 16 03:25:28 PM PDT 24
Finished May 16 03:25:50 PM PDT 24
Peak memory 204840 kb
Host smart-e7030611-cbc0-4239-ab47-5a98401beee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39736
91220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.3973691220
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.351398522
Short name T1570
Test name
Test status
Simulation time 8373229527 ps
CPU time 10.53 seconds
Started May 16 03:25:34 PM PDT 24
Finished May 16 03:25:51 PM PDT 24
Peak memory 204852 kb
Host smart-ac0ded57-f950-4af2-8a6a-b2fffa6003ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35139
8522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.351398522
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2445278243
Short name T1557
Test name
Test status
Simulation time 8388903054 ps
CPU time 11 seconds
Started May 16 03:25:32 PM PDT 24
Finished May 16 03:25:50 PM PDT 24
Peak memory 204892 kb
Host smart-38cdff46-fde1-4b0f-8169-7ee0c4a44205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24452
78243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2445278243
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.789877667
Short name T1086
Test name
Test status
Simulation time 8488794805 ps
CPU time 10.82 seconds
Started May 16 03:25:27 PM PDT 24
Finished May 16 03:25:47 PM PDT 24
Peak memory 204848 kb
Host smart-6235ad10-cbd9-47a1-8f2e-26164fec5d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78987
7667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.789877667
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.661739924
Short name T1765
Test name
Test status
Simulation time 8364400665 ps
CPU time 11.97 seconds
Started May 16 03:25:28 PM PDT 24
Finished May 16 03:25:49 PM PDT 24
Peak memory 204896 kb
Host smart-712c6e72-1d22-40de-9f3a-bdc747413752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66173
9924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.661739924
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3361638815
Short name T644
Test name
Test status
Simulation time 8449706267 ps
CPU time 11.08 seconds
Started May 16 03:25:27 PM PDT 24
Finished May 16 03:25:47 PM PDT 24
Peak memory 204872 kb
Host smart-d9b76eb8-5895-4f45-bbe8-871d18d612f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33616
38815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3361638815
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2603751676
Short name T463
Test name
Test status
Simulation time 9165697475 ps
CPU time 12.76 seconds
Started May 16 03:25:31 PM PDT 24
Finished May 16 03:25:51 PM PDT 24
Peak memory 204872 kb
Host smart-73b6a9cc-1a5f-4d96-97ed-374102135370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26037
51676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2603751676
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.716079606
Short name T908
Test name
Test status
Simulation time 8505744367 ps
CPU time 11.94 seconds
Started May 16 03:25:27 PM PDT 24
Finished May 16 03:25:48 PM PDT 24
Peak memory 204864 kb
Host smart-1462fa3d-02f2-4b73-b308-50f1b14852f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71607
9606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.716079606
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2654764750
Short name T1035
Test name
Test status
Simulation time 8449067995 ps
CPU time 12.18 seconds
Started May 16 03:25:28 PM PDT 24
Finished May 16 03:25:49 PM PDT 24
Peak memory 204900 kb
Host smart-6c057a80-c244-4b82-8dcb-0e690d169e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26547
64750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2654764750
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.30175521
Short name T1028
Test name
Test status
Simulation time 8370118286 ps
CPU time 10.8 seconds
Started May 16 03:25:31 PM PDT 24
Finished May 16 03:25:50 PM PDT 24
Peak memory 204832 kb
Host smart-169625e7-9030-4920-95ab-c9693779e62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30175
521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.30175521
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.941773470
Short name T859
Test name
Test status
Simulation time 8403012438 ps
CPU time 13.48 seconds
Started May 16 03:25:29 PM PDT 24
Finished May 16 03:25:51 PM PDT 24
Peak memory 204756 kb
Host smart-fe44d9af-0ba0-4d3b-aad3-d45c27992269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94177
3470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.941773470
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3231124936
Short name T616
Test name
Test status
Simulation time 8424948908 ps
CPU time 10.88 seconds
Started May 16 03:25:38 PM PDT 24
Finished May 16 03:25:55 PM PDT 24
Peak memory 204852 kb
Host smart-5c2e41a2-73df-4e7b-8ed0-98ec69f30d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32311
24936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3231124936
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.126485882
Short name T606
Test name
Test status
Simulation time 11569579275 ps
CPU time 14.88 seconds
Started May 16 03:25:32 PM PDT 24
Finished May 16 03:25:54 PM PDT 24
Peak memory 204892 kb
Host smart-c28ff208-8369-421d-8ddb-32b3875536dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12648
5882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.126485882
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3681674561
Short name T1042
Test name
Test status
Simulation time 8418989832 ps
CPU time 11.15 seconds
Started May 16 03:25:37 PM PDT 24
Finished May 16 03:25:54 PM PDT 24
Peak memory 204840 kb
Host smart-be26426c-9e02-4cdd-a9d4-426e19647446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36816
74561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3681674561
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1177354803
Short name T641
Test name
Test status
Simulation time 8387233037 ps
CPU time 11.75 seconds
Started May 16 03:25:30 PM PDT 24
Finished May 16 03:25:49 PM PDT 24
Peak memory 204820 kb
Host smart-573d103a-f957-4624-a778-f07cae1ef894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11773
54803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1177354803
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.156700379
Short name T144
Test name
Test status
Simulation time 8436847735 ps
CPU time 13.58 seconds
Started May 16 03:25:31 PM PDT 24
Finished May 16 03:25:53 PM PDT 24
Peak memory 204868 kb
Host smart-d69344fb-1696-49b8-b624-93b1413f4ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15670
0379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.156700379
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1656048568
Short name T800
Test name
Test status
Simulation time 8412725273 ps
CPU time 11.91 seconds
Started May 16 03:25:29 PM PDT 24
Finished May 16 03:25:49 PM PDT 24
Peak memory 204812 kb
Host smart-891fc508-454f-4971-a34e-ec11587c86c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16560
48568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1656048568
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3676704990
Short name T1053
Test name
Test status
Simulation time 8375704045 ps
CPU time 11.8 seconds
Started May 16 03:25:32 PM PDT 24
Finished May 16 03:25:51 PM PDT 24
Peak memory 204912 kb
Host smart-bb6476a6-ac4c-46fc-a73e-86fbed3e3eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36767
04990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3676704990
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.685077080
Short name T514
Test name
Test status
Simulation time 8431617248 ps
CPU time 10.65 seconds
Started May 16 03:25:31 PM PDT 24
Finished May 16 03:25:50 PM PDT 24
Peak memory 204904 kb
Host smart-ae7156c9-dab5-4540-8aed-c37903b4a879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68507
7080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.685077080
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2841854425
Short name T212
Test name
Test status
Simulation time 8386005453 ps
CPU time 14.82 seconds
Started May 16 03:25:29 PM PDT 24
Finished May 16 03:25:52 PM PDT 24
Peak memory 204916 kb
Host smart-ab0606bd-137f-45d5-b6fc-367bfb84dace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28418
54425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2841854425
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.3211892236
Short name T1740
Test name
Test status
Simulation time 8384767302 ps
CPU time 12.12 seconds
Started May 16 03:25:36 PM PDT 24
Finished May 16 03:25:54 PM PDT 24
Peak memory 204880 kb
Host smart-74a0443b-c866-4769-8388-ee60bce3bcd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32118
92236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.3211892236
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3155612766
Short name T1679
Test name
Test status
Simulation time 8379426904 ps
CPU time 12.47 seconds
Started May 16 03:25:27 PM PDT 24
Finished May 16 03:25:49 PM PDT 24
Peak memory 204800 kb
Host smart-bcc68949-af91-407d-82dd-0b8c3e731168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31556
12766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3155612766
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.73926725
Short name T923
Test name
Test status
Simulation time 8362642077 ps
CPU time 11.57 seconds
Started May 16 03:25:36 PM PDT 24
Finished May 16 03:25:54 PM PDT 24
Peak memory 204820 kb
Host smart-f4ebf185-0ae6-4501-87d2-ce4cc6d03aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73926
725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.73926725
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.710043156
Short name T252
Test name
Test status
Simulation time 28352383516 ps
CPU time 55.37 seconds
Started May 16 03:25:27 PM PDT 24
Finished May 16 03:26:32 PM PDT 24
Peak memory 204784 kb
Host smart-73c93e3d-9030-4d3f-9567-9a2caae4d43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71004
3156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.710043156
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1904340197
Short name T663
Test name
Test status
Simulation time 8438295072 ps
CPU time 11.24 seconds
Started May 16 03:25:36 PM PDT 24
Finished May 16 03:25:54 PM PDT 24
Peak memory 204824 kb
Host smart-4b46e127-208c-40bc-9206-b719c765b506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19043
40197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1904340197
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2989999799
Short name T386
Test name
Test status
Simulation time 8448944825 ps
CPU time 13.08 seconds
Started May 16 03:25:27 PM PDT 24
Finished May 16 03:25:49 PM PDT 24
Peak memory 204856 kb
Host smart-3e7388a8-f8c6-4d8e-aa4c-e78c18ff6dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29899
99799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2989999799
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.1478015401
Short name T765
Test name
Test status
Simulation time 8394711854 ps
CPU time 12.54 seconds
Started May 16 03:25:31 PM PDT 24
Finished May 16 03:25:51 PM PDT 24
Peak memory 204924 kb
Host smart-68bc827c-f355-4a84-a1e3-df986a42cfdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14780
15401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.1478015401
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.1583297929
Short name T1407
Test name
Test status
Simulation time 8360032662 ps
CPU time 10.62 seconds
Started May 16 03:25:28 PM PDT 24
Finished May 16 03:25:47 PM PDT 24
Peak memory 204816 kb
Host smart-0058b802-794b-4c7d-893a-41dce4555fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15832
97929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.1583297929
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1218543603
Short name T169
Test name
Test status
Simulation time 8381050136 ps
CPU time 10.95 seconds
Started May 16 03:25:31 PM PDT 24
Finished May 16 03:25:50 PM PDT 24
Peak memory 204836 kb
Host smart-e934d66c-f7f8-4855-9d25-c33ca120e7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12185
43603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1218543603
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3268987277
Short name T1299
Test name
Test status
Simulation time 8368486140 ps
CPU time 13.59 seconds
Started May 16 03:25:32 PM PDT 24
Finished May 16 03:25:53 PM PDT 24
Peak memory 204852 kb
Host smart-1206d614-c523-4634-818e-11cfbf5cf739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32689
87277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3268987277
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3153672604
Short name T188
Test name
Test status
Simulation time 8465837796 ps
CPU time 11.05 seconds
Started May 16 03:25:25 PM PDT 24
Finished May 16 03:25:46 PM PDT 24
Peak memory 204884 kb
Host smart-bb9834a3-5f9d-4500-804c-f7caece8d984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31536
72604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3153672604
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2703486517
Short name T28
Test name
Test status
Simulation time 8391174538 ps
CPU time 11.64 seconds
Started May 16 03:25:36 PM PDT 24
Finished May 16 03:25:54 PM PDT 24
Peak memory 204880 kb
Host smart-7505ab07-c744-4b31-84e0-0ffbd6e315fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27034
86517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2703486517
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1345710478
Short name T491
Test name
Test status
Simulation time 8376290418 ps
CPU time 13.82 seconds
Started May 16 03:25:27 PM PDT 24
Finished May 16 03:25:50 PM PDT 24
Peak memory 204880 kb
Host smart-2d539b31-4f6b-4886-b379-9cbbd48f5824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13457
10478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1345710478
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.220797738
Short name T1364
Test name
Test status
Simulation time 8464423126 ps
CPU time 13.15 seconds
Started May 16 03:19:41 PM PDT 24
Finished May 16 03:19:59 PM PDT 24
Peak memory 204832 kb
Host smart-4b807d13-a673-48b1-8a01-fad006797f59
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=220797738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.220797738
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.1981415162
Short name T1319
Test name
Test status
Simulation time 8391311548 ps
CPU time 12.07 seconds
Started May 16 03:19:47 PM PDT 24
Finished May 16 03:20:05 PM PDT 24
Peak memory 204788 kb
Host smart-13bfba6b-470d-4335-88ba-83321d6cc0de
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1981415162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.1981415162
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.2072913793
Short name T805
Test name
Test status
Simulation time 8454554346 ps
CPU time 12.19 seconds
Started May 16 03:19:41 PM PDT 24
Finished May 16 03:19:58 PM PDT 24
Peak memory 204848 kb
Host smart-a4645cd6-757f-445a-bc05-f562c2143c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20729
13793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.2072913793
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.773774312
Short name T1671
Test name
Test status
Simulation time 8374970917 ps
CPU time 10.52 seconds
Started May 16 03:19:36 PM PDT 24
Finished May 16 03:19:51 PM PDT 24
Peak memory 204848 kb
Host smart-b9f46f32-f03a-4652-89a7-6d713e5ea5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77377
4312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.773774312
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1441129108
Short name T1590
Test name
Test status
Simulation time 8838806227 ps
CPU time 13.33 seconds
Started May 16 03:19:33 PM PDT 24
Finished May 16 03:19:51 PM PDT 24
Peak memory 204864 kb
Host smart-bd7548c5-ffb5-4c7f-ab5b-da70a210ade8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14411
29108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1441129108
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.4219190137
Short name T579
Test name
Test status
Simulation time 8379666244 ps
CPU time 11.87 seconds
Started May 16 03:19:36 PM PDT 24
Finished May 16 03:19:54 PM PDT 24
Peak memory 204768 kb
Host smart-1e524224-c93a-4ac1-b7bf-25d6df12195c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42191
90137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.4219190137
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.133576774
Short name T1156
Test name
Test status
Simulation time 8400272299 ps
CPU time 10.75 seconds
Started May 16 03:19:35 PM PDT 24
Finished May 16 03:19:51 PM PDT 24
Peak memory 204884 kb
Host smart-b0d93de2-436d-4ad0-9c9f-c6da22363342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13357
6774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.133576774
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3310462266
Short name T1746
Test name
Test status
Simulation time 9226452898 ps
CPU time 12.17 seconds
Started May 16 03:19:36 PM PDT 24
Finished May 16 03:19:53 PM PDT 24
Peak memory 204920 kb
Host smart-61abbdd4-4be9-4446-a0fa-ef8254989b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33104
62266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3310462266
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1484598097
Short name T819
Test name
Test status
Simulation time 8396282641 ps
CPU time 12.12 seconds
Started May 16 03:19:34 PM PDT 24
Finished May 16 03:19:51 PM PDT 24
Peak memory 204700 kb
Host smart-2cbc9f04-3db0-451b-b574-c804cb0231d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14845
98097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1484598097
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.564176349
Short name T1664
Test name
Test status
Simulation time 8444764690 ps
CPU time 12.84 seconds
Started May 16 03:19:42 PM PDT 24
Finished May 16 03:19:59 PM PDT 24
Peak memory 204840 kb
Host smart-db99d35c-cdd8-47b7-b8c4-c39f4fa36d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56417
6349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.564176349
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1786685156
Short name T1196
Test name
Test status
Simulation time 8370835786 ps
CPU time 12.27 seconds
Started May 16 03:19:42 PM PDT 24
Finished May 16 03:19:59 PM PDT 24
Peak memory 204816 kb
Host smart-6b8c36df-3250-4009-9c79-f0c8ae53369f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17866
85156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1786685156
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3911623531
Short name T151
Test name
Test status
Simulation time 8475378772 ps
CPU time 13.02 seconds
Started May 16 03:19:34 PM PDT 24
Finished May 16 03:19:52 PM PDT 24
Peak memory 204892 kb
Host smart-1ca2dc94-9927-446c-b0a7-f88ceb9c2a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39116
23531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3911623531
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.118226989
Short name T392
Test name
Test status
Simulation time 8403568598 ps
CPU time 12.68 seconds
Started May 16 03:19:34 PM PDT 24
Finished May 16 03:19:51 PM PDT 24
Peak memory 204940 kb
Host smart-44188ead-4285-43bf-b0b8-bb5b1b354823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11822
6989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.118226989
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.3391968733
Short name T1258
Test name
Test status
Simulation time 11527798000 ps
CPU time 13.99 seconds
Started May 16 03:19:33 PM PDT 24
Finished May 16 03:19:52 PM PDT 24
Peak memory 204840 kb
Host smart-38659bfb-1b26-4620-b494-cfebe815defa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33919
68733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.3391968733
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.475326034
Short name T1540
Test name
Test status
Simulation time 8423356529 ps
CPU time 11.04 seconds
Started May 16 03:19:33 PM PDT 24
Finished May 16 03:19:49 PM PDT 24
Peak memory 204836 kb
Host smart-fb4ddb27-d96c-4117-a8a2-1f1513a81d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47532
6034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.475326034
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.482043929
Short name T1273
Test name
Test status
Simulation time 8383328687 ps
CPU time 10.85 seconds
Started May 16 03:19:36 PM PDT 24
Finished May 16 03:19:52 PM PDT 24
Peak memory 204824 kb
Host smart-fe2a61ca-4ad1-432a-a714-2dfabae36c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48204
3929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.482043929
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.750915887
Short name T118
Test name
Test status
Simulation time 8429954737 ps
CPU time 13.77 seconds
Started May 16 03:19:34 PM PDT 24
Finished May 16 03:19:53 PM PDT 24
Peak memory 204848 kb
Host smart-fc8ea5d1-4d48-4334-b25f-954db28d8d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75091
5887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.750915887
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.4068140699
Short name T1130
Test name
Test status
Simulation time 8414442174 ps
CPU time 10.77 seconds
Started May 16 03:19:37 PM PDT 24
Finished May 16 03:19:53 PM PDT 24
Peak memory 204848 kb
Host smart-e83035ce-2e6f-4011-b699-a42a13057771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40681
40699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.4068140699
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2661323736
Short name T1117
Test name
Test status
Simulation time 8389891818 ps
CPU time 12.44 seconds
Started May 16 03:19:37 PM PDT 24
Finished May 16 03:19:55 PM PDT 24
Peak memory 204780 kb
Host smart-dc64a921-89c0-49fa-afe5-db65a08af607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26613
23736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2661323736
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1846995347
Short name T1582
Test name
Test status
Simulation time 8422498225 ps
CPU time 11.54 seconds
Started May 16 03:19:38 PM PDT 24
Finished May 16 03:19:55 PM PDT 24
Peak memory 204796 kb
Host smart-3d132a47-7bbc-42f4-a900-8ff2a45bff3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18469
95347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1846995347
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1752219144
Short name T218
Test name
Test status
Simulation time 8399382130 ps
CPU time 11.54 seconds
Started May 16 03:19:42 PM PDT 24
Finished May 16 03:19:58 PM PDT 24
Peak memory 204920 kb
Host smart-92dd5247-d8b7-4bb9-840c-7b0f6fa0fb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17522
19144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1752219144
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.1184103582
Short name T651
Test name
Test status
Simulation time 8418860227 ps
CPU time 10.82 seconds
Started May 16 03:19:45 PM PDT 24
Finished May 16 03:20:01 PM PDT 24
Peak memory 204740 kb
Host smart-7eb09446-0345-418e-b161-28cb6e91f192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11841
03582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.1184103582
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1221970134
Short name T484
Test name
Test status
Simulation time 8373069726 ps
CPU time 11.5 seconds
Started May 16 03:19:42 PM PDT 24
Finished May 16 03:19:59 PM PDT 24
Peak memory 204796 kb
Host smart-442364e6-c77b-47ba-9738-1f4345a9b8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12219
70134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1221970134
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.983702607
Short name T1386
Test name
Test status
Simulation time 8377587824 ps
CPU time 11.58 seconds
Started May 16 03:19:42 PM PDT 24
Finished May 16 03:19:58 PM PDT 24
Peak memory 204820 kb
Host smart-8ad5ed8a-56c7-4573-af4e-3986253b8f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98370
2607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.983702607
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3031892804
Short name T1222
Test name
Test status
Simulation time 20617377153 ps
CPU time 34.94 seconds
Started May 16 03:19:34 PM PDT 24
Finished May 16 03:20:13 PM PDT 24
Peak memory 204812 kb
Host smart-283cfe67-dd98-45f5-9f72-7110305fae29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30318
92804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3031892804
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2205479243
Short name T1385
Test name
Test status
Simulation time 8428035805 ps
CPU time 12.28 seconds
Started May 16 03:19:33 PM PDT 24
Finished May 16 03:19:50 PM PDT 24
Peak memory 204824 kb
Host smart-ce786e4c-a7a6-425a-9d6c-73e52aab05f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22054
79243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2205479243
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2344851374
Short name T711
Test name
Test status
Simulation time 8396090098 ps
CPU time 10.91 seconds
Started May 16 03:19:34 PM PDT 24
Finished May 16 03:19:50 PM PDT 24
Peak memory 204880 kb
Host smart-4a777ba3-2e99-4922-9df5-54009fb05d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23448
51374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2344851374
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1740231550
Short name T1614
Test name
Test status
Simulation time 8399759970 ps
CPU time 11.69 seconds
Started May 16 03:19:33 PM PDT 24
Finished May 16 03:19:49 PM PDT 24
Peak memory 204816 kb
Host smart-c70125e3-1dbe-4296-8cd1-378e09fcf105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17402
31550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1740231550
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2740606554
Short name T961
Test name
Test status
Simulation time 8372315839 ps
CPU time 13.28 seconds
Started May 16 03:19:39 PM PDT 24
Finished May 16 03:19:57 PM PDT 24
Peak memory 204840 kb
Host smart-502e0c52-4a60-4835-b0c1-223cbaca0ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27406
06554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2740606554
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3879333865
Short name T1698
Test name
Test status
Simulation time 8380145729 ps
CPU time 11.45 seconds
Started May 16 03:19:46 PM PDT 24
Finished May 16 03:20:03 PM PDT 24
Peak memory 204748 kb
Host smart-70143d26-9cd5-4909-9c25-4d192a23713b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38793
33865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3879333865
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.2880316031
Short name T1577
Test name
Test status
Simulation time 8364735222 ps
CPU time 13.12 seconds
Started May 16 03:19:36 PM PDT 24
Finished May 16 03:19:54 PM PDT 24
Peak memory 204852 kb
Host smart-84882d66-b39e-4b4b-bc57-bc3f084bc368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28803
16031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.2880316031
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2105632961
Short name T727
Test name
Test status
Simulation time 8412220087 ps
CPU time 12.46 seconds
Started May 16 03:19:34 PM PDT 24
Finished May 16 03:19:50 PM PDT 24
Peak memory 204892 kb
Host smart-acd4982d-99af-4867-a8f7-be21aae90763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21056
32961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2105632961
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3983991456
Short name T1534
Test name
Test status
Simulation time 8397619089 ps
CPU time 11.44 seconds
Started May 16 03:19:42 PM PDT 24
Finished May 16 03:19:58 PM PDT 24
Peak memory 204868 kb
Host smart-ac2df737-d823-4275-83af-a20daf4eb895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39839
91456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3983991456
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1905146970
Short name T798
Test name
Test status
Simulation time 8389687655 ps
CPU time 11.06 seconds
Started May 16 03:19:36 PM PDT 24
Finished May 16 03:19:53 PM PDT 24
Peak memory 204832 kb
Host smart-9054d251-2b2d-44a3-bb5a-f8ccb942096d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19051
46970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1905146970
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.4074236732
Short name T1188
Test name
Test status
Simulation time 8472067754 ps
CPU time 12.24 seconds
Started May 16 03:19:53 PM PDT 24
Finished May 16 03:20:17 PM PDT 24
Peak memory 204900 kb
Host smart-7231aa9e-610c-4bfc-9528-b9c89095608c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4074236732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.4074236732
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.3869979309
Short name T1138
Test name
Test status
Simulation time 8374392085 ps
CPU time 11.07 seconds
Started May 16 03:19:55 PM PDT 24
Finished May 16 03:20:17 PM PDT 24
Peak memory 204812 kb
Host smart-91575bb5-91ca-400b-8d95-d99633cd6726
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3869979309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.3869979309
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.948639971
Short name T1294
Test name
Test status
Simulation time 8458487531 ps
CPU time 11.04 seconds
Started May 16 03:19:52 PM PDT 24
Finished May 16 03:20:15 PM PDT 24
Peak memory 204780 kb
Host smart-9dceee17-ce83-47b9-8cde-524d5ce09092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94863
9971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.948639971
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2215764572
Short name T1174
Test name
Test status
Simulation time 8381321061 ps
CPU time 11.13 seconds
Started May 16 03:19:40 PM PDT 24
Finished May 16 03:19:56 PM PDT 24
Peak memory 204748 kb
Host smart-6c3e36c8-885f-48e8-b8d6-e51a8a8b2b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22157
64572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2215764572
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1638816104
Short name T1047
Test name
Test status
Simulation time 8369645831 ps
CPU time 12.38 seconds
Started May 16 03:19:40 PM PDT 24
Finished May 16 03:19:57 PM PDT 24
Peak memory 204876 kb
Host smart-1f941fe4-12fb-4fd7-8e83-bedeb3a14d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16388
16104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1638816104
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2119640363
Short name T740
Test name
Test status
Simulation time 9135028171 ps
CPU time 11.84 seconds
Started May 16 03:19:44 PM PDT 24
Finished May 16 03:20:01 PM PDT 24
Peak memory 204948 kb
Host smart-6469feae-8f04-47f9-a48c-3029f7eb7ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21196
40363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2119640363
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.5865336
Short name T734
Test name
Test status
Simulation time 8375311061 ps
CPU time 11.56 seconds
Started May 16 03:19:44 PM PDT 24
Finished May 16 03:20:00 PM PDT 24
Peak memory 204844 kb
Host smart-caa7a66b-c1a2-47f4-b9c7-423d9e19887d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58653
36 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.5865336
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2470113270
Short name T701
Test name
Test status
Simulation time 8374928626 ps
CPU time 11.1 seconds
Started May 16 03:19:40 PM PDT 24
Finished May 16 03:19:56 PM PDT 24
Peak memory 204848 kb
Host smart-a196bfcb-e1a3-4658-9d7f-109d5b8c2abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24701
13270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2470113270
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1050887995
Short name T806
Test name
Test status
Simulation time 9091253902 ps
CPU time 12.35 seconds
Started May 16 03:19:42 PM PDT 24
Finished May 16 03:20:00 PM PDT 24
Peak memory 204724 kb
Host smart-c29c3539-a1ea-4024-a86e-6707e9f90457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10508
87995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1050887995
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2246857856
Short name T374
Test name
Test status
Simulation time 8576803740 ps
CPU time 13.8 seconds
Started May 16 03:19:41 PM PDT 24
Finished May 16 03:19:59 PM PDT 24
Peak memory 204816 kb
Host smart-0532bc8e-9c83-4329-b3f0-f413b8f663ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22468
57856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2246857856
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2522385820
Short name T786
Test name
Test status
Simulation time 8403679839 ps
CPU time 11.33 seconds
Started May 16 03:19:51 PM PDT 24
Finished May 16 03:20:13 PM PDT 24
Peak memory 204696 kb
Host smart-5797c3e2-8137-4213-9e46-ee394a89b029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
85820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2522385820
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.629224834
Short name T719
Test name
Test status
Simulation time 8426707246 ps
CPU time 13.88 seconds
Started May 16 03:19:52 PM PDT 24
Finished May 16 03:20:18 PM PDT 24
Peak memory 204864 kb
Host smart-67fe23f2-5908-4ae5-9fb5-050197390aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62922
4834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.629224834
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.559244728
Short name T1436
Test name
Test status
Simulation time 8381751467 ps
CPU time 11.83 seconds
Started May 16 03:19:44 PM PDT 24
Finished May 16 03:20:01 PM PDT 24
Peak memory 204880 kb
Host smart-b9eac174-860c-47b5-87f1-99a75afef1b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55924
4728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.559244728
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.4150690698
Short name T1237
Test name
Test status
Simulation time 8405678803 ps
CPU time 13.32 seconds
Started May 16 03:19:43 PM PDT 24
Finished May 16 03:20:01 PM PDT 24
Peak memory 204716 kb
Host smart-b0ec3049-ecae-450a-827e-704c923a6e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41506
90698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.4150690698
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1995117822
Short name T661
Test name
Test status
Simulation time 11550826122 ps
CPU time 14.84 seconds
Started May 16 03:19:40 PM PDT 24
Finished May 16 03:20:00 PM PDT 24
Peak memory 204820 kb
Host smart-4571d64b-8e2d-4789-84aa-fbc4bb3725ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19951
17822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1995117822
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2201356231
Short name T772
Test name
Test status
Simulation time 8415465813 ps
CPU time 11.11 seconds
Started May 16 03:19:43 PM PDT 24
Finished May 16 03:19:59 PM PDT 24
Peak memory 204856 kb
Host smart-213dc678-e7d6-4395-9047-7cead72d5e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22013
56231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2201356231
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2021113248
Short name T1322
Test name
Test status
Simulation time 8374349058 ps
CPU time 11.71 seconds
Started May 16 03:19:43 PM PDT 24
Finished May 16 03:20:00 PM PDT 24
Peak memory 204852 kb
Host smart-2d5cf4cc-034a-4547-919c-17f62b79bf6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20211
13248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2021113248
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.640236656
Short name T142
Test name
Test status
Simulation time 8437627143 ps
CPU time 12.32 seconds
Started May 16 03:19:42 PM PDT 24
Finished May 16 03:19:59 PM PDT 24
Peak memory 204924 kb
Host smart-598e54b4-a729-487c-9c98-e49a2471a013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64023
6656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.640236656
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3146040280
Short name T884
Test name
Test status
Simulation time 8420097080 ps
CPU time 11.46 seconds
Started May 16 03:19:43 PM PDT 24
Finished May 16 03:19:59 PM PDT 24
Peak memory 204752 kb
Host smart-85262133-035d-4072-b670-843c29f1013d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31460
40280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3146040280
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1731234716
Short name T534
Test name
Test status
Simulation time 8384606142 ps
CPU time 11.45 seconds
Started May 16 03:19:43 PM PDT 24
Finished May 16 03:19:59 PM PDT 24
Peak memory 204868 kb
Host smart-0b19cbbf-7ed5-4494-b66a-cbcb9f5c6b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17312
34716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1731234716
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.565587813
Short name T959
Test name
Test status
Simulation time 8390962674 ps
CPU time 11.97 seconds
Started May 16 03:19:53 PM PDT 24
Finished May 16 03:20:17 PM PDT 24
Peak memory 204884 kb
Host smart-537e6ac0-82c7-469a-97ef-7a1d26429e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56558
7813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.565587813
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.195548560
Short name T199
Test name
Test status
Simulation time 8379603141 ps
CPU time 12.01 seconds
Started May 16 03:19:51 PM PDT 24
Finished May 16 03:20:14 PM PDT 24
Peak memory 204900 kb
Host smart-33f87224-8f7a-461d-8437-09bb3b2009a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19554
8560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.195548560
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_eop_single_bit_handling.179264513
Short name T474
Test name
Test status
Simulation time 8390201540 ps
CPU time 10.24 seconds
Started May 16 03:19:52 PM PDT 24
Finished May 16 03:20:13 PM PDT 24
Peak memory 204804 kb
Host smart-ee98b5c9-bc78-4e56-8394-faece80ccd38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17926
4513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_eop_single_bit_handling.179264513
Directory /workspace/6.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2925740653
Short name T1597
Test name
Test status
Simulation time 8368230723 ps
CPU time 12.99 seconds
Started May 16 03:19:51 PM PDT 24
Finished May 16 03:20:15 PM PDT 24
Peak memory 204816 kb
Host smart-0de8d9b3-eee3-47bf-9dde-ac52d65e9337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29257
40653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2925740653
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.219276598
Short name T1185
Test name
Test status
Simulation time 8367556335 ps
CPU time 12.42 seconds
Started May 16 03:19:49 PM PDT 24
Finished May 16 03:20:09 PM PDT 24
Peak memory 204820 kb
Host smart-29152631-1058-4be2-8a8b-08d7d1dd87a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21927
6598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.219276598
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3030986033
Short name T552
Test name
Test status
Simulation time 31087284312 ps
CPU time 60.47 seconds
Started May 16 03:19:51 PM PDT 24
Finished May 16 03:21:02 PM PDT 24
Peak memory 204704 kb
Host smart-fd78c431-1742-4c1b-929d-ebceb8c89026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30309
86033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3030986033
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1809892700
Short name T1687
Test name
Test status
Simulation time 8399586592 ps
CPU time 14.2 seconds
Started May 16 03:19:50 PM PDT 24
Finished May 16 03:20:13 PM PDT 24
Peak memory 204876 kb
Host smart-a9c101d6-d5d5-4cca-a086-8beea16e3749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18098
92700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1809892700
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3186097518
Short name T621
Test name
Test status
Simulation time 8423522213 ps
CPU time 11.83 seconds
Started May 16 03:19:52 PM PDT 24
Finished May 16 03:20:15 PM PDT 24
Peak memory 204816 kb
Host smart-f544d2c3-8761-482e-a1ed-55c752097105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31860
97518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3186097518
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.534389653
Short name T1355
Test name
Test status
Simulation time 8400994512 ps
CPU time 12.52 seconds
Started May 16 03:19:53 PM PDT 24
Finished May 16 03:20:17 PM PDT 24
Peak memory 204884 kb
Host smart-ffd70063-580b-4288-bd86-d9e3f793c1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53438
9653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.534389653
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.564319353
Short name T1074
Test name
Test status
Simulation time 8373380225 ps
CPU time 12.68 seconds
Started May 16 03:19:51 PM PDT 24
Finished May 16 03:20:14 PM PDT 24
Peak memory 204896 kb
Host smart-e41cb47e-92a5-4b2f-8a28-79930ae6f983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56431
9353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.564319353
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2887234745
Short name T1543
Test name
Test status
Simulation time 8381406154 ps
CPU time 12.84 seconds
Started May 16 03:19:51 PM PDT 24
Finished May 16 03:20:15 PM PDT 24
Peak memory 204848 kb
Host smart-71bd697f-9f62-4349-a588-4ab8049ee557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28872
34745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2887234745
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1750122652
Short name T665
Test name
Test status
Simulation time 8406690289 ps
CPU time 12.69 seconds
Started May 16 03:19:49 PM PDT 24
Finished May 16 03:20:08 PM PDT 24
Peak memory 204860 kb
Host smart-9fce9861-fac9-4793-82b3-a9b3ff99d48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17501
22652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1750122652
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3052222581
Short name T748
Test name
Test status
Simulation time 8426481392 ps
CPU time 13.02 seconds
Started May 16 03:19:41 PM PDT 24
Finished May 16 03:19:59 PM PDT 24
Peak memory 204796 kb
Host smart-b81df754-0ddf-4331-8e07-1fbf1acfc8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30522
22581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3052222581
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.849283802
Short name T360
Test name
Test status
Simulation time 8421397304 ps
CPU time 11.63 seconds
Started May 16 03:19:51 PM PDT 24
Finished May 16 03:20:12 PM PDT 24
Peak memory 204904 kb
Host smart-b4a54317-9f74-4a9b-a63e-d17f3f7757ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84928
3802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.849283802
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.105615747
Short name T876
Test name
Test status
Simulation time 8405780400 ps
CPU time 13.54 seconds
Started May 16 03:19:50 PM PDT 24
Finished May 16 03:20:11 PM PDT 24
Peak memory 204804 kb
Host smart-ca51140a-6bfe-4d0f-9342-2113848ba1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
5747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.105615747
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.1551193698
Short name T895
Test name
Test status
Simulation time 8470366997 ps
CPU time 11.17 seconds
Started May 16 03:20:00 PM PDT 24
Finished May 16 03:20:22 PM PDT 24
Peak memory 204680 kb
Host smart-b27f6424-865a-472a-9431-cf3323bbaf03
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1551193698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.1551193698
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.2217259066
Short name T866
Test name
Test status
Simulation time 8407275045 ps
CPU time 11.39 seconds
Started May 16 03:19:58 PM PDT 24
Finished May 16 03:20:21 PM PDT 24
Peak memory 204888 kb
Host smart-bef48a59-e689-47fa-8369-67d52aba76e9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2217259066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.2217259066
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.4231702588
Short name T326
Test name
Test status
Simulation time 8463857958 ps
CPU time 13.29 seconds
Started May 16 03:19:59 PM PDT 24
Finished May 16 03:20:23 PM PDT 24
Peak memory 204868 kb
Host smart-5dfece1d-caad-43ee-9549-bd1b94ef66c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42317
02588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.4231702588
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3942372821
Short name T758
Test name
Test status
Simulation time 8377439856 ps
CPU time 12.2 seconds
Started May 16 03:19:52 PM PDT 24
Finished May 16 03:20:16 PM PDT 24
Peak memory 204804 kb
Host smart-7c5c3005-0e11-4206-a8e5-40118ba63ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39423
72821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3942372821
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2084734349
Short name T919
Test name
Test status
Simulation time 8956754029 ps
CPU time 12.71 seconds
Started May 16 03:19:49 PM PDT 24
Finished May 16 03:20:09 PM PDT 24
Peak memory 204896 kb
Host smart-133c0b7a-045b-4dcb-a9da-34d87edc851f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20847
34349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2084734349
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.1402837352
Short name T648
Test name
Test status
Simulation time 8369593169 ps
CPU time 12.45 seconds
Started May 16 03:19:51 PM PDT 24
Finished May 16 03:20:15 PM PDT 24
Peak memory 204824 kb
Host smart-18d7048d-736a-4b27-b2ff-2612ffb69da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14028
37352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1402837352
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2275091991
Short name T393
Test name
Test status
Simulation time 8379003428 ps
CPU time 12.87 seconds
Started May 16 03:19:50 PM PDT 24
Finished May 16 03:20:13 PM PDT 24
Peak memory 204860 kb
Host smart-71b49b95-9cde-4a0e-b6bb-2dbe3198e6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22750
91991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2275091991
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.4183584483
Short name T771
Test name
Test status
Simulation time 9138043172 ps
CPU time 15.07 seconds
Started May 16 03:19:52 PM PDT 24
Finished May 16 03:20:18 PM PDT 24
Peak memory 204820 kb
Host smart-9927babd-e879-4b3e-b4f3-263ed5f9376e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41835
84483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.4183584483
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2944782228
Short name T575
Test name
Test status
Simulation time 8534659081 ps
CPU time 13.42 seconds
Started May 16 03:19:49 PM PDT 24
Finished May 16 03:20:10 PM PDT 24
Peak memory 204848 kb
Host smart-ddd82873-1e11-40e3-86c1-56b8b0295881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29447
82228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2944782228
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3399732892
Short name T1017
Test name
Test status
Simulation time 8432517737 ps
CPU time 11.89 seconds
Started May 16 03:19:59 PM PDT 24
Finished May 16 03:20:22 PM PDT 24
Peak memory 204780 kb
Host smart-35f869b1-8223-4556-bd17-7f25dad55b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33997
32892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3399732892
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.4286824423
Short name T1289
Test name
Test status
Simulation time 8367948306 ps
CPU time 10.5 seconds
Started May 16 03:19:57 PM PDT 24
Finished May 16 03:20:18 PM PDT 24
Peak memory 204804 kb
Host smart-00f78594-5211-4e69-b5ae-3cc82310fc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42868
24423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.4286824423
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3941013555
Short name T1680
Test name
Test status
Simulation time 8446421240 ps
CPU time 12.06 seconds
Started May 16 03:19:51 PM PDT 24
Finished May 16 03:20:13 PM PDT 24
Peak memory 204876 kb
Host smart-2590c8ab-5312-4ce9-b74b-4e38e9a98c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39410
13555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3941013555
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1243854131
Short name T1225
Test name
Test status
Simulation time 8477402510 ps
CPU time 11.81 seconds
Started May 16 03:19:49 PM PDT 24
Finished May 16 03:20:09 PM PDT 24
Peak memory 204756 kb
Host smart-aed7a225-dd3f-4a31-8f60-1a092a0eab56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12438
54131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1243854131
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2575343795
Short name T574
Test name
Test status
Simulation time 11574721698 ps
CPU time 14.26 seconds
Started May 16 03:19:51 PM PDT 24
Finished May 16 03:20:16 PM PDT 24
Peak memory 204888 kb
Host smart-5770aec5-8ed3-4566-9b4b-27b6645f5f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25753
43795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2575343795
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3996725089
Short name T1402
Test name
Test status
Simulation time 8418820033 ps
CPU time 12.14 seconds
Started May 16 03:19:50 PM PDT 24
Finished May 16 03:20:10 PM PDT 24
Peak memory 204808 kb
Host smart-75887198-8913-45b0-8e2d-8d836cd840cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39967
25089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3996725089
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3975921858
Short name T511
Test name
Test status
Simulation time 8373634463 ps
CPU time 13.2 seconds
Started May 16 03:19:52 PM PDT 24
Finished May 16 03:20:16 PM PDT 24
Peak memory 204852 kb
Host smart-afa5b32a-1127-4291-ac85-899b4a01a80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39759
21858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3975921858
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1387691142
Short name T131
Test name
Test status
Simulation time 8411520639 ps
CPU time 11.48 seconds
Started May 16 03:19:50 PM PDT 24
Finished May 16 03:20:10 PM PDT 24
Peak memory 204872 kb
Host smart-1c34cd4e-c4e5-4ff4-9377-012973459a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13876
91142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1387691142
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1836989252
Short name T1535
Test name
Test status
Simulation time 8422532023 ps
CPU time 11.21 seconds
Started May 16 03:19:53 PM PDT 24
Finished May 16 03:20:16 PM PDT 24
Peak memory 204812 kb
Host smart-07014249-4131-49da-aaf5-9a58bc479806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18369
89252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1836989252
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1456796883
Short name T238
Test name
Test status
Simulation time 8418053706 ps
CPU time 11.65 seconds
Started May 16 03:19:50 PM PDT 24
Finished May 16 03:20:11 PM PDT 24
Peak memory 204892 kb
Host smart-18afd2b4-2b75-47a6-9eea-1d17c2e492f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14567
96883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1456796883
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2112234374
Short name T433
Test name
Test status
Simulation time 8413302678 ps
CPU time 11.14 seconds
Started May 16 03:19:48 PM PDT 24
Finished May 16 03:20:07 PM PDT 24
Peak memory 204864 kb
Host smart-0071544a-3b10-4807-a4c2-e7f09b13ef8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21122
34374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2112234374
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1661597938
Short name T183
Test name
Test status
Simulation time 8381214746 ps
CPU time 12.54 seconds
Started May 16 03:20:04 PM PDT 24
Finished May 16 03:20:25 PM PDT 24
Peak memory 204808 kb
Host smart-35788f04-de08-448e-bcc2-6006c1bd5e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16615
97938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1661597938
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.3644988789
Short name T1040
Test name
Test status
Simulation time 8464358556 ps
CPU time 10.63 seconds
Started May 16 03:20:03 PM PDT 24
Finished May 16 03:20:23 PM PDT 24
Peak memory 204772 kb
Host smart-ed8e1928-87df-4517-a77f-3f56877415f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36449
88789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.3644988789
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2280483942
Short name T817
Test name
Test status
Simulation time 8369180511 ps
CPU time 11.36 seconds
Started May 16 03:20:02 PM PDT 24
Finished May 16 03:20:24 PM PDT 24
Peak memory 204828 kb
Host smart-d440f47d-1969-41c2-9c02-a2170697f6f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22804
83942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2280483942
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.428769371
Short name T13
Test name
Test status
Simulation time 8415091600 ps
CPU time 10.92 seconds
Started May 16 03:20:01 PM PDT 24
Finished May 16 03:20:22 PM PDT 24
Peak memory 204852 kb
Host smart-30231253-f174-438d-bd5e-494752605f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42876
9371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.428769371
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.85950910
Short name T528
Test name
Test status
Simulation time 8394160640 ps
CPU time 13.64 seconds
Started May 16 03:19:51 PM PDT 24
Finished May 16 03:20:14 PM PDT 24
Peak memory 204880 kb
Host smart-982d7a26-9d58-46aa-ba80-13da24fde958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85950
910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.85950910
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3751135913
Short name T626
Test name
Test status
Simulation time 8399923868 ps
CPU time 10.75 seconds
Started May 16 03:19:54 PM PDT 24
Finished May 16 03:20:17 PM PDT 24
Peak memory 204804 kb
Host smart-33ceda7b-8187-442e-9d65-303e75441b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37511
35913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3751135913
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.849667840
Short name T109
Test name
Test status
Simulation time 8416083354 ps
CPU time 13.05 seconds
Started May 16 03:19:54 PM PDT 24
Finished May 16 03:20:19 PM PDT 24
Peak memory 204796 kb
Host smart-fdd45345-df65-4630-8999-c66ae5cdb430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84966
7840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.849667840
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.754913829
Short name T690
Test name
Test status
Simulation time 8364309297 ps
CPU time 11.56 seconds
Started May 16 03:20:03 PM PDT 24
Finished May 16 03:20:24 PM PDT 24
Peak memory 204828 kb
Host smart-12ca2ae8-6ae8-4854-8061-ab7cfba3d5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75491
3829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.754913829
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3415981509
Short name T1145
Test name
Test status
Simulation time 8369964823 ps
CPU time 11.61 seconds
Started May 16 03:19:58 PM PDT 24
Finished May 16 03:20:20 PM PDT 24
Peak memory 204840 kb
Host smart-cdb16b40-e538-4688-86ac-826bd6e34e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34159
81509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3415981509
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1207509404
Short name T667
Test name
Test status
Simulation time 8454360217 ps
CPU time 11.13 seconds
Started May 16 03:19:52 PM PDT 24
Finished May 16 03:20:14 PM PDT 24
Peak memory 204880 kb
Host smart-9820cdd9-b40d-4581-abba-aefa8b723d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12075
09404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1207509404
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2502067605
Short name T1125
Test name
Test status
Simulation time 8377565713 ps
CPU time 11.48 seconds
Started May 16 03:19:58 PM PDT 24
Finished May 16 03:20:21 PM PDT 24
Peak memory 204892 kb
Host smart-1b4cf50a-eba2-407f-b6a3-430b0ddf6f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25020
67605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2502067605
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3487380742
Short name T1261
Test name
Test status
Simulation time 8399272559 ps
CPU time 10.84 seconds
Started May 16 03:20:03 PM PDT 24
Finished May 16 03:20:23 PM PDT 24
Peak memory 204848 kb
Host smart-d2fcecf9-0d23-4427-b5f9-c75515a2ab0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34873
80742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3487380742
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.707034409
Short name T576
Test name
Test status
Simulation time 8466319356 ps
CPU time 11.99 seconds
Started May 16 03:20:09 PM PDT 24
Finished May 16 03:20:28 PM PDT 24
Peak memory 204876 kb
Host smart-1dea12da-a53a-45dc-b771-e5269c643fa9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=707034409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.707034409
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.447781809
Short name T1405
Test name
Test status
Simulation time 8408147648 ps
CPU time 13.1 seconds
Started May 16 03:20:06 PM PDT 24
Finished May 16 03:20:27 PM PDT 24
Peak memory 204884 kb
Host smart-6092f761-7755-436a-bb90-7c768e9b958b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=447781809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.447781809
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.3303192036
Short name T1682
Test name
Test status
Simulation time 8429724106 ps
CPU time 11.22 seconds
Started May 16 03:20:08 PM PDT 24
Finished May 16 03:20:27 PM PDT 24
Peak memory 204836 kb
Host smart-f7871a5d-bbd8-44c0-9363-860e87255a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33031
92036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.3303192036
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3733009065
Short name T1655
Test name
Test status
Simulation time 8419634498 ps
CPU time 11.87 seconds
Started May 16 03:19:58 PM PDT 24
Finished May 16 03:20:21 PM PDT 24
Peak memory 204772 kb
Host smart-52fcc5ed-e82a-4464-95a7-ef3d16b8b2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37330
09065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3733009065
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.1824720887
Short name T211
Test name
Test status
Simulation time 9132628503 ps
CPU time 13.7 seconds
Started May 16 03:19:57 PM PDT 24
Finished May 16 03:20:21 PM PDT 24
Peak memory 204896 kb
Host smart-e30570da-be67-4846-b297-fbcd9af580e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18247
20887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1824720887
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.17228833
Short name T524
Test name
Test status
Simulation time 8399694160 ps
CPU time 12.02 seconds
Started May 16 03:19:58 PM PDT 24
Finished May 16 03:20:21 PM PDT 24
Peak memory 204896 kb
Host smart-82af6089-4ace-4179-9ba8-78ccfa97c2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17228
833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.17228833
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3932158738
Short name T1290
Test name
Test status
Simulation time 8381554922 ps
CPU time 11.53 seconds
Started May 16 03:19:59 PM PDT 24
Finished May 16 03:20:21 PM PDT 24
Peak memory 204900 kb
Host smart-e101f5e2-aac5-46bb-86d7-92552c920d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39321
58738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3932158738
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.213120236
Short name T519
Test name
Test status
Simulation time 9153709531 ps
CPU time 13.61 seconds
Started May 16 03:20:02 PM PDT 24
Finished May 16 03:20:26 PM PDT 24
Peak memory 204824 kb
Host smart-cccaff0c-6efb-448f-ba7d-3373506e92c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21312
0236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.213120236
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.4094802123
Short name T794
Test name
Test status
Simulation time 8464277814 ps
CPU time 13.11 seconds
Started May 16 03:19:59 PM PDT 24
Finished May 16 03:20:23 PM PDT 24
Peak memory 204800 kb
Host smart-074ff82e-e887-4785-8d3b-965368022d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40948
02123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.4094802123
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3752799084
Short name T921
Test name
Test status
Simulation time 8382510715 ps
CPU time 11.93 seconds
Started May 16 03:20:06 PM PDT 24
Finished May 16 03:20:26 PM PDT 24
Peak memory 204844 kb
Host smart-04a47294-ced8-42ce-b32b-eabaccd19f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37527
99084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3752799084
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3631952157
Short name T1700
Test name
Test status
Simulation time 8475476898 ps
CPU time 13.36 seconds
Started May 16 03:19:57 PM PDT 24
Finished May 16 03:20:22 PM PDT 24
Peak memory 204848 kb
Host smart-4ae0636d-be60-4048-8884-c1dddce87450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36319
52157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3631952157
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.235690258
Short name T1497
Test name
Test status
Simulation time 8430022798 ps
CPU time 11.19 seconds
Started May 16 03:19:57 PM PDT 24
Finished May 16 03:20:19 PM PDT 24
Peak memory 204864 kb
Host smart-ae377f84-511a-40da-bcaf-1593c5d02f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23569
0258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.235690258
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3303474348
Short name T471
Test name
Test status
Simulation time 11528148744 ps
CPU time 14.57 seconds
Started May 16 03:19:59 PM PDT 24
Finished May 16 03:20:25 PM PDT 24
Peak memory 204872 kb
Host smart-c1d880d4-9eca-49b5-aaec-94f7466a6361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33034
74348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3303474348
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1013378879
Short name T1066
Test name
Test status
Simulation time 8421973367 ps
CPU time 12.16 seconds
Started May 16 03:20:02 PM PDT 24
Finished May 16 03:20:24 PM PDT 24
Peak memory 204856 kb
Host smart-bb1b46e0-61ea-40ba-8302-7631d21f170c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10133
78879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1013378879
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2176317386
Short name T952
Test name
Test status
Simulation time 8409989835 ps
CPU time 12.06 seconds
Started May 16 03:20:02 PM PDT 24
Finished May 16 03:20:24 PM PDT 24
Peak memory 204856 kb
Host smart-e6016cad-d882-4a9a-b348-5fd1a5c85dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21763
17386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2176317386
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1166503559
Short name T1352
Test name
Test status
Simulation time 8393520304 ps
CPU time 12.69 seconds
Started May 16 03:19:58 PM PDT 24
Finished May 16 03:20:21 PM PDT 24
Peak memory 204956 kb
Host smart-de664783-96ff-4cf8-bb5b-a8dfb122fcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11665
03559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1166503559
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3748544601
Short name T722
Test name
Test status
Simulation time 8391224906 ps
CPU time 12.37 seconds
Started May 16 03:19:59 PM PDT 24
Finished May 16 03:20:22 PM PDT 24
Peak memory 204992 kb
Host smart-7aa06ecd-1482-4575-b36d-506885e8ba3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37485
44601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3748544601
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3714253206
Short name T1139
Test name
Test status
Simulation time 8420418960 ps
CPU time 11.42 seconds
Started May 16 03:19:58 PM PDT 24
Finished May 16 03:20:20 PM PDT 24
Peak memory 204872 kb
Host smart-543577a7-40ec-4696-9d26-2f0fc7a1e86f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37142
53206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3714253206
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.4090886052
Short name T217
Test name
Test status
Simulation time 8469144076 ps
CPU time 14.71 seconds
Started May 16 03:20:09 PM PDT 24
Finished May 16 03:20:31 PM PDT 24
Peak memory 204860 kb
Host smart-fdf98a7c-99b4-4c5a-92a9-14e62535ba65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40908
86052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.4090886052
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.2993609346
Short name T1124
Test name
Test status
Simulation time 8424519675 ps
CPU time 13.17 seconds
Started May 16 03:20:07 PM PDT 24
Finished May 16 03:20:28 PM PDT 24
Peak memory 204712 kb
Host smart-a7564d1c-df0b-494b-92d4-a46ab6db4479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29936
09346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.2993609346
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2749746899
Short name T1263
Test name
Test status
Simulation time 8375732440 ps
CPU time 11.94 seconds
Started May 16 03:20:07 PM PDT 24
Finished May 16 03:20:27 PM PDT 24
Peak memory 204820 kb
Host smart-dc8cc779-b704-42f6-84dd-ff9115caf143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27497
46899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2749746899
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1106729797
Short name T1030
Test name
Test status
Simulation time 8361773949 ps
CPU time 13.12 seconds
Started May 16 03:20:07 PM PDT 24
Finished May 16 03:20:28 PM PDT 24
Peak memory 204860 kb
Host smart-83ebb4b9-9194-445e-bf12-dbe194e017a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11067
29797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1106729797
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1022387700
Short name T1354
Test name
Test status
Simulation time 8375851021 ps
CPU time 11.01 seconds
Started May 16 03:19:57 PM PDT 24
Finished May 16 03:20:19 PM PDT 24
Peak memory 204864 kb
Host smart-3bb4b0e0-efcd-42a5-85ba-993c4c71d010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10223
87700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1022387700
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3209938600
Short name T1376
Test name
Test status
Simulation time 8395834193 ps
CPU time 11.13 seconds
Started May 16 03:20:00 PM PDT 24
Finished May 16 03:20:22 PM PDT 24
Peak memory 204824 kb
Host smart-f0706138-708e-4ac3-a4e8-5fa916f23bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32099
38600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3209938600
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2809034550
Short name T940
Test name
Test status
Simulation time 8394183753 ps
CPU time 12.68 seconds
Started May 16 03:19:57 PM PDT 24
Finished May 16 03:20:21 PM PDT 24
Peak memory 204784 kb
Host smart-e926bbe9-2934-4a78-b938-8180e0dc63e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28090
34550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2809034550
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2906587130
Short name T1499
Test name
Test status
Simulation time 8365562147 ps
CPU time 11.61 seconds
Started May 16 03:20:00 PM PDT 24
Finished May 16 03:20:22 PM PDT 24
Peak memory 204832 kb
Host smart-eb1f4147-fe51-4ac5-8bd0-21336046f3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29065
87130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2906587130
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3056618462
Short name T1199
Test name
Test status
Simulation time 8393974012 ps
CPU time 11.72 seconds
Started May 16 03:20:08 PM PDT 24
Finished May 16 03:20:27 PM PDT 24
Peak memory 204876 kb
Host smart-b712c23e-79c7-4454-a0dd-a221071f4f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30566
18462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3056618462
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1994438968
Short name T47
Test name
Test status
Simulation time 8368389565 ps
CPU time 11.56 seconds
Started May 16 03:20:03 PM PDT 24
Finished May 16 03:20:24 PM PDT 24
Peak memory 204828 kb
Host smart-36dc0be3-6043-4bc1-9275-6993cba0ffb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19944
38968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1994438968
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.516756902
Short name T175
Test name
Test status
Simulation time 8470804723 ps
CPU time 13.92 seconds
Started May 16 03:20:01 PM PDT 24
Finished May 16 03:20:25 PM PDT 24
Peak memory 204828 kb
Host smart-6a56eefa-c87f-49c9-91bc-27080caadd8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51675
6902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.516756902
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2779827149
Short name T1712
Test name
Test status
Simulation time 8385663769 ps
CPU time 11.55 seconds
Started May 16 03:20:00 PM PDT 24
Finished May 16 03:20:22 PM PDT 24
Peak memory 204732 kb
Host smart-2c4f120b-f973-468a-8797-71a552e80935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27798
27149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2779827149
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1396190063
Short name T783
Test name
Test status
Simulation time 8417285814 ps
CPU time 12.22 seconds
Started May 16 03:20:01 PM PDT 24
Finished May 16 03:20:23 PM PDT 24
Peak memory 204820 kb
Host smart-9d67df34-1611-4705-a9a5-dff04d32d106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13961
90063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1396190063
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.2995661747
Short name T423
Test name
Test status
Simulation time 8468201159 ps
CPU time 13.67 seconds
Started May 16 03:20:16 PM PDT 24
Finished May 16 03:20:35 PM PDT 24
Peak memory 204720 kb
Host smart-7c550a6e-28a2-46c3-98f1-47234cc89530
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2995661747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.2995661747
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.1731363548
Short name T591
Test name
Test status
Simulation time 8377502524 ps
CPU time 12.48 seconds
Started May 16 03:20:16 PM PDT 24
Finished May 16 03:20:34 PM PDT 24
Peak memory 204924 kb
Host smart-e62f9562-819d-4a80-9654-123a7c8bbd91
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1731363548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.1731363548
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.1520209579
Short name T1530
Test name
Test status
Simulation time 8402480280 ps
CPU time 12.14 seconds
Started May 16 03:20:17 PM PDT 24
Finished May 16 03:20:35 PM PDT 24
Peak memory 204816 kb
Host smart-2b526d6b-5df8-4006-90e7-e0d3b92bf1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15202
09579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.1520209579
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1452533222
Short name T1395
Test name
Test status
Simulation time 8375117789 ps
CPU time 10.99 seconds
Started May 16 03:20:05 PM PDT 24
Finished May 16 03:20:25 PM PDT 24
Peak memory 204844 kb
Host smart-ed8de4b5-11c6-41d7-a957-fd5ea10d54fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14525
33222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1452533222
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.377229428
Short name T812
Test name
Test status
Simulation time 8384229760 ps
CPU time 13.04 seconds
Started May 16 03:20:07 PM PDT 24
Finished May 16 03:20:28 PM PDT 24
Peak memory 204884 kb
Host smart-29dab8dd-4da4-4edd-b4e8-7d5f4a3b0e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37722
9428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.377229428
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1787586110
Short name T39
Test name
Test status
Simulation time 8994264168 ps
CPU time 11.99 seconds
Started May 16 03:20:06 PM PDT 24
Finished May 16 03:20:26 PM PDT 24
Peak memory 204924 kb
Host smart-0c728c8c-b0cd-4d04-870d-4e012426af80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17875
86110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1787586110
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.69343578
Short name T1105
Test name
Test status
Simulation time 8366936943 ps
CPU time 10.64 seconds
Started May 16 03:20:05 PM PDT 24
Finished May 16 03:20:24 PM PDT 24
Peak memory 204744 kb
Host smart-14bf8d76-2f16-4275-a98a-62abfb382a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69343
578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.69343578
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1260739508
Short name T312
Test name
Test status
Simulation time 8420231622 ps
CPU time 11.41 seconds
Started May 16 03:20:10 PM PDT 24
Finished May 16 03:20:28 PM PDT 24
Peak memory 204876 kb
Host smart-8e2c9448-9ebe-465e-8943-ef7019b01bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12607
39508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1260739508
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3765082654
Short name T619
Test name
Test status
Simulation time 9086013592 ps
CPU time 12.2 seconds
Started May 16 03:20:10 PM PDT 24
Finished May 16 03:20:29 PM PDT 24
Peak memory 204820 kb
Host smart-ba5090ab-22e0-4f08-9b41-c5c15cc01a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37650
82654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3765082654
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2682536183
Short name T1015
Test name
Test status
Simulation time 8410209913 ps
CPU time 12.38 seconds
Started May 16 03:20:10 PM PDT 24
Finished May 16 03:20:29 PM PDT 24
Peak memory 204836 kb
Host smart-ebd67ca8-69ba-46bc-b525-6b392caced24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26825
36183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2682536183
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.768138577
Short name T942
Test name
Test status
Simulation time 8467949564 ps
CPU time 13.59 seconds
Started May 16 03:20:16 PM PDT 24
Finished May 16 03:20:35 PM PDT 24
Peak memory 204860 kb
Host smart-5278edc1-21d3-405e-a491-6ef5e613bd52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76813
8577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.768138577
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1077663221
Short name T1602
Test name
Test status
Simulation time 8371555083 ps
CPU time 11.31 seconds
Started May 16 03:20:17 PM PDT 24
Finished May 16 03:20:34 PM PDT 24
Peak memory 204800 kb
Host smart-4f09a2dc-bf81-47ac-a20b-acd7fe83420b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10776
63221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1077663221
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2424453340
Short name T749
Test name
Test status
Simulation time 8499522292 ps
CPU time 11.1 seconds
Started May 16 03:20:07 PM PDT 24
Finished May 16 03:20:26 PM PDT 24
Peak memory 204800 kb
Host smart-93637cbe-0435-481d-b9cd-473acb355b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24244
53340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2424453340
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3863638844
Short name T1166
Test name
Test status
Simulation time 8402819189 ps
CPU time 12.13 seconds
Started May 16 03:20:08 PM PDT 24
Finished May 16 03:20:28 PM PDT 24
Peak memory 204912 kb
Host smart-cd6f16be-93e8-4605-8ddd-d19b3d08cfcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38636
38844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3863638844
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.748128024
Short name T669
Test name
Test status
Simulation time 11482264624 ps
CPU time 15.43 seconds
Started May 16 03:20:06 PM PDT 24
Finished May 16 03:20:29 PM PDT 24
Peak memory 204808 kb
Host smart-cf6680e1-eafd-485a-9c57-1529ae9822f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74812
8024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.748128024
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3842984697
Short name T501
Test name
Test status
Simulation time 8416986376 ps
CPU time 12.88 seconds
Started May 16 03:20:09 PM PDT 24
Finished May 16 03:20:29 PM PDT 24
Peak memory 204856 kb
Host smart-aea8f203-c59b-4c22-918c-d0500dab4981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38429
84697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3842984697
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3320031324
Short name T797
Test name
Test status
Simulation time 8376021990 ps
CPU time 11.55 seconds
Started May 16 03:20:09 PM PDT 24
Finished May 16 03:20:28 PM PDT 24
Peak memory 204876 kb
Host smart-f8b9fd0a-5807-4af8-b826-2465842baa8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33200
31324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3320031324
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.447417713
Short name T1071
Test name
Test status
Simulation time 8423560592 ps
CPU time 12.57 seconds
Started May 16 03:20:07 PM PDT 24
Finished May 16 03:20:28 PM PDT 24
Peak memory 204884 kb
Host smart-150ff30d-1fb2-4ec1-bdff-1df36f081a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44741
7713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.447417713
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3111033322
Short name T1459
Test name
Test status
Simulation time 8413529739 ps
CPU time 13.37 seconds
Started May 16 03:20:05 PM PDT 24
Finished May 16 03:20:27 PM PDT 24
Peak memory 204792 kb
Host smart-d62d05e7-0128-42d6-819e-8682309cc76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31110
33322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3111033322
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3950591170
Short name T1734
Test name
Test status
Simulation time 8389252418 ps
CPU time 11.35 seconds
Started May 16 03:20:13 PM PDT 24
Finished May 16 03:20:30 PM PDT 24
Peak memory 204760 kb
Host smart-1737da0f-ffb6-4904-9dba-c95c610d98bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39505
91170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3950591170
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.4076513165
Short name T390
Test name
Test status
Simulation time 8384784274 ps
CPU time 10.92 seconds
Started May 16 03:20:15 PM PDT 24
Finished May 16 03:20:32 PM PDT 24
Peak memory 204780 kb
Host smart-1386cd49-b41e-4f7c-ad36-48bd7427ff73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40765
13165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.4076513165
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2489159964
Short name T623
Test name
Test status
Simulation time 8379435791 ps
CPU time 11.97 seconds
Started May 16 03:20:16 PM PDT 24
Finished May 16 03:20:33 PM PDT 24
Peak memory 204836 kb
Host smart-95ef1c5b-98d4-4689-92ea-76aa1f1321c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24891
59964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2489159964
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.2823128543
Short name T1464
Test name
Test status
Simulation time 8421821369 ps
CPU time 10.41 seconds
Started May 16 03:20:15 PM PDT 24
Finished May 16 03:20:31 PM PDT 24
Peak memory 204828 kb
Host smart-26b48a39-19f5-4618-aaf6-fbd2c1899ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28231
28543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.2823128543
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2462651327
Short name T1111
Test name
Test status
Simulation time 8369574411 ps
CPU time 12.17 seconds
Started May 16 03:20:15 PM PDT 24
Finished May 16 03:20:33 PM PDT 24
Peak memory 204812 kb
Host smart-9270f48f-6f1d-4ffc-aeae-5940cf06167b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24626
51327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2462651327
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.424142933
Short name T981
Test name
Test status
Simulation time 8378410313 ps
CPU time 11.5 seconds
Started May 16 03:20:15 PM PDT 24
Finished May 16 03:20:32 PM PDT 24
Peak memory 204788 kb
Host smart-7934b074-bec3-4529-8485-b255cf15b035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42414
2933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.424142933
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.46313614
Short name T1485
Test name
Test status
Simulation time 14183470877 ps
CPU time 26.36 seconds
Started May 16 03:20:14 PM PDT 24
Finished May 16 03:20:46 PM PDT 24
Peak memory 204876 kb
Host smart-67b9ea83-3a3e-49a2-a28f-f5d07f4ecabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46313
614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.46313614
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.333854003
Short name T1281
Test name
Test status
Simulation time 8466700536 ps
CPU time 11.62 seconds
Started May 16 03:20:15 PM PDT 24
Finished May 16 03:20:32 PM PDT 24
Peak memory 204828 kb
Host smart-50d575fd-94cc-452d-a6f2-6d81612fe1c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33385
4003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.333854003
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2914789204
Short name T1721
Test name
Test status
Simulation time 8427595434 ps
CPU time 12.96 seconds
Started May 16 03:20:15 PM PDT 24
Finished May 16 03:20:33 PM PDT 24
Peak memory 204788 kb
Host smart-f07c9bcd-78cd-4f6a-9312-32707de5e59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29147
89204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2914789204
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.258906947
Short name T911
Test name
Test status
Simulation time 8402424574 ps
CPU time 12.85 seconds
Started May 16 03:20:14 PM PDT 24
Finished May 16 03:20:33 PM PDT 24
Peak memory 204728 kb
Host smart-7fb8d43e-63dd-47e7-83d1-617ddda39ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25890
6947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.258906947
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1323024847
Short name T1363
Test name
Test status
Simulation time 8369438207 ps
CPU time 14.38 seconds
Started May 16 03:20:17 PM PDT 24
Finished May 16 03:20:37 PM PDT 24
Peak memory 204896 kb
Host smart-2c093e5c-21f4-4539-97c9-24985e4e2828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13230
24847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1323024847
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.607577685
Short name T477
Test name
Test status
Simulation time 8379894085 ps
CPU time 11.66 seconds
Started May 16 03:20:15 PM PDT 24
Finished May 16 03:20:32 PM PDT 24
Peak memory 204824 kb
Host smart-7f5578b9-4013-4499-b85c-84773097a9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60757
7685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.607577685
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1873701660
Short name T366
Test name
Test status
Simulation time 8374193080 ps
CPU time 11.34 seconds
Started May 16 03:20:14 PM PDT 24
Finished May 16 03:20:31 PM PDT 24
Peak memory 204872 kb
Host smart-a54e722c-9a20-46ec-b425-ec0b8bed3a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18737
01660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1873701660
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1254049298
Short name T1478
Test name
Test status
Simulation time 8409209934 ps
CPU time 10.74 seconds
Started May 16 03:20:06 PM PDT 24
Finished May 16 03:20:25 PM PDT 24
Peak memory 204904 kb
Host smart-d5286b87-209a-4618-9bac-c9f324389819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12540
49298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1254049298
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.613900691
Short name T409
Test name
Test status
Simulation time 8431201873 ps
CPU time 11.28 seconds
Started May 16 03:20:16 PM PDT 24
Finished May 16 03:20:33 PM PDT 24
Peak memory 204888 kb
Host smart-781e4a4c-9b16-424c-a8b3-d4f4fbf97cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61390
0691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.613900691
Directory /workspace/9.usbdev_stall_priority_over_nak/latest
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