Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5182503	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	392678	1		T2	3		T3	4		T4	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5337522	1		T2	2922		T3	2897		T4	2895
values[0x0]	118221	1		T2	1		T3	5		T4	4
values[0x1]	119438	1		T2	5		T3	3		T4	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3886676	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	1688505	1		T2	770		T3	710		T4	765

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32259	1		T2	13		T3	2		T18	7
valid_sources[0x01]	17270	1		T2	19		T3	5		T18	8
valid_sources[0x02]	16616	1		T2	7		T3	7		T18	9
valid_sources[0x03]	16953	1		T2	16		T3	9		T4	7
valid_sources[0x04]	19825	1		T2	11		T3	15		T4	1
valid_sources[0x05]	25441	1		T2	15		T3	6		T4	85
valid_sources[0x06]	21387	1		T2	11		T3	9		T18	9
valid_sources[0x07]	20081	1		T2	8		T3	16		T4	30
valid_sources[0x08]	22958	1		T2	17		T3	6		T18	9
valid_sources[0x09]	23420	1		T2	10		T3	5		T4	13
valid_sources[0x0a]	19853	1		T2	18		T3	17		T18	17
valid_sources[0x0b]	19498	1		T2	8		T3	6		T4	1
valid_sources[0x0c]	16918	1		T2	5		T3	16		T4	54
valid_sources[0x0d]	22924	1		T2	7		T3	11		T18	4
valid_sources[0x0e]	16737	1		T2	12		T3	10		T4	15
valid_sources[0x0f]	28285	1		T2	18		T3	12		T18	9
valid_sources[0x10]	19985	1		T2	17		T3	3		T4	130
valid_sources[0x11]	22611	1		T2	7		T3	8		T18	7
valid_sources[0x12]	20114	1		T2	9		T3	8		T18	18
valid_sources[0x13]	16871	1		T2	22		T3	5		T4	2
valid_sources[0x14]	19127	1		T2	14		T3	6		T18	10
valid_sources[0x15]	25813	1		T2	5		T3	17		T18	4
valid_sources[0x16]	16664	1		T2	11		T3	5		T18	15
valid_sources[0x17]	16390	1		T2	13		T3	8		T18	20
valid_sources[0x18]	19842	1		T2	9		T3	14		T18	29
valid_sources[0x19]	20446	1		T2	9		T3	21		T18	17
valid_sources[0x1a]	19692	1		T2	8		T3	4		T18	13
valid_sources[0x1b]	18345	1		T2	9		T3	9		T4	45
valid_sources[0x1c]	23484	1		T2	14		T3	4		T18	10
valid_sources[0x1d]	16923	1		T2	11		T3	27		T18	12
valid_sources[0x1e]	26062	1		T2	13		T3	20		T4	5
valid_sources[0x1f]	19678	1		T2	11		T3	13		T18	3
valid_sources[0x20]	19929	1		T2	19		T3	17		T18	1
valid_sources[0x21]	26572	1		T2	12		T3	8		T18	14
valid_sources[0x22]	17715	1		T2	5		T3	7		T18	14
valid_sources[0x23]	20076	1		T2	13		T3	6		T4	50
valid_sources[0x24]	19341	1		T2	9		T3	16		T18	21
valid_sources[0x25]	19960	1		T2	7		T3	22		T4	6
valid_sources[0x26]	23777	1		T2	7		T3	13		T4	20
valid_sources[0x27]	20078	1		T2	13		T3	19		T18	2
valid_sources[0x28]	22992	1		T2	7		T3	5		T4	18
valid_sources[0x29]	17208	1		T2	5		T3	17		T18	19
valid_sources[0x2a]	22301	1		T2	11		T3	11		T18	23
valid_sources[0x2b]	16619	1		T2	7		T3	13		T18	1
valid_sources[0x2c]	26079	1		T2	6		T3	15		T4	25
valid_sources[0x2d]	17214	1		T2	11		T3	11		T18	11
valid_sources[0x2e]	22739	1		T2	16		T3	14		T18	5
valid_sources[0x2f]	23723	1		T2	14		T3	16		T18	5
valid_sources[0x30]	17293	1		T2	24		T3	14		T4	45
valid_sources[0x31]	19749	1		T2	18		T3	9		T18	27
valid_sources[0x32]	19640	1		T2	11		T3	11		T18	7
valid_sources[0x33]	22286	1		T2	7		T3	9		T4	33
valid_sources[0x34]	26215	1		T2	12		T3	4		T4	88
valid_sources[0x35]	16671	1		T2	2		T3	18		T18	16
valid_sources[0x36]	19596	1		T2	16		T3	15		T18	5
valid_sources[0x37]	22549	1		T2	14		T3	16		T18	1
valid_sources[0x38]	23580	1		T2	10		T3	8		T18	9
valid_sources[0x39]	29312	1		T2	6		T3	11		T4	27
valid_sources[0x3a]	23104	1		T2	10		T3	13		T18	13
valid_sources[0x3b]	17381	1		T2	12		T3	7		T18	3
valid_sources[0x3c]	20079	1		T2	20		T3	11		T18	15
valid_sources[0x3d]	34938	1		T2	9		T3	16		T4	9
valid_sources[0x3e]	19898	1		T2	13		T3	10		T18	13
valid_sources[0x3f]	19459	1		T2	15		T3	11		T18	6
valid_sources[0x40]	16891	1		T2	16		T3	24		T18	7
valid_sources[0x41]	28843	1		T2	18		T3	11		T4	24
valid_sources[0x42]	19968	1		T2	9		T3	8		T18	22
valid_sources[0x43]	16935	1		T2	16		T3	13		T4	4
valid_sources[0x44]	23164	1		T2	9		T3	7		T18	2
valid_sources[0x45]	16701	1		T2	14		T3	18		T4	7
valid_sources[0x46]	16515	1		T2	3		T3	14		T18	14
valid_sources[0x47]	17119	1		T2	17		T3	7		T4	6
valid_sources[0x48]	20501	1		T2	6		T3	7		T4	6
valid_sources[0x49]	22347	1		T2	14		T3	3		T18	31
valid_sources[0x4a]	23474	1		T2	11		T3	3		T4	6
valid_sources[0x4b]	23072	1		T2	12		T3	4		T4	50
valid_sources[0x4c]	28680	1		T2	11		T3	26		T18	8
valid_sources[0x4d]	19660	1		T2	7		T3	14		T18	10
valid_sources[0x4e]	16852	1		T2	8		T3	17		T18	1
valid_sources[0x4f]	25734	1		T2	16		T3	16		T4	5
valid_sources[0x50]	19358	1		T2	4		T3	11		T18	5
valid_sources[0x51]	28859	1		T2	35		T3	16		T18	5
valid_sources[0x52]	20152	1		T2	11		T3	9		T18	11
valid_sources[0x53]	16544	1		T2	11		T3	15		T18	10
valid_sources[0x54]	16881	1		T2	5		T3	11		T18	16
valid_sources[0x55]	19233	1		T2	5		T3	9		T18	2
valid_sources[0x56]	22605	1		T2	18		T3	7		T4	50
valid_sources[0x57]	33145	1		T2	18		T3	13		T18	17
valid_sources[0x58]	23211	1		T2	8		T3	12		T18	24
valid_sources[0x59]	26848	1		T2	17		T3	5		T4	7
valid_sources[0x5a]	22968	1		T2	19		T3	6		T18	18
valid_sources[0x5b]	20093	1		T2	12		T3	6		T18	8
valid_sources[0x5c]	20707	1		T2	8		T3	7		T18	18
valid_sources[0x5d]	23114	1		T2	12		T3	17		T4	51
valid_sources[0x5e]	22940	1		T2	11		T3	8		T4	69
valid_sources[0x5f]	20250	1		T2	10		T3	16		T18	8
valid_sources[0x60]	16602	1		T2	6		T3	13		T4	97
valid_sources[0x61]	26031	1		T2	7		T3	9		T19	5
valid_sources[0x62]	22581	1		T2	11		T3	9		T18	25
valid_sources[0x63]	19592	1		T2	8		T3	8		T4	84
valid_sources[0x64]	26350	1		T2	20		T3	8		T18	12
valid_sources[0x65]	16290	1		T2	10		T3	15		T18	8
valid_sources[0x66]	22726	1		T2	8		T3	19		T18	5
valid_sources[0x67]	19764	1		T2	10		T3	16		T4	14
valid_sources[0x68]	19667	1		T2	5		T3	11		T18	16
valid_sources[0x69]	19455	1		T2	25		T3	8		T4	5
valid_sources[0x6a]	19578	1		T2	14		T3	16		T18	10
valid_sources[0x6b]	22726	1		T2	16		T3	11		T18	10
valid_sources[0x6c]	19775	1		T2	14		T3	2		T4	22
valid_sources[0x6d]	20339	1		T2	9		T3	12		T18	3
valid_sources[0x6e]	22439	1		T2	15		T3	13		T18	11
valid_sources[0x6f]	16991	1		T2	14		T3	23		T18	10
valid_sources[0x70]	20292	1		T2	8		T3	8		T18	5
valid_sources[0x71]	22597	1		T2	7		T3	22		T18	1
valid_sources[0x72]	20352	1		T2	6		T3	7		T18	26
valid_sources[0x73]	22099	1		T2	23		T3	15		T4	25
valid_sources[0x74]	23825	1		T2	2		T3	12		T18	8
valid_sources[0x75]	19830	1		T2	17		T3	10		T18	12
valid_sources[0x76]	23620	1		T2	14		T3	16		T4	34
valid_sources[0x77]	26164	1		T2	11		T3	21		T4	52
valid_sources[0x78]	23079	1		T2	9		T3	9		T18	8
valid_sources[0x79]	25199	1		T2	12		T3	16		T4	27
valid_sources[0x7a]	25449	1		T2	14		T3	11		T18	15
valid_sources[0x7b]	25819	1		T2	23		T3	8		T18	27
valid_sources[0x7c]	25664	1		T2	8		T3	13		T4	16
valid_sources[0x7d]	19647	1		T2	12		T3	2		T18	22
valid_sources[0x7e]	20270	1		T2	8		T3	9		T18	4
valid_sources[0x7f]	20286	1		T2	19		T3	18		T18	22
valid_sources[0x80]	20246	1		T2	12		T3	8		T18	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

207577

1

T2

1

T17

2

T18

2

values[0x0]

all_enables

biggest_size

96817

1

T2

1

T3

3

T4

2

values[0x1]

all_enables

biggest_size

88284

1

T2

1

T3

1

T4

1