Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	5196971	1		T2	2925		T3	2901		T4	2900
full_word	393672	1		T2	3		T3	4		T4	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5590323	1		T2	2928		T3	2905		T4	2903
auto[TlIntgErrCmd]	111	1		T65	4		T118	6		T218	4
auto[TlIntgErrData]	104	1		T65	1		T118	8		T218	3
auto[TlIntgErrBoth]	105	1		T65	5		T118	6		T218	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5339362	1		T2	2922		T3	2897		T4	2895
auto[1]	251281	1		T2	6		T3	8		T4	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5131463	1		T2	2921		T3	2897		T4	2895
auto[TlIntgErrNone]	partial	auto[1]	65218	1		T2	4		T3	4		T4	5
auto[TlIntgErrNone]	full_word	auto[0]	207747	1		T2	1		T17	2		T18	2
auto[TlIntgErrNone]	full_word	auto[1]	185895	1		T2	2		T3	4		T4	3
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T65	1		T118	3		T218	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T65	2		T118	2		T218	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T65	1		T218	1		T290	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T118	1		T292	1		T264	1
auto[TlIntgErrData]	partial	auto[0]	49	1		T118	5		T218	2		T228	3
auto[TlIntgErrData]	partial	auto[1]	45	1		T65	1		T118	3		T218	1
auto[TlIntgErrData]	full_word	auto[0]	7	1		T228	2		T215	2		T290	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T264	1		T293	1		T294	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T65	3		T118	2		T228	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T65	2		T118	3		T218	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T118	1		T266	1		T295	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T295	1		T294	2		-	-