Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.84	93.83	70.15	93.58		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	719528728	12607	0	0
ep_in_enable_rd_A	719528728	3869	0	0
ep_out_enable_rd_A	719528728	3805	0	0
in_iso_rd_A	719528728	4087	0	0
intr_enable_rd_A	719528728	5448	0	0
out_iso_rd_A	719528728	4220	0	0
phy_config_rd_A	719528728	2583	0	0
phy_pins_drive_rd_A	719528728	3366	0	0
rxenable_setup_rd_A	719528728	3824	0	0
set_nak_out_rd_A	719528728	4267	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	12607	0	0
T59	13226	775	0	0
T60	3543	7	0	0
T61	4045	22	0	0
T65	11020	2	0	0
T117	3719	6	0	0
T118	23451	5	0	0
T120	3043	7	0	0
T217	8082	492	0	0
T220	6093	168	0	0
T227	4115	6	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	3869	0	0
T63	5142	13	0	0
T64	4271	42	0	0
T214	7852	48	0	0
T228	45683	577	0	0
T245	4338	14	0	0
T253	3982	5	0	0
T262	16466	315	0	0
T263	5284	16	0	0
T264	36415	484	0	0
T265	7134	62	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	3805	0	0
T59	13226	6	0	0
T63	5142	9	0	0
T64	4271	29	0	0
T214	7852	12	0	0
T227	4115	36	0	0
T228	45683	566	0	0
T245	4338	89	0	0
T253	3982	92	0	0
T262	16466	99	0	0
T263	5284	10	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	4087	0	0
T64	4271	31	0	0
T214	7852	42	0	0
T228	45683	548	0	0
T245	4338	9	0	0
T253	3982	86	0	0
T262	16466	237	0	0
T263	5284	22	0	0
T264	36415	462	0	0
T265	7134	10	0	0
T266	30932	330	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	5448	0	0
T63	5142	23	0	0
T64	4271	24	0	0
T70	3043	30	0	0
T72	1399	6	0	0
T214	7852	59	0	0
T217	8082	7	0	0
T227	4115	8	0	0
T228	45683	698	0	0
T262	16466	456	0	0
T267	1689	24	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	4220	0	0
T63	5142	8	0	0
T64	4271	11	0	0
T214	7852	34	0	0
T227	4115	14	0	0
T228	45683	482	0	0
T243	3280	55	0	0
T245	4338	54	0	0
T253	3982	33	0	0
T262	16466	269	0	0
T263	5284	40	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	2583	0	0
T63	5142	8	0	0
T214	7852	28	0	0
T228	45683	285	0	0
T243	3280	39	0	0
T245	4338	25	0	0
T253	3982	18	0	0
T262	16466	92	0	0
T263	5284	44	0	0
T264	36415	290	0	0
T268	11848	2	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	3366	0	0
T63	5142	12	0	0
T64	4271	6	0	0
T214	7852	2	0	0
T228	45683	330	0	0
T243	3280	12	0	0
T245	4338	42	0	0
T253	3982	19	0	0
T262	16466	176	0	0
T263	5284	18	0	0
T269	11962	7	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	3824	0	0
T63	5142	4	0	0
T64	4271	34	0	0
T214	7852	35	0	0
T227	4115	18	0	0
T228	45683	600	0	0
T243	3280	37	0	0
T245	4338	46	0	0
T253	3982	48	0	0
T262	16466	174	0	0
T263	5284	12	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	4267	0	0
T63	5142	14	0	0
T64	4271	46	0	0
T214	7852	3	0	0
T227	4115	29	0	0
T228	45683	475	0	0
T245	4338	50	0	0
T253	3982	10	0	0
T262	16466	361	0	0
T263	5284	17	0	0
T264	36415	679	0	0