Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.84	93.83	70.15	93.58		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.84	93.83	70.15	93.58		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.84	93.83	70.15	93.58		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T29,T45

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T29,T45

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T29,T45
1	1	0	Not Covered
1	1	1	Covered	T2,T29,T45

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T29,T45
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	717951266	589045	0	0
DepthKnown_A	717951266	717819167	0	0
RvalidKnown_A	717951266	717819167	0	0
WreadyKnown_A	717951266	717819167	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	717951266	589045	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	589045	0	0
T2	402367	560	0	0
T3	403716	0	0	0
T4	401928	0	0	0
T17	402799	0	0	0
T18	401964	0	0	0
T19	403093	0	0	0
T20	404380	0	0	0
T21	403014	0	0	0
T22	403060	0	0	0
T23	401879	0	0	0
T29	0	558	0	0
T42	0	2610	0	0
T45	0	559	0	0
T49	0	1681	0	0
T50	0	568	0	0
T66	0	564	0	0
T91	0	556	0	0
T112	0	545	0	0
T113	0	546	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	589045	0	0
T2	402367	560	0	0
T3	403716	0	0	0
T4	401928	0	0	0
T17	402799	0	0	0
T18	401964	0	0	0
T19	403093	0	0	0
T20	404380	0	0	0
T21	403014	0	0	0
T22	403060	0	0	0
T23	401879	0	0	0
T29	0	558	0	0
T42	0	2610	0	0
T45	0	559	0	0
T49	0	1681	0	0
T50	0	568	0	0
T66	0	564	0	0
T91	0	556	0	0
T112	0	545	0	0
T113	0	546	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T3,T4,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T17
1	1	0	Not Covered
1	1	1	Covered	T3,T17,T19

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T17
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	717951266	20164862	0	0
DepthKnown_A	717951266	717819167	0	0
RvalidKnown_A	717951266	717819167	0	0
WreadyKnown_A	717951266	717819167	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	717951266	20164862	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	20164862	0	0
T3	403716	1781	0	0
T4	401928	1400	0	0
T17	402799	590	0	0
T18	401964	0	0	0
T19	403093	818	0	0
T20	404380	1494	0	0
T21	403014	2409	0	0
T22	403060	556	0	0
T23	401879	300	0	0
T27	403217	303	0	0
T28	0	18674	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	20164862	0	0
T3	403716	1781	0	0
T4	401928	1400	0	0
T17	402799	590	0	0
T18	401964	0	0	0
T19	403093	818	0	0
T20	404380	1494	0	0
T21	403014	2409	0	0
T22	403060	556	0	0
T23	401879	300	0	0
T27	403217	303	0	0
T28	0	18674	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T17
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T22

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	717951266	2023363	0	0
DepthKnown_A	717951266	717819167	0	0
RvalidKnown_A	717951266	717819167	0	0
WreadyKnown_A	717951266	717819167	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	717951266	2023363	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	2023363	0	0
T2	402367	1088	0	0
T3	403716	1483	0	0
T4	401928	0	0	0
T17	402799	98	0	0
T18	401964	0	0	0
T19	403093	102	0	0
T20	404380	2371	0	0
T21	403014	0	0	0
T22	403060	105	0	0
T23	401879	115	0	0
T27	0	1441	0	0
T28	0	1220	0	0
T29	0	203	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	2023363	0	0
T2	402367	1088	0	0
T3	403716	1483	0	0
T4	401928	0	0	0
T17	402799	98	0	0
T18	401964	0	0	0
T19	403093	102	0	0
T20	404380	2371	0	0
T21	403014	0	0	0
T22	403060	105	0	0
T23	401879	115	0	0
T27	0	1441	0	0
T28	0	1220	0	0
T29	0	203	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	719528728	5773421	0	0
DepthKnown_A	719528728	719348331	0	0
RvalidKnown_A	719528728	719348331	0	0
WreadyKnown_A	719528728	719348331	0	0
gen_passthru_fifo.paramCheckPass	1869	1869	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	5773421	0	0
T2	402367	2928	0	0
T3	403716	2905	0	0
T4	401928	2903	0	0
T17	402799	3091	0	0
T18	401964	2970	0	0
T19	403093	2977	0	0
T20	404380	2977	0	0
T21	403014	3088	0	0
T22	403060	2976	0	0
T23	401879	2974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1869	1869	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	719528728	10381566	0	0
DepthKnown_A	719528728	719348331	0	0
RvalidKnown_A	719528728	719348331	0	0
WreadyKnown_A	719528728	719348331	0	0
gen_passthru_fifo.paramCheckPass	1869	1869	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	10381566	0	0
T2	402367	9135	0	0
T3	403716	12540	0	0
T4	401928	12383	0	0
T17	402799	3091	0	0
T18	401964	2970	0	0
T19	403093	2977	0	0
T20	404380	2977	0	0
T21	403014	3088	0	0
T22	403060	2976	0	0
T23	401879	2974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1869	1869	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	719528728	296655	0	0
DepthKnown_A	719528728	719348331	0	0
RvalidKnown_A	719528728	719348331	0	0
WreadyKnown_A	719528728	719348331	0	0
gen_passthru_fifo.paramCheckPass	1869	1869	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	296655	0	0
T8	401967	0	0	0
T14	0	6701	0	0
T15	0	2572	0	0
T22	403060	2	0	0
T23	401879	0	0	0
T27	403217	0	0	0
T28	443635	0	0	0
T29	405468	21	0	0
T45	403543	0	0	0
T52	403584	14	0	0
T66	0	19	0	0
T67	0	2	0	0
T91	402081	0	0	0
T97	403981	0	0	0
T107	0	16	0	0
T108	0	16	0	0
T111	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1869	1869	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	719528728	551859	0	0
DepthKnown_A	719528728	719348331	0	0
RvalidKnown_A	719528728	719348331	0	0
WreadyKnown_A	719528728	719348331	0	0
gen_passthru_fifo.paramCheckPass	1869	1869	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	551859	0	0
T8	401967	0	0	0
T14	0	6701	0	0
T15	0	2572	0	0
T22	403060	2	0	0
T23	401879	0	0	0
T27	403217	0	0	0
T28	443635	0	0	0
T29	405468	50	0	0
T45	403543	0	0	0
T52	403584	14	0	0
T66	0	19	0	0
T67	0	2	0	0
T91	402081	0	0	0
T97	403981	0	0	0
T107	0	16	0	0
T108	0	52	0	0
T111	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1869	1869	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	719528728	5429641	0	0
DepthKnown_A	719528728	719348331	0	0
RvalidKnown_A	719528728	719348331	0	0
WreadyKnown_A	719528728	719348331	0	0
gen_passthru_fifo.paramCheckPass	1869	1869	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	5429641	0	0
T2	402367	2928	0	0
T3	403716	2905	0	0
T4	401928	2903	0	0
T17	402799	3091	0	0
T18	401964	2970	0	0
T19	403093	2977	0	0
T20	404380	2977	0	0
T21	403014	3088	0	0
T22	403060	2974	0	0
T23	401879	2974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1869	1869	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	719528728	9829707	0	0
DepthKnown_A	719528728	719348331	0	0
RvalidKnown_A	719528728	719348331	0	0
WreadyKnown_A	719528728	719348331	0	0
gen_passthru_fifo.paramCheckPass	1869	1869	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	9829707	0	0
T2	402367	9135	0	0
T3	403716	12540	0	0
T4	401928	12383	0	0
T17	402799	3091	0	0
T18	401964	2970	0	0
T19	403093	2977	0	0
T20	404380	2977	0	0
T21	403014	3088	0	0
T22	403060	2974	0	0
T23	401879	2974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719528728	719348331	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1869	1869	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T29,T52
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T22,T29,T52

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T22,T29,T52

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T29,T107,T66
1	1	0	Not Covered
1	1	1	Covered	T22,T29,T52

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T22,T29,T52
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T22,T29,T52

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T22,T29,T52
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	717951266	504247	0	0
DepthKnown_A	717951266	717819167	0	0
RvalidKnown_A	717951266	717819167	0	0
WreadyKnown_A	717951266	717819167	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	717951266	504247	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	504247	0	0
T8	401967	0	0	0
T14	0	6701	0	0
T15	0	2572	0	0
T22	403060	2	0	0
T23	401879	0	0	0
T27	403217	0	0	0
T28	443635	0	0	0
T29	405468	50	0	0
T45	403543	0	0	0
T52	403584	14	0	0
T66	0	19	0	0
T67	0	2	0	0
T91	402081	0	0	0
T97	403981	0	0	0
T107	0	16	0	0
T108	0	52	0	0
T111	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	504247	0	0
T8	401967	0	0	0
T14	0	6701	0	0
T15	0	2572	0	0
T22	403060	2	0	0
T23	401879	0	0	0
T27	403217	0	0	0
T28	443635	0	0	0
T29	405468	50	0	0
T45	403543	0	0	0
T52	403584	14	0	0
T66	0	19	0	0
T67	0	2	0	0
T91	402081	0	0	0
T97	403981	0	0	0
T107	0	16	0	0
T108	0	52	0	0
T111	0	8	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T29,T52
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T22,T29,T52

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T22,T29,T52

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T22,T29,T52

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T22,T29,T52
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T22,T29,T52

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T22,T29,T52
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	717951266	157662	0	0
DepthKnown_A	717951266	717819167	0	0
RvalidKnown_A	717951266	717819167	0	0
WreadyKnown_A	717951266	717819167	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	717951266	157662	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	157662	0	0
T8	401967	0	0	0
T14	0	3941	0	0
T15	0	1484	0	0
T22	403060	2	0	0
T23	401879	0	0	0
T27	403217	0	0	0
T28	443635	0	0	0
T29	405468	17	0	0
T45	403543	0	0	0
T52	403584	14	0	0
T66	0	3	0	0
T67	0	2	0	0
T91	402081	0	0	0
T97	403981	0	0	0
T107	0	16	0	0
T108	0	16	0	0
T111	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	157662	0	0
T8	401967	0	0	0
T14	0	3941	0	0
T15	0	1484	0	0
T22	403060	2	0	0
T23	401879	0	0	0
T27	403217	0	0	0
T28	443635	0	0	0
T29	405468	17	0	0
T45	403543	0	0	0
T52	403584	14	0	0
T66	0	3	0	0
T67	0	2	0	0
T91	402081	0	0	0
T97	403981	0	0	0
T107	0	16	0	0
T108	0	16	0	0
T111	0	8	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T29,T108,T110
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T22,T29,T52

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T22,T29,T52

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T29,T107,T66
1	1	0	Not Covered
1	1	1	Covered	T22,T29,T52

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T22,T29,T52

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T22,T29,T52

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T29,T108,T110
1	0	Covered	T22,T29,T52
1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T22,T29,T52
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T29,T52
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T22,T29,T52

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T22,T29,T52
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	717951266	307128	0	0
DepthKnown_A	717951266	717819167	0	0
RvalidKnown_A	717951266	717819167	0	0
WreadyKnown_A	717951266	717819167	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	717951266	307128	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	307128	0	0
T8	401967	0	0	0
T14	0	3941	0	0
T15	0	1484	0	0
T22	403060	2	0	0
T23	401879	0	0	0
T27	403217	0	0	0
T28	443635	0	0	0
T29	405468	41	0	0
T45	403543	0	0	0
T52	403584	14	0	0
T66	0	3	0	0
T67	0	2	0	0
T91	402081	0	0	0
T97	403981	0	0	0
T107	0	16	0	0
T108	0	52	0	0
T111	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	717819167	0	0
T2	402367	402314	0	0
T3	403716	403629	0	0
T4	401928	401851	0	0
T17	402799	402726	0	0
T18	401964	401904	0	0
T19	403093	403042	0	0
T20	404380	404319	0	0
T21	403014	402946	0	0
T22	403060	403004	0	0
T23	401879	401826	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	717951266	307128	0	0
T8	401967	0	0	0
T14	0	3941	0	0
T15	0	1484	0	0
T22	403060	2	0	0
T23	401879	0	0	0
T27	403217	0	0	0
T28	443635	0	0	0
T29	405468	41	0	0
T45	403543	0	0	0
T52	403584	14	0	0
T66	0	3	0	0
T67	0	2	0	0
T91	402081	0	0	0
T97	403981	0	0	0
T107	0	16	0	0
T108	0	52	0	0
T111	0	8	0	0