Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5062276	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	421603	1		T1	169		T2	22		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5234005	1		T1	3067		T2	2942		T3	2963
values[0x0]	124586	1		T1	41		T2	3		T3	5
values[0x1]	125288	1		T1	36		T2	4		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3798851	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	1685028	1		T1	895		T2	729		T3	738

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16716	1		T1	7		T2	5		T3	13
valid_sources[0x01]	19625	1		T1	22		T2	13		T3	20
valid_sources[0x02]	17187	1		T1	12		T2	14		T3	17
valid_sources[0x03]	19107	1		T1	12		T2	13		T3	9
valid_sources[0x04]	17417	1		T1	15		T2	8		T3	15
valid_sources[0x05]	19459	1		T1	13		T2	13		T3	6
valid_sources[0x06]	26001	1		T1	14		T2	15		T3	10
valid_sources[0x07]	28967	1		T1	14		T2	6		T3	10
valid_sources[0x08]	28370	1		T1	9		T2	9		T3	11
valid_sources[0x09]	20310	1		T1	6		T2	11		T3	14
valid_sources[0x0a]	19750	1		T1	33		T2	15		T3	12
valid_sources[0x0b]	19740	1		T1	12		T2	9		T3	13
valid_sources[0x0c]	25324	1		T1	12		T2	16		T3	7
valid_sources[0x0d]	18691	1		T1	8		T2	19		T3	18
valid_sources[0x0e]	22906	1		T1	13		T2	10		T3	4
valid_sources[0x0f]	16551	1		T1	8		T2	8		T3	8
valid_sources[0x10]	20510	1		T1	24		T2	5		T3	10
valid_sources[0x11]	21829	1		T1	12		T2	11		T3	3
valid_sources[0x12]	26725	1		T1	11		T2	6		T3	7
valid_sources[0x13]	20002	1		T1	13		T2	11		T3	4
valid_sources[0x14]	22737	1		T1	8		T2	13		T3	8
valid_sources[0x15]	17140	1		T1	12		T2	12		T3	15
valid_sources[0x16]	25151	1		T1	11		T2	12		T3	6
valid_sources[0x17]	26163	1		T1	16		T2	8		T3	4
valid_sources[0x18]	16392	1		T1	6		T2	14		T3	13
valid_sources[0x19]	19953	1		T1	15		T2	5		T3	20
valid_sources[0x1a]	22279	1		T1	13		T2	15		T3	10
valid_sources[0x1b]	19608	1		T1	9		T2	8		T3	10
valid_sources[0x1c]	22712	1		T1	7		T2	22		T3	8
valid_sources[0x1d]	19522	1		T1	21		T2	6		T3	15
valid_sources[0x1e]	19609	1		T1	16		T2	12		T3	16
valid_sources[0x1f]	19499	1		T1	8		T2	13		T3	16
valid_sources[0x20]	20163	1		T1	7		T2	5		T3	14
valid_sources[0x21]	23669	1		T1	9		T2	7		T3	13
valid_sources[0x22]	18847	1		T1	21		T2	8		T3	15
valid_sources[0x23]	19475	1		T1	10		T2	12		T3	14
valid_sources[0x24]	19282	1		T1	8		T2	9		T3	16
valid_sources[0x25]	25406	1		T1	5		T2	9		T3	9
valid_sources[0x26]	19393	1		T1	8		T2	13		T3	13
valid_sources[0x27]	22296	1		T1	16		T2	11		T3	14
valid_sources[0x28]	22730	1		T1	7		T2	10		T3	13
valid_sources[0x29]	21202	1		T1	16		T2	26		T3	9
valid_sources[0x2a]	27726	1		T1	8		T2	15		T3	9
valid_sources[0x2b]	25474	1		T1	12		T2	15		T3	7
valid_sources[0x2c]	20337	1		T1	9		T2	12		T3	12
valid_sources[0x2d]	16610	1		T1	12		T2	6		T3	13
valid_sources[0x2e]	18864	1		T1	14		T2	11		T3	9
valid_sources[0x2f]	23100	1		T1	17		T2	8		T3	14
valid_sources[0x30]	22559	1		T1	15		T2	8		T3	13
valid_sources[0x31]	19279	1		T1	11		T2	8		T3	18
valid_sources[0x32]	19261	1		T1	8		T2	12		T3	6
valid_sources[0x33]	20448	1		T1	10		T2	17		T3	12
valid_sources[0x34]	27844	1		T1	15		T2	14		T3	5
valid_sources[0x35]	24868	1		T1	5		T2	14		T3	12
valid_sources[0x36]	19198	1		T1	17		T2	7		T3	8
valid_sources[0x37]	30679	1		T1	14		T2	9		T3	8
valid_sources[0x38]	21795	1		T1	11		T2	7		T3	9
valid_sources[0x39]	19512	1		T1	9		T2	14		T3	11
valid_sources[0x3a]	19211	1		T1	12		T2	14		T3	10
valid_sources[0x3b]	22324	1		T1	16		T2	4		T3	18
valid_sources[0x3c]	24822	1		T1	24		T2	9		T3	8
valid_sources[0x3d]	22553	1		T1	11		T2	11		T3	7
valid_sources[0x3e]	22373	1		T1	8		T2	7		T3	20
valid_sources[0x3f]	26409	1		T1	13		T2	7		T3	9
valid_sources[0x40]	16211	1		T1	12		T2	14		T3	22
valid_sources[0x41]	19212	1		T1	8		T2	4		T3	12
valid_sources[0x42]	22265	1		T1	19		T2	9		T3	4
valid_sources[0x43]	22326	1		T1	12		T2	17		T3	8
valid_sources[0x44]	16713	1		T1	15		T2	6		T3	18
valid_sources[0x45]	25470	1		T1	7		T2	9		T3	8
valid_sources[0x46]	19443	1		T1	18		T2	16		T3	19
valid_sources[0x47]	28167	1		T1	9		T2	6		T3	8
valid_sources[0x48]	22871	1		T1	9		T2	5		T3	18
valid_sources[0x49]	19932	1		T1	17		T2	10		T3	17
valid_sources[0x4a]	25348	1		T1	7		T2	16		T3	12
valid_sources[0x4b]	23372	1		T1	13		T2	17		T3	17
valid_sources[0x4c]	22310	1		T1	9		T2	13		T3	16
valid_sources[0x4d]	17359	1		T1	11		T2	8		T3	10
valid_sources[0x4e]	15288	1		T1	18		T2	6		T3	8
valid_sources[0x4f]	22264	1		T1	15		T2	8		T3	17
valid_sources[0x50]	35074	1		T1	8		T2	18		T3	8
valid_sources[0x51]	19369	1		T1	10		T2	16		T3	12
valid_sources[0x52]	21839	1		T1	16		T2	8		T3	11
valid_sources[0x53]	23053	1		T1	19		T2	21		T3	16
valid_sources[0x54]	19623	1		T1	8		T2	12		T3	19
valid_sources[0x55]	22424	1		T1	11		T2	13		T3	11
valid_sources[0x56]	16907	1		T1	20		T2	15		T3	14
valid_sources[0x57]	19813	1		T1	13		T2	14		T3	11
valid_sources[0x58]	25471	1		T1	21		T2	7		T3	3
valid_sources[0x59]	18955	1		T1	9		T2	13		T3	15
valid_sources[0x5a]	19690	1		T1	11		T2	5		T3	19
valid_sources[0x5b]	25795	1		T1	9		T2	17		T3	15
valid_sources[0x5c]	17166	1		T1	16		T2	14		T3	11
valid_sources[0x5d]	29354	1		T1	9		T2	25		T3	19
valid_sources[0x5e]	16548	1		T1	10		T2	8		T3	16
valid_sources[0x5f]	16995	1		T1	14		T2	16		T3	16
valid_sources[0x60]	20500	1		T1	13		T2	11		T3	10
valid_sources[0x61]	28600	1		T1	11		T2	8		T3	17
valid_sources[0x62]	19464	1		T1	8		T2	8		T3	11
valid_sources[0x63]	20692	1		T1	9		T2	9		T3	12
valid_sources[0x64]	25651	1		T1	9		T2	16		T3	15
valid_sources[0x65]	16511	1		T1	11		T2	8		T3	7
valid_sources[0x66]	22000	1		T1	11		T2	19		T3	10
valid_sources[0x67]	26163	1		T1	3		T2	8		T3	9
valid_sources[0x68]	22698	1		T1	9		T2	6		T3	8
valid_sources[0x69]	26066	1		T1	18		T2	21		T3	8
valid_sources[0x6a]	20006	1		T1	6		T2	15		T3	12
valid_sources[0x6b]	25609	1		T1	10		T2	11		T3	11
valid_sources[0x6c]	19186	1		T1	15		T2	23		T3	8
valid_sources[0x6d]	25630	1		T1	9		T2	17		T3	6
valid_sources[0x6e]	16784	1		T1	14		T2	19		T3	9
valid_sources[0x6f]	29392	1		T1	6		T2	18		T3	4
valid_sources[0x70]	19234	1		T1	12		T2	7		T3	8
valid_sources[0x71]	28049	1		T1	23		T2	19		T3	8
valid_sources[0x72]	20192	1		T1	16		T2	15		T3	19
valid_sources[0x73]	16062	1		T1	11		T2	13		T3	17
valid_sources[0x74]	22551	1		T1	15		T2	18		T3	11
valid_sources[0x75]	16386	1		T1	14		T2	14		T3	25
valid_sources[0x76]	21348	1		T1	5		T2	9		T3	8
valid_sources[0x77]	25163	1		T1	18		T2	15		T3	11
valid_sources[0x78]	17051	1		T1	15		T2	14		T3	8
valid_sources[0x79]	22346	1		T1	14		T2	12		T3	9
valid_sources[0x7a]	25474	1		T1	11		T2	10		T3	13
valid_sources[0x7b]	22758	1		T1	13		T2	10		T3	7
valid_sources[0x7c]	22594	1		T1	9		T2	10		T3	13
valid_sources[0x7d]	17147	1		T1	9		T2	6		T3	10
valid_sources[0x7e]	16419	1		T1	26		T2	12		T3	6
valid_sources[0x7f]	19472	1		T1	11		T2	15		T3	6
valid_sources[0x80]	23009	1		T1	6		T2	5		T3	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

224418

1

T1

131

T2

19

T3

2

values[0x0]

all_enables

biggest_size

102932

1

T1

26

T2

2

T3

3

values[0x1]

all_enables

biggest_size

94253

1

T1

12

T2

1

T9

2