Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	5078195	1		T1	2975		T2	2927		T3	2967
full_word	422759	1		T1	169		T2	22		T3	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5500684	1		T1	3144		T2	2949		T3	2972
auto[TlIntgErrCmd]	83	1		T75	4		T204	3		T210	5
auto[TlIntgErrData]	100	1		T75	4		T204	3		T210	9
auto[TlIntgErrBoth]	87	1		T75	2		T204	4		T210	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5236167	1		T1	3067		T2	2942		T3	2963
auto[1]	264787	1		T1	77		T2	7		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5011405	1		T1	2936		T2	2923		T3	2961
auto[TlIntgErrNone]	partial	auto[1]	66544	1		T1	39		T2	4		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	224621	1		T1	131		T2	19		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	198114	1		T1	38		T2	3		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T75	3		T204	2		T210	2
auto[TlIntgErrCmd]	partial	auto[1]	34	1		T210	2		T208	2		T245	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T204	1		T210	1		T266	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T75	1		T245	1		T267	1
auto[TlIntgErrData]	partial	auto[0]	57	1		T75	3		T204	2		T210	8
auto[TlIntgErrData]	partial	auto[1]	34	1		T204	1		T210	1		T208	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T75	1		T267	1		T263	2
auto[TlIntgErrData]	full_word	auto[1]	4	1		T245	1		T268	1		T269	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T75	1		T210	4		T208	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T75	1		T204	3		T210	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T270	1		T267	1		T264	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T204	1		T269	1		T207	1