Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.89	94.44	73.13	93.12		93.75	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	706867777	12871	0	0
ep_in_enable_rd_A	706867777	3297	0	0
ep_out_enable_rd_A	706867777	2596	0	0
in_iso_rd_A	706867777	2858	0	0
intr_enable_rd_A	706867777	4051	0	0
out_iso_rd_A	706867777	3066	0	0
phy_config_rd_A	706867777	1902	0	0
phy_pins_drive_rd_A	706867777	2498	0	0
rxenable_setup_rd_A	706867777	3174	0	0
set_nak_out_rd_A	706867777	3208	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706867777	12871	0	0
T76	5524	6	0	0
T77	15227	1158	0	0
T118	6120	23	0	0
T119	3949	6	0	0
T120	6796	21	0	0
T205	8307	19	0	0
T208	9364	3	0	0
T209	7281	600	0	0
T210	47570	5	0	0
T222	11777	18	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706867777	3297	0	0
T75	25510	241	0	0
T76	5524	9	0	0
T81	3410	9	0	0
T210	47570	568	0	0
T222	11777	46	0	0
T223	24839	361	0	0
T241	2637	2	0	0
T245	16244	302	0	0
T246	9130	79	0	0
T247	4977	31	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706867777	2596	0	0
T75	25510	145	0	0
T76	5524	51	0	0
T78	3770	9	0	0
T210	47570	376	0	0
T222	11777	57	0	0
T223	24839	230	0	0
T241	2637	3	0	0
T245	16244	131	0	0
T246	9130	71	0	0
T247	4977	26	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706867777	2858	0	0
T75	25510	293	0	0
T76	5524	4	0	0
T78	3770	8	0	0
T81	3410	2	0	0
T210	47570	569	0	0
T222	11777	59	0	0
T223	24839	136	0	0
T245	16244	200	0	0
T246	9130	41	0	0
T247	4977	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706867777	4051	0	0
T75	25510	331	0	0
T76	5524	4	0	0
T78	3770	2	0	0
T81	3410	2	0	0
T87	1876	19	0	0
T210	47570	723	0	0
T222	11777	93	0	0
T241	2637	63	0	0
T248	2378	17	0	0
T249	2996	12	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706867777	3066	0	0
T75	25510	268	0	0
T76	5524	5	0	0
T78	3770	2	0	0
T81	3410	8	0	0
T210	47570	482	0	0
T222	11777	23	0	0
T223	24839	273	0	0
T241	2637	46	0	0
T245	16244	304	0	0
T246	9130	50	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706867777	1902	0	0
T75	25510	144	0	0
T76	5524	27	0	0
T78	3770	6	0	0
T81	3410	4	0	0
T210	47570	237	0	0
T222	11777	42	0	0
T223	24839	93	0	0
T241	2637	35	0	0
T245	16244	157	0	0
T246	9130	40	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706867777	2498	0	0
T75	25510	193	0	0
T76	5524	3	0	0
T78	3770	2	0	0
T81	3410	2	0	0
T210	47570	378	0	0
T222	11777	22	0	0
T223	24839	103	0	0
T241	2637	1	0	0
T245	16244	202	0	0
T246	9130	80	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706867777	3174	0	0
T75	25510	206	0	0
T76	5524	6	0	0
T81	3410	12	0	0
T210	47570	506	0	0
T222	11777	106	0	0
T223	24839	271	0	0
T241	2637	51	0	0
T245	16244	333	0	0
T246	9130	28	0	0
T247	4977	46	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706867777	3208	0	0
T75	25510	157	0	0
T76	5524	8	0	0
T78	3770	9	0	0
T81	3410	3	0	0
T210	47570	637	0	0
T222	11777	38	0	0
T223	24839	250	0	0
T241	2637	34	0	0
T245	16244	263	0	0
T246	9130	28	0	0