Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6837813	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	462866	1		T1	7		T2	8		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7029619	1		T1	3701		T2	3697		T3	3472
values[0x0]	135073	1		T1	3		T2	2		T3	5
values[0x1]	135987	1		T1	8		T2	9		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5126411	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	2174268	1		T1	964		T2	973		T3	879

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27934	1		T1	12		T2	20		T3	6
valid_sources[0x01]	39010	1		T1	18		T2	9		T3	17
valid_sources[0x02]	29129	1		T1	14		T2	13		T3	18
valid_sources[0x03]	34875	1		T1	12		T2	25		T3	13
valid_sources[0x04]	31873	1		T1	21		T2	13		T3	13
valid_sources[0x05]	29665	1		T1	15		T2	22		T3	11
valid_sources[0x06]	25320	1		T1	17		T2	8		T3	12
valid_sources[0x07]	31292	1		T1	13		T2	14		T3	12
valid_sources[0x08]	28806	1		T1	10		T2	19		T3	18
valid_sources[0x09]	22388	1		T1	15		T2	21		T3	4
valid_sources[0x0a]	25244	1		T1	10		T2	13		T3	9
valid_sources[0x0b]	32736	1		T1	20		T2	14		T3	11
valid_sources[0x0c]	25250	1		T1	14		T2	17		T3	19
valid_sources[0x0d]	25666	1		T1	11		T2	15		T3	11
valid_sources[0x0e]	22992	1		T1	11		T2	19		T3	21
valid_sources[0x0f]	25747	1		T1	17		T2	11		T3	12
valid_sources[0x10]	28640	1		T1	13		T2	13		T3	17
valid_sources[0x11]	21522	1		T1	15		T2	12		T3	7
valid_sources[0x12]	24900	1		T1	10		T2	12		T3	12
valid_sources[0x13]	36429	1		T1	20		T2	14		T3	15
valid_sources[0x14]	31751	1		T1	18		T2	14		T3	16
valid_sources[0x15]	29275	1		T1	10		T2	22		T3	17
valid_sources[0x16]	26463	1		T1	15		T2	11		T3	15
valid_sources[0x17]	35977	1		T1	23		T2	17		T3	11
valid_sources[0x18]	32708	1		T1	13		T2	9		T3	11
valid_sources[0x19]	28525	1		T1	16		T2	10		T3	17
valid_sources[0x1a]	25014	1		T1	14		T2	17		T3	23
valid_sources[0x1b]	26142	1		T1	5		T2	12		T3	11
valid_sources[0x1c]	24556	1		T1	13		T2	17		T3	6
valid_sources[0x1d]	25068	1		T1	10		T2	17		T3	14
valid_sources[0x1e]	33273	1		T1	11		T2	16		T3	10
valid_sources[0x1f]	22239	1		T1	15		T2	17		T3	11
valid_sources[0x20]	27990	1		T1	19		T2	10		T3	14
valid_sources[0x21]	25596	1		T1	15		T2	6		T3	13
valid_sources[0x22]	24831	1		T1	21		T2	11		T3	13
valid_sources[0x23]	32809	1		T1	18		T2	14		T3	16
valid_sources[0x24]	21112	1		T1	14		T2	13		T3	13
valid_sources[0x25]	24231	1		T1	8		T2	12		T3	10
valid_sources[0x26]	24408	1		T1	16		T2	14		T3	14
valid_sources[0x27]	47644	1		T1	12		T2	23		T3	12
valid_sources[0x28]	25846	1		T1	10		T2	13		T3	9
valid_sources[0x29]	33183	1		T1	13		T2	12		T3	16
valid_sources[0x2a]	21512	1		T1	12		T2	10		T3	11
valid_sources[0x2b]	32316	1		T1	18		T2	16		T3	12
valid_sources[0x2c]	46536	1		T1	9		T2	19		T3	16
valid_sources[0x2d]	32662	1		T1	18		T2	14		T3	12
valid_sources[0x2e]	39124	1		T1	20		T2	20		T3	12
valid_sources[0x2f]	40024	1		T1	15		T2	21		T3	9
valid_sources[0x30]	40360	1		T1	11		T2	15		T3	15
valid_sources[0x31]	22843	1		T1	12		T2	16		T3	11
valid_sources[0x32]	28148	1		T1	15		T2	18		T3	9
valid_sources[0x33]	25136	1		T1	18		T2	27		T3	18
valid_sources[0x34]	29121	1		T1	20		T2	14		T3	13
valid_sources[0x35]	24756	1		T1	19		T2	13		T3	16
valid_sources[0x36]	30003	1		T1	16		T2	19		T3	15
valid_sources[0x37]	33102	1		T1	20		T2	9		T3	8
valid_sources[0x38]	24839	1		T1	17		T2	22		T3	12
valid_sources[0x39]	25886	1		T1	10		T2	5		T3	15
valid_sources[0x3a]	21266	1		T1	12		T2	13		T3	16
valid_sources[0x3b]	30355	1		T1	13		T2	14		T3	12
valid_sources[0x3c]	25574	1		T1	19		T2	13		T3	2
valid_sources[0x3d]	22291	1		T1	14		T2	25		T3	18
valid_sources[0x3e]	33383	1		T1	17		T2	8		T3	14
valid_sources[0x3f]	29281	1		T1	11		T2	16		T3	15
valid_sources[0x40]	36031	1		T1	9		T2	9		T3	16
valid_sources[0x41]	28309	1		T1	22		T2	25		T3	12
valid_sources[0x42]	29681	1		T1	15		T2	13		T3	13
valid_sources[0x43]	28820	1		T1	7		T2	14		T3	18
valid_sources[0x44]	29002	1		T1	18		T2	28		T3	13
valid_sources[0x45]	36759	1		T1	19		T2	13		T3	14
valid_sources[0x46]	35926	1		T1	12		T2	9		T3	9
valid_sources[0x47]	28328	1		T1	21		T2	16		T3	20
valid_sources[0x48]	39635	1		T1	25		T2	14		T3	16
valid_sources[0x49]	22467	1		T1	10		T2	19		T3	18
valid_sources[0x4a]	25513	1		T1	11		T2	9		T3	9
valid_sources[0x4b]	36284	1		T1	8		T2	13		T3	11
valid_sources[0x4c]	30281	1		T1	10		T2	15		T3	21
valid_sources[0x4d]	25624	1		T1	13		T2	15		T3	12
valid_sources[0x4e]	22576	1		T1	17		T2	12		T3	14
valid_sources[0x4f]	35807	1		T1	20		T2	20		T3	14
valid_sources[0x50]	24730	1		T1	17		T2	15		T3	15
valid_sources[0x51]	25407	1		T1	14		T2	12		T3	15
valid_sources[0x52]	21195	1		T1	9		T2	9		T3	14
valid_sources[0x53]	28396	1		T1	18		T2	13		T3	10
valid_sources[0x54]	22427	1		T1	12		T2	13		T3	10
valid_sources[0x55]	28468	1		T1	15		T2	13		T3	17
valid_sources[0x56]	33010	1		T1	20		T2	13		T3	11
valid_sources[0x57]	21332	1		T1	10		T2	13		T3	17
valid_sources[0x58]	25812	1		T1	18		T2	13		T3	17
valid_sources[0x59]	21521	1		T1	15		T2	13		T3	12
valid_sources[0x5a]	21294	1		T1	19		T2	4		T3	7
valid_sources[0x5b]	28271	1		T1	14		T2	12		T3	3
valid_sources[0x5c]	25507	1		T1	18		T2	12		T3	24
valid_sources[0x5d]	25082	1		T1	19		T2	16		T3	15
valid_sources[0x5e]	24876	1		T1	15		T2	7		T3	5
valid_sources[0x5f]	28038	1		T1	14		T2	8		T3	16
valid_sources[0x60]	26160	1		T1	16		T2	11		T3	8
valid_sources[0x61]	24319	1		T1	14		T2	18		T3	17
valid_sources[0x62]	35733	1		T1	10		T2	17		T3	11
valid_sources[0x63]	25574	1		T1	18		T2	15		T3	11
valid_sources[0x64]	30174	1		T1	15		T2	16		T3	14
valid_sources[0x65]	26041	1		T1	21		T2	21		T3	17
valid_sources[0x66]	25530	1		T1	10		T2	15		T3	15
valid_sources[0x67]	25271	1		T1	18		T2	11		T3	11
valid_sources[0x68]	32612	1		T1	15		T2	8		T3	11
valid_sources[0x69]	25429	1		T1	22		T2	14		T3	18
valid_sources[0x6a]	24899	1		T1	12		T2	24		T3	13
valid_sources[0x6b]	34460	1		T1	23		T2	13		T3	12
valid_sources[0x6c]	25207	1		T1	14		T2	10		T3	11
valid_sources[0x6d]	36938	1		T1	20		T2	12		T3	19
valid_sources[0x6e]	39672	1		T1	17		T2	10		T3	15
valid_sources[0x6f]	28573	1		T1	14		T2	15		T3	23
valid_sources[0x70]	24803	1		T1	9		T2	14		T3	17
valid_sources[0x71]	21702	1		T1	13		T2	18		T3	11
valid_sources[0x72]	28706	1		T1	11		T2	8		T3	15
valid_sources[0x73]	25199	1		T1	15		T2	12		T3	12
valid_sources[0x74]	28647	1		T1	21		T2	12		T3	18
valid_sources[0x75]	21385	1		T1	18		T2	11		T3	17
valid_sources[0x76]	25572	1		T1	16		T2	22		T3	14
valid_sources[0x77]	24801	1		T1	10		T2	20		T3	19
valid_sources[0x78]	33267	1		T1	12		T2	14		T3	15
valid_sources[0x79]	33592	1		T1	16		T2	8		T3	13
valid_sources[0x7a]	25234	1		T1	14		T2	20		T3	20
valid_sources[0x7b]	25798	1		T1	8		T2	12		T3	16
valid_sources[0x7c]	36350	1		T1	18		T2	15		T3	8
valid_sources[0x7d]	29150	1		T1	12		T2	19		T3	8
valid_sources[0x7e]	21403	1		T1	7		T2	17		T3	15
valid_sources[0x7f]	32429	1		T1	15		T2	9		T3	10
valid_sources[0x80]	36871	1		T1	15		T2	13		T3	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

247873

1

T1

1

T26

1

T23

1

values[0x0]

all_enables

biggest_size

112254

1

T1

2

T2

2

T3

5

values[0x1]

all_enables

biggest_size

102739

1

T1

4

T2

6

T26

1