Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	6851879	1		T1	3705		T2	3700		T3	3474
full_word	463814	1		T1	7		T2	8		T3	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7315383	1		T1	3712		T2	3708		T3	3479
auto[TlIntgErrCmd]	107	1		T199	7		T223	2		T224	8
auto[TlIntgErrData]	98	1		T199	4		T223	4		T224	4
auto[TlIntgErrBoth]	105	1		T199	9		T223	4		T224	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	7031416	1		T1	3701		T2	3697		T3	3472
auto[1]	284277	1		T1	11		T2	11		T3	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6783217	1		T1	3700		T2	3697		T3	3472
auto[TlIntgErrNone]	partial	auto[1]	68374	1		T1	5		T2	3		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	248041	1		T1	1		T26	1		T23	1
auto[TlIntgErrNone]	full_word	auto[1]	215751	1		T1	6		T2	8		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T199	3		T223	1		T224	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T199	3		T223	1		T224	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T282	1		T283	2		T284	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T199	1		T285	1		T286	1
auto[TlIntgErrData]	partial	auto[0]	54	1		T199	2		T223	2		T224	2
auto[TlIntgErrData]	partial	auto[1]	36	1		T223	2		T224	2		T287	1
auto[TlIntgErrData]	full_word	auto[0]	7	1		T199	1		T287	1		T288	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T199	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	49	1		T199	6		T223	1		T224	5
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T199	3		T223	2		T224	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T223	1		T224	1		T289	2