Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	968132179	11297	0	0
ep_in_enable_rd_A	968132179	1897	0	0
ep_out_enable_rd_A	968132179	2529	0	0
in_iso_rd_A	968132179	2010	0	0
intr_enable_rd_A	968132179	2975	0	0
out_iso_rd_A	968132179	2186	0	0
phy_config_rd_A	968132179	1421	0	0
phy_pins_drive_rd_A	968132179	1852	0	0
rxenable_setup_rd_A	968132179	2020	0	0
set_nak_out_rd_A	968132179	2305	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	11297	0	0
T199	43738	7	0	0
T200	4944	14	0	0
T201	3598	375	0	0
T220	4903	628	0	0
T223	47464	6	0	0
T225	4622	25	0	0
T226	8895	489	0	0
T230	8883	360	0	0
T233	5320	15	0	0
T236	4309	21	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	1897	0	0
T207	3155	5	0	0
T254	18682	170	0	0
T255	56680	195	0	0
T259	4600	24	0	0
T269	5555	38	0	0
T273	5612	14	0	0
T274	5207	7	0	0
T275	47793	193	0	0
T276	46723	440	0	0
T277	3679	2	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	2529	0	0
T207	3155	4	0	0
T254	18682	160	0	0
T255	56680	257	0	0
T259	4600	61	0	0
T269	5555	46	0	0
T273	5612	1	0	0
T274	5207	56	0	0
T275	47793	239	0	0
T276	46723	498	0	0
T277	3679	39	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	2010	0	0
T207	3155	8	0	0
T254	18682	167	0	0
T255	56680	255	0	0
T259	4600	2	0	0
T269	5555	18	0	0
T273	5612	5	0	0
T274	5207	55	0	0
T275	47793	243	0	0
T276	46723	537	0	0
T277	3679	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	2975	0	0
T99	1522	8	0	0
T206	1903	36	0	0
T207	3155	3	0	0
T254	18682	179	0	0
T269	5555	25	0	0
T273	5612	7	0	0
T278	5052	9	0	0
T279	3138	32	0	0
T280	2244	2	0	0
T281	2592	21	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	2186	0	0
T207	3155	3	0	0
T254	18682	155	0	0
T255	56680	228	0	0
T259	4600	18	0	0
T269	5555	20	0	0
T273	5612	75	0	0
T274	5207	11	0	0
T275	47793	173	0	0
T276	46723	561	0	0
T277	3679	42	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	1421	0	0
T207	3155	5	0	0
T254	18682	175	0	0
T255	56680	235	0	0
T259	4600	21	0	0
T269	5555	20	0	0
T273	5612	20	0	0
T274	5207	12	0	0
T275	47793	89	0	0
T276	46723	300	0	0
T277	3679	28	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	1852	0	0
T207	3155	5	0	0
T254	18682	185	0	0
T255	56680	241	0	0
T259	4600	31	0	0
T269	5555	27	0	0
T273	5612	17	0	0
T274	5207	41	0	0
T275	47793	182	0	0
T276	46723	425	0	0
T277	3679	22	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	2020	0	0
T207	3155	1	0	0
T254	18682	203	0	0
T255	56680	213	0	0
T259	4600	22	0	0
T269	5555	17	0	0
T273	5612	11	0	0
T274	5207	12	0	0
T275	47793	209	0	0
T276	46723	414	0	0
T277	3679	5	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	2305	0	0
T207	3155	1	0	0
T254	18682	197	0	0
T255	56680	210	0	0
T259	4600	7	0	0
T269	5555	14	0	0
T273	5612	2	0	0
T274	5207	41	0	0
T275	47793	353	0	0
T276	46723	602	0	0
T277	3679	36	0	0