Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T78,T79,T80
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T19,T45,T63

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T19,T45,T63

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T19,T45,T63
1	1	0	Not Covered
1	1	1	Covered	T19,T45,T63

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T19,T45,T63
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	966443363	570035	0	0
DepthKnown_A	966443363	966296424	0	0
RvalidKnown_A	966443363	966296424	0	0
WreadyKnown_A	966443363	966296424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	966443363	570035	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	570035	0	0
T8	638644	0	0	0
T19	486480	566	0	0
T24	636521	0	0	0
T25	485702	0	0	0
T45	0	1471	0	0
T63	0	556	0	0
T64	481961	0	0	0
T67	482667	0	0	0
T77	483761	0	0	0
T78	0	6651	0	0
T79	0	1308	0	0
T81	483973	0	0	0
T82	483479	0	0	0
T86	482532	0	0	0
T87	0	1572	0	0
T88	0	570	0	0
T89	0	553	0	0
T90	0	576	0	0
T91	0	745	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	570035	0	0
T8	638644	0	0	0
T19	486480	566	0	0
T24	636521	0	0	0
T25	485702	0	0	0
T45	0	1471	0	0
T63	0	556	0	0
T64	481961	0	0	0
T67	482667	0	0	0
T77	483761	0	0	0
T78	0	6651	0	0
T79	0	1308	0	0
T81	483973	0	0	0
T82	483479	0	0	0
T86	482532	0	0	0
T87	0	1572	0	0
T88	0	570	0	0
T89	0	553	0	0
T90	0	576	0	0
T91	0	745	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T78,T79,T80
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T26

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T26

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T26
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	966443363	23835150	0	0
DepthKnown_A	966443363	966296424	0	0
RvalidKnown_A	966443363	966296424	0	0
WreadyKnown_A	966443363	966296424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	966443363	23835150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	23835150	0	0
T1	634861	1935	0	0
T2	484120	1322	0	0
T3	482253	0	0	0
T4	636554	1000	0	0
T5	634348	599	0	0
T6	637129	830	0	0
T7	0	344	0	0
T14	484792	3250	0	0
T15	482460	1091	0	0
T23	484215	2562	0	0
T26	483980	1012	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	23835150	0	0
T1	634861	1935	0	0
T2	484120	1322	0	0
T3	482253	0	0	0
T4	636554	1000	0	0
T5	634348	599	0	0
T6	637129	830	0	0
T7	0	344	0	0
T14	484792	3250	0	0
T15	482460	1091	0	0
T23	484215	2562	0	0
T26	483980	1012	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	966443363	2293054	0	0
DepthKnown_A	966443363	966296424	0	0
RvalidKnown_A	966443363	966296424	0	0
WreadyKnown_A	966443363	966296424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	966443363	2293054	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	2293054	0	0
T1	634861	98	0	0
T2	484120	2172	0	0
T3	482253	0	0	0
T4	636554	108	0	0
T5	634348	103	0	0
T6	637129	101	0	0
T7	0	106	0	0
T8	0	105	0	0
T14	484792	0	0	0
T15	482460	0	0	0
T18	0	103	0	0
T19	0	206	0	0
T23	484215	0	0	0
T26	483980	0	0	0
T67	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	2293054	0	0
T1	634861	98	0	0
T2	484120	2172	0	0
T3	482253	0	0	0
T4	636554	108	0	0
T5	634348	103	0	0
T6	637129	101	0	0
T7	0	106	0	0
T8	0	105	0	0
T14	484792	0	0	0
T15	482460	0	0	0
T18	0	103	0	0
T19	0	206	0	0
T23	484215	0	0	0
T26	483980	0	0	0
T67	0	95	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	968132179	7604141	0	0
DepthKnown_A	968132179	967933379	0	0
RvalidKnown_A	968132179	967933379	0	0
WreadyKnown_A	968132179	967933379	0	0
gen_passthru_fifo.paramCheckPass	2039	2039	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	7604141	0	0
T1	634861	3712	0	0
T2	484120	3708	0	0
T3	482253	3479	0	0
T4	636554	3683	0	0
T5	634348	3673	0	0
T6	637129	3573	0	0
T14	484792	3706	0	0
T15	482460	3512	0	0
T23	484215	3704	0	0
T26	483980	3568	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2039	2039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T23	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	968132179	13724158	0	0
DepthKnown_A	968132179	967933379	0	0
RvalidKnown_A	968132179	967933379	0	0
WreadyKnown_A	968132179	967933379	0	0
gen_passthru_fifo.paramCheckPass	2039	2039	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	13724158	0	0
T1	634861	3712	0	0
T2	484120	3708	0	0
T3	482253	14961	0	0
T4	636554	3683	0	0
T5	634348	3673	0	0
T6	637129	11445	0	0
T14	484792	3706	0	0
T15	482460	10948	0	0
T23	484215	3704	0	0
T26	483980	3568	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2039	2039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T23	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	968132179	352670	0	0
DepthKnown_A	968132179	967933379	0	0
RvalidKnown_A	968132179	967933379	0	0
WreadyKnown_A	968132179	967933379	0	0
gen_passthru_fifo.paramCheckPass	2039	2039	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	352670	0	0
T8	638644	0	0	0
T18	484056	12	0	0
T19	486480	26	0	0
T24	636521	0	0	0
T25	485702	0	0	0
T63	0	26	0	0
T64	481961	0	0	0
T67	482667	2	0	0
T73	0	16	0	0
T77	483761	0	0	0
T81	483973	2	0	0
T82	483479	3	0	0
T83	0	2	0	0
T84	0	100	0	0
T85	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2039	2039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T23	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	968132179	641618	0	0
DepthKnown_A	968132179	967933379	0	0
RvalidKnown_A	968132179	967933379	0	0
WreadyKnown_A	968132179	967933379	0	0
gen_passthru_fifo.paramCheckPass	2039	2039	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	641618	0	0
T8	638644	0	0	0
T18	484056	44	0	0
T19	486480	26	0	0
T24	636521	0	0	0
T25	485702	0	0	0
T63	0	26	0	0
T64	481961	0	0	0
T67	482667	16	0	0
T73	0	71	0	0
T77	483761	0	0	0
T81	483973	2	0	0
T82	483479	3	0	0
T83	0	2	0	0
T84	0	100	0	0
T85	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2039	2039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T23	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	968132179	7196217	0	0
DepthKnown_A	968132179	967933379	0	0
RvalidKnown_A	968132179	967933379	0	0
WreadyKnown_A	968132179	967933379	0	0
gen_passthru_fifo.paramCheckPass	2039	2039	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	7196217	0	0
T1	634861	3712	0	0
T2	484120	3708	0	0
T3	482253	3479	0	0
T4	636554	3683	0	0
T5	634348	3673	0	0
T6	637129	3573	0	0
T14	484792	3706	0	0
T15	482460	3512	0	0
T23	484215	3704	0	0
T26	483980	3568	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2039	2039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T23	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	968132179	13082540	0	0
DepthKnown_A	968132179	967933379	0	0
RvalidKnown_A	968132179	967933379	0	0
WreadyKnown_A	968132179	967933379	0	0
gen_passthru_fifo.paramCheckPass	2039	2039	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	13082540	0	0
T1	634861	3712	0	0
T2	484120	3708	0	0
T3	482253	14961	0	0
T4	636554	3683	0	0
T5	634348	3673	0	0
T6	637129	11445	0	0
T14	484792	3706	0	0
T15	482460	10948	0	0
T23	484215	3704	0	0
T26	483980	3568	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2039	2039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T23	1	1	0	0
T26	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T67
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T19,T67

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T18,T19,T67

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T18,T67,T73
1	1	0	Not Covered
1	1	1	Covered	T18,T19,T67

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T18,T19,T67
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T18,T19,T67

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T67
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	966443363	605040	0	0
DepthKnown_A	966443363	966296424	0	0
RvalidKnown_A	966443363	966296424	0	0
WreadyKnown_A	966443363	966296424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	966443363	605040	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	605040	0	0
T8	638644	0	0	0
T18	484056	44	0	0
T19	486480	26	0	0
T24	636521	0	0	0
T25	485702	0	0	0
T63	0	26	0	0
T64	481961	0	0	0
T67	482667	16	0	0
T73	0	71	0	0
T77	483761	0	0	0
T81	483973	2	0	0
T82	483479	3	0	0
T83	0	2	0	0
T84	0	100	0	0
T85	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	605040	0	0
T8	638644	0	0	0
T18	484056	44	0	0
T19	486480	26	0	0
T24	636521	0	0	0
T25	485702	0	0	0
T63	0	26	0	0
T64	481961	0	0	0
T67	482667	16	0	0
T73	0	71	0	0
T77	483761	0	0	0
T81	483973	2	0	0
T82	483479	3	0	0
T83	0	2	0	0
T84	0	100	0	0
T85	0	2	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T67
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T19,T67

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T18,T19,T67

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T18,T19,T67

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T18,T19,T67
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T18,T19,T67

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T67
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	966443363	193026	0	0
DepthKnown_A	966443363	966296424	0	0
RvalidKnown_A	966443363	966296424	0	0
WreadyKnown_A	966443363	966296424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	966443363	193026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	193026	0	0
T8	638644	0	0	0
T18	484056	12	0	0
T19	486480	17	0	0
T24	636521	0	0	0
T25	485702	0	0	0
T63	0	18	0	0
T64	481961	0	0	0
T67	482667	2	0	0
T73	0	16	0	0
T77	483761	0	0	0
T81	483973	2	0	0
T82	483479	3	0	0
T83	0	2	0	0
T84	0	100	0	0
T85	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	193026	0	0
T8	638644	0	0	0
T18	484056	12	0	0
T19	486480	17	0	0
T24	636521	0	0	0
T25	485702	0	0	0
T63	0	18	0	0
T64	481961	0	0	0
T67	482667	2	0	0
T73	0	16	0	0
T77	483761	0	0	0
T81	483973	2	0	0
T82	483479	3	0	0
T83	0	2	0	0
T84	0	100	0	0
T85	0	2	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T67,T73
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T19,T67

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T18,T19,T67

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T18,T67,T73
1	1	0	Not Covered
1	1	1	Covered	T18,T19,T67

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T19,T67

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T19,T67

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T67,T73
1	0	Covered	T18,T19,T67
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T18,T19,T67
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T67
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T18,T19,T67

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T67
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	966443363	367661	0	0
DepthKnown_A	966443363	966296424	0	0
RvalidKnown_A	966443363	966296424	0	0
WreadyKnown_A	966443363	966296424	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	966443363	367661	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	367661	0	0
T8	638644	0	0	0
T18	484056	44	0	0
T19	486480	17	0	0
T24	636521	0	0	0
T25	485702	0	0	0
T63	0	18	0	0
T64	481961	0	0	0
T67	482667	16	0	0
T73	0	71	0	0
T77	483761	0	0	0
T81	483973	2	0	0
T82	483479	3	0	0
T83	0	2	0	0
T84	0	100	0	0
T85	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	966296424	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	966443363	367661	0	0
T8	638644	0	0	0
T18	484056	44	0	0
T19	486480	17	0	0
T24	636521	0	0	0
T25	485702	0	0	0
T63	0	18	0	0
T64	481961	0	0	0
T67	482667	16	0	0
T73	0	71	0	0
T77	483761	0	0	0
T81	483973	2	0	0
T82	483479	3	0	0
T83	0	2	0	0
T84	0	100	0	0
T85	0	2	0	0