Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wake_events_cdc	68.40	94.12	46.15			83.33	50.00
tb.dut.u_reg.u_wake_control_cdc	97.73	100.00	90.91			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wake_events_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.40	94.12	46.15			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.94	90.62	52.94			84.21	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.47	99.76	98.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	82.08	89.80	57.14			81.40	100.00
u_src_to_dst_req	56.41	92.31	33.33			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_wake_control_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	96.08	96.43			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.47	99.76	98.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.88	87.50	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1936264358	353749	0	0
DstReqKnown_A	23288138	23250134	0	0
SrcAckBusyChk_A	1936264358	1205	0	0
SrcBusyKnown_A	1936264358	1935866758	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1936264358	353749	0	0
T4	636554	499	0	0
T5	634348	469	0	0
T6	637129	330	0	0
T7	633980	325	0	0
T8	0	751	0	0
T9	0	262	0	0
T10	0	374	0	0
T11	0	321	0	0
T12	0	267	0	0
T13	0	340	0	0
T14	484792	0	0	0
T15	482460	0	0	0
T16	482137	0	0	0
T17	485256	0	0	0
T18	484056	0	0	0
T19	486480	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23288138	23250134	0	0
T1	19706	19688	0	0
T2	19182	19166	0	0
T3	9904	9894	0	0
T4	13340	13328	0	0
T5	15276	15262	0	0
T6	19352	19340	0	0
T14	12664	12642	0	0
T15	12944	12930	0	0
T23	9542	9530	0	0
T26	5040	5026	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1936264358	1205	0	0
T4	636554	2	0	0
T5	634348	2	0	0
T6	637129	2	0	0
T7	633980	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	484792	0	0	0
T15	482460	0	0	0
T16	482137	0	0	0
T17	485256	0	0	0
T18	484056	0	0	0
T19	486480	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1936264358	1935866758	0	0
T1	1269722	1269588	0	0
T2	968240	968082	0	0
T3	964506	964364	0	0
T4	1273108	1272908	0	0
T5	1268696	1268574	0	0
T6	1274258	1274104	0	0
T14	969584	969456	0	0
T15	964920	964816	0	0
T23	968430	968284	0	0
T26	967960	967802	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	65	0	0
ALWAYS	71	5	4	80.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	7	7	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65		unreachable
71	1	1
72	1	1
73	1	1
74		unreachable
75	1	1
76	0	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123		unreachable
124		unreachable
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150		unreachable
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Total	Covered	Percent
Conditions	13	6	46.15
Logical	13	6	46.15
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	71	3	2	66.67
IF	115	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	968132179	0	0	0
DstReqKnown_A	11644069	11625067	0	0
SrcAckBusyChk_A	968132179	0	0	0
SrcBusyKnown_A	968132179	967933379	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11644069	11625067	0	0
T1	9853	9844	0	0
T2	9591	9583	0	0
T3	4952	4947	0	0
T4	6670	6664	0	0
T5	7638	7631	0	0
T6	9676	9670	0	0
T14	6332	6321	0	0
T15	6472	6465	0	0
T23	4771	4765	0	0
T26	2520	2513	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T4,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	968132179	353749	0	0
DstReqKnown_A	11644069	11625067	0	0
SrcAckBusyChk_A	968132179	1205	0	0
SrcBusyKnown_A	968132179	967933379	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	353749	0	0
T4	636554	499	0	0
T5	634348	469	0	0
T6	637129	330	0	0
T7	633980	325	0	0
T8	0	751	0	0
T9	0	262	0	0
T10	0	374	0	0
T11	0	321	0	0
T12	0	267	0	0
T13	0	340	0	0
T14	484792	0	0	0
T15	482460	0	0	0
T16	482137	0	0	0
T17	485256	0	0	0
T18	484056	0	0	0
T19	486480	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11644069	11625067	0	0
T1	9853	9844	0	0
T2	9591	9583	0	0
T3	4952	4947	0	0
T4	6670	6664	0	0
T5	7638	7631	0	0
T6	9676	9670	0	0
T14	6332	6321	0	0
T15	6472	6465	0	0
T23	4771	4765	0	0
T26	2520	2513	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	1205	0	0
T4	636554	2	0	0
T5	634348	2	0	0
T6	637129	2	0	0
T7	633980	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	484792	0	0	0
T15	482460	0	0	0
T16	482137	0	0	0
T17	485256	0	0	0
T18	484056	0	0	0
T19	486480	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968132179	967933379	0	0
T1	634861	634794	0	0
T2	484120	484041	0	0
T3	482253	482182	0	0
T4	636554	636454	0	0
T5	634348	634287	0	0
T6	637129	637052	0	0
T14	484792	484728	0	0
T15	482460	482408	0	0
T23	484215	484142	0	0
T26	483980	483901	0	0