Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.56 97.44 92.01 97.86 70.31 95.72 98.17 96.40


Total test records in report: 2039
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T2003 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3918588902 May 23 03:31:58 PM PDT 24 May 23 03:32:02 PM PDT 24 88100365 ps
T2004 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3452057242 May 23 03:32:28 PM PDT 24 May 23 03:32:33 PM PDT 24 74906736 ps
T2005 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1809585174 May 23 03:32:25 PM PDT 24 May 23 03:32:28 PM PDT 24 42165927 ps
T2006 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.638579236 May 23 03:32:23 PM PDT 24 May 23 03:32:26 PM PDT 24 157307906 ps
T2007 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1373187247 May 23 03:32:26 PM PDT 24 May 23 03:32:34 PM PDT 24 883729474 ps
T2008 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3027727184 May 23 03:31:55 PM PDT 24 May 23 03:31:58 PM PDT 24 55525113 ps
T2009 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2589579664 May 23 03:31:57 PM PDT 24 May 23 03:32:02 PM PDT 24 261927370 ps
T2010 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1846562871 May 23 03:32:04 PM PDT 24 May 23 03:32:07 PM PDT 24 66642849 ps
T2011 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1887645106 May 23 03:32:28 PM PDT 24 May 23 03:32:34 PM PDT 24 181606120 ps
T2012 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3723474371 May 23 03:31:54 PM PDT 24 May 23 03:31:57 PM PDT 24 58476210 ps
T2013 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.914112658 May 23 03:31:57 PM PDT 24 May 23 03:32:00 PM PDT 24 67861653 ps
T2014 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1375299857 May 23 03:31:58 PM PDT 24 May 23 03:32:03 PM PDT 24 92781443 ps
T284 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1278129396 May 23 03:32:11 PM PDT 24 May 23 03:32:18 PM PDT 24 1033014478 ps
T2015 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3489935682 May 23 03:32:42 PM PDT 24 May 23 03:32:47 PM PDT 24 38687069 ps
T2016 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1111352931 May 23 03:32:07 PM PDT 24 May 23 03:32:10 PM PDT 24 96436428 ps
T2017 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2142776130 May 23 03:32:29 PM PDT 24 May 23 03:32:35 PM PDT 24 111047855 ps
T2018 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2676844366 May 23 03:32:28 PM PDT 24 May 23 03:32:33 PM PDT 24 42291077 ps
T2019 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1938415780 May 23 03:32:05 PM PDT 24 May 23 03:32:09 PM PDT 24 216944016 ps
T2020 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1958366367 May 23 03:32:11 PM PDT 24 May 23 03:32:14 PM PDT 24 37012883 ps
T2021 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1241632188 May 23 03:32:40 PM PDT 24 May 23 03:32:42 PM PDT 24 38337249 ps
T2022 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.936211346 May 23 03:32:24 PM PDT 24 May 23 03:32:27 PM PDT 24 182257815 ps
T2023 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.295299671 May 23 03:32:27 PM PDT 24 May 23 03:32:34 PM PDT 24 171254843 ps
T2024 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1879984103 May 23 03:32:24 PM PDT 24 May 23 03:32:26 PM PDT 24 37960151 ps
T2025 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.548348083 May 23 03:32:24 PM PDT 24 May 23 03:32:28 PM PDT 24 310498309 ps
T2026 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1307160197 May 23 03:32:27 PM PDT 24 May 23 03:32:32 PM PDT 24 169687554 ps
T2027 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3647168027 May 23 03:32:09 PM PDT 24 May 23 03:32:12 PM PDT 24 217630437 ps
T2028 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3426589160 May 23 03:32:42 PM PDT 24 May 23 03:32:47 PM PDT 24 55479870 ps
T2029 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2309171039 May 23 03:32:05 PM PDT 24 May 23 03:32:07 PM PDT 24 41499076 ps
T2030 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1839281264 May 23 03:31:55 PM PDT 24 May 23 03:31:59 PM PDT 24 180380880 ps
T2031 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.665976141 May 23 03:32:10 PM PDT 24 May 23 03:32:14 PM PDT 24 134450246 ps
T2032 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.871903310 May 23 03:32:40 PM PDT 24 May 23 03:32:43 PM PDT 24 41192497 ps
T2033 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3576751097 May 23 03:32:24 PM PDT 24 May 23 03:32:26 PM PDT 24 52923733 ps
T286 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.101328555 May 23 03:32:11 PM PDT 24 May 23 03:32:16 PM PDT 24 424780848 ps
T2034 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2852634322 May 23 03:31:56 PM PDT 24 May 23 03:32:01 PM PDT 24 105217621 ps
T2035 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.4019446937 May 23 03:32:39 PM PDT 24 May 23 03:32:41 PM PDT 24 98008554 ps
T2036 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.162343565 May 23 03:31:54 PM PDT 24 May 23 03:31:57 PM PDT 24 76874718 ps
T2037 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1495521246 May 23 03:32:12 PM PDT 24 May 23 03:32:17 PM PDT 24 424263469 ps
T2038 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3508959963 May 23 03:32:30 PM PDT 24 May 23 03:32:36 PM PDT 24 45947813 ps
T2039 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1961395065 May 23 03:32:26 PM PDT 24 May 23 03:32:32 PM PDT 24 72098668 ps

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1963667466
Short name T4
Test name
Test status
Simulation time 13261357197 ps
CPU time 19.28 seconds
Started May 23 03:42:24 PM PDT 24
Finished May 23 03:42:51 PM PDT 24
Peak memory 204996 kb
Host smart-a1797cea-67b4-4b7e-b60a-0cedfdc16aa0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1963667466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1963667466
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1924934619
Short name T206
Test name
Test status
Simulation time 39660849 ps
CPU time 0.66 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:53 PM PDT 24
Peak memory 204456 kb
Host smart-53ad46c9-d9ab-4673-9c88-2c4191c67432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1924934619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1924934619
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.926109708
Short name T84
Test name
Test status
Simulation time 10825868826 ps
CPU time 14.69 seconds
Started May 23 03:42:41 PM PDT 24
Finished May 23 03:43:10 PM PDT 24
Peak memory 204960 kb
Host smart-d6a543c8-13d3-4a88-bf2f-3d1968878d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92610
9708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.926109708
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1417223755
Short name T199
Test name
Test status
Simulation time 911219161 ps
CPU time 4.82 seconds
Started May 23 03:31:57 PM PDT 24
Finished May 23 03:32:04 PM PDT 24
Peak memory 204868 kb
Host smart-8823aff7-dfbe-416d-a9fc-cf2a3dba009f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1417223755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1417223755
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/31.usbdev_smoke.602408622
Short name T19
Test name
Test status
Simulation time 10134854249 ps
CPU time 12.85 seconds
Started May 23 03:42:42 PM PDT 24
Finished May 23 03:43:08 PM PDT 24
Peak memory 204936 kb
Host smart-aace6898-be8f-4d91-b38e-1722c9a8b2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60240
8622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.602408622
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.3154077049
Short name T75
Test name
Test status
Simulation time 10111972957 ps
CPU time 13.89 seconds
Started May 23 03:40:56 PM PDT 24
Finished May 23 03:41:20 PM PDT 24
Peak memory 204948 kb
Host smart-8f1983ba-9b1e-4458-a3f2-a9283a66d9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31540
77049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3154077049
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3202854004
Short name T100
Test name
Test status
Simulation time 63549916 ps
CPU time 0.66 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:33 PM PDT 24
Peak memory 204492 kb
Host smart-e3832bd5-f835-4dd9-8c4e-b92da25298a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3202854004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3202854004
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1073454725
Short name T32
Test name
Test status
Simulation time 10091007103 ps
CPU time 13.36 seconds
Started May 23 03:39:58 PM PDT 24
Finished May 23 03:40:21 PM PDT 24
Peak memory 204996 kb
Host smart-54ce79fc-2258-4252-9814-f4bfa26b1ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10734
54725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1073454725
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.4043100707
Short name T2
Test name
Test status
Simulation time 10085694731 ps
CPU time 13.55 seconds
Started May 23 03:42:57 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204940 kb
Host smart-4c4832ed-a360-43f2-bc61-986b2b1caf43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40431
00707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.4043100707
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3665802496
Short name T3
Test name
Test status
Simulation time 10046791206 ps
CPU time 13.34 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:31 PM PDT 24
Peak memory 204980 kb
Host smart-c4003096-a099-4191-a8ed-7a7f1405df67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36658
02496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3665802496
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3133461941
Short name T230
Test name
Test status
Simulation time 185069294 ps
CPU time 1.97 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:30 PM PDT 24
Peak memory 204860 kb
Host smart-45796a2e-4d5e-4f17-8aa7-75592d8cabde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3133461941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3133461941
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3061691230
Short name T96
Test name
Test status
Simulation time 10198290363 ps
CPU time 14.16 seconds
Started May 23 03:40:41 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 205012 kb
Host smart-da052079-65ef-4a67-8f58-6a5315102e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30616
91230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3061691230
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2582445674
Short name T12
Test name
Test status
Simulation time 13265074223 ps
CPU time 16.46 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:43 PM PDT 24
Peak memory 204980 kb
Host smart-e7e1c8f9-76ad-47a2-a876-e660ee86215f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2582445674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2582445674
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3840078676
Short name T28
Test name
Test status
Simulation time 10049501833 ps
CPU time 13.99 seconds
Started May 23 03:42:32 PM PDT 24
Finished May 23 03:42:57 PM PDT 24
Peak memory 204944 kb
Host smart-e2b2d80d-2575-4dc0-975b-957cdb7d2d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38400
78676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3840078676
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.1236075480
Short name T60
Test name
Test status
Simulation time 10618088291 ps
CPU time 14.85 seconds
Started May 23 03:41:46 PM PDT 24
Finished May 23 03:42:06 PM PDT 24
Peak memory 204932 kb
Host smart-cece846a-672a-4cb1-a3b1-bbf918ee5aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12360
75480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.1236075480
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1010144661
Short name T303
Test name
Test status
Simulation time 48406446 ps
CPU time 0.69 seconds
Started May 23 03:32:42 PM PDT 24
Finished May 23 03:32:47 PM PDT 24
Peak memory 204456 kb
Host smart-28d306ad-ff72-4e96-991e-c3057d5ee164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1010144661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1010144661
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1003491712
Short name T254
Test name
Test status
Simulation time 389229792 ps
CPU time 3.41 seconds
Started May 23 03:31:54 PM PDT 24
Finished May 23 03:31:59 PM PDT 24
Peak memory 204712 kb
Host smart-07585b9a-ca86-4cba-9123-7d50ec65eeb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1003491712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1003491712
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.616146532
Short name T69
Test name
Test status
Simulation time 10155960597 ps
CPU time 13.86 seconds
Started May 23 03:43:04 PM PDT 24
Finished May 23 03:43:30 PM PDT 24
Peak memory 204948 kb
Host smart-eeb78fd6-8461-472e-b219-34f0d1560d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61614
6532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.616146532
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.814622097
Short name T196
Test name
Test status
Simulation time 771289083 ps
CPU time 1.6 seconds
Started May 23 03:39:26 PM PDT 24
Finished May 23 03:39:37 PM PDT 24
Peak memory 221860 kb
Host smart-00dc927d-1ce8-4306-9a79-b51a98cffed0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=814622097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.814622097
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.4127294658
Short name T481
Test name
Test status
Simulation time 10202347226 ps
CPU time 14.48 seconds
Started May 23 03:39:22 PM PDT 24
Finished May 23 03:39:46 PM PDT 24
Peak memory 204940 kb
Host smart-314390a1-26d6-4e7f-a283-ed8f5fbaeb7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41272
94658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.4127294658
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1345087145
Short name T38
Test name
Test status
Simulation time 13288259002 ps
CPU time 15.58 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:55 PM PDT 24
Peak memory 204924 kb
Host smart-cb6c57e9-1a5f-4820-94f2-e2da6f8ec869
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1345087145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.1345087145
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.1458456632
Short name T493
Test name
Test status
Simulation time 10066108876 ps
CPU time 14.95 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 204964 kb
Host smart-66f21582-ab8a-4274-8351-b0d8265e1cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14584
56632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1458456632
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3467147546
Short name T297
Test name
Test status
Simulation time 43351844 ps
CPU time 0.75 seconds
Started May 23 03:32:41 PM PDT 24
Finished May 23 03:32:45 PM PDT 24
Peak memory 204520 kb
Host smart-d6395563-bfa7-408a-a53e-d8de9583826d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3467147546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3467147546
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3385919609
Short name T170
Test name
Test status
Simulation time 20343915741 ps
CPU time 34.43 seconds
Started May 23 03:40:56 PM PDT 24
Finished May 23 03:41:40 PM PDT 24
Peak memory 204956 kb
Host smart-423fe506-2cac-43a5-9ecd-05de199b8a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33859
19609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3385919609
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3648906726
Short name T299
Test name
Test status
Simulation time 42869120 ps
CPU time 0.68 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:49 PM PDT 24
Peak memory 204504 kb
Host smart-6a27d118-51c6-4492-84d8-ac0a8bdd5c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3648906726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3648906726
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.235061123
Short name T289
Test name
Test status
Simulation time 668977242 ps
CPU time 5.08 seconds
Started May 23 03:31:57 PM PDT 24
Finished May 23 03:32:04 PM PDT 24
Peak memory 204856 kb
Host smart-0dd48c42-d0d9-4125-874e-7916469c6616
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=235061123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.235061123
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1109074595
Short name T361
Test name
Test status
Simulation time 10100000837 ps
CPU time 13.98 seconds
Started May 23 03:39:47 PM PDT 24
Finished May 23 03:40:06 PM PDT 24
Peak memory 204916 kb
Host smart-436185e2-a1cb-46f5-8dcb-65f8f8840b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11090
74595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1109074595
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1768834336
Short name T439
Test name
Test status
Simulation time 14284834317 ps
CPU time 21.26 seconds
Started May 23 03:39:29 PM PDT 24
Finished May 23 03:39:59 PM PDT 24
Peak memory 204956 kb
Host smart-62e56576-acb0-497b-8838-10318598a66a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1768834336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.1768834336
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2437465746
Short name T218
Test name
Test status
Simulation time 5118482974 ps
CPU time 41.32 seconds
Started May 23 03:39:20 PM PDT 24
Finished May 23 03:40:11 PM PDT 24
Peak memory 204916 kb
Host smart-c63a5261-bd96-4548-bc41-da18afa2985a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24374
65746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2437465746
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3033409561
Short name T271
Test name
Test status
Simulation time 289847640 ps
CPU time 1.82 seconds
Started May 23 03:31:56 PM PDT 24
Finished May 23 03:32:00 PM PDT 24
Peak memory 204892 kb
Host smart-19232e58-4236-4b52-adeb-38ea8643f0b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3033409561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3033409561
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2362034711
Short name T238
Test name
Test status
Simulation time 148170438 ps
CPU time 2.79 seconds
Started May 23 03:32:08 PM PDT 24
Finished May 23 03:32:12 PM PDT 24
Peak memory 204856 kb
Host smart-04b32cb0-73d5-416a-876e-875570142b79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2362034711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2362034711
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3360185462
Short name T283
Test name
Test status
Simulation time 1763888466 ps
CPU time 5.46 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:35 PM PDT 24
Peak memory 204880 kb
Host smart-ddfd05d7-6038-4386-af68-41a941b09d92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3360185462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3360185462
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1642671457
Short name T91
Test name
Test status
Simulation time 10054045387 ps
CPU time 15.19 seconds
Started May 23 03:39:31 PM PDT 24
Finished May 23 03:39:55 PM PDT 24
Peak memory 204976 kb
Host smart-bd17a0c1-373b-4e8b-81f0-2123d651f5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16426
71457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1642671457
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.936499091
Short name T55
Test name
Test status
Simulation time 11028778790 ps
CPU time 17.75 seconds
Started May 23 03:41:40 PM PDT 24
Finished May 23 03:42:05 PM PDT 24
Peak memory 204952 kb
Host smart-4b32d415-fd40-43d8-860f-683a9d450f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93649
9091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.936499091
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3383873537
Short name T227
Test name
Test status
Simulation time 10043992858 ps
CPU time 13.11 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 204960 kb
Host smart-0cfa41c5-d3d3-4c8e-a692-faaff0af6a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33838
73537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3383873537
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.849941640
Short name T486
Test name
Test status
Simulation time 10091163264 ps
CPU time 13.73 seconds
Started May 23 03:39:45 PM PDT 24
Finished May 23 03:40:03 PM PDT 24
Peak memory 204972 kb
Host smart-2242b66d-44bb-4f7f-9b13-1382b977115b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84994
1640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.849941640
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1643466599
Short name T194
Test name
Test status
Simulation time 13224864628 ps
CPU time 17.24 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204948 kb
Host smart-fae3b554-00f4-4c47-9660-59e075a7eac3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1643466599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.1643466599
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2312688650
Short name T1089
Test name
Test status
Simulation time 10097107314 ps
CPU time 13.31 seconds
Started May 23 03:39:25 PM PDT 24
Finished May 23 03:39:48 PM PDT 24
Peak memory 204956 kb
Host smart-c37302a1-b1f1-4d2f-83c6-5877f380e449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23126
88650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2312688650
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2704245013
Short name T139
Test name
Test status
Simulation time 10141756109 ps
CPU time 14.35 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:54 PM PDT 24
Peak memory 205004 kb
Host smart-a4158806-dbc2-4e09-b3c4-e4f25c92e950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27042
45013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2704245013
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.35943444
Short name T142
Test name
Test status
Simulation time 10074193732 ps
CPU time 13.4 seconds
Started May 23 03:40:43 PM PDT 24
Finished May 23 03:41:08 PM PDT 24
Peak memory 204960 kb
Host smart-e53507e2-ec09-420d-82fc-120cf7fa71a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35943
444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.35943444
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2361373214
Short name T190
Test name
Test status
Simulation time 10071271188 ps
CPU time 13.47 seconds
Started May 23 03:40:47 PM PDT 24
Finished May 23 03:41:12 PM PDT 24
Peak memory 204968 kb
Host smart-1582f057-8966-4f0b-a37f-dc354c58ff63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23613
73214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2361373214
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2774452721
Short name T181
Test name
Test status
Simulation time 10086347398 ps
CPU time 14.27 seconds
Started May 23 03:41:10 PM PDT 24
Finished May 23 03:41:33 PM PDT 24
Peak memory 204968 kb
Host smart-60e0350b-5d54-4e05-b04f-47ab39ede462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27744
52721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2774452721
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.279234005
Short name T151
Test name
Test status
Simulation time 10154678086 ps
CPU time 15.93 seconds
Started May 23 03:41:33 PM PDT 24
Finished May 23 03:41:58 PM PDT 24
Peak memory 205016 kb
Host smart-58cdf940-6c69-436a-b551-76ec027e1900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27923
4005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.279234005
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1708856477
Short name T182
Test name
Test status
Simulation time 10084286725 ps
CPU time 15.93 seconds
Started May 23 03:41:47 PM PDT 24
Finished May 23 03:42:09 PM PDT 24
Peak memory 204980 kb
Host smart-64b4a22e-c48b-461c-91b8-c0fc9585d989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17088
56477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1708856477
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2460985745
Short name T187
Test name
Test status
Simulation time 10057145090 ps
CPU time 13.95 seconds
Started May 23 03:42:14 PM PDT 24
Finished May 23 03:42:38 PM PDT 24
Peak memory 204936 kb
Host smart-ab934098-a3e6-4420-abd3-dadd7bebd9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24609
85745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2460985745
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3482739156
Short name T135
Test name
Test status
Simulation time 10054050552 ps
CPU time 12.65 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:01 PM PDT 24
Peak memory 204928 kb
Host smart-66bd26d9-e9ab-4771-9413-af4ac6756da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34827
39156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3482739156
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2545137887
Short name T191
Test name
Test status
Simulation time 10094852640 ps
CPU time 13.68 seconds
Started May 23 03:43:05 PM PDT 24
Finished May 23 03:43:30 PM PDT 24
Peak memory 204960 kb
Host smart-91ac99d0-0f43-405d-8c5f-b216fc3ad193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25451
37887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2545137887
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.980181397
Short name T923
Test name
Test status
Simulation time 11054863219 ps
CPU time 17.61 seconds
Started May 23 03:43:56 PM PDT 24
Finished May 23 03:44:21 PM PDT 24
Peak memory 204980 kb
Host smart-6f4173be-fac1-4460-b574-234f6b7988ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98018
1397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.980181397
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1570403307
Short name T337
Test name
Test status
Simulation time 10052687874 ps
CPU time 15.4 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:55 PM PDT 24
Peak memory 204948 kb
Host smart-5346323a-25d6-4a7d-9b8a-980293ce0dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15704
03307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1570403307
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3936606698
Short name T422
Test name
Test status
Simulation time 10045167598 ps
CPU time 14 seconds
Started May 23 03:39:30 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 205024 kb
Host smart-81314cf8-44cf-430f-92c6-92fbb7982728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39366
06698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3936606698
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3158146072
Short name T47
Test name
Test status
Simulation time 10055823924 ps
CPU time 13.15 seconds
Started May 23 03:39:31 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 204912 kb
Host smart-4bb641fb-0399-4a43-8fd9-731761e6710d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31581
46072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3158146072
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.162343565
Short name T2036
Test name
Test status
Simulation time 76874718 ps
CPU time 1.82 seconds
Started May 23 03:31:54 PM PDT 24
Finished May 23 03:31:57 PM PDT 24
Peak memory 212928 kb
Host smart-b4311202-389e-4056-93b1-e83f5b8d76c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=162343565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.162343565
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3719364999
Short name T223
Test name
Test status
Simulation time 988841653 ps
CPU time 3.41 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 204796 kb
Host smart-6ae8e030-4544-4c99-aeee-c7d7356b0953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3719364999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3719364999
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.4233463006
Short name T34
Test name
Test status
Simulation time 10058384946 ps
CPU time 13.13 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:39 PM PDT 24
Peak memory 204960 kb
Host smart-589af696-dfe3-437f-9273-b07a066af094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42334
63006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.4233463006
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.15028715
Short name T97
Test name
Test status
Simulation time 10098629247 ps
CPU time 13.07 seconds
Started May 23 03:39:24 PM PDT 24
Finished May 23 03:39:51 PM PDT 24
Peak memory 204932 kb
Host smart-63c4c77e-5710-49c8-8428-20966ca30410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15028
715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.15028715
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.852516602
Short name T124
Test name
Test status
Simulation time 10082125318 ps
CPU time 12.52 seconds
Started May 23 03:39:35 PM PDT 24
Finished May 23 03:39:54 PM PDT 24
Peak memory 204964 kb
Host smart-205563ed-cb43-4763-b202-2f9898230f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85251
6602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.852516602
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2843941000
Short name T130
Test name
Test status
Simulation time 10076076451 ps
CPU time 16.37 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:57 PM PDT 24
Peak memory 204976 kb
Host smart-2390d717-562d-4fa3-936c-37dfcbaa0018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28439
41000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2843941000
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3369185554
Short name T116
Test name
Test status
Simulation time 10132571975 ps
CPU time 13.15 seconds
Started May 23 03:40:38 PM PDT 24
Finished May 23 03:41:02 PM PDT 24
Peak memory 204920 kb
Host smart-7b029f60-19d8-4964-b416-7e8d233c65b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33691
85554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3369185554
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1506982509
Short name T94
Test name
Test status
Simulation time 34048360504 ps
CPU time 64.71 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:58 PM PDT 24
Peak memory 204996 kb
Host smart-31d128b9-4246-4c9b-ac9b-beee908db387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15069
82509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1506982509
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1739997913
Short name T128
Test name
Test status
Simulation time 10095998610 ps
CPU time 13.78 seconds
Started May 23 03:40:45 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204944 kb
Host smart-217e734d-4477-4692-aaec-84d5f7454bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17399
97913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1739997913
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1767092453
Short name T50
Test name
Test status
Simulation time 10381504894 ps
CPU time 14.44 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:23 PM PDT 24
Peak memory 204972 kb
Host smart-009fd181-f79e-4361-b2f2-9b9ab9a06bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17670
92453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1767092453
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3165392931
Short name T113
Test name
Test status
Simulation time 10126409623 ps
CPU time 14.75 seconds
Started May 23 03:41:31 PM PDT 24
Finished May 23 03:41:54 PM PDT 24
Peak memory 204940 kb
Host smart-78a25c34-ae9d-46af-a455-85894ff5ad03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31653
92931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3165392931
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.957445624
Short name T119
Test name
Test status
Simulation time 10108701223 ps
CPU time 13.83 seconds
Started May 23 03:41:47 PM PDT 24
Finished May 23 03:42:07 PM PDT 24
Peak memory 205004 kb
Host smart-a7b228cf-88f1-47e9-b2b0-6c54ded69e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95744
5624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.957445624
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.41164545
Short name T102
Test name
Test status
Simulation time 10151998536 ps
CPU time 12.73 seconds
Started May 23 03:41:55 PM PDT 24
Finished May 23 03:42:15 PM PDT 24
Peak memory 204960 kb
Host smart-1d862ab7-1ce3-4a11-b14e-3c392022b0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41164
545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.41164545
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2300808099
Short name T52
Test name
Test status
Simulation time 10088291321 ps
CPU time 14.22 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204936 kb
Host smart-4141bf08-16c5-4cc9-901a-1edeb8fa1ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23008
08099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2300808099
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.484997536
Short name T1483
Test name
Test status
Simulation time 10199139489 ps
CPU time 13.94 seconds
Started May 23 03:42:35 PM PDT 24
Finished May 23 03:43:01 PM PDT 24
Peak memory 204884 kb
Host smart-7918b93b-2eb6-4dc7-b1c8-53800272e774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48499
7536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.484997536
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.86302305
Short name T1249
Test name
Test status
Simulation time 10089235137 ps
CPU time 14.04 seconds
Started May 23 03:42:55 PM PDT 24
Finished May 23 03:43:23 PM PDT 24
Peak memory 204912 kb
Host smart-47bf0aa7-e7f7-48fb-a204-6eb65876902d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86302
305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.86302305
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2631748225
Short name T177
Test name
Test status
Simulation time 10085693265 ps
CPU time 13.51 seconds
Started May 23 03:42:48 PM PDT 24
Finished May 23 03:43:15 PM PDT 24
Peak memory 205000 kb
Host smart-aa971742-bad1-4593-9946-46e18c256db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26317
48225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2631748225
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2377001413
Short name T105
Test name
Test status
Simulation time 10234469798 ps
CPU time 13.53 seconds
Started May 23 03:43:03 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 204964 kb
Host smart-f2aa02d7-eaa4-47c3-9737-21658bcb2767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23770
01413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2377001413
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1925099829
Short name T255
Test name
Test status
Simulation time 1180842542 ps
CPU time 5.57 seconds
Started May 23 03:31:52 PM PDT 24
Finished May 23 03:31:59 PM PDT 24
Peak memory 204768 kb
Host smart-357c95a1-e6b7-48aa-b16b-8700f692f669
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1925099829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1925099829
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1766384191
Short name T1946
Test name
Test status
Simulation time 66063169 ps
CPU time 0.83 seconds
Started May 23 03:31:55 PM PDT 24
Finished May 23 03:31:57 PM PDT 24
Peak memory 204552 kb
Host smart-010727d6-7d84-44b7-94ea-87c01db4e540
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1766384191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1766384191
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.504194531
Short name T200
Test name
Test status
Simulation time 103016451 ps
CPU time 1.3 seconds
Started May 23 03:32:04 PM PDT 24
Finished May 23 03:32:07 PM PDT 24
Peak memory 212944 kb
Host smart-d073efd5-6b18-4310-8025-32569403ec21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504194531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.504194531
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.591129923
Short name T2001
Test name
Test status
Simulation time 73543432 ps
CPU time 0.99 seconds
Started May 23 03:31:53 PM PDT 24
Finished May 23 03:31:55 PM PDT 24
Peak memory 204716 kb
Host smart-b878ecb1-c5f6-4b42-83ac-21b76f045d9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=591129923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.591129923
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2672970556
Short name T300
Test name
Test status
Simulation time 68028245 ps
CPU time 0.68 seconds
Started May 23 03:31:51 PM PDT 24
Finished May 23 03:31:54 PM PDT 24
Peak memory 204488 kb
Host smart-b613815a-4b60-4467-811a-0e6a3cf4968a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2672970556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2672970556
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.11035486
Short name T261
Test name
Test status
Simulation time 169763304 ps
CPU time 2.34 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:15 PM PDT 24
Peak memory 212840 kb
Host smart-91753961-1b26-4f58-9fb7-ad5a9e902617
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=11035486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.11035486
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.265969955
Short name T2002
Test name
Test status
Simulation time 108211289 ps
CPU time 2.43 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:16 PM PDT 24
Peak memory 204548 kb
Host smart-01fbb17f-1812-4412-800a-f72f8700e513
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=265969955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.265969955
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1776522349
Short name T224
Test name
Test status
Simulation time 503380055 ps
CPU time 4.08 seconds
Started May 23 03:31:56 PM PDT 24
Finished May 23 03:32:02 PM PDT 24
Peak memory 204804 kb
Host smart-fffa35c1-88bf-4041-b58d-cdfccff6b41b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1776522349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1776522349
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3918588902
Short name T2003
Test name
Test status
Simulation time 88100365 ps
CPU time 1.96 seconds
Started May 23 03:31:58 PM PDT 24
Finished May 23 03:32:02 PM PDT 24
Peak memory 204672 kb
Host smart-96bc8510-a464-462a-850d-a00a9514bc8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3918588902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3918588902
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2404832068
Short name T221
Test name
Test status
Simulation time 899758297 ps
CPU time 5.32 seconds
Started May 23 03:31:55 PM PDT 24
Finished May 23 03:32:01 PM PDT 24
Peak memory 204712 kb
Host smart-b3da0b9f-7d8f-4939-9813-652bf8b95b8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2404832068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2404832068
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.914112658
Short name T2013
Test name
Test status
Simulation time 67861653 ps
CPU time 0.79 seconds
Started May 23 03:31:57 PM PDT 24
Finished May 23 03:32:00 PM PDT 24
Peak memory 204504 kb
Host smart-1c163f76-f8df-4297-af8a-3bf618a2eab7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=914112658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.914112658
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1769903468
Short name T236
Test name
Test status
Simulation time 89784343 ps
CPU time 2.51 seconds
Started May 23 03:31:56 PM PDT 24
Finished May 23 03:32:01 PM PDT 24
Peak memory 217648 kb
Host smart-4d12a652-b8dc-42f7-8a54-ab946b1cd652
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769903468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1769903468
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1846562871
Short name T2010
Test name
Test status
Simulation time 66642849 ps
CPU time 0.89 seconds
Started May 23 03:32:04 PM PDT 24
Finished May 23 03:32:07 PM PDT 24
Peak memory 204516 kb
Host smart-60c5cc60-bb9c-48b2-8612-785f79d2b77e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1846562871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1846562871
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2939666975
Short name T298
Test name
Test status
Simulation time 43858017 ps
CPU time 0.63 seconds
Started May 23 03:31:57 PM PDT 24
Finished May 23 03:32:00 PM PDT 24
Peak memory 204484 kb
Host smart-018ba617-3019-4f3c-9da5-c4ce5f5304f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2939666975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2939666975
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1375299857
Short name T2014
Test name
Test status
Simulation time 92781443 ps
CPU time 2.4 seconds
Started May 23 03:31:58 PM PDT 24
Finished May 23 03:32:03 PM PDT 24
Peak memory 213016 kb
Host smart-ee0713fc-4600-4bd3-b0b1-e7773e03a2e0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1375299857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1375299857
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2589579664
Short name T2009
Test name
Test status
Simulation time 261927370 ps
CPU time 2.38 seconds
Started May 23 03:31:57 PM PDT 24
Finished May 23 03:32:02 PM PDT 24
Peak memory 204668 kb
Host smart-6befdd6d-a1c6-4f3f-9a54-c64f41fcac64
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2589579664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2589579664
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2861607301
Short name T1954
Test name
Test status
Simulation time 76037056 ps
CPU time 1.05 seconds
Started May 23 03:32:05 PM PDT 24
Finished May 23 03:32:08 PM PDT 24
Peak memory 204872 kb
Host smart-6c0aefa5-1129-49f6-babf-7443355daa56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2861607301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2861607301
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.186969367
Short name T1965
Test name
Test status
Simulation time 82124594 ps
CPU time 1.87 seconds
Started May 23 03:31:56 PM PDT 24
Finished May 23 03:32:00 PM PDT 24
Peak memory 212948 kb
Host smart-e0905126-322f-4d8a-b449-4a0be682de24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=186969367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.186969367
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1054765990
Short name T1986
Test name
Test status
Simulation time 129832532 ps
CPU time 1.63 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:32 PM PDT 24
Peak memory 213092 kb
Host smart-2ae23eb8-10d9-4ef8-ad42-edf9649fd170
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054765990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1054765990
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2513485136
Short name T263
Test name
Test status
Simulation time 94011134 ps
CPU time 1.03 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:31 PM PDT 24
Peak memory 204804 kb
Host smart-73aae570-4cf1-482d-8545-9bb97b82938f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2513485136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2513485136
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2892681128
Short name T280
Test name
Test status
Simulation time 46771539 ps
CPU time 0.64 seconds
Started May 23 03:32:24 PM PDT 24
Finished May 23 03:32:26 PM PDT 24
Peak memory 204468 kb
Host smart-ff81a0ec-8b7a-49ab-91ea-492ffc6f2969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2892681128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2892681128
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.729742066
Short name T269
Test name
Test status
Simulation time 115751879 ps
CPU time 1.14 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:31 PM PDT 24
Peak memory 204844 kb
Host smart-f303b6a5-42a2-4801-b758-b957903a4f60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=729742066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.729742066
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1961395065
Short name T2039
Test name
Test status
Simulation time 72098668 ps
CPU time 1.75 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:32 PM PDT 24
Peak memory 204824 kb
Host smart-5b18cf7a-59b3-4a0e-9188-be5187f5015b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1961395065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1961395065
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2597063092
Short name T1992
Test name
Test status
Simulation time 1104747857 ps
CPU time 5.7 seconds
Started May 23 03:32:25 PM PDT 24
Finished May 23 03:32:33 PM PDT 24
Peak memory 204788 kb
Host smart-acff2fd3-d867-4089-a476-be2124b3ab57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2597063092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2597063092
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.638579236
Short name T2006
Test name
Test status
Simulation time 157307906 ps
CPU time 1.62 seconds
Started May 23 03:32:23 PM PDT 24
Finished May 23 03:32:26 PM PDT 24
Peak memory 221128 kb
Host smart-17d21738-234c-4fa3-afb8-82ffbc83c028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638579236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.638579236
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2203484174
Short name T1983
Test name
Test status
Simulation time 48287306 ps
CPU time 0.8 seconds
Started May 23 03:32:23 PM PDT 24
Finished May 23 03:32:25 PM PDT 24
Peak memory 204540 kb
Host smart-a72ec6ba-ab8a-453c-a065-2c58fb194f7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2203484174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2203484174
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1809585174
Short name T2005
Test name
Test status
Simulation time 42165927 ps
CPU time 0.69 seconds
Started May 23 03:32:25 PM PDT 24
Finished May 23 03:32:28 PM PDT 24
Peak memory 204460 kb
Host smart-7ab114a0-fd5f-48ea-94c4-6b2004dcd360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1809585174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1809585174
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.440651480
Short name T1984
Test name
Test status
Simulation time 96519769 ps
CPU time 1.59 seconds
Started May 23 03:32:29 PM PDT 24
Finished May 23 03:32:35 PM PDT 24
Peak memory 204908 kb
Host smart-4385ee0a-ad9c-41d0-a8bd-23dbc8bd1baa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=440651480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.440651480
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.295299671
Short name T2023
Test name
Test status
Simulation time 171254843 ps
CPU time 2.21 seconds
Started May 23 03:32:27 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 204776 kb
Host smart-3b24e22b-c813-464c-8960-589283ccda19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=295299671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.295299671
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.548348083
Short name T2025
Test name
Test status
Simulation time 310498309 ps
CPU time 2.51 seconds
Started May 23 03:32:24 PM PDT 24
Finished May 23 03:32:28 PM PDT 24
Peak memory 204812 kb
Host smart-9980729c-a28c-49fd-8c90-952bf3015d00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=548348083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.548348083
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1307160197
Short name T2026
Test name
Test status
Simulation time 169687554 ps
CPU time 1.74 seconds
Started May 23 03:32:27 PM PDT 24
Finished May 23 03:32:32 PM PDT 24
Peak memory 213132 kb
Host smart-0c191307-c0cc-4c30-8b81-64145bd54910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307160197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1307160197
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2136926668
Short name T1994
Test name
Test status
Simulation time 69080546 ps
CPU time 0.95 seconds
Started May 23 03:32:27 PM PDT 24
Finished May 23 03:32:32 PM PDT 24
Peak memory 204796 kb
Host smart-231f1633-5d73-4742-a7cf-2278f44c2678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2136926668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2136926668
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1879984103
Short name T2024
Test name
Test status
Simulation time 37960151 ps
CPU time 0.67 seconds
Started May 23 03:32:24 PM PDT 24
Finished May 23 03:32:26 PM PDT 24
Peak memory 204472 kb
Host smart-8e527181-2e3a-4070-8926-272c928b89b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1879984103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1879984103
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1565229043
Short name T1964
Test name
Test status
Simulation time 190397240 ps
CPU time 1.16 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:31 PM PDT 24
Peak memory 204868 kb
Host smart-47cc59b3-420e-43ec-9a34-6e101fbf2a2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1565229043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1565229043
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.974369726
Short name T231
Test name
Test status
Simulation time 283574423 ps
CPU time 3.11 seconds
Started May 23 03:32:24 PM PDT 24
Finished May 23 03:32:29 PM PDT 24
Peak memory 220656 kb
Host smart-f60c9b6a-e118-4388-b791-a5ec31d86c08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=974369726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.974369726
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.756890472
Short name T276
Test name
Test status
Simulation time 973404249 ps
CPU time 4.88 seconds
Started May 23 03:32:31 PM PDT 24
Finished May 23 03:32:41 PM PDT 24
Peak memory 204868 kb
Host smart-7577ab7e-8634-48d1-82b2-0e9151b834e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=756890472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.756890472
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1851128745
Short name T1951
Test name
Test status
Simulation time 110275549 ps
CPU time 1.41 seconds
Started May 23 03:32:30 PM PDT 24
Finished May 23 03:32:36 PM PDT 24
Peak memory 214656 kb
Host smart-940f1993-179c-4ac1-96a8-5e09c9fb96f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851128745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1851128745
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2664043791
Short name T277
Test name
Test status
Simulation time 76662712 ps
CPU time 0.84 seconds
Started May 23 03:32:23 PM PDT 24
Finished May 23 03:32:26 PM PDT 24
Peak memory 204572 kb
Host smart-5f6303e4-637e-496c-94da-b7abf22d3007
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2664043791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2664043791
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3576751097
Short name T2033
Test name
Test status
Simulation time 52923733 ps
CPU time 0.69 seconds
Started May 23 03:32:24 PM PDT 24
Finished May 23 03:32:26 PM PDT 24
Peak memory 204528 kb
Host smart-0ec550f7-64a3-4c2e-8ea6-63a606402bb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3576751097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3576751097
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1893864840
Short name T1963
Test name
Test status
Simulation time 123484143 ps
CPU time 1.54 seconds
Started May 23 03:32:29 PM PDT 24
Finished May 23 03:32:35 PM PDT 24
Peak memory 204888 kb
Host smart-973339c9-5739-4710-8149-7b24160cc4a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1893864840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1893864840
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4073962348
Short name T234
Test name
Test status
Simulation time 96990659 ps
CPU time 2.54 seconds
Started May 23 03:32:25 PM PDT 24
Finished May 23 03:32:29 PM PDT 24
Peak memory 214032 kb
Host smart-172689f2-0427-4153-a9d1-5062f015e5e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4073962348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4073962348
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1373187247
Short name T2007
Test name
Test status
Simulation time 883729474 ps
CPU time 5.18 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 204844 kb
Host smart-22a9c7cf-be37-4b96-802b-3c26befea46a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1373187247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1373187247
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.936211346
Short name T2022
Test name
Test status
Simulation time 182257815 ps
CPU time 1.26 seconds
Started May 23 03:32:24 PM PDT 24
Finished May 23 03:32:27 PM PDT 24
Peak memory 213024 kb
Host smart-0ef84edb-2ed4-4b6d-b370-2643611dfa0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936211346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.936211346
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.570465416
Short name T257
Test name
Test status
Simulation time 41805929 ps
CPU time 0.8 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:33 PM PDT 24
Peak memory 204512 kb
Host smart-fb1a776c-5bc8-4b0f-93b6-c85d1390e14d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=570465416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.570465416
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.4267901348
Short name T99
Test name
Test status
Simulation time 31721296 ps
CPU time 0.64 seconds
Started May 23 03:32:30 PM PDT 24
Finished May 23 03:32:36 PM PDT 24
Peak memory 204464 kb
Host smart-69e5d7f4-dc8e-4694-8881-6a37caf879d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4267901348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.4267901348
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1907970639
Short name T1972
Test name
Test status
Simulation time 110551144 ps
CPU time 1.01 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 204768 kb
Host smart-22bc48f1-c8f4-4996-8d28-6ce67b25ab2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1907970639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1907970639
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1980753277
Short name T235
Test name
Test status
Simulation time 96362138 ps
CPU time 1.25 seconds
Started May 23 03:32:25 PM PDT 24
Finished May 23 03:32:28 PM PDT 24
Peak memory 204780 kb
Host smart-e2502b4a-e050-429e-9b96-4b5724ab154c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1980753277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1980753277
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3238768742
Short name T241
Test name
Test status
Simulation time 73536663 ps
CPU time 1.28 seconds
Started May 23 03:32:25 PM PDT 24
Finished May 23 03:32:29 PM PDT 24
Peak memory 213052 kb
Host smart-caa60686-5b2d-416d-ac7e-97b34b4f9cbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238768742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3238768742
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2313111568
Short name T1959
Test name
Test status
Simulation time 52597290 ps
CPU time 1.01 seconds
Started May 23 03:32:27 PM PDT 24
Finished May 23 03:32:32 PM PDT 24
Peak memory 204524 kb
Host smart-a94e3b47-ad04-4137-ad5b-02cadacea79f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2313111568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2313111568
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1075027991
Short name T101
Test name
Test status
Simulation time 48042953 ps
CPU time 0.66 seconds
Started May 23 03:32:23 PM PDT 24
Finished May 23 03:32:26 PM PDT 24
Peak memory 204516 kb
Host smart-20877ff9-a2d9-4031-9551-18e230d3044b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1075027991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1075027991
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1720444268
Short name T1991
Test name
Test status
Simulation time 83053381 ps
CPU time 1.11 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:31 PM PDT 24
Peak memory 204840 kb
Host smart-fcbf840f-fbfd-48c2-9f1d-f8fe59d1523a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1720444268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1720444268
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3168365814
Short name T1973
Test name
Test status
Simulation time 634125148 ps
CPU time 3.01 seconds
Started May 23 03:32:29 PM PDT 24
Finished May 23 03:32:37 PM PDT 24
Peak memory 204864 kb
Host smart-96da8f57-6a5c-4572-b250-b0586c22b1d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3168365814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3168365814
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1075358165
Short name T225
Test name
Test status
Simulation time 96318579 ps
CPU time 2.55 seconds
Started May 23 03:32:23 PM PDT 24
Finished May 23 03:32:27 PM PDT 24
Peak memory 213016 kb
Host smart-e561416e-6850-4348-904b-969a4fe0f44c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075358165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1075358165
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.504640816
Short name T259
Test name
Test status
Simulation time 95853159 ps
CPU time 1.08 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:33 PM PDT 24
Peak memory 204768 kb
Host smart-92c5ec5f-cca4-44cd-a2f2-fc2489c9b0e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=504640816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.504640816
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3452057242
Short name T2004
Test name
Test status
Simulation time 74906736 ps
CPU time 0.72 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:33 PM PDT 24
Peak memory 204476 kb
Host smart-85105f80-7ff5-450d-bab0-83c13b5810db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3452057242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3452057242
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.234611321
Short name T1955
Test name
Test status
Simulation time 166255389 ps
CPU time 1.71 seconds
Started May 23 03:32:25 PM PDT 24
Finished May 23 03:32:28 PM PDT 24
Peak memory 204908 kb
Host smart-b6eafd05-6e8f-401a-a01e-4dbe84ff18fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=234611321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.234611321
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1077811862
Short name T239
Test name
Test status
Simulation time 167020881 ps
CPU time 2.27 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:30 PM PDT 24
Peak memory 212956 kb
Host smart-3edd4104-395d-41b6-b7dd-47c2fc0ea7cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1077811862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1077811862
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2142776130
Short name T2017
Test name
Test status
Simulation time 111047855 ps
CPU time 1.27 seconds
Started May 23 03:32:29 PM PDT 24
Finished May 23 03:32:35 PM PDT 24
Peak memory 213036 kb
Host smart-affef587-3db2-45cf-8388-ae189acd47d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142776130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2142776130
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3302142961
Short name T266
Test name
Test status
Simulation time 104876484 ps
CPU time 0.88 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:31 PM PDT 24
Peak memory 204464 kb
Host smart-3b83f817-bea9-4e55-a9c4-98742667f2b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3302142961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3302142961
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2129602554
Short name T1966
Test name
Test status
Simulation time 38811879 ps
CPU time 0.65 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:33 PM PDT 24
Peak memory 204488 kb
Host smart-fb511847-ca46-4478-ac3c-465c4628e264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2129602554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2129602554
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3752188990
Short name T1947
Test name
Test status
Simulation time 486526346 ps
CPU time 1.87 seconds
Started May 23 03:32:25 PM PDT 24
Finished May 23 03:32:29 PM PDT 24
Peak memory 204780 kb
Host smart-1b3a3d51-6d08-47c2-ba7a-e0b3d4c5faad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3752188990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3752188990
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1084670039
Short name T201
Test name
Test status
Simulation time 74981977 ps
CPU time 1.32 seconds
Started May 23 03:32:25 PM PDT 24
Finished May 23 03:32:28 PM PDT 24
Peak memory 204844 kb
Host smart-75eec74d-8130-4093-9489-718f5c961892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1084670039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1084670039
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3801305390
Short name T285
Test name
Test status
Simulation time 593727430 ps
CPU time 4.29 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 204832 kb
Host smart-76013cb9-9434-4c39-b180-2c30d19d0adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3801305390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3801305390
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.605881725
Short name T237
Test name
Test status
Simulation time 148627663 ps
CPU time 2.49 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:32 PM PDT 24
Peak memory 213024 kb
Host smart-8448af55-dd43-491a-b048-98413c5fd86b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605881725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde
v_csr_mem_rw_with_rand_reset.605881725
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1875179990
Short name T1948
Test name
Test status
Simulation time 104484212 ps
CPU time 1.04 seconds
Started May 23 03:32:27 PM PDT 24
Finished May 23 03:32:31 PM PDT 24
Peak memory 204692 kb
Host smart-a33b0c49-45d6-4ded-8310-790b7c21dc63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1875179990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1875179990
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2102624777
Short name T1979
Test name
Test status
Simulation time 149870672 ps
CPU time 1.55 seconds
Started May 23 03:32:29 PM PDT 24
Finished May 23 03:32:35 PM PDT 24
Peak memory 204940 kb
Host smart-f2f39031-636a-4e43-8443-8a112551f258
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2102624777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2102624777
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1236983796
Short name T226
Test name
Test status
Simulation time 185335715 ps
CPU time 1.98 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 204888 kb
Host smart-ea4af653-a144-49b4-aeb1-5390a9f3dd69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1236983796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1236983796
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3740359444
Short name T288
Test name
Test status
Simulation time 366816139 ps
CPU time 2.55 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 204820 kb
Host smart-f90b67b2-6f08-439b-9576-da18310d1881
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3740359444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3740359444
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2835265034
Short name T233
Test name
Test status
Simulation time 110850554 ps
CPU time 1.23 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 213016 kb
Host smart-a6e109ab-0eab-488e-af67-8957a2e85034
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835265034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2835265034
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4123095767
Short name T253
Test name
Test status
Simulation time 58401535 ps
CPU time 0.85 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 204604 kb
Host smart-6877e3ca-c622-4fb0-94ac-561084c56e19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4123095767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4123095767
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4234190885
Short name T292
Test name
Test status
Simulation time 51897257 ps
CPU time 0.69 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:30 PM PDT 24
Peak memory 204468 kb
Host smart-3b1ffe27-b710-43a5-b87a-b973a8a601f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4234190885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.4234190885
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3852628207
Short name T1988
Test name
Test status
Simulation time 126315028 ps
CPU time 1.22 seconds
Started May 23 03:32:25 PM PDT 24
Finished May 23 03:32:28 PM PDT 24
Peak memory 204860 kb
Host smart-824c09ab-729d-4d65-abd3-200d58f18fa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3852628207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3852628207
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1575914365
Short name T1974
Test name
Test status
Simulation time 103602433 ps
CPU time 1.59 seconds
Started May 23 03:32:27 PM PDT 24
Finished May 23 03:32:33 PM PDT 24
Peak memory 204816 kb
Host smart-d2b35c84-6965-4730-bd77-7439aa3814b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1575914365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1575914365
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3402327453
Short name T287
Test name
Test status
Simulation time 1152961123 ps
CPU time 5.42 seconds
Started May 23 03:32:26 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 204772 kb
Host smart-44d33788-9c3a-4633-8ac4-612ebfb3c2e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3402327453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3402327453
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2280844422
Short name T265
Test name
Test status
Simulation time 95179237 ps
CPU time 1.81 seconds
Started May 23 03:31:54 PM PDT 24
Finished May 23 03:31:57 PM PDT 24
Peak memory 204640 kb
Host smart-f599de9e-1671-414a-9f78-d78b85591641
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2280844422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2280844422
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1862010497
Short name T1961
Test name
Test status
Simulation time 742988608 ps
CPU time 7.34 seconds
Started May 23 03:31:50 PM PDT 24
Finished May 23 03:32:00 PM PDT 24
Peak memory 204768 kb
Host smart-28f89b66-6596-4a5c-ac50-129965ba13bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1862010497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1862010497
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2382850123
Short name T256
Test name
Test status
Simulation time 54277891 ps
CPU time 0.77 seconds
Started May 23 03:31:58 PM PDT 24
Finished May 23 03:32:00 PM PDT 24
Peak memory 204496 kb
Host smart-c8df82f3-9fe3-4499-ac85-19fa20b19b02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2382850123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2382850123
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2727327773
Short name T1949
Test name
Test status
Simulation time 169135251 ps
CPU time 1.81 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:15 PM PDT 24
Peak memory 213056 kb
Host smart-4b35a886-f217-490a-970a-69c15888a226
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727327773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2727327773
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2692040424
Short name T252
Test name
Test status
Simulation time 44496291 ps
CPU time 0.75 seconds
Started May 23 03:31:57 PM PDT 24
Finished May 23 03:32:00 PM PDT 24
Peak memory 204496 kb
Host smart-d04252f7-7556-49cb-8194-0e22a0dfe62c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2692040424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2692040424
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2065514369
Short name T204
Test name
Test status
Simulation time 35280167 ps
CPU time 0.67 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:14 PM PDT 24
Peak memory 204416 kb
Host smart-03203837-fc78-446d-8de6-587cf052cfc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2065514369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2065514369
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3723474371
Short name T2012
Test name
Test status
Simulation time 58476210 ps
CPU time 1.44 seconds
Started May 23 03:31:54 PM PDT 24
Finished May 23 03:31:57 PM PDT 24
Peak memory 212960 kb
Host smart-9f1b56b0-7c0e-476b-b3a9-f0a684a2c2de
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3723474371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3723474371
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.342358223
Short name T1967
Test name
Test status
Simulation time 189496915 ps
CPU time 4 seconds
Started May 23 03:32:04 PM PDT 24
Finished May 23 03:32:10 PM PDT 24
Peak memory 204680 kb
Host smart-653cccb6-51d7-40bc-971b-e1802cedae13
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=342358223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.342358223
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.430550088
Short name T1950
Test name
Test status
Simulation time 98435208 ps
CPU time 1.11 seconds
Started May 23 03:31:56 PM PDT 24
Finished May 23 03:31:59 PM PDT 24
Peak memory 204820 kb
Host smart-fb4ac1af-0a70-42c2-a670-07dcf1744162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=430550088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.430550088
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1871199578
Short name T220
Test name
Test status
Simulation time 102158160 ps
CPU time 2.49 seconds
Started May 23 03:32:04 PM PDT 24
Finished May 23 03:32:08 PM PDT 24
Peak memory 220308 kb
Host smart-46c9ffff-f0e7-4263-8637-8ae2e57119bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1871199578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1871199578
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1278129396
Short name T284
Test name
Test status
Simulation time 1033014478 ps
CPU time 5.2 seconds
Started May 23 03:32:11 PM PDT 24
Finished May 23 03:32:18 PM PDT 24
Peak memory 204796 kb
Host smart-753708d9-50a1-4318-9890-b6963b2603c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1278129396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1278129396
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3490027767
Short name T1990
Test name
Test status
Simulation time 35685620 ps
CPU time 0.66 seconds
Started May 23 03:32:27 PM PDT 24
Finished May 23 03:32:31 PM PDT 24
Peak memory 204496 kb
Host smart-e1cebfc0-2b7a-4541-a02a-2506a9bdd9a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3490027767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3490027767
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3703350578
Short name T1999
Test name
Test status
Simulation time 38988387 ps
CPU time 0.69 seconds
Started May 23 03:32:29 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 204424 kb
Host smart-e6151f92-60a9-4440-9d4a-87bba12cf76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3703350578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3703350578
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3508959963
Short name T2038
Test name
Test status
Simulation time 45947813 ps
CPU time 0.71 seconds
Started May 23 03:32:30 PM PDT 24
Finished May 23 03:32:36 PM PDT 24
Peak memory 204464 kb
Host smart-e8f6b4c1-5bd7-49d5-b566-c7d9865d36b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3508959963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3508959963
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.349791597
Short name T304
Test name
Test status
Simulation time 32854720 ps
CPU time 0.73 seconds
Started May 23 03:32:29 PM PDT 24
Finished May 23 03:32:35 PM PDT 24
Peak memory 204424 kb
Host smart-fa0c4e37-fe9e-49fb-a8e3-f8bd7a23516f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=349791597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.349791597
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2676844366
Short name T2018
Test name
Test status
Simulation time 42291077 ps
CPU time 0.7 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:33 PM PDT 24
Peak memory 204508 kb
Host smart-124ff1a8-884d-4724-8401-a5b791f4fd4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2676844366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2676844366
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3870114699
Short name T278
Test name
Test status
Simulation time 105267514 ps
CPU time 0.72 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:33 PM PDT 24
Peak memory 204492 kb
Host smart-2a97a598-e0f1-47ea-805f-138088ffc35d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3870114699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3870114699
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.871903310
Short name T2032
Test name
Test status
Simulation time 41192497 ps
CPU time 0.65 seconds
Started May 23 03:32:40 PM PDT 24
Finished May 23 03:32:43 PM PDT 24
Peak memory 204460 kb
Host smart-19094a49-cc61-43fe-9a4c-0897581bdc2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=871903310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.871903310
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3426589160
Short name T2028
Test name
Test status
Simulation time 55479870 ps
CPU time 0.65 seconds
Started May 23 03:32:42 PM PDT 24
Finished May 23 03:32:47 PM PDT 24
Peak memory 204492 kb
Host smart-ee84d646-814d-4874-a936-a417c64f8b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3426589160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3426589160
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.4019446937
Short name T2035
Test name
Test status
Simulation time 98008554 ps
CPU time 0.72 seconds
Started May 23 03:32:39 PM PDT 24
Finished May 23 03:32:41 PM PDT 24
Peak memory 204468 kb
Host smart-41106638-6703-4a13-82a6-093a44e14f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4019446937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.4019446937
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1241632188
Short name T2021
Test name
Test status
Simulation time 38337249 ps
CPU time 0.7 seconds
Started May 23 03:32:40 PM PDT 24
Finished May 23 03:32:42 PM PDT 24
Peak memory 204532 kb
Host smart-3f3981df-d7dd-4979-8476-c100de265b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1241632188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1241632188
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1938415780
Short name T2019
Test name
Test status
Simulation time 216944016 ps
CPU time 2.13 seconds
Started May 23 03:32:05 PM PDT 24
Finished May 23 03:32:09 PM PDT 24
Peak memory 204828 kb
Host smart-42b71829-b4fb-42df-ae7c-7b1911ccc66a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1938415780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1938415780
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2950557182
Short name T258
Test name
Test status
Simulation time 1083840313 ps
CPU time 7.42 seconds
Started May 23 03:31:53 PM PDT 24
Finished May 23 03:32:02 PM PDT 24
Peak memory 204736 kb
Host smart-3b484533-57b4-49fe-867f-25a41da6031a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2950557182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2950557182
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3222805163
Short name T260
Test name
Test status
Simulation time 120359640 ps
CPU time 0.94 seconds
Started May 23 03:31:58 PM PDT 24
Finished May 23 03:32:01 PM PDT 24
Peak memory 204600 kb
Host smart-343efd53-b3dd-4756-ac2a-53d4a5696c60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3222805163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3222805163
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3416161399
Short name T1957
Test name
Test status
Simulation time 160794510 ps
CPU time 1.8 seconds
Started May 23 03:32:04 PM PDT 24
Finished May 23 03:32:07 PM PDT 24
Peak memory 213004 kb
Host smart-fcb6556a-154b-4dff-a93c-835a9afd26b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416161399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3416161399
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1861353673
Short name T240
Test name
Test status
Simulation time 53692459 ps
CPU time 0.8 seconds
Started May 23 03:31:50 PM PDT 24
Finished May 23 03:31:54 PM PDT 24
Peak memory 204596 kb
Host smart-76ee9fa9-28cf-44c8-b8b6-5e642b7e7f7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1861353673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1861353673
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3027727184
Short name T2008
Test name
Test status
Simulation time 55525113 ps
CPU time 0.67 seconds
Started May 23 03:31:55 PM PDT 24
Finished May 23 03:31:58 PM PDT 24
Peak memory 204448 kb
Host smart-ac28dfc2-894b-49e1-8eaa-a89757de45a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3027727184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3027727184
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1839281264
Short name T2030
Test name
Test status
Simulation time 180380880 ps
CPU time 2.21 seconds
Started May 23 03:31:55 PM PDT 24
Finished May 23 03:31:59 PM PDT 24
Peak memory 212908 kb
Host smart-dd0f0476-6f41-4420-8bc9-cd05baa969c5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1839281264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1839281264
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2852634322
Short name T2034
Test name
Test status
Simulation time 105217621 ps
CPU time 2.22 seconds
Started May 23 03:31:56 PM PDT 24
Finished May 23 03:32:01 PM PDT 24
Peak memory 204620 kb
Host smart-9ad8cf6e-6b6b-4326-8b8e-3a9c1782eb97
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2852634322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2852634322
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2581589157
Short name T1997
Test name
Test status
Simulation time 350822205 ps
CPU time 1.57 seconds
Started May 23 03:32:04 PM PDT 24
Finished May 23 03:32:08 PM PDT 24
Peak memory 204852 kb
Host smart-c047a956-70f5-4c76-bf0b-b011ab0c836e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2581589157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2581589157
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.197941831
Short name T1978
Test name
Test status
Simulation time 168738434 ps
CPU time 1.93 seconds
Started May 23 03:32:04 PM PDT 24
Finished May 23 03:32:08 PM PDT 24
Peak memory 204848 kb
Host smart-93c3d667-1ead-43ce-945a-b8189984874f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=197941831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.197941831
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3441364975
Short name T275
Test name
Test status
Simulation time 995691006 ps
CPU time 5.16 seconds
Started May 23 03:31:49 PM PDT 24
Finished May 23 03:31:57 PM PDT 24
Peak memory 204840 kb
Host smart-e3165a9b-272a-4890-a413-ebd8e3f6350c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3441364975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3441364975
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3031152187
Short name T1996
Test name
Test status
Simulation time 40162083 ps
CPU time 0.67 seconds
Started May 23 03:32:40 PM PDT 24
Finished May 23 03:32:43 PM PDT 24
Peak memory 204472 kb
Host smart-93156952-fae0-4dab-93c1-a23b238bc434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3031152187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3031152187
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3489935682
Short name T2015
Test name
Test status
Simulation time 38687069 ps
CPU time 0.65 seconds
Started May 23 03:32:42 PM PDT 24
Finished May 23 03:32:47 PM PDT 24
Peak memory 204496 kb
Host smart-ac05bb57-9ff1-4847-94f4-fe20ef4172e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3489935682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3489935682
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.969970586
Short name T1998
Test name
Test status
Simulation time 52738879 ps
CPU time 0.68 seconds
Started May 23 03:32:41 PM PDT 24
Finished May 23 03:32:44 PM PDT 24
Peak memory 204492 kb
Host smart-c20a11aa-d989-4e28-a2e3-c78ffab2badf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=969970586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.969970586
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3407795069
Short name T1968
Test name
Test status
Simulation time 35419389 ps
CPU time 0.67 seconds
Started May 23 03:32:41 PM PDT 24
Finished May 23 03:32:44 PM PDT 24
Peak memory 204496 kb
Host smart-a941a774-a9a5-4bf4-9218-bfcb1c4ab90e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3407795069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3407795069
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.622636849
Short name T301
Test name
Test status
Simulation time 51812480 ps
CPU time 0.68 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:52 PM PDT 24
Peak memory 204464 kb
Host smart-3db9c82b-adee-4b49-9e76-756e5b9bc9a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=622636849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.622636849
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1102727925
Short name T1962
Test name
Test status
Simulation time 96140267 ps
CPU time 0.73 seconds
Started May 23 03:32:41 PM PDT 24
Finished May 23 03:32:44 PM PDT 24
Peak memory 204488 kb
Host smart-39fa53b8-72e2-456f-87f2-383fe3de96d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1102727925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1102727925
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2749522121
Short name T205
Test name
Test status
Simulation time 36857508 ps
CPU time 0.65 seconds
Started May 23 03:32:41 PM PDT 24
Finished May 23 03:32:45 PM PDT 24
Peak memory 204424 kb
Host smart-c16233ea-6506-4f43-8459-a3daee98ffaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2749522121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2749522121
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1154565594
Short name T1970
Test name
Test status
Simulation time 64626985 ps
CPU time 0.69 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:48 PM PDT 24
Peak memory 204444 kb
Host smart-a19f9ed8-aad2-4b9f-a064-9e36d6b4ddb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1154565594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1154565594
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1776742476
Short name T1987
Test name
Test status
Simulation time 45176950 ps
CPU time 0.64 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:52 PM PDT 24
Peak memory 204500 kb
Host smart-3d3f06de-b841-4076-b47c-5fe468a4faff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1776742476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1776742476
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3016027027
Short name T262
Test name
Test status
Simulation time 107408015 ps
CPU time 1.83 seconds
Started May 23 03:32:08 PM PDT 24
Finished May 23 03:32:11 PM PDT 24
Peak memory 204700 kb
Host smart-62a67c4e-ad86-4eac-b62e-d43a2f00aec3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3016027027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3016027027
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.611322360
Short name T1980
Test name
Test status
Simulation time 706813421 ps
CPU time 4.16 seconds
Started May 23 03:32:11 PM PDT 24
Finished May 23 03:32:18 PM PDT 24
Peak memory 204788 kb
Host smart-3ed04a5e-1195-4b65-9c6b-4234fe1a8a97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=611322360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.611322360
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1375242781
Short name T207
Test name
Test status
Simulation time 65743189 ps
CPU time 0.81 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:13 PM PDT 24
Peak memory 204480 kb
Host smart-20c86492-0769-49e0-bda2-70963f09c75d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1375242781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1375242781
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.777976867
Short name T273
Test name
Test status
Simulation time 116928090 ps
CPU time 1.43 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:13 PM PDT 24
Peak memory 213116 kb
Host smart-854ff164-d507-4c5a-8c8d-1bc7ec4040e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777976867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.777976867
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.850849403
Short name T267
Test name
Test status
Simulation time 53884249 ps
CPU time 0.89 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:13 PM PDT 24
Peak memory 204500 kb
Host smart-f831cceb-0506-423f-b070-1233867c9cac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=850849403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.850849403
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2309171039
Short name T2029
Test name
Test status
Simulation time 41499076 ps
CPU time 0.65 seconds
Started May 23 03:32:05 PM PDT 24
Finished May 23 03:32:07 PM PDT 24
Peak memory 204504 kb
Host smart-ef73820f-06d9-4546-888b-21799e03c8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2309171039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2309171039
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3205091161
Short name T264
Test name
Test status
Simulation time 118008247 ps
CPU time 1.47 seconds
Started May 23 03:32:05 PM PDT 24
Finished May 23 03:32:08 PM PDT 24
Peak memory 204836 kb
Host smart-7248e47e-db90-4e0d-8f2e-38757ce8ea50
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3205091161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3205091161
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4103364357
Short name T1971
Test name
Test status
Simulation time 173568095 ps
CPU time 4.39 seconds
Started May 23 03:31:58 PM PDT 24
Finished May 23 03:32:04 PM PDT 24
Peak memory 204664 kb
Host smart-4c4f0229-8ba4-48b8-aba4-da7769a64a54
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4103364357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.4103364357
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3647168027
Short name T2027
Test name
Test status
Simulation time 217630437 ps
CPU time 1.71 seconds
Started May 23 03:32:09 PM PDT 24
Finished May 23 03:32:12 PM PDT 24
Peak memory 204828 kb
Host smart-2ce94ae7-609b-44cb-9476-fdae5aba08e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3647168027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3647168027
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2609749392
Short name T1977
Test name
Test status
Simulation time 288425037 ps
CPU time 3.5 seconds
Started May 23 03:31:54 PM PDT 24
Finished May 23 03:31:58 PM PDT 24
Peak memory 204820 kb
Host smart-4274dbcc-e172-420a-a76c-df0e6385ced4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2609749392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2609749392
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1957159983
Short name T1981
Test name
Test status
Simulation time 37642115 ps
CPU time 0.69 seconds
Started May 23 03:32:41 PM PDT 24
Finished May 23 03:32:45 PM PDT 24
Peak memory 204476 kb
Host smart-3c2ddb7e-ec7f-4fa6-abc9-f763114f75de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1957159983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1957159983
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.711276686
Short name T293
Test name
Test status
Simulation time 49941194 ps
CPU time 0.65 seconds
Started May 23 03:32:44 PM PDT 24
Finished May 23 03:32:50 PM PDT 24
Peak memory 204496 kb
Host smart-8f665a04-9526-4593-ab01-6e271f3ca183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=711276686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.711276686
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2146080253
Short name T294
Test name
Test status
Simulation time 41641845 ps
CPU time 0.66 seconds
Started May 23 03:32:43 PM PDT 24
Finished May 23 03:32:49 PM PDT 24
Peak memory 204500 kb
Host smart-0d59f0c9-8659-4d29-9eff-777bfd8d55ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2146080253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2146080253
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1872548521
Short name T2000
Test name
Test status
Simulation time 88899301 ps
CPU time 0.69 seconds
Started May 23 03:32:39 PM PDT 24
Finished May 23 03:32:41 PM PDT 24
Peak memory 204444 kb
Host smart-4fee6298-cfc0-4414-b71b-4a95daefc435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1872548521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1872548521
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2927787678
Short name T1960
Test name
Test status
Simulation time 31153909 ps
CPU time 0.68 seconds
Started May 23 03:32:45 PM PDT 24
Finished May 23 03:32:52 PM PDT 24
Peak memory 204432 kb
Host smart-fc0b3326-bcb0-4563-b76c-af8f16904b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2927787678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2927787678
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2949484161
Short name T290
Test name
Test status
Simulation time 38304639 ps
CPU time 0.73 seconds
Started May 23 03:32:40 PM PDT 24
Finished May 23 03:32:43 PM PDT 24
Peak memory 204452 kb
Host smart-ae973e89-a84c-4957-b957-fceb60461410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2949484161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2949484161
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4151685777
Short name T302
Test name
Test status
Simulation time 40584438 ps
CPU time 0.68 seconds
Started May 23 03:32:42 PM PDT 24
Finished May 23 03:32:48 PM PDT 24
Peak memory 204520 kb
Host smart-657012b4-3067-42b7-a42d-e22346b35d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4151685777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.4151685777
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.305755454
Short name T1956
Test name
Test status
Simulation time 103897034 ps
CPU time 2.04 seconds
Started May 23 03:32:12 PM PDT 24
Finished May 23 03:32:17 PM PDT 24
Peak memory 212988 kb
Host smart-d8b22b91-b7d4-4243-bfe1-ee6d7a433309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305755454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.305755454
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.836392912
Short name T251
Test name
Test status
Simulation time 45632939 ps
CPU time 0.87 seconds
Started May 23 03:32:09 PM PDT 24
Finished May 23 03:32:11 PM PDT 24
Peak memory 204564 kb
Host smart-1e7eadf7-3fbd-4fc2-a19b-1cc318fc41a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=836392912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.836392912
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1958366367
Short name T2020
Test name
Test status
Simulation time 37012883 ps
CPU time 0.66 seconds
Started May 23 03:32:11 PM PDT 24
Finished May 23 03:32:14 PM PDT 24
Peak memory 204488 kb
Host smart-74385d32-69df-4344-ab4b-e4e707229847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1958366367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1958366367
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3311411105
Short name T270
Test name
Test status
Simulation time 243638133 ps
CPU time 1.9 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:14 PM PDT 24
Peak memory 204812 kb
Host smart-0369bcf6-bfe8-4d42-8bd8-5912e06ed8b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3311411105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3311411105
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.665976141
Short name T2031
Test name
Test status
Simulation time 134450246 ps
CPU time 1.63 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:14 PM PDT 24
Peak memory 204800 kb
Host smart-c83cc4b6-5954-41fb-aabe-9dfada297cfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=665976141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.665976141
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.101328555
Short name T286
Test name
Test status
Simulation time 424780848 ps
CPU time 2.9 seconds
Started May 23 03:32:11 PM PDT 24
Finished May 23 03:32:16 PM PDT 24
Peak memory 204856 kb
Host smart-5d190cd9-6b04-45b9-9daf-8ad52f3bd981
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=101328555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.101328555
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3030446432
Short name T1958
Test name
Test status
Simulation time 98742277 ps
CPU time 2.11 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:14 PM PDT 24
Peak memory 213040 kb
Host smart-387e23fe-2172-43f8-9d4a-ff2229c36962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030446432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3030446432
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3448213765
Short name T1995
Test name
Test status
Simulation time 53067285 ps
CPU time 0.81 seconds
Started May 23 03:32:08 PM PDT 24
Finished May 23 03:32:10 PM PDT 24
Peak memory 204524 kb
Host smart-d7d78222-4909-4a3c-98ce-1cb2c8b15cf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3448213765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3448213765
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.821892241
Short name T281
Test name
Test status
Simulation time 54026489 ps
CPU time 0.66 seconds
Started May 23 03:32:08 PM PDT 24
Finished May 23 03:32:10 PM PDT 24
Peak memory 204452 kb
Host smart-dfa16a0e-6f56-4284-9ddc-756e60dd54f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=821892241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.821892241
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1297157192
Short name T202
Test name
Test status
Simulation time 229188580 ps
CPU time 1.68 seconds
Started May 23 03:32:08 PM PDT 24
Finished May 23 03:32:11 PM PDT 24
Peak memory 204844 kb
Host smart-de65ea97-64eb-46a0-9105-ac1ff172e12c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1297157192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1297157192
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.415080947
Short name T282
Test name
Test status
Simulation time 275550372 ps
CPU time 2.35 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:15 PM PDT 24
Peak memory 204812 kb
Host smart-b7596279-0f12-4cb2-8a69-28f50b0ac0f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=415080947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.415080947
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1111352931
Short name T2016
Test name
Test status
Simulation time 96436428 ps
CPU time 1.99 seconds
Started May 23 03:32:07 PM PDT 24
Finished May 23 03:32:10 PM PDT 24
Peak memory 212976 kb
Host smart-eeb5a973-a3a5-4901-a91c-dee72fac6387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111352931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1111352931
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3297988929
Short name T1985
Test name
Test status
Simulation time 69629879 ps
CPU time 0.95 seconds
Started May 23 03:32:09 PM PDT 24
Finished May 23 03:32:11 PM PDT 24
Peak memory 204724 kb
Host smart-ab404e3b-b626-468e-81c9-d54c3911fa46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3297988929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3297988929
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3700094133
Short name T1989
Test name
Test status
Simulation time 51017236 ps
CPU time 0.74 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:13 PM PDT 24
Peak memory 204444 kb
Host smart-84ec84e5-8fff-4021-9647-0ab0fd930bf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3700094133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3700094133
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3373725426
Short name T1953
Test name
Test status
Simulation time 73151010 ps
CPU time 1.01 seconds
Started May 23 03:32:08 PM PDT 24
Finished May 23 03:32:10 PM PDT 24
Peak memory 204904 kb
Host smart-1aa8387c-a86d-4b48-969f-7c61600306c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3373725426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3373725426
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2285453681
Short name T232
Test name
Test status
Simulation time 207264636 ps
CPU time 2.12 seconds
Started May 23 03:32:11 PM PDT 24
Finished May 23 03:32:15 PM PDT 24
Peak memory 213012 kb
Host smart-e2e37c54-dc2f-418c-b252-5bee3ea866c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2285453681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2285453681
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1495521246
Short name T2037
Test name
Test status
Simulation time 424263469 ps
CPU time 2.35 seconds
Started May 23 03:32:12 PM PDT 24
Finished May 23 03:32:17 PM PDT 24
Peak memory 204820 kb
Host smart-d1a79547-db66-43a7-acc3-9b1a549de166
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1495521246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1495521246
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2636617955
Short name T1952
Test name
Test status
Simulation time 74778698 ps
CPU time 1.29 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:14 PM PDT 24
Peak memory 213120 kb
Host smart-793b4b00-e7da-47e7-994e-5d2798187500
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636617955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2636617955
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2132278972
Short name T1969
Test name
Test status
Simulation time 66440317 ps
CPU time 0.85 seconds
Started May 23 03:32:09 PM PDT 24
Finished May 23 03:32:12 PM PDT 24
Peak memory 204500 kb
Host smart-67bcb4e9-b003-42a9-927e-0743ab8e053c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2132278972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2132278972
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3766240650
Short name T291
Test name
Test status
Simulation time 39403019 ps
CPU time 0.71 seconds
Started May 23 03:32:12 PM PDT 24
Finished May 23 03:32:15 PM PDT 24
Peak memory 204208 kb
Host smart-6c879e3c-442c-4493-88bd-93a374bd4f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3766240650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3766240650
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2879157959
Short name T268
Test name
Test status
Simulation time 214763465 ps
CPU time 1.55 seconds
Started May 23 03:32:09 PM PDT 24
Finished May 23 03:32:11 PM PDT 24
Peak memory 204860 kb
Host smart-b9847410-5d90-43ef-a520-91ac82385cb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2879157959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2879157959
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1228074972
Short name T1993
Test name
Test status
Simulation time 234275661 ps
CPU time 2.71 seconds
Started May 23 03:32:10 PM PDT 24
Finished May 23 03:32:15 PM PDT 24
Peak memory 204844 kb
Host smart-2d6d7919-0b70-4502-838d-1441a81873b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1228074972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1228074972
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1117413282
Short name T1975
Test name
Test status
Simulation time 280469301 ps
CPU time 2.43 seconds
Started May 23 03:32:11 PM PDT 24
Finished May 23 03:32:16 PM PDT 24
Peak memory 204844 kb
Host smart-89e04efc-9dbf-4426-8ae9-daa391284ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1117413282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1117413282
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2671915240
Short name T274
Test name
Test status
Simulation time 108492039 ps
CPU time 1.24 seconds
Started May 23 03:32:27 PM PDT 24
Finished May 23 03:32:32 PM PDT 24
Peak memory 214572 kb
Host smart-bcaef2f5-fd8e-414e-ba5c-672fa4c24955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671915240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2671915240
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3761603145
Short name T1976
Test name
Test status
Simulation time 53045152 ps
CPU time 0.83 seconds
Started May 23 03:32:25 PM PDT 24
Finished May 23 03:32:27 PM PDT 24
Peak memory 204468 kb
Host smart-485690c5-b9c7-49d2-9818-8c87aa0bc6b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3761603145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3761603145
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4189771361
Short name T279
Test name
Test status
Simulation time 65399797 ps
CPU time 0.69 seconds
Started May 23 03:32:27 PM PDT 24
Finished May 23 03:32:31 PM PDT 24
Peak memory 204488 kb
Host smart-f07b944d-8ef2-42e4-b014-746057af9172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4189771361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.4189771361
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1887645106
Short name T2011
Test name
Test status
Simulation time 181606120 ps
CPU time 1.53 seconds
Started May 23 03:32:28 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 204864 kb
Host smart-72d2f125-745c-4b81-93c8-55c44269d415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1887645106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1887645106
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2333410229
Short name T1982
Test name
Test status
Simulation time 269517305 ps
CPU time 3.29 seconds
Started May 23 03:32:12 PM PDT 24
Finished May 23 03:32:17 PM PDT 24
Peak memory 204684 kb
Host smart-6efef0e7-b704-4756-9bc1-993f16e40ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2333410229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2333410229
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1276679259
Short name T1945
Test name
Test status
Simulation time 565497282 ps
CPU time 3.01 seconds
Started May 23 03:32:11 PM PDT 24
Finished May 23 03:32:17 PM PDT 24
Peak memory 204916 kb
Host smart-f4ee0ea2-4cda-41e3-9d7a-262b9980f0ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1276679259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1276679259
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.1986627153
Short name T585
Test name
Test status
Simulation time 10168997908 ps
CPU time 13.85 seconds
Started May 23 03:39:25 PM PDT 24
Finished May 23 03:39:49 PM PDT 24
Peak memory 204988 kb
Host smart-3a0d5ba8-776e-45b9-ad79-5d6cc420e411
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1986627153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.1986627153
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.3063920553
Short name T360
Test name
Test status
Simulation time 10073164622 ps
CPU time 12.5 seconds
Started May 23 03:39:42 PM PDT 24
Finished May 23 03:40:00 PM PDT 24
Peak memory 204864 kb
Host smart-43c65dea-6609-4e8a-92b4-430bd76457fa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3063920553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.3063920553
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.2012409775
Short name T380
Test name
Test status
Simulation time 10091128702 ps
CPU time 13.33 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:10 PM PDT 24
Peak memory 205008 kb
Host smart-1b19af09-d0e6-4a7a-a7ed-4de7d8a77093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20124
09775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.2012409775
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1138957939
Short name T1934
Test name
Test status
Simulation time 13366693316 ps
CPU time 16.37 seconds
Started May 23 03:39:16 PM PDT 24
Finished May 23 03:39:41 PM PDT 24
Peak memory 204976 kb
Host smart-fec3d4a5-d053-47c3-8ff8-8b0943af4767
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1138957939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.1138957939
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.2172100771
Short name T1398
Test name
Test status
Simulation time 13381618484 ps
CPU time 19.04 seconds
Started May 23 03:39:14 PM PDT 24
Finished May 23 03:39:47 PM PDT 24
Peak memory 205012 kb
Host smart-d16f5591-7c01-4a89-b7a0-cbad95632f51
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2172100771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2172100771
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.1084538832
Short name T1535
Test name
Test status
Simulation time 13333049714 ps
CPU time 16.96 seconds
Started May 23 03:39:26 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 204984 kb
Host smart-0cca97dc-a233-4202-b568-8dd11147ee5c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1084538832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.1084538832
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1365330601
Short name T809
Test name
Test status
Simulation time 10049211867 ps
CPU time 13.16 seconds
Started May 23 03:39:21 PM PDT 24
Finished May 23 03:39:43 PM PDT 24
Peak memory 204968 kb
Host smart-ec451c68-88f0-41a2-b672-327979f7e5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13653
30601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1365330601
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.498499423
Short name T538
Test name
Test status
Simulation time 10096066581 ps
CPU time 13.6 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:39 PM PDT 24
Peak memory 204944 kb
Host smart-b3735402-3cf3-44a7-8bc5-5f8d1152e53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49849
9423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.498499423
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3063650533
Short name T1911
Test name
Test status
Simulation time 10513010728 ps
CPU time 14.79 seconds
Started May 23 03:39:26 PM PDT 24
Finished May 23 03:39:50 PM PDT 24
Peak memory 204928 kb
Host smart-5726fa0d-00d5-475f-969d-6016ac43e386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30636
50533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3063650533
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_enable.3518775282
Short name T1275
Test name
Test status
Simulation time 10077449478 ps
CPU time 12.73 seconds
Started May 23 03:39:23 PM PDT 24
Finished May 23 03:39:45 PM PDT 24
Peak memory 204928 kb
Host smart-501407f4-1078-4ea0-9c57-57fc0cfb4bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35187
75282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3518775282
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.448688620
Short name T1303
Test name
Test status
Simulation time 10771031762 ps
CPU time 17.4 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:37 PM PDT 24
Peak memory 204964 kb
Host smart-9e64024e-2804-4a79-961c-a0612aa5c001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44868
8620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.448688620
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.3277806680
Short name T1865
Test name
Test status
Simulation time 10054286466 ps
CPU time 13.99 seconds
Started May 23 03:39:26 PM PDT 24
Finished May 23 03:39:50 PM PDT 24
Peak memory 204960 kb
Host smart-f0dfb55c-cdd7-4023-89cf-53518d2ed4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32778
06680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.3277806680
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2891907155
Short name T1501
Test name
Test status
Simulation time 10040110354 ps
CPU time 13.55 seconds
Started May 23 03:39:26 PM PDT 24
Finished May 23 03:39:49 PM PDT 24
Peak memory 204904 kb
Host smart-5c03609f-57a5-4d10-9fb1-f16542453d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28919
07155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2891907155
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3500959006
Short name T397
Test name
Test status
Simulation time 10091091838 ps
CPU time 12.73 seconds
Started May 23 03:39:24 PM PDT 24
Finished May 23 03:39:47 PM PDT 24
Peak memory 204976 kb
Host smart-c86ff9fe-bfc3-4ce4-919d-405c0a78b63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35009
59006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3500959006
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1175236114
Short name T1040
Test name
Test status
Simulation time 10153651491 ps
CPU time 13.45 seconds
Started May 23 03:39:15 PM PDT 24
Finished May 23 03:39:37 PM PDT 24
Peak memory 204936 kb
Host smart-5dd8287f-4c7a-4c8c-8523-6332197acbfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11752
36114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1175236114
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1130387484
Short name T667
Test name
Test status
Simulation time 13188019755 ps
CPU time 15.57 seconds
Started May 23 03:39:17 PM PDT 24
Finished May 23 03:39:41 PM PDT 24
Peak memory 204992 kb
Host smart-6b39cc95-4a1a-4ccb-a4b8-9c898e3811d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11303
87484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1130387484
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3871479322
Short name T1415
Test name
Test status
Simulation time 10112206315 ps
CPU time 13.82 seconds
Started May 23 03:39:24 PM PDT 24
Finished May 23 03:39:48 PM PDT 24
Peak memory 204984 kb
Host smart-7a9d509f-a5d0-4f6d-ab95-8ffeec4937a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38714
79322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3871479322
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2626746993
Short name T765
Test name
Test status
Simulation time 10051305987 ps
CPU time 15.43 seconds
Started May 23 03:39:23 PM PDT 24
Finished May 23 03:39:49 PM PDT 24
Peak memory 204912 kb
Host smart-a43476e8-0a8f-4ea3-b0d0-5bf298f254d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26267
46993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2626746993
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3615694421
Short name T73
Test name
Test status
Simulation time 10129157362 ps
CPU time 14.29 seconds
Started May 23 03:39:24 PM PDT 24
Finished May 23 03:39:48 PM PDT 24
Peak memory 204924 kb
Host smart-c16711c6-c683-41a0-a479-5a413d5cd703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36156
94421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3615694421
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3806339172
Short name T1554
Test name
Test status
Simulation time 10088051274 ps
CPU time 12.78 seconds
Started May 23 03:39:23 PM PDT 24
Finished May 23 03:39:46 PM PDT 24
Peak memory 204976 kb
Host smart-cb5f63d5-1773-470c-bf95-1a171058ec56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38063
39172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3806339172
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3538020737
Short name T1604
Test name
Test status
Simulation time 10056776858 ps
CPU time 13.13 seconds
Started May 23 03:39:23 PM PDT 24
Finished May 23 03:39:46 PM PDT 24
Peak memory 204944 kb
Host smart-3b554821-c9e0-47ec-ae65-a5351784fac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35380
20737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3538020737
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1809015148
Short name T1243
Test name
Test status
Simulation time 10099039580 ps
CPU time 13.34 seconds
Started May 23 03:39:27 PM PDT 24
Finished May 23 03:39:49 PM PDT 24
Peak memory 204952 kb
Host smart-8e49a380-3a4f-4791-96cd-7d867999ca32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18090
15148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1809015148
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2306477510
Short name T1390
Test name
Test status
Simulation time 10067864834 ps
CPU time 14.79 seconds
Started May 23 03:39:25 PM PDT 24
Finished May 23 03:39:50 PM PDT 24
Peak memory 204964 kb
Host smart-7e4fe3f7-e2a6-48ce-b779-bceb2db6a01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23064
77510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2306477510
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.1369482275
Short name T1305
Test name
Test status
Simulation time 23316831073 ps
CPU time 42.7 seconds
Started May 23 03:39:16 PM PDT 24
Finished May 23 03:40:07 PM PDT 24
Peak memory 204976 kb
Host smart-aab5fced-ba57-4529-ab11-46f192b0c055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13694
82275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.1369482275
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.90104253
Short name T1804
Test name
Test status
Simulation time 10088786188 ps
CPU time 13.99 seconds
Started May 23 03:39:21 PM PDT 24
Finished May 23 03:39:44 PM PDT 24
Peak memory 204968 kb
Host smart-2fc2f945-35d3-4624-aac4-25346c2079e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90104
253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.90104253
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1351921074
Short name T993
Test name
Test status
Simulation time 10109145185 ps
CPU time 14.12 seconds
Started May 23 03:39:12 PM PDT 24
Finished May 23 03:39:34 PM PDT 24
Peak memory 204948 kb
Host smart-457dd55d-04b7-412a-99d1-f3e2dbfbd672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519
21074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1351921074
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.529978078
Short name T1234
Test name
Test status
Simulation time 10079847542 ps
CPU time 15.57 seconds
Started May 23 03:39:20 PM PDT 24
Finished May 23 03:39:46 PM PDT 24
Peak memory 204932 kb
Host smart-0f8b5e76-4d89-4c9f-8616-a4b2cc1681df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52997
8078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.529978078
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.4219420728
Short name T966
Test name
Test status
Simulation time 10041304836 ps
CPU time 14.88 seconds
Started May 23 03:39:22 PM PDT 24
Finished May 23 03:39:47 PM PDT 24
Peak memory 204936 kb
Host smart-eb1ede34-75f0-4833-9899-19f71d0cd019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42194
20728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.4219420728
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.124751824
Short name T746
Test name
Test status
Simulation time 10105960211 ps
CPU time 13.62 seconds
Started May 23 03:39:42 PM PDT 24
Finished May 23 03:40:01 PM PDT 24
Peak memory 204968 kb
Host smart-0a3e537d-a149-425a-8209-6d2971d957eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12475
1824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.124751824
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1389956516
Short name T1153
Test name
Test status
Simulation time 10069240011 ps
CPU time 14.56 seconds
Started May 23 03:39:29 PM PDT 24
Finished May 23 03:39:52 PM PDT 24
Peak memory 204908 kb
Host smart-d657f8ac-231a-43dc-996a-60c19e6fbe94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13899
56516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1389956516
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1504861164
Short name T1025
Test name
Test status
Simulation time 10123112762 ps
CPU time 14.08 seconds
Started May 23 03:39:21 PM PDT 24
Finished May 23 03:39:44 PM PDT 24
Peak memory 204992 kb
Host smart-8dc2eccb-fe17-48c5-a374-60bee48028c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15048
61164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1504861164
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3550407631
Short name T516
Test name
Test status
Simulation time 10054047534 ps
CPU time 14.03 seconds
Started May 23 03:39:44 PM PDT 24
Finished May 23 03:40:03 PM PDT 24
Peak memory 205004 kb
Host smart-fb184382-184f-40be-b983-836244c5bb96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35504
07631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3550407631
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.1256453036
Short name T1096
Test name
Test status
Simulation time 10057563067 ps
CPU time 12.9 seconds
Started May 23 03:39:23 PM PDT 24
Finished May 23 03:39:46 PM PDT 24
Peak memory 204936 kb
Host smart-ca7ea00d-83e4-49b9-954b-7ab34b3bf120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12564
53036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.1256453036
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.3679655748
Short name T1515
Test name
Test status
Simulation time 10139170374 ps
CPU time 12.93 seconds
Started May 23 03:39:26 PM PDT 24
Finished May 23 03:39:48 PM PDT 24
Peak memory 204996 kb
Host smart-9252983c-4404-483d-9c09-80fc89d3ffe0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3679655748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.3679655748
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.1295797925
Short name T391
Test name
Test status
Simulation time 10095994277 ps
CPU time 14.41 seconds
Started May 23 03:39:29 PM PDT 24
Finished May 23 03:39:52 PM PDT 24
Peak memory 204900 kb
Host smart-ab0fe18a-17fc-49a9-b382-5de9de3da688
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1295797925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.1295797925
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.3902662948
Short name T562
Test name
Test status
Simulation time 10093180456 ps
CPU time 13.72 seconds
Started May 23 03:39:42 PM PDT 24
Finished May 23 03:40:01 PM PDT 24
Peak memory 204920 kb
Host smart-13af2f71-f4a1-4f92-a1bb-422694a70a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39026
62948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.3902662948
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.4164556583
Short name T1435
Test name
Test status
Simulation time 13235133319 ps
CPU time 16.86 seconds
Started May 23 03:39:29 PM PDT 24
Finished May 23 03:39:55 PM PDT 24
Peak memory 204932 kb
Host smart-53df502b-0468-4e6a-aeb3-a13934117cbf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4164556583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.4164556583
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.129485396
Short name T1872
Test name
Test status
Simulation time 13212365303 ps
CPU time 15.93 seconds
Started May 23 03:39:31 PM PDT 24
Finished May 23 03:39:55 PM PDT 24
Peak memory 204916 kb
Host smart-eb79635e-b7e4-4710-9403-d77572074529
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=129485396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.129485396
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3290429855
Short name T934
Test name
Test status
Simulation time 10048052838 ps
CPU time 14.77 seconds
Started May 23 03:39:39 PM PDT 24
Finished May 23 03:39:59 PM PDT 24
Peak memory 204936 kb
Host smart-0069581c-7baa-4f52-b2b2-80a4a9d7d74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32904
29855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3290429855
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.95110372
Short name T1901
Test name
Test status
Simulation time 10078459004 ps
CPU time 13.87 seconds
Started May 23 03:39:39 PM PDT 24
Finished May 23 03:39:58 PM PDT 24
Peak memory 204904 kb
Host smart-9f35ea0c-f681-4a6d-ae26-a3ec6971a73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95110
372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.95110372
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2125389404
Short name T720
Test name
Test status
Simulation time 10141740505 ps
CPU time 15.1 seconds
Started May 23 03:39:38 PM PDT 24
Finished May 23 03:39:59 PM PDT 24
Peak memory 204948 kb
Host smart-5e7af6d6-3b5d-42a2-970e-6aa7e9012c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21253
89404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2125389404
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3649770811
Short name T995
Test name
Test status
Simulation time 10074405231 ps
CPU time 14.13 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:12 PM PDT 24
Peak memory 204848 kb
Host smart-bbcc0d17-b16e-41d8-ba07-73b75c85467f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36497
70811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3649770811
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.1668844708
Short name T1667
Test name
Test status
Simulation time 10078557990 ps
CPU time 12.84 seconds
Started May 23 03:39:39 PM PDT 24
Finished May 23 03:39:57 PM PDT 24
Peak memory 205024 kb
Host smart-63b5c259-3cab-460f-bdc4-42d607242bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16688
44708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1668844708
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1836678936
Short name T377
Test name
Test status
Simulation time 10069201591 ps
CPU time 16.39 seconds
Started May 23 03:39:25 PM PDT 24
Finished May 23 03:39:51 PM PDT 24
Peak memory 204928 kb
Host smart-ab849b88-6c00-4e63-a9f6-dd64e211c7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18366
78936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1836678936
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.4166181586
Short name T1569
Test name
Test status
Simulation time 10102755150 ps
CPU time 12.95 seconds
Started May 23 03:39:48 PM PDT 24
Finished May 23 03:40:07 PM PDT 24
Peak memory 204936 kb
Host smart-18c8fed9-c1da-47c3-8f8b-6313d5a1c7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41661
81586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.4166181586
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3179599451
Short name T1918
Test name
Test status
Simulation time 10048256894 ps
CPU time 14.61 seconds
Started May 23 03:39:28 PM PDT 24
Finished May 23 03:39:52 PM PDT 24
Peak memory 204920 kb
Host smart-8bc08833-02af-4b6a-bcb6-9894426399ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31795
99451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3179599451
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1501750180
Short name T1709
Test name
Test status
Simulation time 10119690243 ps
CPU time 14.61 seconds
Started May 23 03:39:26 PM PDT 24
Finished May 23 03:39:50 PM PDT 24
Peak memory 205020 kb
Host smart-3a06895c-4f20-4712-9391-ac7de83e86c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15017
50180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1501750180
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.979260702
Short name T1187
Test name
Test status
Simulation time 10079278812 ps
CPU time 14.63 seconds
Started May 23 03:39:37 PM PDT 24
Finished May 23 03:39:58 PM PDT 24
Peak memory 204972 kb
Host smart-4769914e-2e62-4574-a756-76daaacc759b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97926
0702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.979260702
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.3891204746
Short name T1227
Test name
Test status
Simulation time 13260273342 ps
CPU time 15.64 seconds
Started May 23 03:39:27 PM PDT 24
Finished May 23 03:39:52 PM PDT 24
Peak memory 204984 kb
Host smart-b2c4f1e3-2d9b-4304-8028-e99cb0aefa66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38912
04746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3891204746
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.778852396
Short name T1706
Test name
Test status
Simulation time 10100792511 ps
CPU time 15.76 seconds
Started May 23 03:39:40 PM PDT 24
Finished May 23 03:40:01 PM PDT 24
Peak memory 204956 kb
Host smart-16854c08-f1e6-4ac2-8224-3f2faa6c76b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77885
2396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.778852396
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.499785987
Short name T1548
Test name
Test status
Simulation time 10049997605 ps
CPU time 16.55 seconds
Started May 23 03:39:26 PM PDT 24
Finished May 23 03:39:52 PM PDT 24
Peak memory 204932 kb
Host smart-90913bcc-e922-4caf-90f1-2e06a7c8a09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49978
5987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.499785987
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.2377954164
Short name T1756
Test name
Test status
Simulation time 10098762602 ps
CPU time 14.01 seconds
Started May 23 03:39:26 PM PDT 24
Finished May 23 03:39:50 PM PDT 24
Peak memory 204928 kb
Host smart-c0178269-8fcb-4f03-a8fc-7a19e5ff1a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23779
54164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.2377954164
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3639033761
Short name T1333
Test name
Test status
Simulation time 10055514575 ps
CPU time 13.1 seconds
Started May 23 03:39:31 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 204944 kb
Host smart-757fda68-a88d-461b-ba6a-82915b370dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36390
33761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3639033761
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.734654598
Short name T1624
Test name
Test status
Simulation time 10094963036 ps
CPU time 16.68 seconds
Started May 23 03:39:30 PM PDT 24
Finished May 23 03:39:56 PM PDT 24
Peak memory 204944 kb
Host smart-f97ce2a8-8820-42ae-a306-651c4f84e39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73465
4598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.734654598
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.910222706
Short name T452
Test name
Test status
Simulation time 10089603228 ps
CPU time 14.35 seconds
Started May 23 03:39:28 PM PDT 24
Finished May 23 03:39:51 PM PDT 24
Peak memory 204988 kb
Host smart-5fa3a2ec-d46a-4533-bde2-67dc675c2293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91022
2706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.910222706
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1317811981
Short name T939
Test name
Test status
Simulation time 10040141805 ps
CPU time 14.86 seconds
Started May 23 03:39:45 PM PDT 24
Finished May 23 03:40:05 PM PDT 24
Peak memory 204956 kb
Host smart-bc59ea9c-9a29-4569-8001-6b4cbdc87860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13178
11981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1317811981
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1262233076
Short name T834
Test name
Test status
Simulation time 28207698568 ps
CPU time 56.4 seconds
Started May 23 03:39:28 PM PDT 24
Finished May 23 03:40:34 PM PDT 24
Peak memory 205028 kb
Host smart-7555712a-6c09-4270-97c0-4e2d7dc5148f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12622
33076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1262233076
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.4072973969
Short name T1663
Test name
Test status
Simulation time 10096912863 ps
CPU time 12.87 seconds
Started May 23 03:39:42 PM PDT 24
Finished May 23 03:40:00 PM PDT 24
Peak memory 204916 kb
Host smart-91539435-abdf-4e13-ab59-648078ec9e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40729
73969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.4072973969
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.3611178978
Short name T1401
Test name
Test status
Simulation time 10106943839 ps
CPU time 14.65 seconds
Started May 23 03:39:27 PM PDT 24
Finished May 23 03:39:51 PM PDT 24
Peak memory 204940 kb
Host smart-faaa3353-0bdd-4975-968a-100d8a2c13a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36111
78978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.3611178978
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3076372427
Short name T1168
Test name
Test status
Simulation time 10063473947 ps
CPU time 12.61 seconds
Started May 23 03:39:27 PM PDT 24
Finished May 23 03:39:49 PM PDT 24
Peak memory 204956 kb
Host smart-3ed802e7-d997-4b84-8202-9cc363efe77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30763
72427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3076372427
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.584153377
Short name T208
Test name
Test status
Simulation time 1189455826 ps
CPU time 2.17 seconds
Started May 23 03:39:42 PM PDT 24
Finished May 23 03:39:49 PM PDT 24
Peak memory 221848 kb
Host smart-1e243e49-b48c-48a8-a92c-f603ff66918e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=584153377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.584153377
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1146409418
Short name T898
Test name
Test status
Simulation time 10116376188 ps
CPU time 16.48 seconds
Started May 23 03:39:28 PM PDT 24
Finished May 23 03:39:54 PM PDT 24
Peak memory 204916 kb
Host smart-9fc8ed8b-1026-406b-9094-9a4f46ae4f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11464
09418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1146409418
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3261427698
Short name T499
Test name
Test status
Simulation time 10087089348 ps
CPU time 12.55 seconds
Started May 23 03:39:35 PM PDT 24
Finished May 23 03:39:55 PM PDT 24
Peak memory 204912 kb
Host smart-c0d067fd-47b7-4c95-9048-40c6a3361454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32614
27698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3261427698
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.111025876
Short name T1610
Test name
Test status
Simulation time 10142113818 ps
CPU time 15.84 seconds
Started May 23 03:39:30 PM PDT 24
Finished May 23 03:39:54 PM PDT 24
Peak memory 204968 kb
Host smart-d60332c6-eaf6-4bff-b781-cc2a86e608d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11102
5876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.111025876
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.932203455
Short name T1425
Test name
Test status
Simulation time 10095559826 ps
CPU time 14.83 seconds
Started May 23 03:39:30 PM PDT 24
Finished May 23 03:39:54 PM PDT 24
Peak memory 204972 kb
Host smart-4c9f450f-3762-4242-86dc-d4abf3f907ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93220
3455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.932203455
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1064192535
Short name T602
Test name
Test status
Simulation time 10075810349 ps
CPU time 15.35 seconds
Started May 23 03:39:30 PM PDT 24
Finished May 23 03:39:54 PM PDT 24
Peak memory 204964 kb
Host smart-d2e59046-8012-49d5-9d24-89c54c7711ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10641
92535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1064192535
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.371166104
Short name T57
Test name
Test status
Simulation time 10137287133 ps
CPU time 14.64 seconds
Started May 23 03:40:39 PM PDT 24
Finished May 23 03:41:05 PM PDT 24
Peak memory 204980 kb
Host smart-133604cd-0516-4a5f-bb00-933b5a4194bc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=371166104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.371166104
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.1992835565
Short name T474
Test name
Test status
Simulation time 10075479571 ps
CPU time 15.75 seconds
Started May 23 03:40:23 PM PDT 24
Finished May 23 03:40:48 PM PDT 24
Peak memory 204928 kb
Host smart-bf75b31f-a776-409b-ac52-c2d3a3cde985
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1992835565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.1992835565
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.2039152236
Short name T1922
Test name
Test status
Simulation time 10100826539 ps
CPU time 12.49 seconds
Started May 23 03:40:22 PM PDT 24
Finished May 23 03:40:44 PM PDT 24
Peak memory 204992 kb
Host smart-3b5c89d6-3ee1-4568-b5b8-f24d54e4552f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20391
52236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.2039152236
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.4040623364
Short name T1917
Test name
Test status
Simulation time 13668823525 ps
CPU time 17.23 seconds
Started May 23 03:40:21 PM PDT 24
Finished May 23 03:40:48 PM PDT 24
Peak memory 204956 kb
Host smart-cdd18b76-8961-4fab-a25b-e4af7f4b45b2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4040623364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.4040623364
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1455486464
Short name T820
Test name
Test status
Simulation time 13242715970 ps
CPU time 16.78 seconds
Started May 23 03:40:27 PM PDT 24
Finished May 23 03:40:53 PM PDT 24
Peak memory 204904 kb
Host smart-3d1765e0-4b94-4f7e-9362-31eb9c98eb75
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1455486464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1455486464
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3650165644
Short name T1556
Test name
Test status
Simulation time 10051336493 ps
CPU time 13.38 seconds
Started May 23 03:40:22 PM PDT 24
Finished May 23 03:40:45 PM PDT 24
Peak memory 204964 kb
Host smart-3ddd45dd-ee0e-4078-9502-ec09cb9f984c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36501
65644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3650165644
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3636125811
Short name T1703
Test name
Test status
Simulation time 10054674334 ps
CPU time 14.34 seconds
Started May 23 03:40:18 PM PDT 24
Finished May 23 03:40:43 PM PDT 24
Peak memory 204772 kb
Host smart-6c201744-0c50-410f-aa62-2a14a654d36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36361
25811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3636125811
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2598989662
Short name T1618
Test name
Test status
Simulation time 11066574520 ps
CPU time 14.34 seconds
Started May 23 03:40:26 PM PDT 24
Finished May 23 03:40:50 PM PDT 24
Peak memory 205024 kb
Host smart-75af78c8-1df6-4a3c-b21c-de6a3d85a12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25989
89662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2598989662
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.150327674
Short name T689
Test name
Test status
Simulation time 10049523247 ps
CPU time 12.94 seconds
Started May 23 03:40:28 PM PDT 24
Finished May 23 03:40:50 PM PDT 24
Peak memory 204960 kb
Host smart-9befd459-5c50-4249-8874-a96e17adee49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15032
7674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.150327674
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.4113599739
Short name T475
Test name
Test status
Simulation time 10118563152 ps
CPU time 14.12 seconds
Started May 23 03:40:27 PM PDT 24
Finished May 23 03:40:51 PM PDT 24
Peak memory 204916 kb
Host smart-e21eef6e-3e02-4ddb-a1b2-d44e6ad766b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41135
99739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.4113599739
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2997272374
Short name T824
Test name
Test status
Simulation time 10861136086 ps
CPU time 16.61 seconds
Started May 23 03:40:20 PM PDT 24
Finished May 23 03:40:47 PM PDT 24
Peak memory 204960 kb
Host smart-edb4d817-b17e-419d-8a70-499ebf77e49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29972
72374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2997272374
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1382993921
Short name T1218
Test name
Test status
Simulation time 10208429787 ps
CPU time 14.83 seconds
Started May 23 03:40:27 PM PDT 24
Finished May 23 03:40:51 PM PDT 24
Peak memory 204932 kb
Host smart-d1665067-3f14-4a82-9e76-a5f5cccb2165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13829
93921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1382993921
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.785014609
Short name T1796
Test name
Test status
Simulation time 10151821635 ps
CPU time 14.99 seconds
Started May 23 03:40:30 PM PDT 24
Finished May 23 03:40:54 PM PDT 24
Peak memory 204968 kb
Host smart-20398047-93da-4ba0-a79b-322a9afe4f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78501
4609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.785014609
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2701000150
Short name T1672
Test name
Test status
Simulation time 10075361911 ps
CPU time 13.18 seconds
Started May 23 03:40:20 PM PDT 24
Finished May 23 03:40:43 PM PDT 24
Peak memory 204912 kb
Host smart-7f3fa17b-fc24-4c84-a9bf-b4ea790ffbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27010
00150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2701000150
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.448593584
Short name T1042
Test name
Test status
Simulation time 10079789317 ps
CPU time 15.3 seconds
Started May 23 03:40:27 PM PDT 24
Finished May 23 03:40:52 PM PDT 24
Peak memory 204904 kb
Host smart-0d68d8c5-b372-4390-a399-0eaad7c94040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44859
3584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.448593584
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.339684422
Short name T584
Test name
Test status
Simulation time 10122017617 ps
CPU time 12.25 seconds
Started May 23 03:40:34 PM PDT 24
Finished May 23 03:40:55 PM PDT 24
Peak memory 204972 kb
Host smart-28f0d4d4-1cfa-4d23-9dd2-cd2482fc4435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33968
4422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.339684422
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1912868364
Short name T844
Test name
Test status
Simulation time 13177818607 ps
CPU time 15.7 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:55 PM PDT 24
Peak memory 205000 kb
Host smart-a65f8687-3d7c-4ac9-9dbc-9fb813c67756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19128
68364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1912868364
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2127860527
Short name T525
Test name
Test status
Simulation time 10118165431 ps
CPU time 12.65 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:52 PM PDT 24
Peak memory 204972 kb
Host smart-88d9d4a7-5ea1-4f21-9de0-dcc20a1b5ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21278
60527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2127860527
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1823847370
Short name T1385
Test name
Test status
Simulation time 10096799537 ps
CPU time 14.1 seconds
Started May 23 03:40:21 PM PDT 24
Finished May 23 03:40:45 PM PDT 24
Peak memory 204964 kb
Host smart-d80298a6-ea7b-4bc5-ae0d-3c14c548eef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18238
47370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1823847370
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1459579573
Short name T1054
Test name
Test status
Simulation time 10100232739 ps
CPU time 13.49 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:53 PM PDT 24
Peak memory 204944 kb
Host smart-68789a1a-a697-47e2-bc97-922a934374c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14595
79573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1459579573
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1230973801
Short name T1718
Test name
Test status
Simulation time 10051884942 ps
CPU time 14.38 seconds
Started May 23 03:40:30 PM PDT 24
Finished May 23 03:40:53 PM PDT 24
Peak memory 204956 kb
Host smart-2980033a-0af8-4da0-9443-9b62d5278f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12309
73801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1230973801
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3212405740
Short name T1602
Test name
Test status
Simulation time 10077982713 ps
CPU time 12.78 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:54 PM PDT 24
Peak memory 204956 kb
Host smart-9f244681-1a1d-4ec0-becc-91704f5d142e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32124
05740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3212405740
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.3433397258
Short name T559
Test name
Test status
Simulation time 10086595892 ps
CPU time 12.65 seconds
Started May 23 03:40:21 PM PDT 24
Finished May 23 03:40:43 PM PDT 24
Peak memory 204920 kb
Host smart-895d2275-8181-4162-a0e5-247f2251c2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34333
97258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.3433397258
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.37460654
Short name T1290
Test name
Test status
Simulation time 10061889916 ps
CPU time 13.58 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:53 PM PDT 24
Peak memory 204972 kb
Host smart-2289eac0-4ab5-4f08-9380-ddec5085f109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37460
654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.37460654
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2683209897
Short name T635
Test name
Test status
Simulation time 10040698785 ps
CPU time 13.16 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:54 PM PDT 24
Peak memory 204972 kb
Host smart-e0764664-9e2e-4b5a-a40d-1d7acf766176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26832
09897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2683209897
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1074881045
Short name T247
Test name
Test status
Simulation time 21727853592 ps
CPU time 36.48 seconds
Started May 23 03:40:33 PM PDT 24
Finished May 23 03:41:18 PM PDT 24
Peak memory 205040 kb
Host smart-690072a0-fb43-41bb-b635-3e2b28b1d151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10748
81045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1074881045
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3738778440
Short name T1827
Test name
Test status
Simulation time 10132187618 ps
CPU time 14.53 seconds
Started May 23 03:40:35 PM PDT 24
Finished May 23 03:40:59 PM PDT 24
Peak memory 204992 kb
Host smart-fa2a030e-3e92-4661-ad11-40423d70cf3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37387
78440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3738778440
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2862586180
Short name T531
Test name
Test status
Simulation time 10129469290 ps
CPU time 14.07 seconds
Started May 23 03:40:33 PM PDT 24
Finished May 23 03:40:56 PM PDT 24
Peak memory 205004 kb
Host smart-73b3c5dd-db52-4a34-ae92-fb45215cecc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28625
86180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2862586180
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.2063227642
Short name T619
Test name
Test status
Simulation time 10058476640 ps
CPU time 13.16 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:53 PM PDT 24
Peak memory 204968 kb
Host smart-3757fdd0-ea0e-4c66-b2c3-48d022ebe3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20632
27642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.2063227642
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.470254402
Short name T1803
Test name
Test status
Simulation time 10050068129 ps
CPU time 13.61 seconds
Started May 23 03:40:30 PM PDT 24
Finished May 23 03:40:52 PM PDT 24
Peak memory 204948 kb
Host smart-cdeca07b-9c51-4697-8d2f-8f8613b93ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47025
4402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.470254402
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3013832496
Short name T1410
Test name
Test status
Simulation time 10059681660 ps
CPU time 12.81 seconds
Started May 23 03:40:38 PM PDT 24
Finished May 23 03:41:01 PM PDT 24
Peak memory 204916 kb
Host smart-cf9ae97d-ceaa-4fe1-aba1-78b6ed47472a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30138
32496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3013832496
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3000603198
Short name T1472
Test name
Test status
Simulation time 10050182419 ps
CPU time 13.62 seconds
Started May 23 03:40:28 PM PDT 24
Finished May 23 03:40:51 PM PDT 24
Peak memory 204984 kb
Host smart-b5511355-56f1-4061-b1ee-62c4a047a3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30006
03198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3000603198
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.81438283
Short name T1928
Test name
Test status
Simulation time 10139330502 ps
CPU time 13.51 seconds
Started May 23 03:40:22 PM PDT 24
Finished May 23 03:40:45 PM PDT 24
Peak memory 204960 kb
Host smart-f3aba3c7-e50f-4488-b736-cb78742304b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81438
283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.81438283
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2547492700
Short name T412
Test name
Test status
Simulation time 10081616213 ps
CPU time 14.57 seconds
Started May 23 03:40:33 PM PDT 24
Finished May 23 03:40:56 PM PDT 24
Peak memory 204976 kb
Host smart-4e139b7d-9ae8-4368-bf30-e148d113c842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25474
92700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2547492700
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.955582320
Short name T906
Test name
Test status
Simulation time 10143541684 ps
CPU time 13.63 seconds
Started May 23 03:40:41 PM PDT 24
Finished May 23 03:41:06 PM PDT 24
Peak memory 204920 kb
Host smart-11ada59b-370d-47b4-926f-3bbdb864ca92
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=955582320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.955582320
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.1953959050
Short name T984
Test name
Test status
Simulation time 10063376366 ps
CPU time 12.75 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:53 PM PDT 24
Peak memory 204960 kb
Host smart-53ff291c-c871-490a-acfd-f936107d9f89
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1953959050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.1953959050
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.1224046346
Short name T1307
Test name
Test status
Simulation time 10165083758 ps
CPU time 14.45 seconds
Started May 23 03:40:44 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204964 kb
Host smart-36154488-1b8c-4c60-8b42-4ead2dc331d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12240
46346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.1224046346
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3272266560
Short name T1138
Test name
Test status
Simulation time 13775634387 ps
CPU time 16.36 seconds
Started May 23 03:40:39 PM PDT 24
Finished May 23 03:41:06 PM PDT 24
Peak memory 204916 kb
Host smart-cbfb492e-d288-4b46-a0fa-f9ea9620faac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3272266560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.3272266560
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.101826856
Short name T1805
Test name
Test status
Simulation time 13278941304 ps
CPU time 17.9 seconds
Started May 23 03:40:38 PM PDT 24
Finished May 23 03:41:06 PM PDT 24
Peak memory 204968 kb
Host smart-ea90d755-b63f-44fc-a04f-b7759ffbdba5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=101826856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.101826856
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.359548915
Short name T1221
Test name
Test status
Simulation time 13402609466 ps
CPU time 16.92 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204952 kb
Host smart-36ebaea3-69f5-4cad-a53f-428cd754f56b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=359548915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.359548915
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.474622479
Short name T418
Test name
Test status
Simulation time 10110298822 ps
CPU time 13.37 seconds
Started May 23 03:40:25 PM PDT 24
Finished May 23 03:40:47 PM PDT 24
Peak memory 204996 kb
Host smart-1917c7c3-d801-422a-9a26-5f9c3eda1c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47462
2479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.474622479
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2862134452
Short name T169
Test name
Test status
Simulation time 10988607041 ps
CPU time 14.35 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:55 PM PDT 24
Peak memory 205064 kb
Host smart-8121a483-7432-439e-ab5b-f99acd31ab91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28621
34452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2862134452
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.355197563
Short name T1339
Test name
Test status
Simulation time 10063275882 ps
CPU time 13.62 seconds
Started May 23 03:40:27 PM PDT 24
Finished May 23 03:40:50 PM PDT 24
Peak memory 204936 kb
Host smart-e7939fe9-e0ae-4b3e-80e7-30dc43d0b3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35519
7563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.355197563
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.773015987
Short name T1311
Test name
Test status
Simulation time 10067577260 ps
CPU time 13.72 seconds
Started May 23 03:40:33 PM PDT 24
Finished May 23 03:40:55 PM PDT 24
Peak memory 205016 kb
Host smart-6c012a97-39c0-42bd-8bd1-5ee13c78eae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77301
5987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.773015987
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.893876085
Short name T426
Test name
Test status
Simulation time 10904313253 ps
CPU time 15.58 seconds
Started May 23 03:40:43 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204940 kb
Host smart-6b8d73e4-9f58-4b98-8705-151db0484c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89387
6085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.893876085
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3564052644
Short name T1439
Test name
Test status
Simulation time 10237081225 ps
CPU time 14.58 seconds
Started May 23 03:40:27 PM PDT 24
Finished May 23 03:40:51 PM PDT 24
Peak memory 204932 kb
Host smart-f279b5e7-f9dd-4121-b995-48dca04d64d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35640
52644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3564052644
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.398211975
Short name T1361
Test name
Test status
Simulation time 10123917434 ps
CPU time 13.02 seconds
Started May 23 03:40:43 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 204928 kb
Host smart-48e7576e-1217-4077-8a5f-63ae2354896c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39821
1975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.398211975
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1404935276
Short name T1563
Test name
Test status
Simulation time 10106496505 ps
CPU time 15.02 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:09 PM PDT 24
Peak memory 204984 kb
Host smart-17cc7dde-8c4a-437d-8a3a-20a378ce221e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14049
35276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1404935276
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2858049975
Short name T1857
Test name
Test status
Simulation time 10114478114 ps
CPU time 12.81 seconds
Started May 23 03:40:26 PM PDT 24
Finished May 23 03:40:48 PM PDT 24
Peak memory 204948 kb
Host smart-98b3f875-6347-4500-b1c5-dc06670b5e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28580
49975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2858049975
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.734710788
Short name T1268
Test name
Test status
Simulation time 10091474395 ps
CPU time 14.93 seconds
Started May 23 03:40:19 PM PDT 24
Finished May 23 03:40:44 PM PDT 24
Peak memory 204844 kb
Host smart-b1c3164c-68d9-4d3c-b070-ed9b7ef5ece7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73471
0788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.734710788
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.759912382
Short name T1211
Test name
Test status
Simulation time 13187061361 ps
CPU time 15.94 seconds
Started May 23 03:40:28 PM PDT 24
Finished May 23 03:40:53 PM PDT 24
Peak memory 204884 kb
Host smart-807e8536-2a0c-494a-a96c-e1c332aca949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75991
2382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.759912382
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.412808288
Short name T1371
Test name
Test status
Simulation time 10097460755 ps
CPU time 14.74 seconds
Started May 23 03:40:24 PM PDT 24
Finished May 23 03:40:48 PM PDT 24
Peak memory 204908 kb
Host smart-51ae99e5-0a65-487b-a0dd-1a98dd5d0540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41280
8288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.412808288
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2786302302
Short name T1744
Test name
Test status
Simulation time 10064696321 ps
CPU time 12.77 seconds
Started May 23 03:40:22 PM PDT 24
Finished May 23 03:40:45 PM PDT 24
Peak memory 204960 kb
Host smart-ac4e7b2e-050f-40ac-a9e5-082e8aa6068b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27863
02302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2786302302
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1812327868
Short name T1571
Test name
Test status
Simulation time 10105982931 ps
CPU time 12.66 seconds
Started May 23 03:40:41 PM PDT 24
Finished May 23 03:41:04 PM PDT 24
Peak memory 204888 kb
Host smart-937d6670-2b4e-4983-9fa5-0ac86585eb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18123
27868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1812327868
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3589225290
Short name T1798
Test name
Test status
Simulation time 10106673503 ps
CPU time 13.71 seconds
Started May 23 03:40:30 PM PDT 24
Finished May 23 03:40:52 PM PDT 24
Peak memory 204968 kb
Host smart-9cbc8c6d-4308-4970-bb3f-1bc87e0d56cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35892
25290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3589225290
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1619813574
Short name T1812
Test name
Test status
Simulation time 10080249416 ps
CPU time 13.54 seconds
Started May 23 03:40:44 PM PDT 24
Finished May 23 03:41:09 PM PDT 24
Peak memory 204956 kb
Host smart-74fe5dac-8bd4-4c00-ac45-c83a9ff8051f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16198
13574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1619813574
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.532078408
Short name T1711
Test name
Test status
Simulation time 10082294365 ps
CPU time 14.24 seconds
Started May 23 03:40:29 PM PDT 24
Finished May 23 03:40:52 PM PDT 24
Peak memory 204972 kb
Host smart-9519aec6-d99c-4fe3-a2f2-7336e1872040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53207
8408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.532078408
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.616844819
Short name T1741
Test name
Test status
Simulation time 10071583924 ps
CPU time 14.69 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:56 PM PDT 24
Peak memory 205012 kb
Host smart-c0552af6-5149-41f9-bd76-72c13e63366a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61684
4819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.616844819
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.712262235
Short name T56
Test name
Test status
Simulation time 10036508624 ps
CPU time 13.42 seconds
Started May 23 03:40:43 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 204952 kb
Host smart-7c8c5d23-8239-4e21-8116-ace2fe1cab42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71226
2235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.712262235
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1062826169
Short name T1555
Test name
Test status
Simulation time 10082016917 ps
CPU time 12.62 seconds
Started May 23 03:40:46 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204948 kb
Host smart-185c99a9-12dd-4b32-96fe-df0ee83d7347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10628
26169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1062826169
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.725138367
Short name T1086
Test name
Test status
Simulation time 10099189649 ps
CPU time 13.39 seconds
Started May 23 03:40:29 PM PDT 24
Finished May 23 03:40:51 PM PDT 24
Peak memory 204964 kb
Host smart-5b8cdf61-bcc7-4d79-9d5a-82d42e17ae45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72513
8367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.725138367
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.4244487802
Short name T813
Test name
Test status
Simulation time 10132780223 ps
CPU time 13.93 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 204984 kb
Host smart-b7e15d85-f202-4091-8086-87cae4a02c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42444
87802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.4244487802
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3672215531
Short name T916
Test name
Test status
Simulation time 10082302434 ps
CPU time 14.37 seconds
Started May 23 03:40:33 PM PDT 24
Finished May 23 03:40:57 PM PDT 24
Peak memory 204972 kb
Host smart-fe25fdfe-f757-4836-a78c-977b01d2d4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36722
15531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3672215531
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.3067401043
Short name T842
Test name
Test status
Simulation time 10053074469 ps
CPU time 15.33 seconds
Started May 23 03:40:45 PM PDT 24
Finished May 23 03:41:12 PM PDT 24
Peak memory 204952 kb
Host smart-36433960-9fd3-4c9e-bf69-976dfb7c4574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30674
01043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.3067401043
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2557117893
Short name T1122
Test name
Test status
Simulation time 10045799966 ps
CPU time 12.98 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:54 PM PDT 24
Peak memory 204884 kb
Host smart-23fb4256-3781-454f-8d2e-11bdf56b6349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25571
17893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2557117893
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3506082649
Short name T680
Test name
Test status
Simulation time 10069573103 ps
CPU time 12.9 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:53 PM PDT 24
Peak memory 205032 kb
Host smart-9c5bf1c4-02d9-4d70-90f3-05e2ab9cd5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35060
82649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3506082649
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.202982057
Short name T958
Test name
Test status
Simulation time 10118124828 ps
CPU time 14.34 seconds
Started May 23 03:40:36 PM PDT 24
Finished May 23 03:41:00 PM PDT 24
Peak memory 204952 kb
Host smart-2fc16054-b759-4c10-af19-c05fcc720019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20298
2057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.202982057
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.265662909
Short name T1190
Test name
Test status
Simulation time 10069204235 ps
CPU time 13.97 seconds
Started May 23 03:40:41 PM PDT 24
Finished May 23 03:41:06 PM PDT 24
Peak memory 204948 kb
Host smart-5c98d3e6-7358-4a21-a241-c15592ddab89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26566
2909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.265662909
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3828763938
Short name T1586
Test name
Test status
Simulation time 10062181088 ps
CPU time 13.27 seconds
Started May 23 03:40:30 PM PDT 24
Finished May 23 03:40:52 PM PDT 24
Peak memory 204980 kb
Host smart-9b29ee83-97b1-4cea-9286-ecbd533a09f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38287
63938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3828763938
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.3927757530
Short name T1396
Test name
Test status
Simulation time 10151493588 ps
CPU time 13.85 seconds
Started May 23 03:40:41 PM PDT 24
Finished May 23 03:41:06 PM PDT 24
Peak memory 204984 kb
Host smart-11ae1790-d620-4c89-b7bf-d44ecac52101
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3927757530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.3927757530
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.2068765800
Short name T837
Test name
Test status
Simulation time 10053398482 ps
CPU time 12.86 seconds
Started May 23 03:40:43 PM PDT 24
Finished May 23 03:41:08 PM PDT 24
Peak memory 204924 kb
Host smart-011b5d65-b450-4e51-a9e4-459c3bb4fe20
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2068765800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.2068765800
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.3336466864
Short name T345
Test name
Test status
Simulation time 10063309627 ps
CPU time 14.1 seconds
Started May 23 03:40:41 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 204988 kb
Host smart-9862d325-a141-48c6-b012-115701136437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33364
66864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.3336466864
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.2123815665
Short name T1030
Test name
Test status
Simulation time 14199831920 ps
CPU time 17.62 seconds
Started May 23 03:40:47 PM PDT 24
Finished May 23 03:41:16 PM PDT 24
Peak memory 204956 kb
Host smart-be53f6b9-498c-4a23-a764-2a05c9b19e60
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2123815665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.2123815665
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3113264902
Short name T608
Test name
Test status
Simulation time 13222822508 ps
CPU time 17.03 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:56 PM PDT 24
Peak memory 204928 kb
Host smart-95ff1bfd-7631-4374-a549-a25a89c6ba06
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3113264902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3113264902
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.3875914537
Short name T1870
Test name
Test status
Simulation time 13239395555 ps
CPU time 16.6 seconds
Started May 23 03:40:33 PM PDT 24
Finished May 23 03:40:58 PM PDT 24
Peak memory 204880 kb
Host smart-f29efc19-ffa2-4c35-8576-cd11ff7a9ce3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3875914537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.3875914537
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3944237271
Short name T1100
Test name
Test status
Simulation time 10065445170 ps
CPU time 12.65 seconds
Started May 23 03:40:38 PM PDT 24
Finished May 23 03:41:00 PM PDT 24
Peak memory 204980 kb
Host smart-09e1564b-4ab9-4533-9b94-bdc02a4853bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39442
37271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3944237271
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2579016162
Short name T1889
Test name
Test status
Simulation time 10915854663 ps
CPU time 14.42 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:55 PM PDT 24
Peak memory 205088 kb
Host smart-41df3864-7b97-4169-9713-cba780d6e587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25790
16162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2579016162
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.202975135
Short name T1628
Test name
Test status
Simulation time 10043577390 ps
CPU time 14.85 seconds
Started May 23 03:40:43 PM PDT 24
Finished May 23 03:41:09 PM PDT 24
Peak memory 204900 kb
Host smart-c6565684-03ca-43f3-bb55-de4dda455f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20297
5135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.202975135
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.472370516
Short name T946
Test name
Test status
Simulation time 10071437645 ps
CPU time 13.55 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:54 PM PDT 24
Peak memory 204960 kb
Host smart-cc6559d7-b89a-4a95-a858-60ba35c23e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47237
0516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.472370516
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2732728926
Short name T1523
Test name
Test status
Simulation time 10931711874 ps
CPU time 14.88 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:56 PM PDT 24
Peak memory 204928 kb
Host smart-ac05369b-df0d-45ff-b2fb-f6ee2e4192c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27327
28926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2732728926
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.447276543
Short name T735
Test name
Test status
Simulation time 10182131123 ps
CPU time 14.54 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:54 PM PDT 24
Peak memory 204964 kb
Host smart-9c13a0a4-948f-4629-963b-b90cd95a31d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44727
6543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.447276543
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1029184275
Short name T1579
Test name
Test status
Simulation time 10117812860 ps
CPU time 13.71 seconds
Started May 23 03:40:45 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204936 kb
Host smart-e826bb1a-13c4-4a4e-9c5e-606b8776c297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10291
84275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1029184275
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.318803233
Short name T64
Test name
Test status
Simulation time 10040715234 ps
CPU time 15.03 seconds
Started May 23 03:40:46 PM PDT 24
Finished May 23 03:41:12 PM PDT 24
Peak memory 205016 kb
Host smart-fa7799cf-37ac-4b5f-b47b-ce312903dc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31880
3233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.318803233
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3942702100
Short name T369
Test name
Test status
Simulation time 10090942806 ps
CPU time 13.94 seconds
Started May 23 03:40:33 PM PDT 24
Finished May 23 03:40:56 PM PDT 24
Peak memory 204924 kb
Host smart-776f1478-34fb-4f37-b661-b2b0cf5d32ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39427
02100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3942702100
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1779525289
Short name T1518
Test name
Test status
Simulation time 10091177839 ps
CPU time 16.33 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:57 PM PDT 24
Peak memory 204968 kb
Host smart-ef2a3cf3-f01e-4f9d-b9c2-498e8a2685f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17795
25289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1779525289
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.987103299
Short name T1476
Test name
Test status
Simulation time 13182423830 ps
CPU time 15.42 seconds
Started May 23 03:40:33 PM PDT 24
Finished May 23 03:40:58 PM PDT 24
Peak memory 204976 kb
Host smart-50341f77-ac51-4430-9f1f-f834e37ccdab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98710
3299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.987103299
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1487238828
Short name T1306
Test name
Test status
Simulation time 10130355733 ps
CPU time 14.11 seconds
Started May 23 03:40:41 PM PDT 24
Finished May 23 03:41:06 PM PDT 24
Peak memory 204944 kb
Host smart-0e891539-c186-4524-badb-cd294116a433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14872
38828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1487238828
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.849071617
Short name T805
Test name
Test status
Simulation time 10062626479 ps
CPU time 13.15 seconds
Started May 23 03:40:43 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 204964 kb
Host smart-20d0234b-ddb4-402b-baf8-8c74cf24c252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84907
1617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.849071617
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.890142547
Short name T1274
Test name
Test status
Simulation time 10094447021 ps
CPU time 13.05 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:53 PM PDT 24
Peak memory 204912 kb
Host smart-71a14f41-6fde-4789-9f09-c6f5ec3dbb38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89014
2547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.890142547
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3046564971
Short name T757
Test name
Test status
Simulation time 10131981502 ps
CPU time 14 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:54 PM PDT 24
Peak memory 205024 kb
Host smart-75cd3acb-1b40-45d4-85e4-dfac9446fc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30465
64971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3046564971
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.782114163
Short name T1783
Test name
Test status
Simulation time 10069543348 ps
CPU time 12.9 seconds
Started May 23 03:40:40 PM PDT 24
Finished May 23 03:41:04 PM PDT 24
Peak memory 204960 kb
Host smart-35c4c6fc-5a5a-4e54-ba7f-9f2dc56f0d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78211
4163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.782114163
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.3417077294
Short name T774
Test name
Test status
Simulation time 10062916874 ps
CPU time 14.66 seconds
Started May 23 03:40:38 PM PDT 24
Finished May 23 03:41:03 PM PDT 24
Peak memory 204940 kb
Host smart-21dae650-deba-424a-9bc9-4514f953c49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34170
77294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.3417077294
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3566485026
Short name T1587
Test name
Test status
Simulation time 10041933187 ps
CPU time 13.71 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 204952 kb
Host smart-6ca2d5fc-3b9a-4547-b808-a6dd52cb20d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35664
85026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3566485026
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.4092579205
Short name T811
Test name
Test status
Simulation time 10048229816 ps
CPU time 13.27 seconds
Started May 23 03:40:43 PM PDT 24
Finished May 23 03:41:08 PM PDT 24
Peak memory 204936 kb
Host smart-d2d112a8-db94-4fa5-9856-3b38381e5cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40925
79205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.4092579205
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1256084413
Short name T1115
Test name
Test status
Simulation time 26116573398 ps
CPU time 47.91 seconds
Started May 23 03:40:39 PM PDT 24
Finished May 23 03:41:38 PM PDT 24
Peak memory 205028 kb
Host smart-c3706a61-e61c-48bb-bb0f-aa02805fe7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12560
84413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1256084413
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.462666820
Short name T1562
Test name
Test status
Simulation time 10085255085 ps
CPU time 13.53 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 204952 kb
Host smart-748e2935-e73c-4b90-a55b-8c4d4d478643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46266
6820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.462666820
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3494734353
Short name T1090
Test name
Test status
Simulation time 10136170730 ps
CPU time 14.91 seconds
Started May 23 03:40:27 PM PDT 24
Finished May 23 03:40:52 PM PDT 24
Peak memory 204936 kb
Host smart-6774f1c0-508a-4475-9fce-c5989e4750e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34947
34353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3494734353
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.1105120653
Short name T1851
Test name
Test status
Simulation time 10101465481 ps
CPU time 12.44 seconds
Started May 23 03:40:33 PM PDT 24
Finished May 23 03:40:55 PM PDT 24
Peak memory 204968 kb
Host smart-7a072b38-d83a-4831-9e81-51898117b98b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11051
20653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.1105120653
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.803948595
Short name T1735
Test name
Test status
Simulation time 10043732856 ps
CPU time 15.2 seconds
Started May 23 03:40:31 PM PDT 24
Finished May 23 03:40:55 PM PDT 24
Peak memory 204940 kb
Host smart-acb45618-831f-4c45-92c8-285ed6c3db1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80394
8595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.803948595
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.20914
Short name T1927
Test name
Test status
Simulation time 10044285417 ps
CPU time 13.45 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:06 PM PDT 24
Peak memory 204928 kb
Host smart-8edb2a6f-3793-4b73-9830-3af75225562f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20914
-assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.20914
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2770553906
Short name T1732
Test name
Test status
Simulation time 10070769934 ps
CPU time 13.72 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:55 PM PDT 24
Peak memory 204972 kb
Host smart-4f66796d-27fd-4620-a248-23f33cd85b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27705
53906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2770553906
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2228597256
Short name T1260
Test name
Test status
Simulation time 10120590771 ps
CPU time 15.48 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:56 PM PDT 24
Peak memory 204968 kb
Host smart-f7d6abda-e593-4703-b61c-505979053b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22285
97256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2228597256
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3790090297
Short name T578
Test name
Test status
Simulation time 10058806293 ps
CPU time 13.25 seconds
Started May 23 03:40:39 PM PDT 24
Finished May 23 03:41:03 PM PDT 24
Peak memory 204904 kb
Host smart-45b97129-879b-48ee-b990-1e6319ec31fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37900
90297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3790090297
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2023005777
Short name T457
Test name
Test status
Simulation time 10053333801 ps
CPU time 14.5 seconds
Started May 23 03:40:40 PM PDT 24
Finished May 23 03:41:05 PM PDT 24
Peak memory 204968 kb
Host smart-fccdc1a1-34dc-464c-a022-45ab4c1805ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20230
05777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2023005777
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.2581812034
Short name T956
Test name
Test status
Simulation time 10163973995 ps
CPU time 13.81 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 204956 kb
Host smart-f9834b7a-3100-4898-8c10-6601b9f673ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2581812034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.2581812034
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.1289130670
Short name T1545
Test name
Test status
Simulation time 10085905105 ps
CPU time 13.39 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:21 PM PDT 24
Peak memory 204932 kb
Host smart-10f2914c-2853-484c-8ead-741506fc816b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1289130670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.1289130670
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.2338463981
Short name T1345
Test name
Test status
Simulation time 10084659308 ps
CPU time 13.89 seconds
Started May 23 03:40:53 PM PDT 24
Finished May 23 03:41:17 PM PDT 24
Peak memory 204956 kb
Host smart-2738f358-9b1d-40f6-b277-732901f9c1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23384
63981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.2338463981
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.781101142
Short name T1700
Test name
Test status
Simulation time 13780890621 ps
CPU time 22.01 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:16 PM PDT 24
Peak memory 204948 kb
Host smart-afee30b5-1ac9-468c-9fdc-132a0030957e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=781101142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.781101142
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3100662190
Short name T810
Test name
Test status
Simulation time 13242751731 ps
CPU time 15.66 seconds
Started May 23 03:41:05 PM PDT 24
Finished May 23 03:41:30 PM PDT 24
Peak memory 204972 kb
Host smart-49185b55-38a0-474e-bc52-7bb2cf5457b7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3100662190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3100662190
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.4128144129
Short name T8
Test name
Test status
Simulation time 13304889675 ps
CPU time 17.63 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:11 PM PDT 24
Peak memory 204956 kb
Host smart-5c0d30d9-1ce0-4e95-be71-f3659f1ed42a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4128144129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.4128144129
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3124411352
Short name T448
Test name
Test status
Simulation time 10088268145 ps
CPU time 15.06 seconds
Started May 23 03:40:55 PM PDT 24
Finished May 23 03:41:21 PM PDT 24
Peak memory 204884 kb
Host smart-7e945774-5466-4ef2-9c6e-84a0df6af26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31244
11352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3124411352
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3156076844
Short name T1014
Test name
Test status
Simulation time 10552969197 ps
CPU time 15.82 seconds
Started May 23 03:40:45 PM PDT 24
Finished May 23 03:41:12 PM PDT 24
Peak memory 204972 kb
Host smart-081d6040-28dc-4ee8-8ec3-f77682519335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31560
76844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3156076844
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.111764279
Short name T571
Test name
Test status
Simulation time 10064861772 ps
CPU time 13.91 seconds
Started May 23 03:40:52 PM PDT 24
Finished May 23 03:41:16 PM PDT 24
Peak memory 204964 kb
Host smart-60865506-3054-4824-a16e-783c0584fdba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11176
4279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.111764279
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.404869331
Short name T67
Test name
Test status
Simulation time 10055418145 ps
CPU time 12.84 seconds
Started May 23 03:40:48 PM PDT 24
Finished May 23 03:41:12 PM PDT 24
Peak memory 204976 kb
Host smart-da092d94-1ca0-4e5a-b51a-94bec3c97620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40486
9331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.404869331
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.520611965
Short name T348
Test name
Test status
Simulation time 10650486220 ps
CPU time 13.81 seconds
Started May 23 03:40:47 PM PDT 24
Finished May 23 03:41:12 PM PDT 24
Peak memory 204912 kb
Host smart-882d4824-3b26-4955-a0c9-5bb2ec63163c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52061
1965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.520611965
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2438845291
Short name T529
Test name
Test status
Simulation time 10088555709 ps
CPU time 15.95 seconds
Started May 23 03:40:53 PM PDT 24
Finished May 23 03:41:19 PM PDT 24
Peak memory 204888 kb
Host smart-5fb7c6c4-586d-430e-bfaf-98d190893de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24388
45291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2438845291
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.232507315
Short name T1551
Test name
Test status
Simulation time 10128379757 ps
CPU time 14.87 seconds
Started May 23 03:40:46 PM PDT 24
Finished May 23 03:41:12 PM PDT 24
Peak memory 204908 kb
Host smart-228d510b-7af3-4b88-a473-033960d0b0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23250
7315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.232507315
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3512498143
Short name T847
Test name
Test status
Simulation time 10062068322 ps
CPU time 13.03 seconds
Started May 23 03:40:44 PM PDT 24
Finished May 23 03:41:08 PM PDT 24
Peak memory 204832 kb
Host smart-f8dee25b-b7ea-4dca-8f35-2f57e1a3b7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35124
98143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3512498143
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1428248368
Short name T1080
Test name
Test status
Simulation time 10091588699 ps
CPU time 12.98 seconds
Started May 23 03:40:45 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204940 kb
Host smart-37830094-40c4-4c74-8652-29fa0c1b4f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14282
48368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1428248368
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.934205156
Short name T1689
Test name
Test status
Simulation time 10116307187 ps
CPU time 13.68 seconds
Started May 23 03:40:57 PM PDT 24
Finished May 23 03:41:21 PM PDT 24
Peak memory 204972 kb
Host smart-c6724352-7376-46cd-9f0f-9b7831e27f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93420
5156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.934205156
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3500187663
Short name T1664
Test name
Test status
Simulation time 13247870605 ps
CPU time 19.97 seconds
Started May 23 03:40:49 PM PDT 24
Finished May 23 03:41:20 PM PDT 24
Peak memory 204960 kb
Host smart-f8f10003-4626-4c48-bfac-e6712503c36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35001
87663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3500187663
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1721059268
Short name T376
Test name
Test status
Simulation time 10102833063 ps
CPU time 13 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 204944 kb
Host smart-c89ad1f6-243e-41a6-97fd-a859de9c0742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17210
59268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1721059268
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2594668607
Short name T913
Test name
Test status
Simulation time 10056542305 ps
CPU time 14.7 seconds
Started May 23 03:40:44 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204920 kb
Host smart-0fd93d40-dfb7-4163-96b5-865c484d429e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25946
68607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2594668607
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.661457750
Short name T446
Test name
Test status
Simulation time 10099739979 ps
CPU time 15.57 seconds
Started May 23 03:40:44 PM PDT 24
Finished May 23 03:41:11 PM PDT 24
Peak memory 204912 kb
Host smart-c5434935-4975-424a-b9aa-e9feaddc2b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66145
7750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.661457750
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.695679399
Short name T1939
Test name
Test status
Simulation time 10068673734 ps
CPU time 15.98 seconds
Started May 23 03:40:47 PM PDT 24
Finished May 23 03:41:14 PM PDT 24
Peak memory 204940 kb
Host smart-55e2f60e-bf6a-4a64-8e91-53244c3eeb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69567
9399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.695679399
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.4024655575
Short name T498
Test name
Test status
Simulation time 10051443631 ps
CPU time 13.68 seconds
Started May 23 03:40:43 PM PDT 24
Finished May 23 03:41:08 PM PDT 24
Peak memory 204936 kb
Host smart-8c66b999-c93f-4a03-ac6e-2aa8cca5c769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40246
55575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.4024655575
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.861791747
Short name T45
Test name
Test status
Simulation time 10074738266 ps
CPU time 13.58 seconds
Started May 23 03:40:54 PM PDT 24
Finished May 23 03:41:18 PM PDT 24
Peak memory 204936 kb
Host smart-504ec3c8-dead-40d2-834b-50aa98437c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86179
1747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.861791747
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.1076737421
Short name T1790
Test name
Test status
Simulation time 10104841127 ps
CPU time 13.51 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 204984 kb
Host smart-c5f532da-19bc-4aed-bfea-d323fba8fb9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10767
37421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.1076737421
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.370788369
Short name T647
Test name
Test status
Simulation time 10071735141 ps
CPU time 12.96 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:06 PM PDT 24
Peak memory 204964 kb
Host smart-cefc36fc-70bf-46af-b6d0-05cb5238ff9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37078
8369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.370788369
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2931855762
Short name T936
Test name
Test status
Simulation time 10048706793 ps
CPU time 13.32 seconds
Started May 23 03:40:44 PM PDT 24
Finished May 23 03:41:09 PM PDT 24
Peak memory 204984 kb
Host smart-9e1350c8-e448-494c-9d5c-5fd63c71e058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
55762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2931855762
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2362688985
Short name T93
Test name
Test status
Simulation time 23779561455 ps
CPU time 42.91 seconds
Started May 23 03:40:55 PM PDT 24
Finished May 23 03:41:48 PM PDT 24
Peak memory 204988 kb
Host smart-31e8734b-8e2f-4af9-8f15-eeac00a92eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23626
88985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2362688985
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1670769267
Short name T728
Test name
Test status
Simulation time 10064692505 ps
CPU time 15.82 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204908 kb
Host smart-054a586c-f38b-4143-98df-58133afc672f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16707
69267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1670769267
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2509286839
Short name T1670
Test name
Test status
Simulation time 10136214198 ps
CPU time 12.94 seconds
Started May 23 03:40:44 PM PDT 24
Finished May 23 03:41:08 PM PDT 24
Peak memory 204884 kb
Host smart-a71b434b-ccfb-4ff8-a70a-17db44ad96cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25092
86839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2509286839
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.1329037610
Short name T1007
Test name
Test status
Simulation time 10078338528 ps
CPU time 13.77 seconds
Started May 23 03:40:47 PM PDT 24
Finished May 23 03:41:17 PM PDT 24
Peak memory 204916 kb
Host smart-b93658dd-369b-4a0e-babd-7f2d9c558236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13290
37610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.1329037610
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2594860422
Short name T1528
Test name
Test status
Simulation time 10048760004 ps
CPU time 14.77 seconds
Started May 23 03:40:54 PM PDT 24
Finished May 23 03:41:19 PM PDT 24
Peak memory 204984 kb
Host smart-5b5ef087-2cac-415f-b071-ffb39347cf81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25948
60422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2594860422
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1354744149
Short name T634
Test name
Test status
Simulation time 10052899395 ps
CPU time 13.72 seconds
Started May 23 03:40:52 PM PDT 24
Finished May 23 03:41:16 PM PDT 24
Peak memory 205008 kb
Host smart-59ee5376-0563-4d9e-9db8-df335a492fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13547
44149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1354744149
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3690065287
Short name T62
Test name
Test status
Simulation time 10083079801 ps
CPU time 16.97 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204936 kb
Host smart-9a3c9d12-ca39-4fe4-990e-ac9c2c7b40cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36900
65287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3690065287
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1245306663
Short name T154
Test name
Test status
Simulation time 10145058375 ps
CPU time 13.89 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:07 PM PDT 24
Peak memory 204940 kb
Host smart-feedcb08-bcaf-467a-9c2d-f0cf85aa57a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12453
06663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1245306663
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.902806254
Short name T441
Test name
Test status
Simulation time 10098331513 ps
CPU time 13.08 seconds
Started May 23 03:40:43 PM PDT 24
Finished May 23 03:41:08 PM PDT 24
Peak memory 204904 kb
Host smart-7627f2e4-cffe-415d-8d58-ce5895469f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90280
6254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.902806254
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3621540660
Short name T1780
Test name
Test status
Simulation time 10072987107 ps
CPU time 13.33 seconds
Started May 23 03:40:45 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 205056 kb
Host smart-92f116a7-ae6e-4964-88c7-4aab571d71b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36215
40660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3621540660
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.2222373989
Short name T410
Test name
Test status
Simulation time 10155430389 ps
CPU time 15.82 seconds
Started May 23 03:40:57 PM PDT 24
Finished May 23 03:41:23 PM PDT 24
Peak memory 204952 kb
Host smart-16329eac-4156-4941-a0a0-0370a969dabd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2222373989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.2222373989
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.3883540032
Short name T616
Test name
Test status
Simulation time 10065151583 ps
CPU time 12.91 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 204908 kb
Host smart-f617ee16-649c-41dc-b911-0faf0bd08d41
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3883540032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.3883540032
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.2935779729
Short name T520
Test name
Test status
Simulation time 10116217438 ps
CPU time 16.16 seconds
Started May 23 03:40:57 PM PDT 24
Finished May 23 03:41:23 PM PDT 24
Peak memory 204960 kb
Host smart-3119dad7-4264-4011-bf70-af6d6afbde53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29357
79729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.2935779729
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.264969071
Short name T1148
Test name
Test status
Simulation time 13406995319 ps
CPU time 18.6 seconds
Started May 23 03:40:45 PM PDT 24
Finished May 23 03:41:15 PM PDT 24
Peak memory 205024 kb
Host smart-3332de04-0e71-4f38-820f-9e5c8a2074b3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=264969071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.264969071
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2903229328
Short name T1702
Test name
Test status
Simulation time 13263374845 ps
CPU time 16.64 seconds
Started May 23 03:40:56 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 204928 kb
Host smart-27bf2546-cde7-4216-a17c-6aeb4da66aae
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2903229328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2903229328
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1484129101
Short name T401
Test name
Test status
Simulation time 13226608611 ps
CPU time 18.99 seconds
Started May 23 03:40:43 PM PDT 24
Finished May 23 03:41:13 PM PDT 24
Peak memory 204960 kb
Host smart-79017d71-6756-4958-8f07-8ec89b5cec65
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1484129101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1484129101
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2706794800
Short name T336
Test name
Test status
Simulation time 10054104677 ps
CPU time 13.25 seconds
Started May 23 03:40:45 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204980 kb
Host smart-4fbd7473-9ca0-40a3-8cb2-d81b71078ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27067
94800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2706794800
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.201109166
Short name T716
Test name
Test status
Simulation time 10564340767 ps
CPU time 13.64 seconds
Started May 23 03:40:45 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204964 kb
Host smart-142ab704-296d-4448-80b6-170fe79ff78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20110
9166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.201109166
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.1351837330
Short name T1059
Test name
Test status
Simulation time 10046255566 ps
CPU time 13.23 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:41:23 PM PDT 24
Peak memory 204896 kb
Host smart-e93b9987-37c0-4225-809c-b92b43a35c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13518
37330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.1351837330
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.294162223
Short name T560
Test name
Test status
Simulation time 10050295952 ps
CPU time 12.74 seconds
Started May 23 03:40:51 PM PDT 24
Finished May 23 03:41:14 PM PDT 24
Peak memory 204928 kb
Host smart-e9c62ebb-3504-4cee-b545-42e6c47a8c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29416
2223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.294162223
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1692514519
Short name T357
Test name
Test status
Simulation time 10944669236 ps
CPU time 14.43 seconds
Started May 23 03:40:44 PM PDT 24
Finished May 23 03:41:09 PM PDT 24
Peak memory 204828 kb
Host smart-ae60889d-350d-435b-9b16-1aebbb6d2b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16925
14519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1692514519
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.213014311
Short name T506
Test name
Test status
Simulation time 10075059122 ps
CPU time 13.9 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:21 PM PDT 24
Peak memory 204516 kb
Host smart-cae7e805-26d9-401f-8aa3-0aed2b866421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21301
4311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.213014311
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1739273973
Short name T1539
Test name
Test status
Simulation time 10096113079 ps
CPU time 14.74 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204876 kb
Host smart-9c72bb67-9da4-451e-b865-9e764be73172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17392
73973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1739273973
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3380131597
Short name T1598
Test name
Test status
Simulation time 10048925218 ps
CPU time 13.69 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:21 PM PDT 24
Peak memory 204968 kb
Host smart-92f7e06b-8b94-4cf9-8825-354a21f2aaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33801
31597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3380131597
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.904103625
Short name T1581
Test name
Test status
Simulation time 10131328909 ps
CPU time 15.02 seconds
Started May 23 03:40:56 PM PDT 24
Finished May 23 03:41:21 PM PDT 24
Peak memory 204944 kb
Host smart-891f64a8-00af-4118-808c-a6966792989c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90410
3625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.904103625
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.61764687
Short name T1066
Test name
Test status
Simulation time 10114771952 ps
CPU time 15.1 seconds
Started May 23 03:40:57 PM PDT 24
Finished May 23 03:41:21 PM PDT 24
Peak memory 204884 kb
Host smart-cf4d15db-07de-49fc-93e1-610633b6ded6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61764
687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.61764687
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3203079400
Short name T963
Test name
Test status
Simulation time 13189629902 ps
CPU time 15.46 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:23 PM PDT 24
Peak memory 204928 kb
Host smart-619af7ce-47b5-4e1a-b4ac-9d52cfc51763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32030
79400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3203079400
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3743804914
Short name T1795
Test name
Test status
Simulation time 10113185185 ps
CPU time 15.29 seconds
Started May 23 03:41:05 PM PDT 24
Finished May 23 03:41:30 PM PDT 24
Peak memory 204972 kb
Host smart-c73f9c83-603e-4b9a-8bca-fe41e0e0af9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37438
04914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3743804914
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.286117707
Short name T843
Test name
Test status
Simulation time 10045319526 ps
CPU time 15.12 seconds
Started May 23 03:40:57 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 204944 kb
Host smart-e5aeb3fd-7b91-4735-b67f-0f7c879445f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28611
7707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.286117707
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.4156335326
Short name T1223
Test name
Test status
Simulation time 10133103806 ps
CPU time 13.71 seconds
Started May 23 03:40:54 PM PDT 24
Finished May 23 03:41:18 PM PDT 24
Peak memory 204972 kb
Host smart-4422fc04-bc4f-4de3-bf43-683978073cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41563
35326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.4156335326
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.2559674569
Short name T999
Test name
Test status
Simulation time 10110504609 ps
CPU time 15.38 seconds
Started May 23 03:40:47 PM PDT 24
Finished May 23 03:41:13 PM PDT 24
Peak memory 204996 kb
Host smart-39634229-bfa8-4773-a8c4-db2c5e55e66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25596
74569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.2559674569
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.939061861
Short name T1655
Test name
Test status
Simulation time 10088978545 ps
CPU time 13.83 seconds
Started May 23 03:40:46 PM PDT 24
Finished May 23 03:41:11 PM PDT 24
Peak memory 204996 kb
Host smart-9afee4dc-4c91-4959-9e7f-5b3adc5dd429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93906
1861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.939061861
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.1844619384
Short name T1516
Test name
Test status
Simulation time 10087008909 ps
CPU time 15.18 seconds
Started May 23 03:40:46 PM PDT 24
Finished May 23 03:41:12 PM PDT 24
Peak memory 204972 kb
Host smart-e517acfc-28f2-46a7-87c1-d141816f4425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18446
19384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.1844619384
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2841356947
Short name T1509
Test name
Test status
Simulation time 10056443554 ps
CPU time 13.39 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 204964 kb
Host smart-e19475ae-52b4-4ddb-82c4-9113b39e98d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28413
56947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2841356947
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1476904437
Short name T781
Test name
Test status
Simulation time 10040596251 ps
CPU time 12.97 seconds
Started May 23 03:41:01 PM PDT 24
Finished May 23 03:41:24 PM PDT 24
Peak memory 204968 kb
Host smart-e304788d-8f31-4a90-a869-c09bd1835be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14769
04437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1476904437
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1172739815
Short name T1688
Test name
Test status
Simulation time 10070611105 ps
CPU time 13.97 seconds
Started May 23 03:40:48 PM PDT 24
Finished May 23 03:41:13 PM PDT 24
Peak memory 204964 kb
Host smart-b88423b1-5d98-4120-b7c2-c8efc35b36b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11727
39815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1172739815
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2528807413
Short name T1255
Test name
Test status
Simulation time 10172679783 ps
CPU time 13.47 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:41:24 PM PDT 24
Peak memory 204964 kb
Host smart-b2a22ec9-71c1-4a24-a78a-966731c303ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25288
07413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2528807413
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.620197944
Short name T454
Test name
Test status
Simulation time 10071754812 ps
CPU time 12.52 seconds
Started May 23 03:41:05 PM PDT 24
Finished May 23 03:41:27 PM PDT 24
Peak memory 204968 kb
Host smart-0acd31ef-e015-4655-98c9-db01a7875a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62019
7944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.620197944
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.4257089586
Short name T1336
Test name
Test status
Simulation time 10046798248 ps
CPU time 13.04 seconds
Started May 23 03:40:48 PM PDT 24
Finished May 23 03:41:12 PM PDT 24
Peak memory 204952 kb
Host smart-5ceebe88-34db-4024-9532-f3cdd7f736c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42570
89586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.4257089586
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.110093344
Short name T1799
Test name
Test status
Simulation time 10075906115 ps
CPU time 16.07 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204940 kb
Host smart-a351ba44-f480-44f8-95f3-86380d9a061e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11009
3344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.110093344
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.204697165
Short name T1594
Test name
Test status
Simulation time 10077446220 ps
CPU time 14.35 seconds
Started May 23 03:41:05 PM PDT 24
Finished May 23 03:41:29 PM PDT 24
Peak memory 204972 kb
Host smart-d3400dcc-5480-4720-be71-acbb0260868e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20469
7165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.204697165
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2412783336
Short name T431
Test name
Test status
Simulation time 10159540805 ps
CPU time 13.32 seconds
Started May 23 03:40:54 PM PDT 24
Finished May 23 03:41:17 PM PDT 24
Peak memory 204948 kb
Host smart-42118fff-749e-41c2-a8fe-5f173da8a13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24127
83336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2412783336
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2191527832
Short name T768
Test name
Test status
Simulation time 10105553823 ps
CPU time 13.62 seconds
Started May 23 03:40:51 PM PDT 24
Finished May 23 03:41:16 PM PDT 24
Peak memory 204996 kb
Host smart-926258da-800f-4741-ae8b-40c2eb774fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21915
27832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2191527832
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1560328879
Short name T1399
Test name
Test status
Simulation time 10067340333 ps
CPU time 13.53 seconds
Started May 23 03:40:48 PM PDT 24
Finished May 23 03:41:12 PM PDT 24
Peak memory 204968 kb
Host smart-55a82bf9-3ea9-4b74-a5f7-42d368586575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15603
28879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1560328879
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.4141250723
Short name T739
Test name
Test status
Simulation time 10148445583 ps
CPU time 13.5 seconds
Started May 23 03:41:01 PM PDT 24
Finished May 23 03:41:24 PM PDT 24
Peak memory 205032 kb
Host smart-72a4c77e-51eb-445e-8a23-d5d4d3623eab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4141250723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.4141250723
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.711709148
Short name T570
Test name
Test status
Simulation time 10058853591 ps
CPU time 14.94 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:24 PM PDT 24
Peak memory 204916 kb
Host smart-ffa4980b-6741-446e-9e31-cdbeac51ac05
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=711709148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.711709148
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.2983774323
Short name T599
Test name
Test status
Simulation time 10083699527 ps
CPU time 13.56 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:41:24 PM PDT 24
Peak memory 204948 kb
Host smart-d86c8898-aa6b-44de-8413-e35aaeb9b987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29837
74323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2983774323
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2023722284
Short name T425
Test name
Test status
Simulation time 13705562163 ps
CPU time 18.45 seconds
Started May 23 03:40:57 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204924 kb
Host smart-98d814c0-21be-45b5-abe8-bcc4ce581fd8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2023722284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2023722284
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.4197011046
Short name T1564
Test name
Test status
Simulation time 13298569429 ps
CPU time 17 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:41:28 PM PDT 24
Peak memory 204900 kb
Host smart-ff762813-706a-4aab-8418-bb2b1baba5fe
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4197011046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.4197011046
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2940661691
Short name T745
Test name
Test status
Simulation time 10046078320 ps
CPU time 12.72 seconds
Started May 23 03:41:03 PM PDT 24
Finished May 23 03:41:26 PM PDT 24
Peak memory 204968 kb
Host smart-dadc4908-50b3-4714-9ffa-8a18f9861099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29406
61691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2940661691
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3549464896
Short name T480
Test name
Test status
Simulation time 10039474744 ps
CPU time 12.49 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:20 PM PDT 24
Peak memory 204924 kb
Host smart-86d22731-4c83-40de-8bd8-0ef5641b93f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35494
64896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3549464896
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.1700647089
Short name T1828
Test name
Test status
Simulation time 10057591286 ps
CPU time 13.97 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 204932 kb
Host smart-a0d26534-1d00-4c3f-9569-a74846264566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17006
47089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1700647089
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3601439029
Short name T840
Test name
Test status
Simulation time 10945177352 ps
CPU time 15.18 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:41:26 PM PDT 24
Peak memory 204932 kb
Host smart-440c516c-baff-4528-9cc0-5050e092d75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36014
39029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3601439029
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.4184422695
Short name T79
Test name
Test status
Simulation time 10078472731 ps
CPU time 16.24 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204920 kb
Host smart-6e64315f-3fe6-4503-9c31-99a948d8ae7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41844
22695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.4184422695
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3392866467
Short name T1506
Test name
Test status
Simulation time 10075694688 ps
CPU time 13.91 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:23 PM PDT 24
Peak memory 204928 kb
Host smart-4ea4d572-cf90-4f40-a6b0-bc9d6fa43dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33928
66467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3392866467
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2614636835
Short name T655
Test name
Test status
Simulation time 10081468324 ps
CPU time 13.52 seconds
Started May 23 03:41:02 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204884 kb
Host smart-a0b4aabc-f4eb-4741-9961-493042c9dfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26146
36835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2614636835
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1748383007
Short name T1374
Test name
Test status
Simulation time 10077817743 ps
CPU time 15.61 seconds
Started May 23 03:41:02 PM PDT 24
Finished May 23 03:41:27 PM PDT 24
Peak memory 204972 kb
Host smart-7e33d7b8-8ec4-4a92-ac26-f1bec14db3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17483
83007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1748383007
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3576159734
Short name T721
Test name
Test status
Simulation time 10071396742 ps
CPU time 12.88 seconds
Started May 23 03:41:02 PM PDT 24
Finished May 23 03:41:24 PM PDT 24
Peak memory 204972 kb
Host smart-260ce578-f5d7-461d-a111-7a32b1bef0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35761
59734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3576159734
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2242847608
Short name T775
Test name
Test status
Simulation time 13233092304 ps
CPU time 19.28 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:28 PM PDT 24
Peak memory 204964 kb
Host smart-46eb43c2-5121-4f6f-bd38-b6bfc56523cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22428
47608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2242847608
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1684916426
Short name T1103
Test name
Test status
Simulation time 10099717070 ps
CPU time 13.5 seconds
Started May 23 03:40:56 PM PDT 24
Finished May 23 03:41:19 PM PDT 24
Peak memory 204992 kb
Host smart-af258fec-f67a-4d93-a11d-4bdddb46628e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16849
16426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1684916426
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3113201168
Short name T1269
Test name
Test status
Simulation time 10064725448 ps
CPU time 13.89 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:21 PM PDT 24
Peak memory 204548 kb
Host smart-49159bc0-d851-41b2-8826-c848d492d6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31132
01168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3113201168
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1822210517
Short name T126
Test name
Test status
Simulation time 10101614359 ps
CPU time 12.28 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:41:23 PM PDT 24
Peak memory 204920 kb
Host smart-26b60d10-fc0a-47ce-a094-2f0610121641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18222
10517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1822210517
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1293005497
Short name T1797
Test name
Test status
Simulation time 10090416825 ps
CPU time 12.75 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:41:23 PM PDT 24
Peak memory 204976 kb
Host smart-15593a37-6317-4aab-a8d8-722b3cd76bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12930
05497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1293005497
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1379077582
Short name T1811
Test name
Test status
Simulation time 10096379673 ps
CPU time 14.53 seconds
Started May 23 03:40:56 PM PDT 24
Finished May 23 03:41:20 PM PDT 24
Peak memory 204920 kb
Host smart-771934ed-0bdb-4bb9-89d7-f68e1719e68d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13790
77582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1379077582
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3239619150
Short name T897
Test name
Test status
Simulation time 10054588617 ps
CPU time 13.17 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:20 PM PDT 24
Peak memory 204968 kb
Host smart-5c5d94e7-342d-42ef-a63b-1ad1cc696ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396
19150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3239619150
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.449003249
Short name T192
Test name
Test status
Simulation time 10063418161 ps
CPU time 12.93 seconds
Started May 23 03:41:09 PM PDT 24
Finished May 23 03:41:31 PM PDT 24
Peak memory 204940 kb
Host smart-64a5a451-aae0-467e-b573-8b7ec1d4ad67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44900
3249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.449003249
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.1146268581
Short name T969
Test name
Test status
Simulation time 10062774205 ps
CPU time 14.7 seconds
Started May 23 03:41:03 PM PDT 24
Finished May 23 03:41:27 PM PDT 24
Peak memory 204956 kb
Host smart-e5afeafe-0c99-4c6c-9bfc-6dbf6011ca21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11462
68581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.1146268581
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.19523422
Short name T33
Test name
Test status
Simulation time 10069886636 ps
CPU time 12.65 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 204948 kb
Host smart-f483f1d6-d551-474e-806d-61631f6e7c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19523
422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.19523422
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.4124484258
Short name T1500
Test name
Test status
Simulation time 10074313016 ps
CPU time 14.97 seconds
Started May 23 03:41:02 PM PDT 24
Finished May 23 03:41:27 PM PDT 24
Peak memory 204912 kb
Host smart-dd699b16-ce0c-4913-afd8-bf6e34ac6af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41244
84258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.4124484258
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.4184762817
Short name T37
Test name
Test status
Simulation time 21379138331 ps
CPU time 35.98 seconds
Started May 23 03:41:01 PM PDT 24
Finished May 23 03:41:47 PM PDT 24
Peak memory 205044 kb
Host smart-e2c1d635-8977-4394-ab9f-6d39c69f1936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41847
62817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.4184762817
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2080965599
Short name T1543
Test name
Test status
Simulation time 10089458177 ps
CPU time 16.45 seconds
Started May 23 03:40:56 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 204912 kb
Host smart-6465c57c-e502-416e-a410-3308723223be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20809
65599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2080965599
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2074966813
Short name T329
Test name
Test status
Simulation time 10104214834 ps
CPU time 12.77 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:20 PM PDT 24
Peak memory 204880 kb
Host smart-51e446ed-24d1-4188-9b99-758184ef13f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20749
66813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2074966813
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.2818594961
Short name T1344
Test name
Test status
Simulation time 10098610335 ps
CPU time 16.77 seconds
Started May 23 03:40:57 PM PDT 24
Finished May 23 03:41:24 PM PDT 24
Peak memory 204960 kb
Host smart-359f96f9-23b1-4158-a471-7146ccd9ed3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28185
94961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.2818594961
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2524992210
Short name T143
Test name
Test status
Simulation time 10045087220 ps
CPU time 12.39 seconds
Started May 23 03:41:03 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204980 kb
Host smart-492865b3-e798-478d-8fe0-b1c8aec2f070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25249
92210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2524992210
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2276308166
Short name T1881
Test name
Test status
Simulation time 10068096454 ps
CPU time 12.73 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 204988 kb
Host smart-22331572-13bd-4c57-ad68-432d1bcb1e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22763
08166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2276308166
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3822226521
Short name T1636
Test name
Test status
Simulation time 10099951347 ps
CPU time 13.11 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 204948 kb
Host smart-16e019ae-a90f-4fba-8f2e-fd9a1c1691db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38222
26521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3822226521
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2691834331
Short name T632
Test name
Test status
Simulation time 10059581175 ps
CPU time 14.17 seconds
Started May 23 03:41:02 PM PDT 24
Finished May 23 03:41:26 PM PDT 24
Peak memory 204904 kb
Host smart-ede64ce5-a82b-4266-9526-3ac8bf20dfb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26918
34331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2691834331
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.318281674
Short name T488
Test name
Test status
Simulation time 10067117177 ps
CPU time 12.82 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 204944 kb
Host smart-6bb74232-4d07-4231-b8a6-a4e29bbfbe8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31828
1674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.318281674
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.1556332680
Short name T409
Test name
Test status
Simulation time 10137170379 ps
CPU time 12.64 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204944 kb
Host smart-c91aaaf0-eff5-40a4-bcd7-ea8f255b2eb7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1556332680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.1556332680
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.809437174
Short name T1514
Test name
Test status
Simulation time 10046827756 ps
CPU time 12.28 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204928 kb
Host smart-ae2faad0-4792-48fc-bb5f-4bc3528c2630
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=809437174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.809437174
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.2077881091
Short name T1560
Test name
Test status
Simulation time 10077243710 ps
CPU time 15.56 seconds
Started May 23 03:41:10 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204972 kb
Host smart-5c226a98-9963-4f81-b83a-4ab1c94cd0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20778
81091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.2077881091
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.214355760
Short name T243
Test name
Test status
Simulation time 14107415584 ps
CPU time 16.5 seconds
Started May 23 03:41:07 PM PDT 24
Finished May 23 03:41:33 PM PDT 24
Peak memory 204976 kb
Host smart-5309b883-8767-4dc5-bb0d-353353498a2f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=214355760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.214355760
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3710491934
Short name T851
Test name
Test status
Simulation time 13226809235 ps
CPU time 20.14 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:28 PM PDT 24
Peak memory 204992 kb
Host smart-929e117e-ea94-40df-948d-e167b543aec7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3710491934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3710491934
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2533998603
Short name T1649
Test name
Test status
Simulation time 13297505494 ps
CPU time 18.66 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:41:29 PM PDT 24
Peak memory 204912 kb
Host smart-6cc9c895-2f68-4635-ab51-0977cfbb1e57
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2533998603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2533998603
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.500347230
Short name T1135
Test name
Test status
Simulation time 10064724621 ps
CPU time 13.18 seconds
Started May 23 03:41:01 PM PDT 24
Finished May 23 03:41:24 PM PDT 24
Peak memory 205008 kb
Host smart-bc229035-312f-4a2d-bdd9-042115fbb183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50034
7230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.500347230
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.154906059
Short name T641
Test name
Test status
Simulation time 10227081669 ps
CPU time 15.85 seconds
Started May 23 03:41:03 PM PDT 24
Finished May 23 03:41:29 PM PDT 24
Peak memory 204976 kb
Host smart-13113f5d-c764-460a-895e-73ca14291f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15490
6059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.154906059
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.1027901578
Short name T530
Test name
Test status
Simulation time 10077216026 ps
CPU time 15.27 seconds
Started May 23 03:41:09 PM PDT 24
Finished May 23 03:41:33 PM PDT 24
Peak memory 204940 kb
Host smart-9f321144-345a-47a3-a6d2-421c99869747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10279
01578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1027901578
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.2069078576
Short name T1229
Test name
Test status
Simulation time 10070321593 ps
CPU time 13.51 seconds
Started May 23 03:41:10 PM PDT 24
Finished May 23 03:41:32 PM PDT 24
Peak memory 204960 kb
Host smart-adfc3d65-2b92-4a66-af3d-988eecadb131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20690
78576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2069078576
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1624256643
Short name T59
Test name
Test status
Simulation time 10814337377 ps
CPU time 13.7 seconds
Started May 23 03:41:04 PM PDT 24
Finished May 23 03:41:28 PM PDT 24
Peak memory 204976 kb
Host smart-0871c4e9-9d1b-4038-b98a-2c5c19ccd83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16242
56643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1624256643
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3585707846
Short name T1903
Test name
Test status
Simulation time 10084932481 ps
CPU time 14.43 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204940 kb
Host smart-2428ba32-d0c6-4a2b-a70a-15cf62b3f42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35857
07846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3585707846
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.412520851
Short name T1720
Test name
Test status
Simulation time 10120512815 ps
CPU time 16.74 seconds
Started May 23 03:41:09 PM PDT 24
Finished May 23 03:41:35 PM PDT 24
Peak memory 204956 kb
Host smart-b16004e5-f231-4cf5-bdac-d66fc96f0376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41252
0851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.412520851
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3749180427
Short name T714
Test name
Test status
Simulation time 10069138834 ps
CPU time 12.26 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:33 PM PDT 24
Peak memory 204944 kb
Host smart-0d59ed77-bcc2-47f3-8a39-42712accd1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37491
80427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3749180427
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.561185010
Short name T1367
Test name
Test status
Simulation time 10135500010 ps
CPU time 16.18 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204976 kb
Host smart-a161bb84-3da7-4d41-9e19-805e64339700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56118
5010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.561185010
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.402343159
Short name T947
Test name
Test status
Simulation time 10099640111 ps
CPU time 13.4 seconds
Started May 23 03:40:57 PM PDT 24
Finished May 23 03:41:20 PM PDT 24
Peak memory 205024 kb
Host smart-9cf560da-0705-47da-9faa-7e9c3d4bf184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40234
3159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.402343159
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1081135067
Short name T1613
Test name
Test status
Simulation time 13199282501 ps
CPU time 15.72 seconds
Started May 23 03:41:09 PM PDT 24
Finished May 23 03:41:33 PM PDT 24
Peak memory 204944 kb
Host smart-77ffe769-a817-456e-9fda-87be5e6e6cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811
35067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1081135067
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3097963641
Short name T1733
Test name
Test status
Simulation time 10085585127 ps
CPU time 13.73 seconds
Started May 23 03:41:03 PM PDT 24
Finished May 23 03:41:27 PM PDT 24
Peak memory 204948 kb
Host smart-355b4824-4bc9-476f-8402-d0a2be85af1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30979
63641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3097963641
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3981719527
Short name T310
Test name
Test status
Simulation time 10048108074 ps
CPU time 16.35 seconds
Started May 23 03:41:09 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204920 kb
Host smart-2219c4a6-30aa-43b1-b58e-ac7abafc82bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39817
19527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3981719527
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.921087234
Short name T1212
Test name
Test status
Simulation time 10140862954 ps
CPU time 14.25 seconds
Started May 23 03:41:04 PM PDT 24
Finished May 23 03:41:28 PM PDT 24
Peak memory 204960 kb
Host smart-ffe22830-8143-43f5-9f9e-798b97875c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92108
7234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.921087234
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.86052588
Short name T1250
Test name
Test status
Simulation time 10106960741 ps
CPU time 14.39 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204884 kb
Host smart-c80dbd7b-8257-40e0-a593-f9559b6e8359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86052
588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.86052588
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1578614712
Short name T1715
Test name
Test status
Simulation time 10082643860 ps
CPU time 13.37 seconds
Started May 23 03:40:58 PM PDT 24
Finished May 23 03:41:22 PM PDT 24
Peak memory 205000 kb
Host smart-25b7197d-01a3-4dba-af5e-c9cc9ad25359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15786
14712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1578614712
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2998877007
Short name T1802
Test name
Test status
Simulation time 10103238249 ps
CPU time 15.72 seconds
Started May 23 03:40:59 PM PDT 24
Finished May 23 03:41:25 PM PDT 24
Peak memory 204952 kb
Host smart-6d6e2f2b-4213-4c8c-81d2-a3b4de102104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29988
77007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2998877007
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.3266014497
Short name T870
Test name
Test status
Simulation time 10099109732 ps
CPU time 12.99 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:41 PM PDT 24
Peak memory 205060 kb
Host smart-534123ed-4b7a-4c48-a674-a61ec9737cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32660
14497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.3266014497
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3798063058
Short name T833
Test name
Test status
Simulation time 10070224511 ps
CPU time 13.94 seconds
Started May 23 03:41:10 PM PDT 24
Finished May 23 03:41:33 PM PDT 24
Peak memory 204960 kb
Host smart-60ac1b74-8d53-493a-a059-f45abfc491ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37980
63058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3798063058
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3220919753
Short name T586
Test name
Test status
Simulation time 10040745023 ps
CPU time 13.86 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:35 PM PDT 24
Peak memory 205000 kb
Host smart-122c6786-ea75-4114-8c17-bca76276ff72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32209
19753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3220919753
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3789152113
Short name T1759
Test name
Test status
Simulation time 27987809055 ps
CPU time 53.53 seconds
Started May 23 03:41:00 PM PDT 24
Finished May 23 03:42:04 PM PDT 24
Peak memory 205020 kb
Host smart-1edd194f-6f27-4960-89c0-d7441e364deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37891
52113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3789152113
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.9089055
Short name T1097
Test name
Test status
Simulation time 10110891544 ps
CPU time 14.59 seconds
Started May 23 03:41:06 PM PDT 24
Finished May 23 03:41:30 PM PDT 24
Peak memory 204952 kb
Host smart-f4e8ba9d-a467-4e6a-ac00-909d2b8da67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90890
55 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.9089055
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1094048999
Short name T1185
Test name
Test status
Simulation time 10148854783 ps
CPU time 12.69 seconds
Started May 23 03:41:05 PM PDT 24
Finished May 23 03:41:28 PM PDT 24
Peak memory 204964 kb
Host smart-d45bf3a3-1f69-4f6c-9da9-f6eaa4aae55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10940
48999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1094048999
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.786825967
Short name T213
Test name
Test status
Simulation time 10070983492 ps
CPU time 15.16 seconds
Started May 23 03:41:01 PM PDT 24
Finished May 23 03:41:26 PM PDT 24
Peak memory 204972 kb
Host smart-6b626a6a-e6b0-4c96-8c81-e76dba4e463b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78682
5967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.786825967
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.2767608668
Short name T1724
Test name
Test status
Simulation time 10032300563 ps
CPU time 12.67 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:32 PM PDT 24
Peak memory 204968 kb
Host smart-4c0a0c8a-96f8-4ee7-a37e-f5c18cdc8ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27676
08668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.2767608668
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3076844205
Short name T579
Test name
Test status
Simulation time 10079971534 ps
CPU time 13.05 seconds
Started May 23 03:41:10 PM PDT 24
Finished May 23 03:41:32 PM PDT 24
Peak memory 204968 kb
Host smart-bd1b44dd-7b2f-497e-86e9-9d12be739b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30768
44205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3076844205
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.4108066598
Short name T1378
Test name
Test status
Simulation time 10097363296 ps
CPU time 13.43 seconds
Started May 23 03:41:11 PM PDT 24
Finished May 23 03:41:32 PM PDT 24
Peak memory 204932 kb
Host smart-68e43e60-5160-421c-9636-91ac62d727f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41080
66598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.4108066598
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1899758449
Short name T1576
Test name
Test status
Simulation time 10166146642 ps
CPU time 13.98 seconds
Started May 23 03:41:03 PM PDT 24
Finished May 23 03:41:27 PM PDT 24
Peak memory 204976 kb
Host smart-1df3c335-ba23-430f-b251-344386e425e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18997
58449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1899758449
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2584518972
Short name T1561
Test name
Test status
Simulation time 10065789227 ps
CPU time 13.18 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:33 PM PDT 24
Peak memory 203892 kb
Host smart-7fb3aaae-c32f-4f83-bf07-9982c67fca2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25845
18972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2584518972
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1100328027
Short name T871
Test name
Test status
Simulation time 10056107911 ps
CPU time 12.82 seconds
Started May 23 03:41:10 PM PDT 24
Finished May 23 03:41:31 PM PDT 24
Peak memory 204952 kb
Host smart-262e3414-123f-4e13-a84a-c543d8cd7a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11003
28027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1100328027
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.1476645916
Short name T1171
Test name
Test status
Simulation time 10144825649 ps
CPU time 13.1 seconds
Started May 23 03:41:15 PM PDT 24
Finished May 23 03:41:37 PM PDT 24
Peak memory 204944 kb
Host smart-227eb3f7-93ae-46ad-bd6a-eb90f85514ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1476645916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.1476645916
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.1698345007
Short name T659
Test name
Test status
Simulation time 10045640218 ps
CPU time 15.38 seconds
Started May 23 03:41:11 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204932 kb
Host smart-b750d689-db3f-4e4b-b8e3-58efac6c8b20
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1698345007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.1698345007
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.2116924945
Short name T25
Test name
Test status
Simulation time 10118641950 ps
CPU time 13.22 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204940 kb
Host smart-d949ef32-17fa-4dc3-835b-2a5da9f23c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21169
24945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.2116924945
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2888812129
Short name T1130
Test name
Test status
Simulation time 13736229169 ps
CPU time 15.79 seconds
Started May 23 03:41:09 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204960 kb
Host smart-6c5dcd2e-619a-4855-a451-3fbd90dad3dd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2888812129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.2888812129
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2931410770
Short name T554
Test name
Test status
Simulation time 13373668708 ps
CPU time 17.13 seconds
Started May 23 03:41:11 PM PDT 24
Finished May 23 03:41:37 PM PDT 24
Peak memory 204932 kb
Host smart-4df90541-24ec-4dae-8065-265fb3fe49a4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2931410770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2931410770
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.4143952422
Short name T1779
Test name
Test status
Simulation time 13301618222 ps
CPU time 16.48 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:37 PM PDT 24
Peak memory 204908 kb
Host smart-fd8ef439-3f80-46bf-9d7b-9e0d4c16196c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4143952422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.4143952422
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3624223773
Short name T83
Test name
Test status
Simulation time 10054151403 ps
CPU time 12.47 seconds
Started May 23 03:41:15 PM PDT 24
Finished May 23 03:41:37 PM PDT 24
Peak memory 204884 kb
Host smart-d519fedc-5be2-4a5c-8f53-9456867b3d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36242
23773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3624223773
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2761866621
Short name T591
Test name
Test status
Simulation time 10511443570 ps
CPU time 14.19 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 203892 kb
Host smart-650d32ce-7998-4a83-a118-801ca7481f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27618
66621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2761866621
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3216985834
Short name T323
Test name
Test status
Simulation time 10088559122 ps
CPU time 14.17 seconds
Started May 23 03:41:14 PM PDT 24
Finished May 23 03:41:37 PM PDT 24
Peak memory 204952 kb
Host smart-8166a698-aedb-4c63-a436-aac6f35028a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32169
85834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3216985834
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3517930629
Short name T1056
Test name
Test status
Simulation time 10053209553 ps
CPU time 15.27 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 204992 kb
Host smart-81012928-66cf-4e4b-8808-9563b7244da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35179
30629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3517930629
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1810663896
Short name T1111
Test name
Test status
Simulation time 10801989301 ps
CPU time 16.61 seconds
Started May 23 03:41:10 PM PDT 24
Finished May 23 03:41:35 PM PDT 24
Peak memory 204992 kb
Host smart-71c73b8b-ff6d-4331-81f7-a708d96422bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18106
63896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1810663896
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2912897946
Short name T978
Test name
Test status
Simulation time 10088477974 ps
CPU time 14.64 seconds
Started May 23 03:41:09 PM PDT 24
Finished May 23 03:41:33 PM PDT 24
Peak memory 204920 kb
Host smart-8108db56-6502-43e7-86c2-5705569a0337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29128
97946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2912897946
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.567143233
Short name T1413
Test name
Test status
Simulation time 10091970409 ps
CPU time 13.21 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204904 kb
Host smart-2eb22f00-b5d9-4754-ac1f-51949b980f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56714
3233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.567143233
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.117284652
Short name T681
Test name
Test status
Simulation time 10034195225 ps
CPU time 13.15 seconds
Started May 23 03:41:14 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 204896 kb
Host smart-b6131fe3-943b-4085-af21-430658c83da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11728
4652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.117284652
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.416210023
Short name T1819
Test name
Test status
Simulation time 10174586276 ps
CPU time 13.93 seconds
Started May 23 03:41:10 PM PDT 24
Finished May 23 03:41:32 PM PDT 24
Peak memory 204964 kb
Host smart-728e4fc4-a91a-4881-abf1-6419b51e54bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41621
0023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.416210023
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.670869856
Short name T1606
Test name
Test status
Simulation time 10094621328 ps
CPU time 12.92 seconds
Started May 23 03:41:11 PM PDT 24
Finished May 23 03:41:32 PM PDT 24
Peak memory 204908 kb
Host smart-02b59378-ea7d-47cd-8cb5-d00df35c87a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67086
9856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.670869856
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2501643201
Short name T1176
Test name
Test status
Simulation time 13191194835 ps
CPU time 16.6 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:38 PM PDT 24
Peak memory 204960 kb
Host smart-15179a58-bfcc-4762-8b62-c02940870118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25016
43201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2501643201
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2080254783
Short name T1549
Test name
Test status
Simulation time 10097616245 ps
CPU time 13.51 seconds
Started May 23 03:41:10 PM PDT 24
Finished May 23 03:41:32 PM PDT 24
Peak memory 204912 kb
Host smart-a2b1f8c1-5c16-4563-adbb-7d2d91f94c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20802
54783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2080254783
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3999457332
Short name T349
Test name
Test status
Simulation time 10046513433 ps
CPU time 13.52 seconds
Started May 23 03:41:11 PM PDT 24
Finished May 23 03:41:32 PM PDT 24
Peak memory 204964 kb
Host smart-ee108bb7-1e2e-4dcb-8377-c5d177dd2d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39994
57332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3999457332
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.496246197
Short name T125
Test name
Test status
Simulation time 10124705914 ps
CPU time 12.87 seconds
Started May 23 03:41:10 PM PDT 24
Finished May 23 03:41:32 PM PDT 24
Peak memory 204916 kb
Host smart-573984be-1870-446d-a909-f6ed49ca3232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49624
6197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.496246197
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.648359322
Short name T688
Test name
Test status
Simulation time 10091351819 ps
CPU time 13.28 seconds
Started May 23 03:41:14 PM PDT 24
Finished May 23 03:41:35 PM PDT 24
Peak memory 204912 kb
Host smart-19725c9c-834e-4cb1-90aa-53446981959a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64835
9322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.648359322
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1731904612
Short name T541
Test name
Test status
Simulation time 10067761752 ps
CPU time 12.99 seconds
Started May 23 03:41:11 PM PDT 24
Finished May 23 03:41:32 PM PDT 24
Peak memory 204952 kb
Host smart-62bc9783-e457-48e6-acac-c6b434085de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17319
04612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1731904612
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2372268047
Short name T1121
Test name
Test status
Simulation time 10118395574 ps
CPU time 13.28 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204936 kb
Host smart-17c72876-297e-4b45-b99a-c4e83baf1b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23722
68047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2372268047
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2726270640
Short name T137
Test name
Test status
Simulation time 10110251858 ps
CPU time 14.67 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 204980 kb
Host smart-06f2f490-c5e7-4f21-944d-f722c120ea0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27262
70640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2726270640
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.4076265423
Short name T308
Test name
Test status
Simulation time 10086991664 ps
CPU time 12.92 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204968 kb
Host smart-c4731dca-83e2-42ab-a7f4-9a18b9015d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40762
65423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.4076265423
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2418174190
Short name T1340
Test name
Test status
Simulation time 10059886613 ps
CPU time 13.72 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:35 PM PDT 24
Peak memory 204936 kb
Host smart-806a36d8-af75-4515-bfd6-63b6436ed37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24181
74190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2418174190
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1814293545
Short name T1077
Test name
Test status
Simulation time 10069997985 ps
CPU time 13.59 seconds
Started May 23 03:41:14 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 204964 kb
Host smart-634cefd8-fe12-4b82-a2cd-22152c5b4dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18142
93545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1814293545
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2840950547
Short name T92
Test name
Test status
Simulation time 32958085211 ps
CPU time 63.27 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:42:24 PM PDT 24
Peak memory 205024 kb
Host smart-dd6cc3f6-57bb-4f79-9451-8e13f52a9bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28409
50547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2840950547
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.3838872039
Short name T1869
Test name
Test status
Simulation time 10129399770 ps
CPU time 14.99 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 204992 kb
Host smart-0fe59692-12b5-4758-ba38-e03025699df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38388
72039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3838872039
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2749594014
Short name T1814
Test name
Test status
Simulation time 10107879299 ps
CPU time 13.74 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204960 kb
Host smart-d15b1958-b7e0-4ba5-9e4d-1093a37ab93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27495
94014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2749594014
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.4243835762
Short name T1222
Test name
Test status
Simulation time 10085579858 ps
CPU time 12.33 seconds
Started May 23 03:41:10 PM PDT 24
Finished May 23 03:41:31 PM PDT 24
Peak memory 204908 kb
Host smart-f7a72c5b-21bc-4212-a9a5-61fc10879259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42438
35762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.4243835762
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.901435699
Short name T566
Test name
Test status
Simulation time 10040290760 ps
CPU time 13.08 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204920 kb
Host smart-fc6c901c-d0e5-4889-b714-51f43794d1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90143
5699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.901435699
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.4014900337
Short name T1893
Test name
Test status
Simulation time 10061492338 ps
CPU time 14.81 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 204948 kb
Host smart-596eac28-e6d9-46c5-9646-902e966c861e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40149
00337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.4014900337
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3293158543
Short name T317
Test name
Test status
Simulation time 10051765977 ps
CPU time 13.56 seconds
Started May 23 03:41:14 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 204776 kb
Host smart-8c1d806c-fe4a-482f-b779-c9b9955c5345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32931
58543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3293158543
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.4130550933
Short name T1873
Test name
Test status
Simulation time 10188646477 ps
CPU time 12.82 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204980 kb
Host smart-a6720af8-02eb-4972-b43a-9eea7fb27ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41305
50933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.4130550933
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3807765390
Short name T717
Test name
Test status
Simulation time 10093194290 ps
CPU time 16.07 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:37 PM PDT 24
Peak memory 204992 kb
Host smart-1ee5f953-ad24-46e7-9872-cf1e62209f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38077
65390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3807765390
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.579100670
Short name T997
Test name
Test status
Simulation time 10098509374 ps
CPU time 14.1 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:35 PM PDT 24
Peak memory 204916 kb
Host smart-43839afa-518b-43c8-9f56-5bb2d1b36297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57910
0670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.579100670
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.551656656
Short name T1559
Test name
Test status
Simulation time 10140938006 ps
CPU time 16.19 seconds
Started May 23 03:41:19 PM PDT 24
Finished May 23 03:41:46 PM PDT 24
Peak memory 204956 kb
Host smart-6056f65e-fe03-48af-948c-6028e8b4aabb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=551656656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.551656656
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.2166605308
Short name T857
Test name
Test status
Simulation time 10061749992 ps
CPU time 13.31 seconds
Started May 23 03:41:19 PM PDT 24
Finished May 23 03:41:43 PM PDT 24
Peak memory 204956 kb
Host smart-f2048146-7e5c-4bc5-a93b-b20b629a397e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2166605308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.2166605308
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.2741206948
Short name T350
Test name
Test status
Simulation time 10104942405 ps
CPU time 14.86 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 204960 kb
Host smart-846b2400-338d-4538-80e2-f40283e984af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27412
06948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.2741206948
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3756823126
Short name T1394
Test name
Test status
Simulation time 14228094655 ps
CPU time 16.64 seconds
Started May 23 03:41:15 PM PDT 24
Finished May 23 03:41:42 PM PDT 24
Peak memory 204948 kb
Host smart-74739387-ced9-4125-8532-078cff957baf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3756823126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.3756823126
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2996781915
Short name T1878
Test name
Test status
Simulation time 13225568010 ps
CPU time 18.97 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:40 PM PDT 24
Peak memory 204944 kb
Host smart-2d56e4ef-4dbe-4a21-a2a0-ec6c7ba40a66
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2996781915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2996781915
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3380211575
Short name T1195
Test name
Test status
Simulation time 13297297752 ps
CPU time 17.18 seconds
Started May 23 03:41:16 PM PDT 24
Finished May 23 03:41:43 PM PDT 24
Peak memory 204948 kb
Host smart-1a713b96-67c2-4629-a141-33b12800ad53
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3380211575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.3380211575
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2389067692
Short name T510
Test name
Test status
Simulation time 10081672859 ps
CPU time 14.66 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 204948 kb
Host smart-6aebaa9d-df0e-47e6-afd2-250fb6067826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23890
67692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2389067692
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2824904679
Short name T1213
Test name
Test status
Simulation time 10119265273 ps
CPU time 13.9 seconds
Started May 23 03:41:15 PM PDT 24
Finished May 23 03:41:38 PM PDT 24
Peak memory 205032 kb
Host smart-5aee5254-d022-4405-9173-33ce96746cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28249
04679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2824904679
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.4286618446
Short name T71
Test name
Test status
Simulation time 10038695416 ps
CPU time 13.12 seconds
Started May 23 03:41:20 PM PDT 24
Finished May 23 03:41:44 PM PDT 24
Peak memory 204932 kb
Host smart-ac7ebcd6-6784-45d8-8a0c-a9e34d2197e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42866
18446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.4286618446
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.263087243
Short name T1916
Test name
Test status
Simulation time 10103764698 ps
CPU time 13.06 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204940 kb
Host smart-4c2c98b2-b801-40b2-acd6-e6755ca195f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26308
7243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.263087243
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2411688649
Short name T1769
Test name
Test status
Simulation time 10893307422 ps
CPU time 15.04 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 204956 kb
Host smart-de65a3cd-de42-4e3d-92f9-3a03fba02ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24116
88649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2411688649
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2398056688
Short name T899
Test name
Test status
Simulation time 10130724224 ps
CPU time 13.54 seconds
Started May 23 03:41:12 PM PDT 24
Finished May 23 03:41:34 PM PDT 24
Peak memory 204932 kb
Host smart-e028f96d-64b1-43d4-8218-08b9b3bf676f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23980
56688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2398056688
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.1413781504
Short name T318
Test name
Test status
Simulation time 10132542548 ps
CPU time 13.51 seconds
Started May 23 03:41:20 PM PDT 24
Finished May 23 03:41:44 PM PDT 24
Peak memory 204964 kb
Host smart-73c9b377-8b7d-4b7f-9575-4c1e790e2211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14137
81504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1413781504
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1458504770
Short name T322
Test name
Test status
Simulation time 10064624513 ps
CPU time 14.76 seconds
Started May 23 03:41:17 PM PDT 24
Finished May 23 03:41:42 PM PDT 24
Peak memory 204968 kb
Host smart-a6f59e7c-cb84-456e-9aba-0d42227841c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14585
04770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1458504770
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1620117445
Short name T517
Test name
Test status
Simulation time 10126131354 ps
CPU time 13.96 seconds
Started May 23 03:41:20 PM PDT 24
Finished May 23 03:41:44 PM PDT 24
Peak memory 204968 kb
Host smart-96c8a37f-fb00-43e3-a0b6-9b38dc967fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16201
17445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1620117445
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2907748010
Short name T1347
Test name
Test status
Simulation time 10058921431 ps
CPU time 12.9 seconds
Started May 23 03:41:20 PM PDT 24
Finished May 23 03:41:43 PM PDT 24
Peak memory 204972 kb
Host smart-7fc7ceec-04ae-451f-867f-4d7e53304f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29077
48010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2907748010
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3866306961
Short name T1384
Test name
Test status
Simulation time 13224778858 ps
CPU time 16.26 seconds
Started May 23 03:41:20 PM PDT 24
Finished May 23 03:41:47 PM PDT 24
Peak memory 204964 kb
Host smart-6476ab46-1e8a-4bb2-9b66-061cbc03cf20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38663
06961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3866306961
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2760651574
Short name T1270
Test name
Test status
Simulation time 10109884186 ps
CPU time 14.21 seconds
Started May 23 03:41:14 PM PDT 24
Finished May 23 03:41:37 PM PDT 24
Peak memory 204988 kb
Host smart-3d061d11-439e-47eb-ab21-35ad9e78edbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27606
51574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2760651574
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1319878895
Short name T556
Test name
Test status
Simulation time 10044088896 ps
CPU time 14.25 seconds
Started May 23 03:41:21 PM PDT 24
Finished May 23 03:41:45 PM PDT 24
Peak memory 204972 kb
Host smart-dbf8e3ed-1883-4650-9e0a-d77463254c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13198
78895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1319878895
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.4138430298
Short name T123
Test name
Test status
Simulation time 10177831838 ps
CPU time 12.57 seconds
Started May 23 03:41:25 PM PDT 24
Finished May 23 03:41:46 PM PDT 24
Peak memory 204972 kb
Host smart-1760ac16-cb44-4364-93af-cfe2c85bce9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41384
30298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.4138430298
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2586497864
Short name T497
Test name
Test status
Simulation time 10085614993 ps
CPU time 13.7 seconds
Started May 23 03:41:21 PM PDT 24
Finished May 23 03:41:44 PM PDT 24
Peak memory 204976 kb
Host smart-fbab4dc6-e49d-4b3a-a458-d4ec77ad8941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25864
97864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2586497864
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.532333238
Short name T987
Test name
Test status
Simulation time 10084877345 ps
CPU time 13.03 seconds
Started May 23 03:41:14 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 204956 kb
Host smart-15dacf59-4a16-47ef-86b4-677043164764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53233
3238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.532333238
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1586004240
Short name T505
Test name
Test status
Simulation time 10080025614 ps
CPU time 13.29 seconds
Started May 23 03:41:15 PM PDT 24
Finished May 23 03:41:37 PM PDT 24
Peak memory 205032 kb
Host smart-896b9c34-a337-4435-87df-9ed33838a490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15860
04240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1586004240
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2015805066
Short name T179
Test name
Test status
Simulation time 10061869889 ps
CPU time 12.35 seconds
Started May 23 03:41:17 PM PDT 24
Finished May 23 03:41:39 PM PDT 24
Peak memory 204868 kb
Host smart-929031d6-ebb8-4b85-b03f-1d38a0a2bbe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20158
05066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2015805066
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.2515781817
Short name T1443
Test name
Test status
Simulation time 10050761345 ps
CPU time 13.35 seconds
Started May 23 03:41:17 PM PDT 24
Finished May 23 03:41:40 PM PDT 24
Peak memory 204848 kb
Host smart-3a684a08-5bc1-4cfb-bc83-f46e3febc081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25157
81817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.2515781817
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.2968644458
Short name T697
Test name
Test status
Simulation time 10047580516 ps
CPU time 12.11 seconds
Started May 23 03:41:09 PM PDT 24
Finished May 23 03:41:30 PM PDT 24
Peak memory 204932 kb
Host smart-9ba45356-c539-4fb4-9c3f-38df2de5175c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29686
44458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.2968644458
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.217115949
Short name T977
Test name
Test status
Simulation time 10045443493 ps
CPU time 13.98 seconds
Started May 23 03:41:19 PM PDT 24
Finished May 23 03:41:44 PM PDT 24
Peak memory 204924 kb
Host smart-bf87baae-f770-41ba-974e-9c3beeaca636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21711
5949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.217115949
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.85480
Short name T178
Test name
Test status
Simulation time 23759149813 ps
CPU time 42.76 seconds
Started May 23 03:41:15 PM PDT 24
Finished May 23 03:42:07 PM PDT 24
Peak memory 204972 kb
Host smart-dbb7a3ee-9637-4f46-9ae9-530b7fa99324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85480
-assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.85480
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2229995893
Short name T1536
Test name
Test status
Simulation time 10131369190 ps
CPU time 12.48 seconds
Started May 23 03:41:17 PM PDT 24
Finished May 23 03:41:40 PM PDT 24
Peak memory 204868 kb
Host smart-93f9d9ee-e104-4b8d-8cc2-452b46146a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22299
95893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2229995893
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2721420398
Short name T1141
Test name
Test status
Simulation time 10205160025 ps
CPU time 12.81 seconds
Started May 23 03:41:17 PM PDT 24
Finished May 23 03:41:41 PM PDT 24
Peak memory 204840 kb
Host smart-f5844827-92bb-41c6-8f10-7e04729380ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27214
20398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2721420398
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.420742004
Short name T1456
Test name
Test status
Simulation time 10104653118 ps
CPU time 15.92 seconds
Started May 23 03:41:13 PM PDT 24
Finished May 23 03:41:37 PM PDT 24
Peak memory 205036 kb
Host smart-7dcab0ff-5c44-4751-8a19-7849a4e03a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42074
2004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.420742004
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.237928676
Short name T1041
Test name
Test status
Simulation time 10049371541 ps
CPU time 12.36 seconds
Started May 23 03:41:16 PM PDT 24
Finished May 23 03:41:38 PM PDT 24
Peak memory 204988 kb
Host smart-d911726d-7332-43e8-b361-d90f4f975511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23792
8676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.237928676
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3078122464
Short name T666
Test name
Test status
Simulation time 10053684238 ps
CPU time 12.68 seconds
Started May 23 03:41:14 PM PDT 24
Finished May 23 03:41:35 PM PDT 24
Peak memory 204888 kb
Host smart-57428b64-2ce6-4e64-9eb4-85809dd46b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30781
22464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3078122464
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.925411172
Short name T649
Test name
Test status
Simulation time 10060195240 ps
CPU time 13.1 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:52 PM PDT 24
Peak memory 204936 kb
Host smart-bf1861b9-3395-4e2f-afe0-a0171a693707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92541
1172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.925411172
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2904568083
Short name T1534
Test name
Test status
Simulation time 10148527865 ps
CPU time 13.71 seconds
Started May 23 03:41:14 PM PDT 24
Finished May 23 03:41:37 PM PDT 24
Peak memory 204916 kb
Host smart-b75d81a8-4d05-49e3-92aa-c019cffbd3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29045
68083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2904568083
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.104054878
Short name T1784
Test name
Test status
Simulation time 10071362910 ps
CPU time 13.61 seconds
Started May 23 03:41:15 PM PDT 24
Finished May 23 03:41:38 PM PDT 24
Peak memory 204908 kb
Host smart-d6afe374-b3f7-4f2e-aef5-0e750c3903db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10405
4878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.104054878
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2937557611
Short name T1294
Test name
Test status
Simulation time 10076033993 ps
CPU time 13.18 seconds
Started May 23 03:41:15 PM PDT 24
Finished May 23 03:41:37 PM PDT 24
Peak memory 204940 kb
Host smart-f007dd83-7bb6-41a3-a148-a45459519205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29375
57611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2937557611
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.471601557
Short name T1473
Test name
Test status
Simulation time 10153163397 ps
CPU time 14.24 seconds
Started May 23 03:41:29 PM PDT 24
Finished May 23 03:41:52 PM PDT 24
Peak memory 205036 kb
Host smart-dcb52877-22ed-43a4-89b6-3217332cdbef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=471601557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.471601557
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.3821608691
Short name T748
Test name
Test status
Simulation time 10053594431 ps
CPU time 12.56 seconds
Started May 23 03:41:31 PM PDT 24
Finished May 23 03:41:52 PM PDT 24
Peak memory 204908 kb
Host smart-b7e40c66-8602-4d5f-acdb-c38d70fe1aa3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3821608691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.3821608691
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.3491065294
Short name T427
Test name
Test status
Simulation time 10149868094 ps
CPU time 16.13 seconds
Started May 23 03:41:37 PM PDT 24
Finished May 23 03:42:01 PM PDT 24
Peak memory 204948 kb
Host smart-8d9b94e1-a281-4de6-bf6d-aba4cf2b9806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34910
65294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.3491065294
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.735545872
Short name T399
Test name
Test status
Simulation time 13892110261 ps
CPU time 17.04 seconds
Started May 23 03:41:33 PM PDT 24
Finished May 23 03:41:59 PM PDT 24
Peak memory 204900 kb
Host smart-38e0c84d-6ff1-455a-8012-96388719e7a2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=735545872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.735545872
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.59747825
Short name T892
Test name
Test status
Simulation time 13214490666 ps
CPU time 17.14 seconds
Started May 23 03:41:22 PM PDT 24
Finished May 23 03:41:49 PM PDT 24
Peak memory 204948 kb
Host smart-1bd2a594-db3e-4bb1-b6d4-0ad06aaf2f73
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=59747825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.59747825
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1519003099
Short name T1644
Test name
Test status
Simulation time 13199418101 ps
CPU time 18.26 seconds
Started May 23 03:41:29 PM PDT 24
Finished May 23 03:41:56 PM PDT 24
Peak memory 204940 kb
Host smart-dd2a2d69-b1da-493a-a8bd-84507cf10395
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1519003099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1519003099
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2285309966
Short name T572
Test name
Test status
Simulation time 10052322017 ps
CPU time 13.48 seconds
Started May 23 03:41:22 PM PDT 24
Finished May 23 03:41:45 PM PDT 24
Peak memory 204952 kb
Host smart-62f1aa9f-df81-41fa-8205-c8bca3d27002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22853
09966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2285309966
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.962923352
Short name T1458
Test name
Test status
Simulation time 10037201237 ps
CPU time 14.79 seconds
Started May 23 03:41:33 PM PDT 24
Finished May 23 03:41:57 PM PDT 24
Peak memory 204948 kb
Host smart-fd1524eb-5200-47b9-9b34-fa21102fa4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96292
3352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.962923352
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.1181138283
Short name T1164
Test name
Test status
Simulation time 10048890126 ps
CPU time 13.68 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:53 PM PDT 24
Peak memory 204980 kb
Host smart-db7605b0-d10f-4811-802c-cd50e1e4471b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11811
38283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1181138283
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.2534615674
Short name T315
Test name
Test status
Simulation time 10775268148 ps
CPU time 14.7 seconds
Started May 23 03:41:28 PM PDT 24
Finished May 23 03:41:51 PM PDT 24
Peak memory 204880 kb
Host smart-b8955393-953b-4cff-af2a-71f7edc9d971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25346
15674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2534615674
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1038377413
Short name T1764
Test name
Test status
Simulation time 10255741860 ps
CPU time 17.08 seconds
Started May 23 03:41:20 PM PDT 24
Finished May 23 03:41:47 PM PDT 24
Peak memory 204980 kb
Host smart-9a9d50e4-5645-4e2d-a9e4-07cc90f239e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10383
77413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1038377413
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3384369414
Short name T695
Test name
Test status
Simulation time 10163670629 ps
CPU time 13.62 seconds
Started May 23 03:41:31 PM PDT 24
Finished May 23 03:41:53 PM PDT 24
Peak memory 204932 kb
Host smart-46ebce4d-f4d8-41b3-84d9-2718af9d422e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33843
69414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3384369414
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1033176540
Short name T1532
Test name
Test status
Simulation time 10086254834 ps
CPU time 14.12 seconds
Started May 23 03:41:22 PM PDT 24
Finished May 23 03:41:45 PM PDT 24
Peak memory 204944 kb
Host smart-ab729696-0440-4445-9dea-031fb69280a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10331
76540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1033176540
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2457905331
Short name T1170
Test name
Test status
Simulation time 10116873800 ps
CPU time 14.8 seconds
Started May 23 03:41:21 PM PDT 24
Finished May 23 03:41:49 PM PDT 24
Peak memory 204960 kb
Host smart-ea13ecbe-c7aa-4062-b305-990e36aeca48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24579
05331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2457905331
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.292052423
Short name T1874
Test name
Test status
Simulation time 10084548356 ps
CPU time 13.99 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:53 PM PDT 24
Peak memory 204996 kb
Host smart-67d0e64e-57b3-46cf-b1e9-a7a648d115d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29205
2423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.292052423
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2307432789
Short name T1405
Test name
Test status
Simulation time 13187442088 ps
CPU time 15.52 seconds
Started May 23 03:41:35 PM PDT 24
Finished May 23 03:41:59 PM PDT 24
Peak memory 204976 kb
Host smart-74071794-c267-4ed3-805b-b4e8574c67c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23074
32789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2307432789
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1434643170
Short name T549
Test name
Test status
Simulation time 10088017034 ps
CPU time 14.86 seconds
Started May 23 03:41:28 PM PDT 24
Finished May 23 03:41:51 PM PDT 24
Peak memory 204932 kb
Host smart-16c18b08-c816-4922-bc1b-b746c6ecda58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14346
43170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1434643170
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3201959799
Short name T1723
Test name
Test status
Simulation time 10064402501 ps
CPU time 12.73 seconds
Started May 23 03:41:26 PM PDT 24
Finished May 23 03:41:47 PM PDT 24
Peak memory 204916 kb
Host smart-aceedc21-41db-4a8f-a64e-3d494c95dde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32019
59799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3201959799
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3262864459
Short name T1430
Test name
Test status
Simulation time 10118255255 ps
CPU time 13.34 seconds
Started May 23 03:41:31 PM PDT 24
Finished May 23 03:41:53 PM PDT 24
Peak memory 205004 kb
Host smart-793d6a09-dd04-4395-b384-2abd53079900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32628
64459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3262864459
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.4236617827
Short name T961
Test name
Test status
Simulation time 10085106889 ps
CPU time 13.01 seconds
Started May 23 03:41:29 PM PDT 24
Finished May 23 03:41:50 PM PDT 24
Peak memory 204916 kb
Host smart-c5fd39ae-1b3c-43f2-8f86-6f40af46f6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42366
17827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.4236617827
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.555703079
Short name T865
Test name
Test status
Simulation time 10067613679 ps
CPU time 15.92 seconds
Started May 23 03:41:31 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204936 kb
Host smart-79d4347e-b71c-498a-b9e6-3d169ec426f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55570
3079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.555703079
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.3421292424
Short name T1065
Test name
Test status
Simulation time 10060312665 ps
CPU time 13.99 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:52 PM PDT 24
Peak memory 204956 kb
Host smart-f4d31a16-1d64-4bfb-8fe5-85c01ce9834a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34212
92424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.3421292424
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3561149561
Short name T1763
Test name
Test status
Simulation time 10073547169 ps
CPU time 13.21 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:52 PM PDT 24
Peak memory 204952 kb
Host smart-0a2fc904-f94c-4d45-ab19-05ea1de77af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35611
49561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3561149561
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.2821031303
Short name T1832
Test name
Test status
Simulation time 10076774598 ps
CPU time 12.51 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:54 PM PDT 24
Peak memory 205004 kb
Host smart-b82fd1fe-0e3c-4cb1-b6f7-2b92baf38ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28210
31303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.2821031303
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.4199894999
Short name T863
Test name
Test status
Simulation time 10050931370 ps
CPU time 14.24 seconds
Started May 23 03:41:33 PM PDT 24
Finished May 23 03:41:56 PM PDT 24
Peak memory 204964 kb
Host smart-50548d3b-4b29-4400-bd90-b76f1335e0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41998
94999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.4199894999
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2726351964
Short name T27
Test name
Test status
Simulation time 10095191832 ps
CPU time 14.14 seconds
Started May 23 03:41:28 PM PDT 24
Finished May 23 03:41:50 PM PDT 24
Peak memory 205008 kb
Host smart-932f9e30-b9fe-4d4c-8bd0-5c6bee24e99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27263
51964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2726351964
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.4048264226
Short name T1726
Test name
Test status
Simulation time 25199006843 ps
CPU time 46.73 seconds
Started May 23 03:41:44 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 204960 kb
Host smart-f0d3f63f-5962-4733-a62b-2c1e514a00e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40482
64226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.4048264226
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1261673938
Short name T1739
Test name
Test status
Simulation time 10090668347 ps
CPU time 17.26 seconds
Started May 23 03:41:33 PM PDT 24
Finished May 23 03:41:59 PM PDT 24
Peak memory 204912 kb
Host smart-c8c1973b-fd91-4433-9f98-37820c7c3127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12616
73938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1261673938
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1872616162
Short name T245
Test name
Test status
Simulation time 10076828339 ps
CPU time 13.11 seconds
Started May 23 03:41:27 PM PDT 24
Finished May 23 03:41:49 PM PDT 24
Peak memory 204964 kb
Host smart-bceb120e-fcd6-42b5-80de-c3a288922d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18726
16162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1872616162
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.821609500
Short name T1258
Test name
Test status
Simulation time 10077133846 ps
CPU time 13.91 seconds
Started May 23 03:41:29 PM PDT 24
Finished May 23 03:41:51 PM PDT 24
Peak memory 204992 kb
Host smart-0b86d74c-e879-4453-a3e3-edb3967e25f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82160
9500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.821609500
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.629976221
Short name T1822
Test name
Test status
Simulation time 10041473525 ps
CPU time 13.69 seconds
Started May 23 03:41:21 PM PDT 24
Finished May 23 03:41:44 PM PDT 24
Peak memory 204936 kb
Host smart-42c6adaf-1728-47f0-831d-0c88991ef9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62997
6221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.629976221
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.474586772
Short name T668
Test name
Test status
Simulation time 10079083673 ps
CPU time 13.37 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204976 kb
Host smart-31637f25-9331-4ce5-b4e3-94cc3f0e77ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47458
6772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.474586772
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.150487897
Short name T419
Test name
Test status
Simulation time 10070808736 ps
CPU time 14.15 seconds
Started May 23 03:41:22 PM PDT 24
Finished May 23 03:41:46 PM PDT 24
Peak memory 204976 kb
Host smart-18fbbeaa-8250-4526-9b7c-ddcf3c285176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15048
7897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.150487897
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3909230425
Short name T160
Test name
Test status
Simulation time 10148514115 ps
CPU time 15.41 seconds
Started May 23 03:41:15 PM PDT 24
Finished May 23 03:41:39 PM PDT 24
Peak memory 204868 kb
Host smart-5b8fa2e6-57dc-4789-9064-cbecd9846299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39092
30425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3909230425
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1969911118
Short name T1486
Test name
Test status
Simulation time 10064807262 ps
CPU time 14.25 seconds
Started May 23 03:41:24 PM PDT 24
Finished May 23 03:41:47 PM PDT 24
Peak memory 205036 kb
Host smart-75f2ceba-c991-4a36-bd72-beba340d8c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19699
11118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1969911118
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1618193066
Short name T705
Test name
Test status
Simulation time 10076245031 ps
CPU time 15.59 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:56 PM PDT 24
Peak memory 204988 kb
Host smart-cc4d2540-2095-49f0-a4b0-a638c1f472c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16181
93066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1618193066
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.194007503
Short name T1110
Test name
Test status
Simulation time 10159698462 ps
CPU time 13.57 seconds
Started May 23 03:39:51 PM PDT 24
Finished May 23 03:40:14 PM PDT 24
Peak memory 204948 kb
Host smart-f4a0a8ee-3300-4a3a-a371-b4b2f83c20b5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=194007503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.194007503
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.1559851071
Short name T1517
Test name
Test status
Simulation time 10051542155 ps
CPU time 12.94 seconds
Started May 23 03:39:40 PM PDT 24
Finished May 23 03:39:58 PM PDT 24
Peak memory 204984 kb
Host smart-29d34553-e246-4581-ae9c-b4356f34532e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1559851071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.1559851071
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.219430821
Short name T1312
Test name
Test status
Simulation time 10108062757 ps
CPU time 13.7 seconds
Started May 23 03:39:40 PM PDT 24
Finished May 23 03:39:59 PM PDT 24
Peak memory 204960 kb
Host smart-a03280b6-626c-486e-83e1-3a09e13ae187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21943
0821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.219430821
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1098641851
Short name T543
Test name
Test status
Simulation time 13874148055 ps
CPU time 15.85 seconds
Started May 23 03:39:29 PM PDT 24
Finished May 23 03:39:54 PM PDT 24
Peak memory 204928 kb
Host smart-00f38538-8d31-4819-9649-2abb59039a23
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1098641851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.1098641851
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.2019692625
Short name T605
Test name
Test status
Simulation time 13254869915 ps
CPU time 16.1 seconds
Started May 23 03:39:43 PM PDT 24
Finished May 23 03:40:04 PM PDT 24
Peak memory 205008 kb
Host smart-cc3d76e5-7c1b-4030-b253-7b080be6bd88
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2019692625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2019692625
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.3877415032
Short name T1729
Test name
Test status
Simulation time 13273618997 ps
CPU time 17.02 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:14 PM PDT 24
Peak memory 204920 kb
Host smart-23197dde-ed30-49e3-8d3b-cae21238b610
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3877415032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.3877415032
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2543304079
Short name T85
Test name
Test status
Simulation time 10063453012 ps
CPU time 12.73 seconds
Started May 23 03:39:37 PM PDT 24
Finished May 23 03:39:56 PM PDT 24
Peak memory 204916 kb
Host smart-5ca7f78c-9fbc-461f-9a6e-d55b5f716711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25433
04079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2543304079
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.1690464847
Short name T1414
Test name
Test status
Simulation time 11173282759 ps
CPU time 15.46 seconds
Started May 23 03:39:43 PM PDT 24
Finished May 23 03:40:04 PM PDT 24
Peak memory 204972 kb
Host smart-26d3557f-037a-4571-9019-66a5db0f67e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16904
64847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.1690464847
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2584884560
Short name T552
Test name
Test status
Simulation time 10050409893 ps
CPU time 12.59 seconds
Started May 23 03:39:43 PM PDT 24
Finished May 23 03:40:01 PM PDT 24
Peak memory 204916 kb
Host smart-58a42a07-2201-4cd2-b160-1342595eb759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25848
84560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2584884560
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1591060646
Short name T1197
Test name
Test status
Simulation time 10060089049 ps
CPU time 12.82 seconds
Started May 23 03:39:32 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 204892 kb
Host smart-0e07e384-c181-438c-8e28-0ff70c3990f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15910
60646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1591060646
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2543257809
Short name T1622
Test name
Test status
Simulation time 10081035490 ps
CPU time 14.83 seconds
Started May 23 03:39:37 PM PDT 24
Finished May 23 03:39:58 PM PDT 24
Peak memory 204888 kb
Host smart-7948f400-3828-42d2-8817-4c01dd2138ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25432
57809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2543257809
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2392970241
Short name T416
Test name
Test status
Simulation time 10167633462 ps
CPU time 16.19 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:12 PM PDT 24
Peak memory 204952 kb
Host smart-0c077351-0982-444d-b493-eed3963fa0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23929
70241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2392970241
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3684213898
Short name T328
Test name
Test status
Simulation time 10051176029 ps
CPU time 13.14 seconds
Started May 23 03:39:39 PM PDT 24
Finished May 23 03:39:58 PM PDT 24
Peak memory 204968 kb
Host smart-8c3dfe38-dfec-4c4b-9588-c6ddfbd2871e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36842
13898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3684213898
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3494102431
Short name T628
Test name
Test status
Simulation time 10132800542 ps
CPU time 13.07 seconds
Started May 23 03:39:31 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 204896 kb
Host smart-3139e4c5-6715-439b-bd61-bcc0b939d493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34941
02431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3494102431
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2064197196
Short name T375
Test name
Test status
Simulation time 10083320767 ps
CPU time 13.02 seconds
Started May 23 03:39:27 PM PDT 24
Finished May 23 03:39:49 PM PDT 24
Peak memory 204968 kb
Host smart-6f98904f-e179-4e17-8901-6b3611ff21a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20641
97196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2064197196
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.402702467
Short name T1807
Test name
Test status
Simulation time 13185134264 ps
CPU time 17.11 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:13 PM PDT 24
Peak memory 204952 kb
Host smart-a3a5fe57-fab9-4d1c-88aa-a4ccd2b9cebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40270
2467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.402702467
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3003346569
Short name T1055
Test name
Test status
Simulation time 10104602006 ps
CPU time 13.88 seconds
Started May 23 03:39:31 PM PDT 24
Finished May 23 03:39:54 PM PDT 24
Peak memory 204872 kb
Host smart-bfedd7da-206b-4e69-9c11-3c80c915665b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30033
46569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3003346569
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.110297510
Short name T1492
Test name
Test status
Simulation time 10065839325 ps
CPU time 14.66 seconds
Started May 23 03:39:46 PM PDT 24
Finished May 23 03:40:06 PM PDT 24
Peak memory 204964 kb
Host smart-5bfd79d6-1abe-4783-b96b-2574410dc682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11029
7510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.110297510
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.4062828516
Short name T115
Test name
Test status
Simulation time 10155714128 ps
CPU time 15.15 seconds
Started May 23 03:39:47 PM PDT 24
Finished May 23 03:40:08 PM PDT 24
Peak memory 204944 kb
Host smart-d889c40d-613f-4415-8d58-f901b594c1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40628
28516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.4062828516
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1099699563
Short name T1575
Test name
Test status
Simulation time 10116229257 ps
CPU time 13.34 seconds
Started May 23 03:39:52 PM PDT 24
Finished May 23 03:40:17 PM PDT 24
Peak memory 204940 kb
Host smart-b69c18aa-c488-4642-8bde-42a796e34cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10996
99563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1099699563
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3845190271
Short name T1320
Test name
Test status
Simulation time 10097212608 ps
CPU time 13.24 seconds
Started May 23 03:39:30 PM PDT 24
Finished May 23 03:39:52 PM PDT 24
Peak memory 204940 kb
Host smart-537b5d0c-8323-410b-8717-1d89ab5b3d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38451
90271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3845190271
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3801708007
Short name T1061
Test name
Test status
Simulation time 10056186356 ps
CPU time 14.62 seconds
Started May 23 03:39:48 PM PDT 24
Finished May 23 03:40:09 PM PDT 24
Peak memory 204848 kb
Host smart-fcf66704-7f0d-465f-946c-fa7d265188a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38017
08007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3801708007
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3507706772
Short name T1770
Test name
Test status
Simulation time 10055429522 ps
CPU time 13.9 seconds
Started May 23 03:39:38 PM PDT 24
Finished May 23 03:39:58 PM PDT 24
Peak memory 204988 kb
Host smart-630847b3-135a-449d-94f7-66aca3dc1a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35077
06772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3507706772
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.669443727
Short name T764
Test name
Test status
Simulation time 10076944302 ps
CPU time 12.64 seconds
Started May 23 03:39:47 PM PDT 24
Finished May 23 03:40:05 PM PDT 24
Peak memory 204968 kb
Host smart-a71734c2-e91e-4061-8c0a-3f24c7e11bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66944
3727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.669443727
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.4243909157
Short name T1844
Test name
Test status
Simulation time 10054754804 ps
CPU time 13.21 seconds
Started May 23 03:39:52 PM PDT 24
Finished May 23 03:40:15 PM PDT 24
Peak memory 204900 kb
Host smart-1122de74-8e09-4f3b-aa56-083a27857bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42439
09157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.4243909157
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2909184382
Short name T29
Test name
Test status
Simulation time 10060652056 ps
CPU time 16.09 seconds
Started May 23 03:39:37 PM PDT 24
Finished May 23 03:39:59 PM PDT 24
Peak memory 204940 kb
Host smart-a9017845-1849-4742-9558-bf8d68628610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29091
84382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2909184382
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2906939651
Short name T1611
Test name
Test status
Simulation time 23431010687 ps
CPU time 40.43 seconds
Started May 23 03:39:30 PM PDT 24
Finished May 23 03:40:19 PM PDT 24
Peak memory 205008 kb
Host smart-3e57e012-27b1-43d4-8035-6101da776b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29069
39651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2906939651
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3602654539
Short name T950
Test name
Test status
Simulation time 10101297214 ps
CPU time 14.06 seconds
Started May 23 03:39:30 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 204916 kb
Host smart-71fc1dab-71f5-435a-9ffe-27ad4f580aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36026
54539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3602654539
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2922665534
Short name T1429
Test name
Test status
Simulation time 10082702147 ps
CPU time 12.41 seconds
Started May 23 03:39:25 PM PDT 24
Finished May 23 03:39:47 PM PDT 24
Peak memory 204924 kb
Host smart-648acfe8-5787-4183-b406-a81af6067d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29226
65534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2922665534
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.905367941
Short name T1762
Test name
Test status
Simulation time 10074555164 ps
CPU time 14.32 seconds
Started May 23 03:39:30 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 204964 kb
Host smart-9d33e1ba-fa74-41e1-b58e-59a3da90fbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90536
7941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.905367941
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.663061291
Short name T1173
Test name
Test status
Simulation time 10052908711 ps
CPU time 13.25 seconds
Started May 23 03:39:29 PM PDT 24
Finished May 23 03:39:51 PM PDT 24
Peak memory 204968 kb
Host smart-4e16c635-ccf1-42a5-b994-fa80e41b4283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66306
1291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.663061291
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2789208279
Short name T209
Test name
Test status
Simulation time 498307349 ps
CPU time 1.38 seconds
Started May 23 03:39:51 PM PDT 24
Finished May 23 03:40:03 PM PDT 24
Peak memory 221844 kb
Host smart-ab55d158-1d79-48fb-9b6a-510cc04b14b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2789208279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2789208279
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1569797703
Short name T1324
Test name
Test status
Simulation time 10053494549 ps
CPU time 12.9 seconds
Started May 23 03:39:43 PM PDT 24
Finished May 23 03:40:01 PM PDT 24
Peak memory 204952 kb
Host smart-910fa8c5-f4a3-4e15-a36b-16aca8442561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15697
97703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1569797703
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.213228038
Short name T455
Test name
Test status
Simulation time 10048497946 ps
CPU time 14.5 seconds
Started May 23 03:39:29 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 204964 kb
Host smart-6c808290-7620-49a6-a180-a1bbe49404e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21322
8038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.213228038
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3081719255
Short name T733
Test name
Test status
Simulation time 10165753499 ps
CPU time 15.58 seconds
Started May 23 03:39:39 PM PDT 24
Finished May 23 03:40:00 PM PDT 24
Peak memory 204972 kb
Host smart-23c5d4f6-4bf0-4fae-a3c6-447a67d164cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30817
19255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3081719255
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3350175851
Short name T1508
Test name
Test status
Simulation time 10074726023 ps
CPU time 14.26 seconds
Started May 23 03:39:30 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 204912 kb
Host smart-4ce5a536-ca26-414d-82b8-175428f9a943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33501
75851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3350175851
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3538491307
Short name T1380
Test name
Test status
Simulation time 10057154064 ps
CPU time 14.72 seconds
Started May 23 03:39:48 PM PDT 24
Finished May 23 03:40:09 PM PDT 24
Peak memory 204892 kb
Host smart-73aa8046-d361-4834-a357-800a0eae4662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35384
91307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3538491307
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.3966411015
Short name T1776
Test name
Test status
Simulation time 10145940747 ps
CPU time 13.37 seconds
Started May 23 03:41:34 PM PDT 24
Finished May 23 03:41:56 PM PDT 24
Peak memory 204956 kb
Host smart-3230a46f-fe4f-4f7b-897d-9a6d9e046dc6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3966411015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.3966411015
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.2792630419
Short name T1052
Test name
Test status
Simulation time 10102048606 ps
CPU time 14.18 seconds
Started May 23 03:41:33 PM PDT 24
Finished May 23 03:41:56 PM PDT 24
Peak memory 204964 kb
Host smart-ddca3f3e-98b1-4019-ba23-5c90225245b6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2792630419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.2792630419
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.198257699
Short name T640
Test name
Test status
Simulation time 10081105853 ps
CPU time 13.72 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:53 PM PDT 24
Peak memory 204972 kb
Host smart-7fd6a726-08ca-41de-b53b-673a261a5d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19825
7699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.198257699
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.962562707
Short name T684
Test name
Test status
Simulation time 13946166273 ps
CPU time 16.82 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204968 kb
Host smart-5b777714-5a43-45a8-9ea2-65a9826d62b4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=962562707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.962562707
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.3723369083
Short name T1632
Test name
Test status
Simulation time 13259238163 ps
CPU time 17.32 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:56 PM PDT 24
Peak memory 204916 kb
Host smart-9c2cbd72-ca1b-46da-b1e2-6fe526abbf4a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3723369083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.3723369083
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.312706518
Short name T1434
Test name
Test status
Simulation time 13235848480 ps
CPU time 15.15 seconds
Started May 23 03:41:28 PM PDT 24
Finished May 23 03:41:51 PM PDT 24
Peak memory 204920 kb
Host smart-c7bd85c1-bdf5-4e1b-bce8-548fff41487d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=312706518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.312706518
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.4147441998
Short name T1076
Test name
Test status
Simulation time 10061305135 ps
CPU time 14.68 seconds
Started May 23 03:41:27 PM PDT 24
Finished May 23 03:41:50 PM PDT 24
Peak memory 204964 kb
Host smart-06d4aa1a-0f7c-4fca-bc31-625019403d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41474
41998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.4147441998
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.3554220327
Short name T929
Test name
Test status
Simulation time 10344340603 ps
CPU time 14.24 seconds
Started May 23 03:41:29 PM PDT 24
Finished May 23 03:41:52 PM PDT 24
Peak memory 204936 kb
Host smart-6352b100-62a0-44b0-8ca0-7127d166fdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
20327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.3554220327
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.325739849
Short name T352
Test name
Test status
Simulation time 10071002772 ps
CPU time 13.77 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:57 PM PDT 24
Peak memory 204932 kb
Host smart-7305c4f0-5c60-4923-88b2-5401c51d70c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32573
9849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.325739849
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.2014888531
Short name T869
Test name
Test status
Simulation time 10064787155 ps
CPU time 15.72 seconds
Started May 23 03:41:28 PM PDT 24
Finished May 23 03:41:52 PM PDT 24
Peak memory 204964 kb
Host smart-ce9b076c-d9eb-49a6-964a-1a03e149e1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20148
88531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.2014888531
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.834955790
Short name T1136
Test name
Test status
Simulation time 10900999983 ps
CPU time 14.91 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:54 PM PDT 24
Peak memory 204900 kb
Host smart-d3e988d7-5bf9-4a8c-9b96-6093f5888496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83495
5790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.834955790
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2821547723
Short name T1368
Test name
Test status
Simulation time 10223917928 ps
CPU time 14.91 seconds
Started May 23 03:41:34 PM PDT 24
Finished May 23 03:41:58 PM PDT 24
Peak memory 204960 kb
Host smart-5d5655fc-9304-4692-9c24-896c067cc4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28215
47723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2821547723
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1332368811
Short name T210
Test name
Test status
Simulation time 10112682996 ps
CPU time 12.64 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:54 PM PDT 24
Peak memory 204960 kb
Host smart-f8d97a39-5ab1-4dcf-bff5-ac1711367938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13323
68811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1332368811
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.772638527
Short name T1265
Test name
Test status
Simulation time 10047625013 ps
CPU time 12.91 seconds
Started May 23 03:41:40 PM PDT 24
Finished May 23 03:42:00 PM PDT 24
Peak memory 204964 kb
Host smart-4cfaef10-c2ee-4026-b04b-9fa80a8177f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77263
8527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.772638527
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.271807573
Short name T861
Test name
Test status
Simulation time 10097618303 ps
CPU time 14.41 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204936 kb
Host smart-80058bc4-155d-4d3d-aff4-7d9357ad785c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27180
7573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.271807573
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.304021992
Short name T1386
Test name
Test status
Simulation time 10086028490 ps
CPU time 13.88 seconds
Started May 23 03:41:39 PM PDT 24
Finished May 23 03:42:00 PM PDT 24
Peak memory 204944 kb
Host smart-9f1f699a-cee9-438b-a5dc-47e1972637da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30402
1992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.304021992
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.4110695998
Short name T503
Test name
Test status
Simulation time 13259841916 ps
CPU time 21.05 seconds
Started May 23 03:41:28 PM PDT 24
Finished May 23 03:41:57 PM PDT 24
Peak memory 204944 kb
Host smart-cd9d43d4-a98b-4f0e-9094-7ae67559073b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41106
95998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.4110695998
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2856245126
Short name T1454
Test name
Test status
Simulation time 10095996682 ps
CPU time 15.16 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:53 PM PDT 24
Peak memory 204916 kb
Host smart-8dc7094f-0f43-41f4-b83a-2afe28ddd944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28562
45126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2856245126
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1125642728
Short name T1754
Test name
Test status
Simulation time 10053623568 ps
CPU time 13.03 seconds
Started May 23 03:41:31 PM PDT 24
Finished May 23 03:41:53 PM PDT 24
Peak memory 204904 kb
Host smart-16c1f541-1a8f-4bea-99bd-1ae2e134ce00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11256
42728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1125642728
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3035278104
Short name T1772
Test name
Test status
Simulation time 10107124263 ps
CPU time 13.29 seconds
Started May 23 03:41:31 PM PDT 24
Finished May 23 03:41:53 PM PDT 24
Peak memory 204916 kb
Host smart-055874bd-f146-4e4f-9376-4004bc00264a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30352
78104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3035278104
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.4100586366
Short name T754
Test name
Test status
Simulation time 10102162818 ps
CPU time 14.93 seconds
Started May 23 03:41:31 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204940 kb
Host smart-1b6fcc2e-2c59-4e7a-a373-ae9dc640556b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41005
86366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.4100586366
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1729112000
Short name T378
Test name
Test status
Simulation time 10055526907 ps
CPU time 15.39 seconds
Started May 23 03:41:24 PM PDT 24
Finished May 23 03:41:48 PM PDT 24
Peak memory 204964 kb
Host smart-badf2497-9e4e-4e99-b183-d3aed9bdd19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17291
12000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1729112000
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.3503291694
Short name T1329
Test name
Test status
Simulation time 10096546702 ps
CPU time 13.85 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204960 kb
Host smart-b97aa0b6-fd84-429c-bb13-6dc5f311539b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35032
91694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.3503291694
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3452814376
Short name T991
Test name
Test status
Simulation time 10050572487 ps
CPU time 14.25 seconds
Started May 23 03:41:29 PM PDT 24
Finished May 23 03:41:52 PM PDT 24
Peak memory 204928 kb
Host smart-887e8d37-c921-4f8f-b735-509544ec46f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34528
14376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3452814376
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.261823111
Short name T924
Test name
Test status
Simulation time 10034990066 ps
CPU time 12.42 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:54 PM PDT 24
Peak memory 204904 kb
Host smart-b155deec-8221-4b4a-a19c-2615a25059ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26182
3111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.261823111
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3336039475
Short name T1335
Test name
Test status
Simulation time 15878887223 ps
CPU time 30.82 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:42:12 PM PDT 24
Peak memory 204960 kb
Host smart-8aeaeeb1-ad3e-4fd7-9c7f-57926cf44d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33360
39475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3336039475
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1184799259
Short name T1825
Test name
Test status
Simulation time 10065350876 ps
CPU time 14.46 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:53 PM PDT 24
Peak memory 204980 kb
Host smart-66b281ff-bec5-4147-bf60-70645d658218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11847
99259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1184799259
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.83471232
Short name T763
Test name
Test status
Simulation time 10096883030 ps
CPU time 13.36 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204968 kb
Host smart-9cc5c955-230e-4967-9813-57fbdd92f148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83471
232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.83471232
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3435235787
Short name T1513
Test name
Test status
Simulation time 10071280772 ps
CPU time 15.3 seconds
Started May 23 03:41:31 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204932 kb
Host smart-f9389fa6-8815-4b89-b5ca-b05088f9c1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34352
35787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3435235787
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.393986045
Short name T1767
Test name
Test status
Simulation time 10045590358 ps
CPU time 14.48 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:53 PM PDT 24
Peak memory 204960 kb
Host smart-b2581c73-84a7-4ac2-a04d-04b341c4bd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39398
6045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.393986045
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1208545256
Short name T796
Test name
Test status
Simulation time 10063026288 ps
CPU time 13.35 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:54 PM PDT 24
Peak memory 204968 kb
Host smart-9b8a3524-95b2-420c-aca7-7fad3c144026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12085
45256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1208545256
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.217714723
Short name T1259
Test name
Test status
Simulation time 10049240334 ps
CPU time 12.74 seconds
Started May 23 03:41:31 PM PDT 24
Finished May 23 03:41:52 PM PDT 24
Peak memory 204948 kb
Host smart-f97a834e-8f7c-47fe-bbcb-188cd1c166f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21771
4723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.217714723
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2203747451
Short name T161
Test name
Test status
Simulation time 10125470438 ps
CPU time 16.88 seconds
Started May 23 03:41:31 PM PDT 24
Finished May 23 03:41:56 PM PDT 24
Peak memory 204984 kb
Host smart-c7e8bf02-8d91-44e2-8a35-1ec6fe4a3a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22037
47451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2203747451
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3462482805
Short name T1584
Test name
Test status
Simulation time 10082533101 ps
CPU time 14.07 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204956 kb
Host smart-3f0a00be-e571-4622-9ff1-dc997b21b4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34624
82805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3462482805
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.543734386
Short name T1018
Test name
Test status
Simulation time 10078085012 ps
CPU time 16.23 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204948 kb
Host smart-3ce43420-d013-4785-ba6e-a39e21c627b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54373
4386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.543734386
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.1545966885
Short name T1841
Test name
Test status
Simulation time 10180253455 ps
CPU time 13.17 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:07 PM PDT 24
Peak memory 204960 kb
Host smart-dd93c26d-b4d3-4796-83ed-d519831062fa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1545966885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.1545966885
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.2027906591
Short name T1898
Test name
Test status
Simulation time 10057703481 ps
CPU time 14.42 seconds
Started May 23 03:41:33 PM PDT 24
Finished May 23 03:41:57 PM PDT 24
Peak memory 204928 kb
Host smart-a8105147-59ca-4d80-96bc-8884b55c5ac3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2027906591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.2027906591
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3261059892
Short name T1657
Test name
Test status
Simulation time 10136567311 ps
CPU time 13.71 seconds
Started May 23 03:41:34 PM PDT 24
Finished May 23 03:41:57 PM PDT 24
Peak memory 204972 kb
Host smart-3926a322-d882-44de-b053-09c422db8a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32610
59892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3261059892
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3951600546
Short name T889
Test name
Test status
Simulation time 14259914684 ps
CPU time 17.44 seconds
Started May 23 03:41:41 PM PDT 24
Finished May 23 03:42:05 PM PDT 24
Peak memory 204908 kb
Host smart-5ab92bab-0520-4151-a460-22a7f2f2ce8d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3951600546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.3951600546
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1969607155
Short name T367
Test name
Test status
Simulation time 13241677587 ps
CPU time 20.75 seconds
Started May 23 03:41:33 PM PDT 24
Finished May 23 03:42:03 PM PDT 24
Peak memory 204960 kb
Host smart-50d7aba0-9af6-4c4b-8254-079d5e0c8e61
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1969607155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1969607155
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.59646873
Short name T1696
Test name
Test status
Simulation time 13248851266 ps
CPU time 16.23 seconds
Started May 23 03:41:29 PM PDT 24
Finished May 23 03:41:54 PM PDT 24
Peak memory 204964 kb
Host smart-f70c9c0c-c109-4dbc-810d-69f221c81948
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=59646873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.59646873
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2744268755
Short name T1033
Test name
Test status
Simulation time 10049586758 ps
CPU time 15.69 seconds
Started May 23 03:41:30 PM PDT 24
Finished May 23 03:41:54 PM PDT 24
Peak memory 204968 kb
Host smart-a0cd3415-c47a-4a01-8aa3-d5f406a2eb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27442
68755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2744268755
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3608801305
Short name T1524
Test name
Test status
Simulation time 10049039081 ps
CPU time 12.81 seconds
Started May 23 03:41:33 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204932 kb
Host smart-52bd1fec-c6df-4120-84c4-ed4c70e3f06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36088
01305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3608801305
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3490864597
Short name T1375
Test name
Test status
Simulation time 10061319441 ps
CPU time 13.69 seconds
Started May 23 03:41:36 PM PDT 24
Finished May 23 03:41:58 PM PDT 24
Peak memory 204972 kb
Host smart-1cacd7b4-8082-41af-a47b-114008fbe053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34908
64597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3490864597
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.791896656
Short name T1765
Test name
Test status
Simulation time 10798001815 ps
CPU time 15.48 seconds
Started May 23 03:41:36 PM PDT 24
Finished May 23 03:42:00 PM PDT 24
Peak memory 204868 kb
Host smart-5329b327-5369-4398-8736-f78b94cd95d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79189
6656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.791896656
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1318834804
Short name T979
Test name
Test status
Simulation time 10124991775 ps
CPU time 13.85 seconds
Started May 23 03:41:36 PM PDT 24
Finished May 23 03:41:58 PM PDT 24
Peak memory 204892 kb
Host smart-e199bb1b-e735-477c-9c44-c4b84733c6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13188
34804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1318834804
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3906840695
Short name T583
Test name
Test status
Simulation time 10126569334 ps
CPU time 13.83 seconds
Started May 23 03:41:42 PM PDT 24
Finished May 23 03:42:02 PM PDT 24
Peak memory 204984 kb
Host smart-747336e7-b298-4d98-84d9-c61121f602d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39068
40695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3906840695
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.97333187
Short name T965
Test name
Test status
Simulation time 10038869998 ps
CPU time 13.29 seconds
Started May 23 03:41:40 PM PDT 24
Finished May 23 03:42:01 PM PDT 24
Peak memory 205032 kb
Host smart-c4bfe921-656e-416a-b00d-dc79e10b204e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97333
187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.97333187
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.503013352
Short name T1351
Test name
Test status
Simulation time 10102492337 ps
CPU time 14.18 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204948 kb
Host smart-8ac08a90-27fa-4671-aa36-3dfdeb05287c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50301
3352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.503013352
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.2679206168
Short name T1376
Test name
Test status
Simulation time 13196657912 ps
CPU time 19.76 seconds
Started May 23 03:41:40 PM PDT 24
Finished May 23 03:42:07 PM PDT 24
Peak memory 204996 kb
Host smart-ac90c731-5907-49f9-9bbe-a6dc437009bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26792
06168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.2679206168
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2862495774
Short name T1529
Test name
Test status
Simulation time 10103753351 ps
CPU time 15.75 seconds
Started May 23 03:41:38 PM PDT 24
Finished May 23 03:42:02 PM PDT 24
Peak memory 204968 kb
Host smart-63c00ac9-7143-4888-835d-1efe47adeaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28624
95774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2862495774
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3622914518
Short name T1192
Test name
Test status
Simulation time 10076165962 ps
CPU time 16.21 seconds
Started May 23 03:41:39 PM PDT 24
Finished May 23 03:42:02 PM PDT 24
Peak memory 204952 kb
Host smart-06daf87e-b2db-4899-a1e0-634e88f5b633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36229
14518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3622914518
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.595240127
Short name T114
Test name
Test status
Simulation time 10095619527 ps
CPU time 13.04 seconds
Started May 23 03:41:38 PM PDT 24
Finished May 23 03:41:58 PM PDT 24
Peak memory 204960 kb
Host smart-e0abd030-178f-40d2-9ef9-78b7cf0260ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59524
0127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.595240127
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.258860725
Short name T447
Test name
Test status
Simulation time 10097709074 ps
CPU time 13.87 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204960 kb
Host smart-0cfa19b0-3188-475c-8e0c-da5b776e9e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25886
0725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.258860725
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.420168977
Short name T1710
Test name
Test status
Simulation time 10112621209 ps
CPU time 13.44 seconds
Started May 23 03:41:39 PM PDT 24
Finished May 23 03:42:00 PM PDT 24
Peak memory 204960 kb
Host smart-2ca38126-0769-4c63-8582-8a12fd9d8fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42016
8977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.420168977
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.528567992
Short name T617
Test name
Test status
Simulation time 10071819955 ps
CPU time 13.63 seconds
Started May 23 03:41:39 PM PDT 24
Finished May 23 03:42:00 PM PDT 24
Peak memory 204956 kb
Host smart-48091bd8-48b6-4a17-b6cb-e00f2ef824cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52856
7992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.528567992
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_eop_single_bit_handling.3415047813
Short name T887
Test name
Test status
Simulation time 10100270631 ps
CPU time 13.59 seconds
Started May 23 03:41:37 PM PDT 24
Finished May 23 03:41:58 PM PDT 24
Peak memory 204960 kb
Host smart-f641f8d2-6da9-4c98-85b4-58bd1939829c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34150
47813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_eop_single_bit_handling.3415047813
Directory /workspace/21.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2066413335
Short name T1449
Test name
Test status
Simulation time 10044900462 ps
CPU time 13.91 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 204888 kb
Host smart-c060e579-77e7-4d38-ab6f-ba874799b8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20664
13335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2066413335
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1699600047
Short name T1045
Test name
Test status
Simulation time 10035960598 ps
CPU time 14.29 seconds
Started May 23 03:41:43 PM PDT 24
Finished May 23 03:42:04 PM PDT 24
Peak memory 204964 kb
Host smart-02e777de-076a-4f10-b841-f408e3192bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16996
00047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1699600047
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3891579367
Short name T694
Test name
Test status
Simulation time 32549569568 ps
CPU time 65.22 seconds
Started May 23 03:41:41 PM PDT 24
Finished May 23 03:42:53 PM PDT 24
Peak memory 205032 kb
Host smart-e0d7786b-794a-49a4-836d-7871a3ccf25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38915
79367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3891579367
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.4194211640
Short name T295
Test name
Test status
Simulation time 10089894344 ps
CPU time 14.04 seconds
Started May 23 03:41:35 PM PDT 24
Finished May 23 03:41:57 PM PDT 24
Peak memory 204928 kb
Host smart-ae3e4858-d92e-4ac3-81be-ee2b9e5cda92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41942
11640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.4194211640
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1002370169
Short name T1432
Test name
Test status
Simulation time 10083292512 ps
CPU time 14.55 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:55 PM PDT 24
Peak memory 204940 kb
Host smart-fa7c07fe-9e28-4269-acf0-1ad5cdf3cc74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10023
70169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1002370169
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.3267449840
Short name T760
Test name
Test status
Simulation time 10153783437 ps
CPU time 14.37 seconds
Started May 23 03:41:37 PM PDT 24
Finished May 23 03:41:59 PM PDT 24
Peak memory 204964 kb
Host smart-d4f981a3-13e8-499b-8e82-a2cff90d4109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32674
49840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.3267449840
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3613402107
Short name T26
Test name
Test status
Simulation time 10082776269 ps
CPU time 14.01 seconds
Started May 23 03:41:24 PM PDT 24
Finished May 23 03:41:47 PM PDT 24
Peak memory 204964 kb
Host smart-9bfb46c9-a431-47d1-8398-b28b21b457d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36134
02107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3613402107
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1248687776
Short name T1238
Test name
Test status
Simulation time 10048912876 ps
CPU time 14.82 seconds
Started May 23 03:41:47 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 204236 kb
Host smart-a0d621c5-3d56-43d6-ade2-74ea02d9c28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12486
87776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1248687776
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2515165073
Short name T625
Test name
Test status
Simulation time 10074620724 ps
CPU time 12.16 seconds
Started May 23 03:41:32 PM PDT 24
Finished May 23 03:41:53 PM PDT 24
Peak memory 204940 kb
Host smart-75c16d96-e5bc-4fc7-b540-e11992938fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25151
65073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2515165073
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.424872018
Short name T633
Test name
Test status
Simulation time 10127035467 ps
CPU time 13.77 seconds
Started May 23 03:41:34 PM PDT 24
Finished May 23 03:41:56 PM PDT 24
Peak memory 204956 kb
Host smart-8deca40d-d257-4f75-bb96-a1ee404cdba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
2018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.424872018
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2107521065
Short name T658
Test name
Test status
Simulation time 10073963185 ps
CPU time 13.79 seconds
Started May 23 03:41:42 PM PDT 24
Finished May 23 03:42:02 PM PDT 24
Peak memory 204796 kb
Host smart-f1252809-9d43-4591-b44f-7e2a63997482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21075
21065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2107521065
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.453761905
Short name T772
Test name
Test status
Simulation time 10094754112 ps
CPU time 14.76 seconds
Started May 23 03:41:35 PM PDT 24
Finished May 23 03:41:58 PM PDT 24
Peak memory 204968 kb
Host smart-09093746-ca85-4ee1-ba3c-6ab4772621c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45376
1905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.453761905
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.888334039
Short name T1704
Test name
Test status
Simulation time 10140930798 ps
CPU time 15.74 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:10 PM PDT 24
Peak memory 204976 kb
Host smart-e8206e91-6b12-4354-be13-c729081acf0d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=888334039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.888334039
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.329264677
Short name T1125
Test name
Test status
Simulation time 10066424616 ps
CPU time 14.84 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:09 PM PDT 24
Peak memory 204976 kb
Host smart-583078b6-b160-48e4-a70f-698667712154
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=329264677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.329264677
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.1036610140
Short name T365
Test name
Test status
Simulation time 10068889104 ps
CPU time 14.38 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:09 PM PDT 24
Peak memory 204992 kb
Host smart-085ad71b-bf57-42bf-bb7f-0377006414eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10366
10140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.1036610140
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1039410314
Short name T1313
Test name
Test status
Simulation time 13749108869 ps
CPU time 16.53 seconds
Started May 23 03:41:45 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 204920 kb
Host smart-de24ba4a-aadc-48f9-a4ba-e9fd81e4d2f6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1039410314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.1039410314
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.4263747843
Short name T1786
Test name
Test status
Simulation time 13349228343 ps
CPU time 17.46 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:11 PM PDT 24
Peak memory 204948 kb
Host smart-9e7d278e-a162-4f8b-840b-533ea1384c9a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4263747843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.4263747843
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.727397272
Short name T1011
Test name
Test status
Simulation time 13232546355 ps
CPU time 16.83 seconds
Started May 23 03:41:49 PM PDT 24
Finished May 23 03:42:13 PM PDT 24
Peak memory 204904 kb
Host smart-8d00323e-6a4a-4f29-ae2b-2d9fedf03453
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=727397272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.727397272
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1306117663
Short name T414
Test name
Test status
Simulation time 10059336197 ps
CPU time 14.67 seconds
Started May 23 03:41:45 PM PDT 24
Finished May 23 03:42:06 PM PDT 24
Peak memory 204976 kb
Host smart-7e73a325-d791-4df0-ae35-d5c1361ca177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13061
17663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1306117663
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.367971727
Short name T162
Test name
Test status
Simulation time 10871318357 ps
CPU time 14.41 seconds
Started May 23 03:41:38 PM PDT 24
Finished May 23 03:42:00 PM PDT 24
Peak memory 204968 kb
Host smart-3b196d8f-be72-4c05-8976-76d9382e3161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36797
1727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.367971727
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2233664470
Short name T1497
Test name
Test status
Simulation time 10043991947 ps
CPU time 13.07 seconds
Started May 23 03:41:44 PM PDT 24
Finished May 23 03:42:03 PM PDT 24
Peak memory 204928 kb
Host smart-e8cd2bf6-ed97-40e7-a111-7fc665d64e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22336
64470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2233664470
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2019767346
Short name T1824
Test name
Test status
Simulation time 10075276858 ps
CPU time 13.77 seconds
Started May 23 03:41:41 PM PDT 24
Finished May 23 03:42:01 PM PDT 24
Peak memory 204984 kb
Host smart-eb6efb4c-502c-415e-90a1-50c509ea696c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20197
67346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2019767346
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1189897429
Short name T432
Test name
Test status
Simulation time 10836625288 ps
CPU time 16.95 seconds
Started May 23 03:41:36 PM PDT 24
Finished May 23 03:42:01 PM PDT 24
Peak memory 204992 kb
Host smart-764b06d1-d92b-4901-8949-c4ff717bff53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11898
97429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1189897429
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3737213364
Short name T461
Test name
Test status
Simulation time 10112251451 ps
CPU time 17.74 seconds
Started May 23 03:41:46 PM PDT 24
Finished May 23 03:42:10 PM PDT 24
Peak memory 204928 kb
Host smart-0329c13e-4d26-4279-8136-371a88b1e769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37372
13364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3737213364
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.23870245
Short name T1205
Test name
Test status
Simulation time 10083931947 ps
CPU time 15.99 seconds
Started May 23 03:41:51 PM PDT 24
Finished May 23 03:42:13 PM PDT 24
Peak memory 204888 kb
Host smart-e2c90757-3b97-4903-8c7c-bd5167b2fb22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23870
245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.23870245
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3612122598
Short name T798
Test name
Test status
Simulation time 10062726510 ps
CPU time 14.08 seconds
Started May 23 03:41:42 PM PDT 24
Finished May 23 03:42:03 PM PDT 24
Peak memory 204836 kb
Host smart-19865977-227a-41b9-9760-1a6ee704888d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36121
22598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3612122598
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.818531831
Short name T82
Test name
Test status
Simulation time 10072341202 ps
CPU time 13.4 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:07 PM PDT 24
Peak memory 204928 kb
Host smart-d5683728-076c-404c-b734-c81b75ecb591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81853
1831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.818531831
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2134676822
Short name T890
Test name
Test status
Simulation time 10111596981 ps
CPU time 13.13 seconds
Started May 23 03:41:42 PM PDT 24
Finished May 23 03:42:02 PM PDT 24
Peak memory 204956 kb
Host smart-40806e5d-2033-4314-84a1-074d418fc571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21346
76822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2134676822
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2122837792
Short name T1721
Test name
Test status
Simulation time 13202795490 ps
CPU time 18.26 seconds
Started May 23 03:41:45 PM PDT 24
Finished May 23 03:42:09 PM PDT 24
Peak memory 204940 kb
Host smart-22412338-2af8-4256-a4b2-88d58759466e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21228
37792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2122837792
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.4180102188
Short name T854
Test name
Test status
Simulation time 10083580608 ps
CPU time 14.09 seconds
Started May 23 03:41:46 PM PDT 24
Finished May 23 03:42:06 PM PDT 24
Peak memory 204924 kb
Host smart-e8b9ceb1-ef58-413d-8a9d-4b1d43fc1b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41801
02188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.4180102188
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3842358639
Short name T1369
Test name
Test status
Simulation time 10050644439 ps
CPU time 15.75 seconds
Started May 23 03:41:46 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 204956 kb
Host smart-24de95f9-4099-45a8-a384-d14f9a7a8b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38423
58639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3842358639
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.196877953
Short name T1273
Test name
Test status
Simulation time 10125161215 ps
CPU time 15.06 seconds
Started May 23 03:41:47 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 204944 kb
Host smart-82d3368f-6f08-4200-9881-d80eff839461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19687
7953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.196877953
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3699855163
Short name T1343
Test name
Test status
Simulation time 10089510346 ps
CPU time 14.27 seconds
Started May 23 03:41:46 PM PDT 24
Finished May 23 03:42:06 PM PDT 24
Peak memory 204928 kb
Host smart-a27e5896-eaae-455a-9113-753305b66524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36998
55163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3699855163
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3848595627
Short name T952
Test name
Test status
Simulation time 10062148676 ps
CPU time 13.32 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:07 PM PDT 24
Peak memory 204996 kb
Host smart-ab105f4c-3e86-417d-b956-de07d867abfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38485
95627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3848595627
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2776856719
Short name T1257
Test name
Test status
Simulation time 10103263343 ps
CPU time 14.61 seconds
Started May 23 03:41:42 PM PDT 24
Finished May 23 03:42:03 PM PDT 24
Peak memory 204860 kb
Host smart-64bebb3d-66c6-4d42-bce4-b1b6efdf72a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27768
56719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2776856719
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3930305200
Short name T157
Test name
Test status
Simulation time 10072756335 ps
CPU time 13.31 seconds
Started May 23 03:41:42 PM PDT 24
Finished May 23 03:42:02 PM PDT 24
Peak memory 204872 kb
Host smart-0f3976cf-4243-42e2-9640-361a1221c670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39303
05200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3930305200
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.2053706777
Short name T1761
Test name
Test status
Simulation time 10069423176 ps
CPU time 13.63 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:07 PM PDT 24
Peak memory 204996 kb
Host smart-d75d08ba-7824-478f-ac33-6af73b0accd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20537
06777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.2053706777
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.4184548467
Short name T1057
Test name
Test status
Simulation time 10035033493 ps
CPU time 13.19 seconds
Started May 23 03:41:47 PM PDT 24
Finished May 23 03:42:05 PM PDT 24
Peak memory 204964 kb
Host smart-470bfc04-0f3d-4985-9d98-f3932dac0a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41845
48467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.4184548467
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3648071876
Short name T22
Test name
Test status
Simulation time 10038665837 ps
CPU time 15.27 seconds
Started May 23 03:41:45 PM PDT 24
Finished May 23 03:42:06 PM PDT 24
Peak memory 204924 kb
Host smart-3d7530d4-b1d1-4a59-9695-2d6155d46819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36480
71876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3648071876
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.199082384
Short name T1124
Test name
Test status
Simulation time 26400271241 ps
CPU time 51.92 seconds
Started May 23 03:41:45 PM PDT 24
Finished May 23 03:42:43 PM PDT 24
Peak memory 205004 kb
Host smart-27dff827-d591-4156-b4e7-e378646c1e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19908
2384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.199082384
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.560755422
Short name T1766
Test name
Test status
Simulation time 10053143159 ps
CPU time 15.84 seconds
Started May 23 03:41:46 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 204992 kb
Host smart-c89bb5bf-303d-4a00-9159-1a68a0e2063b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56075
5422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.560755422
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.4201281786
Short name T1755
Test name
Test status
Simulation time 10063785694 ps
CPU time 13.23 seconds
Started May 23 03:41:42 PM PDT 24
Finished May 23 03:42:02 PM PDT 24
Peak memory 204920 kb
Host smart-91ede14a-3175-4832-8325-7b45a44e229a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42012
81786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.4201281786
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.4146061978
Short name T1730
Test name
Test status
Simulation time 10102483760 ps
CPU time 14.03 seconds
Started May 23 03:41:35 PM PDT 24
Finished May 23 03:41:57 PM PDT 24
Peak memory 204944 kb
Host smart-d4e5a45c-28ab-4a2b-8d96-a09a1bfc2f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41460
61978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.4146061978
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.2924444566
Short name T1137
Test name
Test status
Simulation time 10048084769 ps
CPU time 13.4 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 204940 kb
Host smart-afd9cf24-6c15-4ff8-a1f1-f578d745f952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29244
44566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.2924444566
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2169283513
Short name T696
Test name
Test status
Simulation time 10061103642 ps
CPU time 12.69 seconds
Started May 23 03:41:46 PM PDT 24
Finished May 23 03:42:04 PM PDT 24
Peak memory 204964 kb
Host smart-b1fa3ad2-e4b2-43ab-b316-e76c64cf44e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21692
83513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2169283513
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.148036197
Short name T759
Test name
Test status
Simulation time 10045580300 ps
CPU time 15.66 seconds
Started May 23 03:41:40 PM PDT 24
Finished May 23 03:42:03 PM PDT 24
Peak memory 204956 kb
Host smart-12ab5844-2687-4baf-9e8b-240107797fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14803
6197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.148036197
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2189766754
Short name T620
Test name
Test status
Simulation time 10174702737 ps
CPU time 15.9 seconds
Started May 23 03:41:49 PM PDT 24
Finished May 23 03:42:11 PM PDT 24
Peak memory 205032 kb
Host smart-c9f69dd4-bd04-448a-8cde-01d79fb2e01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21897
66754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2189766754
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3315827226
Short name T1692
Test name
Test status
Simulation time 10086755228 ps
CPU time 13.5 seconds
Started May 23 03:41:47 PM PDT 24
Finished May 23 03:42:06 PM PDT 24
Peak memory 204384 kb
Host smart-26230aef-3036-40cc-b52f-b9831933202b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33158
27226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3315827226
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2809382163
Short name T339
Test name
Test status
Simulation time 10061156350 ps
CPU time 14.31 seconds
Started May 23 03:41:53 PM PDT 24
Finished May 23 03:42:14 PM PDT 24
Peak memory 205024 kb
Host smart-d43e8961-add0-420c-ac72-4fe1367a5f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28093
82163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2809382163
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.1511325188
Short name T1895
Test name
Test status
Simulation time 10173516313 ps
CPU time 14.2 seconds
Started May 23 03:41:54 PM PDT 24
Finished May 23 03:42:16 PM PDT 24
Peak memory 204944 kb
Host smart-245692a6-4684-4095-b7d5-6669d17fcf27
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1511325188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.1511325188
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.1505448226
Short name T564
Test name
Test status
Simulation time 10082811514 ps
CPU time 13.04 seconds
Started May 23 03:41:49 PM PDT 24
Finished May 23 03:42:09 PM PDT 24
Peak memory 204972 kb
Host smart-381bd668-6f31-4e74-a9e9-f14109ddb896
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1505448226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.1505448226
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.4022339663
Short name T622
Test name
Test status
Simulation time 10167213340 ps
CPU time 13.17 seconds
Started May 23 03:41:46 PM PDT 24
Finished May 23 03:42:05 PM PDT 24
Peak memory 204940 kb
Host smart-ee5f39cc-ae89-4692-99ed-cf22a6268188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40223
39663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.4022339663
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.479944830
Short name T1216
Test name
Test status
Simulation time 13461636323 ps
CPU time 17.89 seconds
Started May 23 03:41:54 PM PDT 24
Finished May 23 03:42:20 PM PDT 24
Peak memory 204988 kb
Host smart-3a0acfbb-5642-4ef3-8a1d-0b57f11d18f2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=479944830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.479944830
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3585445352
Short name T359
Test name
Test status
Simulation time 13275988981 ps
CPU time 18.05 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:12 PM PDT 24
Peak memory 204972 kb
Host smart-446fd37c-01f8-4ab7-bf66-e58c1dd11c78
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3585445352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3585445352
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3988112265
Short name T1005
Test name
Test status
Simulation time 13228926976 ps
CPU time 15.85 seconds
Started May 23 03:41:44 PM PDT 24
Finished May 23 03:42:06 PM PDT 24
Peak memory 204960 kb
Host smart-87ffa518-9280-488e-b2be-1917de397621
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3988112265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.3988112265
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2333247215
Short name T1150
Test name
Test status
Simulation time 10053915584 ps
CPU time 14.12 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 205012 kb
Host smart-3c026e54-51e2-4358-99ef-7aa0771290ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23332
47215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2333247215
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.1180905854
Short name T1174
Test name
Test status
Simulation time 10042858496 ps
CPU time 12.56 seconds
Started May 23 03:41:54 PM PDT 24
Finished May 23 03:42:14 PM PDT 24
Peak memory 205000 kb
Host smart-007ac7ff-eef7-419b-8196-af30deecb01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11809
05854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.1180905854
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2744538448
Short name T802
Test name
Test status
Simulation time 10183447411 ps
CPU time 13.31 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 205024 kb
Host smart-84edefdc-027f-4e8f-9639-004680a2d703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27445
38448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2744538448
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.4131752552
Short name T364
Test name
Test status
Simulation time 10040384879 ps
CPU time 13.05 seconds
Started May 23 03:41:51 PM PDT 24
Finished May 23 03:42:11 PM PDT 24
Peak memory 205020 kb
Host smart-71965a25-493b-40df-8e1f-a371a1bd3d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41317
52552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.4131752552
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2960583555
Short name T547
Test name
Test status
Simulation time 10070767481 ps
CPU time 15.45 seconds
Started May 23 03:41:54 PM PDT 24
Finished May 23 03:42:17 PM PDT 24
Peak memory 204984 kb
Host smart-b6142acd-f6fc-4237-a983-3e3a3ca7637b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29605
83555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2960583555
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.3209247182
Short name T1914
Test name
Test status
Simulation time 10910396237 ps
CPU time 14.59 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 204936 kb
Host smart-e1281a59-e3cb-41b9-ae37-cb18316b1afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32092
47182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.3209247182
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2363228898
Short name T1866
Test name
Test status
Simulation time 10069875457 ps
CPU time 13.6 seconds
Started May 23 03:41:53 PM PDT 24
Finished May 23 03:42:15 PM PDT 24
Peak memory 204936 kb
Host smart-e216da66-165a-418e-b561-f2b2920a220f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23632
28898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2363228898
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3837114951
Short name T821
Test name
Test status
Simulation time 10128164982 ps
CPU time 15.38 seconds
Started May 23 03:41:50 PM PDT 24
Finished May 23 03:42:12 PM PDT 24
Peak memory 204928 kb
Host smart-5de4cf27-7f21-4869-b0a6-94f6fe3f179e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38371
14951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3837114951
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2426686297
Short name T173
Test name
Test status
Simulation time 10050912419 ps
CPU time 14.08 seconds
Started May 23 03:41:55 PM PDT 24
Finished May 23 03:42:17 PM PDT 24
Peak memory 204932 kb
Host smart-f14035f5-9c3b-46cb-8237-484427d4d93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24266
86297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2426686297
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1578850445
Short name T1295
Test name
Test status
Simulation time 10079824353 ps
CPU time 14.75 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 204992 kb
Host smart-6c35762f-0529-4962-96a4-d315a0c1c4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15788
50445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1578850445
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1796413953
Short name T732
Test name
Test status
Simulation time 10063808676 ps
CPU time 15.4 seconds
Started May 23 03:41:48 PM PDT 24
Finished May 23 03:42:10 PM PDT 24
Peak memory 204988 kb
Host smart-497451b2-fc0e-4de2-9509-21dacf65db64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17964
13953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1796413953
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.186859559
Short name T970
Test name
Test status
Simulation time 13180279049 ps
CPU time 16.71 seconds
Started May 23 03:41:47 PM PDT 24
Finished May 23 03:42:10 PM PDT 24
Peak memory 204972 kb
Host smart-d0ef6ab8-f7a6-4a9d-8198-cd2506983478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18685
9559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.186859559
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1964863282
Short name T453
Test name
Test status
Simulation time 10126303783 ps
CPU time 14.1 seconds
Started May 23 03:41:40 PM PDT 24
Finished May 23 03:42:02 PM PDT 24
Peak memory 204956 kb
Host smart-ed666669-54ba-4ec9-bf5e-46342a525d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19648
63282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1964863282
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2522302494
Short name T1104
Test name
Test status
Simulation time 10128671463 ps
CPU time 13.94 seconds
Started May 23 03:41:35 PM PDT 24
Finished May 23 03:41:57 PM PDT 24
Peak memory 204904 kb
Host smart-7157639b-3a09-4b2f-85f9-5d3f5bc94538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
02494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2522302494
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.2538117013
Short name T523
Test name
Test status
Simulation time 10081491353 ps
CPU time 13.94 seconds
Started May 23 03:41:45 PM PDT 24
Finished May 23 03:42:05 PM PDT 24
Peak memory 204960 kb
Host smart-136f3149-1e30-4981-8ef5-047fffd82f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25381
17013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.2538117013
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1307797668
Short name T631
Test name
Test status
Simulation time 10059700006 ps
CPU time 15.16 seconds
Started May 23 03:41:50 PM PDT 24
Finished May 23 03:42:11 PM PDT 24
Peak memory 204968 kb
Host smart-dd5edb3c-c44b-4b82-8a64-ed382b56e415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13077
97668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1307797668
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.293052144
Short name T926
Test name
Test status
Simulation time 10092295286 ps
CPU time 12.83 seconds
Started May 23 03:41:52 PM PDT 24
Finished May 23 03:42:12 PM PDT 24
Peak memory 205016 kb
Host smart-370980fa-bbe8-4d28-b616-b78b14242685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29305
2144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.293052144
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1640571970
Short name T1198
Test name
Test status
Simulation time 10077080969 ps
CPU time 13.1 seconds
Started May 23 03:41:53 PM PDT 24
Finished May 23 03:42:13 PM PDT 24
Peak memory 205020 kb
Host smart-00d95842-ee03-4d56-bf2b-74a97f51fd69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16405
71970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1640571970
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.3984110533
Short name T1938
Test name
Test status
Simulation time 10113727161 ps
CPU time 16.51 seconds
Started May 23 03:41:37 PM PDT 24
Finished May 23 03:42:01 PM PDT 24
Peak memory 204880 kb
Host smart-e8d97ad8-269c-4a26-bd44-ef3ab64435ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39841
10533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.3984110533
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.619763778
Short name T1315
Test name
Test status
Simulation time 10071653506 ps
CPU time 14.01 seconds
Started May 23 03:41:50 PM PDT 24
Finished May 23 03:42:10 PM PDT 24
Peak memory 205056 kb
Host smart-39b12064-06e1-4a77-b699-182c9af41fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61976
3778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.619763778
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.645587020
Short name T794
Test name
Test status
Simulation time 10054495204 ps
CPU time 13.74 seconds
Started May 23 03:41:44 PM PDT 24
Finished May 23 03:42:04 PM PDT 24
Peak memory 204972 kb
Host smart-4ebc01d9-27fb-4df2-b7c9-c222a3dfe31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64558
7020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.645587020
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3621130866
Short name T1167
Test name
Test status
Simulation time 18620958841 ps
CPU time 36.88 seconds
Started May 23 03:41:49 PM PDT 24
Finished May 23 03:42:32 PM PDT 24
Peak memory 205064 kb
Host smart-5bc82fd4-43e7-4245-9d96-c54326361623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36211
30866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3621130866
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.698744394
Short name T1160
Test name
Test status
Simulation time 10121446284 ps
CPU time 14.14 seconds
Started May 23 03:41:51 PM PDT 24
Finished May 23 03:42:12 PM PDT 24
Peak memory 204988 kb
Host smart-9bc11a12-0714-477a-90ab-54b13a237144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69874
4394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.698744394
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1070001341
Short name T1490
Test name
Test status
Simulation time 10112302905 ps
CPU time 14.28 seconds
Started May 23 03:41:51 PM PDT 24
Finished May 23 03:42:13 PM PDT 24
Peak memory 205052 kb
Host smart-989b8591-e369-405a-8901-8a96863bd381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10700
01341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1070001341
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.2107200749
Short name T313
Test name
Test status
Simulation time 10069308087 ps
CPU time 13.33 seconds
Started May 23 03:41:49 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 205024 kb
Host smart-197a60d8-a8c5-4745-b52c-0ce501ece006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21072
00749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.2107200749
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.445880091
Short name T1114
Test name
Test status
Simulation time 10043616355 ps
CPU time 13.37 seconds
Started May 23 03:41:54 PM PDT 24
Finished May 23 03:42:15 PM PDT 24
Peak memory 204936 kb
Host smart-7cfa085d-8bd6-4c6b-9337-9d4364a6ed0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44588
0091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.445880091
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2528908483
Short name T971
Test name
Test status
Simulation time 10066287690 ps
CPU time 13.77 seconds
Started May 23 03:41:45 PM PDT 24
Finished May 23 03:42:04 PM PDT 24
Peak memory 204980 kb
Host smart-019b9364-ef86-4442-876d-9dc77ca35054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
08483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2528908483
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.679986259
Short name T708
Test name
Test status
Simulation time 10066941601 ps
CPU time 13.11 seconds
Started May 23 03:41:51 PM PDT 24
Finished May 23 03:42:10 PM PDT 24
Peak memory 204928 kb
Host smart-c3f3a582-b28e-46bb-8397-47e685ffafe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67998
6259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.679986259
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1747096568
Short name T1447
Test name
Test status
Simulation time 10148146588 ps
CPU time 13.31 seconds
Started May 23 03:41:49 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 204924 kb
Host smart-d494d605-a997-42ff-ac97-b84a2578a2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17470
96568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1747096568
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1745769098
Short name T1736
Test name
Test status
Simulation time 10090677333 ps
CPU time 12.82 seconds
Started May 23 03:41:49 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 204936 kb
Host smart-e76483eb-2454-4d57-ac7f-33198bd66393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17457
69098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1745769098
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2269483489
Short name T1087
Test name
Test status
Simulation time 10070581402 ps
CPU time 14.73 seconds
Started May 23 03:41:54 PM PDT 24
Finished May 23 03:42:16 PM PDT 24
Peak memory 204936 kb
Host smart-b9d8d192-113c-4309-a8d7-2d0d7eea3398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22694
83489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2269483489
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.1705364488
Short name T656
Test name
Test status
Simulation time 10165267601 ps
CPU time 13.32 seconds
Started May 23 03:42:02 PM PDT 24
Finished May 23 03:42:23 PM PDT 24
Peak memory 204924 kb
Host smart-2b9817e9-2269-4f55-b08e-c5d72e9030a2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1705364488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.1705364488
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.2877472583
Short name T1127
Test name
Test status
Simulation time 10120553929 ps
CPU time 14.75 seconds
Started May 23 03:42:00 PM PDT 24
Finished May 23 03:42:23 PM PDT 24
Peak memory 204968 kb
Host smart-4b6df0c2-5f09-4aa6-be7a-50312918cf33
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2877472583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.2877472583
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.2176253272
Short name T1499
Test name
Test status
Simulation time 10076512274 ps
CPU time 12.54 seconds
Started May 23 03:42:04 PM PDT 24
Finished May 23 03:42:24 PM PDT 24
Peak memory 204948 kb
Host smart-1e91ad72-850a-43ba-9742-fa4c7c033b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21762
53272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.2176253272
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.449341177
Short name T1742
Test name
Test status
Simulation time 14017254155 ps
CPU time 18.53 seconds
Started May 23 03:41:59 PM PDT 24
Finished May 23 03:42:26 PM PDT 24
Peak memory 204920 kb
Host smart-0bf60d1d-40a5-437e-867a-c70148937b9f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=449341177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.449341177
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1400318560
Short name T942
Test name
Test status
Simulation time 13226341636 ps
CPU time 17.46 seconds
Started May 23 03:41:58 PM PDT 24
Finished May 23 03:42:24 PM PDT 24
Peak memory 204916 kb
Host smart-2035003a-87fa-4a5b-8d5a-3e232834ec04
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1400318560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1400318560
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.4102828220
Short name T1004
Test name
Test status
Simulation time 13303973630 ps
CPU time 16.17 seconds
Started May 23 03:41:53 PM PDT 24
Finished May 23 03:42:17 PM PDT 24
Peak memory 204932 kb
Host smart-2c338f68-201c-48b4-84ed-835f81ca4e49
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4102828220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.4102828220
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2556462220
Short name T1338
Test name
Test status
Simulation time 10044498691 ps
CPU time 13.85 seconds
Started May 23 03:41:57 PM PDT 24
Finished May 23 03:42:20 PM PDT 24
Peak memory 204760 kb
Host smart-3d8c418f-7948-47a6-af7f-dbd885382846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25564
62220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2556462220
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.495221935
Short name T1328
Test name
Test status
Simulation time 10693287187 ps
CPU time 14.27 seconds
Started May 23 03:42:02 PM PDT 24
Finished May 23 03:42:24 PM PDT 24
Peak memory 204928 kb
Host smart-953a0ce9-c332-4272-9a30-912bcb25633f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49522
1935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.495221935
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1423640620
Short name T1191
Test name
Test status
Simulation time 10053748892 ps
CPU time 12.94 seconds
Started May 23 03:41:57 PM PDT 24
Finished May 23 03:42:19 PM PDT 24
Peak memory 204980 kb
Host smart-956ab9ed-55e5-4e16-9e07-443c5cb560f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14236
40620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1423640620
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.3436576904
Short name T1646
Test name
Test status
Simulation time 10052601961 ps
CPU time 12.53 seconds
Started May 23 03:41:56 PM PDT 24
Finished May 23 03:42:17 PM PDT 24
Peak memory 204976 kb
Host smart-ea0907e0-b9ec-468d-9b9e-b0ae688d055e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34365
76904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3436576904
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.2376084526
Short name T1876
Test name
Test status
Simulation time 10731077219 ps
CPU time 15.19 seconds
Started May 23 03:41:54 PM PDT 24
Finished May 23 03:42:16 PM PDT 24
Peak memory 204968 kb
Host smart-4361a838-2dd1-4042-b7e9-8fee0bd47308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23760
84526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2376084526
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3514877572
Short name T905
Test name
Test status
Simulation time 10273936200 ps
CPU time 14.15 seconds
Started May 23 03:41:53 PM PDT 24
Finished May 23 03:42:14 PM PDT 24
Peak memory 204956 kb
Host smart-b87c3e90-07cd-4f9d-a089-21c9356e6ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35148
77572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3514877572
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3145527112
Short name T1158
Test name
Test status
Simulation time 10133435018 ps
CPU time 14.23 seconds
Started May 23 03:41:57 PM PDT 24
Finished May 23 03:42:20 PM PDT 24
Peak memory 204932 kb
Host smart-b82d5e75-0067-4c5b-8a2b-fcc1637333ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31455
27112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3145527112
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1516552705
Short name T1327
Test name
Test status
Simulation time 10108331432 ps
CPU time 15.72 seconds
Started May 23 03:41:55 PM PDT 24
Finished May 23 03:42:19 PM PDT 24
Peak memory 204916 kb
Host smart-38160e16-eb1b-451e-916a-be1fde3c0398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15165
52705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1516552705
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.189427593
Short name T609
Test name
Test status
Simulation time 10069343445 ps
CPU time 12.18 seconds
Started May 23 03:42:00 PM PDT 24
Finished May 23 03:42:21 PM PDT 24
Peak memory 204976 kb
Host smart-9f50214b-1472-4d60-acd7-64095eaa5070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18942
7593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.189427593
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.2463680709
Short name T527
Test name
Test status
Simulation time 10103210622 ps
CPU time 13.98 seconds
Started May 23 03:41:59 PM PDT 24
Finished May 23 03:42:21 PM PDT 24
Peak memory 204944 kb
Host smart-18811dcd-3aab-4bdb-8790-f1c139fdd760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24636
80709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.2463680709
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1786715738
Short name T1821
Test name
Test status
Simulation time 13171275573 ps
CPU time 16.03 seconds
Started May 23 03:41:56 PM PDT 24
Finished May 23 03:42:21 PM PDT 24
Peak memory 204992 kb
Host smart-28165b70-b1e3-49db-81c0-f25480fed836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17867
15738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1786715738
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1663889705
Short name T582
Test name
Test status
Simulation time 10095714094 ps
CPU time 12.78 seconds
Started May 23 03:42:02 PM PDT 24
Finished May 23 03:42:23 PM PDT 24
Peak memory 204960 kb
Host smart-48daff36-ac74-4f66-9880-bfc5fe426ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16638
89705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1663889705
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3593267803
Short name T1436
Test name
Test status
Simulation time 10094965499 ps
CPU time 14.48 seconds
Started May 23 03:41:53 PM PDT 24
Finished May 23 03:42:14 PM PDT 24
Peak memory 204936 kb
Host smart-464ee8d6-00b3-4762-80cd-43f208a58f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35932
67803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3593267803
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2033058053
Short name T709
Test name
Test status
Simulation time 10083052075 ps
CPU time 14.68 seconds
Started May 23 03:41:58 PM PDT 24
Finished May 23 03:42:21 PM PDT 24
Peak memory 204936 kb
Host smart-b85ffeac-6c8c-41b6-814f-a8ce3b40f8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20330
58053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2033058053
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2224292319
Short name T1325
Test name
Test status
Simulation time 10088862970 ps
CPU time 13.02 seconds
Started May 23 03:41:55 PM PDT 24
Finished May 23 03:42:16 PM PDT 24
Peak memory 204948 kb
Host smart-f1a2e219-760e-49f3-940c-a86b39cc06a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22242
92319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2224292319
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.546160429
Short name T722
Test name
Test status
Simulation time 10062507716 ps
CPU time 13.47 seconds
Started May 23 03:41:54 PM PDT 24
Finished May 23 03:42:15 PM PDT 24
Peak memory 204960 kb
Host smart-b136080f-b8c5-42dc-a83f-1e78ab72ad1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54616
0429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.546160429
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1019629735
Short name T141
Test name
Test status
Simulation time 10064803445 ps
CPU time 14.29 seconds
Started May 23 03:41:56 PM PDT 24
Finished May 23 03:42:18 PM PDT 24
Peak memory 204976 kb
Host smart-22e12ee8-a38e-4767-99b7-cf1497d4584d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10196
29735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1019629735
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.411619391
Short name T1267
Test name
Test status
Simulation time 10054993529 ps
CPU time 13 seconds
Started May 23 03:41:57 PM PDT 24
Finished May 23 03:42:18 PM PDT 24
Peak memory 204956 kb
Host smart-c829f664-57ef-42e5-9baf-351e56f9c520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41161
9391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.411619391
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.22825246
Short name T1477
Test name
Test status
Simulation time 10052771600 ps
CPU time 13.06 seconds
Started May 23 03:41:57 PM PDT 24
Finished May 23 03:42:19 PM PDT 24
Peak memory 204924 kb
Host smart-e9a66316-55ba-467f-8241-4bab5d08091d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22825
246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.22825246
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1583254146
Short name T945
Test name
Test status
Simulation time 10093826229 ps
CPU time 13.77 seconds
Started May 23 03:42:00 PM PDT 24
Finished May 23 03:42:22 PM PDT 24
Peak memory 204960 kb
Host smart-41f11046-2e56-4a9a-b079-e1fa935d076e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15832
54146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1583254146
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.373590912
Short name T773
Test name
Test status
Simulation time 18402497858 ps
CPU time 35.56 seconds
Started May 23 03:41:54 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 205000 kb
Host smart-acf53c5b-c66c-4686-b34a-4bb33e1942f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37359
0912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.373590912
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3717025478
Short name T371
Test name
Test status
Simulation time 10072270347 ps
CPU time 13.72 seconds
Started May 23 03:42:00 PM PDT 24
Finished May 23 03:42:23 PM PDT 24
Peak memory 204928 kb
Host smart-a113899b-15fd-4641-ba91-ab14df953620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37170
25478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3717025478
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1902845627
Short name T393
Test name
Test status
Simulation time 10101467462 ps
CPU time 14.29 seconds
Started May 23 03:42:05 PM PDT 24
Finished May 23 03:42:27 PM PDT 24
Peak memory 204968 kb
Host smart-e3583369-07fa-4692-8cd6-1aa7baa74151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19028
45627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1902845627
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.489706759
Short name T1448
Test name
Test status
Simulation time 10080048378 ps
CPU time 13.08 seconds
Started May 23 03:41:56 PM PDT 24
Finished May 23 03:42:18 PM PDT 24
Peak memory 204956 kb
Host smart-473d302e-ccf4-44f4-94d5-95c72c3f6c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48970
6759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.489706759
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.4015015844
Short name T43
Test name
Test status
Simulation time 10043871017 ps
CPU time 13.1 seconds
Started May 23 03:41:53 PM PDT 24
Finished May 23 03:42:13 PM PDT 24
Peak memory 205004 kb
Host smart-962512ae-3890-4f24-a9df-5a8c6d85d8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40150
15844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.4015015844
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.577221561
Short name T1495
Test name
Test status
Simulation time 10043269963 ps
CPU time 14.28 seconds
Started May 23 03:41:51 PM PDT 24
Finished May 23 03:42:13 PM PDT 24
Peak memory 204952 kb
Host smart-df7496d2-e990-4928-9cac-4664070a1bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57722
1561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.577221561
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3789673393
Short name T832
Test name
Test status
Simulation time 10068181088 ps
CPU time 13.68 seconds
Started May 23 03:41:52 PM PDT 24
Finished May 23 03:42:13 PM PDT 24
Peak memory 204876 kb
Host smart-146a9373-80ea-4ef3-a6c8-a6e9eb3e09d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37896
73393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3789673393
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2575698853
Short name T769
Test name
Test status
Simulation time 10121558877 ps
CPU time 12.85 seconds
Started May 23 03:41:55 PM PDT 24
Finished May 23 03:42:15 PM PDT 24
Peak memory 204976 kb
Host smart-c3051df8-cf6f-49e0-b77b-98bf2b3edf18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25756
98853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2575698853
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2747489712
Short name T718
Test name
Test status
Simulation time 10067407676 ps
CPU time 13.64 seconds
Started May 23 03:41:53 PM PDT 24
Finished May 23 03:42:14 PM PDT 24
Peak memory 204880 kb
Host smart-d26c1769-c046-4752-9534-b4766e80987e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27474
89712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2747489712
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.4043593144
Short name T1891
Test name
Test status
Simulation time 10074313324 ps
CPU time 14.37 seconds
Started May 23 03:42:02 PM PDT 24
Finished May 23 03:42:25 PM PDT 24
Peak memory 204956 kb
Host smart-6d6d424f-aa95-4465-9fc3-cff7c7d10bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40435
93144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.4043593144
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.2511254667
Short name T545
Test name
Test status
Simulation time 10160847636 ps
CPU time 13.27 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:42:31 PM PDT 24
Peak memory 204912 kb
Host smart-3c963880-16af-4a8e-b105-ccab1ee47303
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2511254667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.2511254667
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.3347477808
Short name T575
Test name
Test status
Simulation time 10073149545 ps
CPU time 13.97 seconds
Started May 23 03:42:07 PM PDT 24
Finished May 23 03:42:29 PM PDT 24
Peak memory 204956 kb
Host smart-08d61d05-9143-45e5-895f-ffa93c6c7bff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3347477808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.3347477808
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.1328028893
Short name T347
Test name
Test status
Simulation time 10142285249 ps
CPU time 12.83 seconds
Started May 23 03:42:10 PM PDT 24
Finished May 23 03:42:32 PM PDT 24
Peak memory 204888 kb
Host smart-86665293-b94b-4e5e-b2c7-e12731977b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13280
28893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.1328028893
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1917080193
Short name T1773
Test name
Test status
Simulation time 14060681629 ps
CPU time 16.89 seconds
Started May 23 03:41:52 PM PDT 24
Finished May 23 03:42:16 PM PDT 24
Peak memory 204916 kb
Host smart-cd4a6955-dcd8-4205-b2d6-f38bb82f67dd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1917080193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.1917080193
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1603457855
Short name T1074
Test name
Test status
Simulation time 13213964749 ps
CPU time 16.2 seconds
Started May 23 03:42:01 PM PDT 24
Finished May 23 03:42:25 PM PDT 24
Peak memory 204972 kb
Host smart-67606298-b062-4d54-9c82-cf7ea6c1a8b7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1603457855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1603457855
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.4225553816
Short name T1855
Test name
Test status
Simulation time 13298742460 ps
CPU time 17.45 seconds
Started May 23 03:42:01 PM PDT 24
Finished May 23 03:42:27 PM PDT 24
Peak memory 204912 kb
Host smart-07500461-ffe3-46aa-aedc-78ac3ee5d1d4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4225553816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.4225553816
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.825663927
Short name T627
Test name
Test status
Simulation time 10069607608 ps
CPU time 15.82 seconds
Started May 23 03:41:54 PM PDT 24
Finished May 23 03:42:17 PM PDT 24
Peak memory 205000 kb
Host smart-bb1a1236-3be2-4fb0-b524-05badf364e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82566
3927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.825663927
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.3520139837
Short name T459
Test name
Test status
Simulation time 10669177244 ps
CPU time 14.33 seconds
Started May 23 03:41:57 PM PDT 24
Finished May 23 03:42:20 PM PDT 24
Peak memory 204872 kb
Host smart-f71eaaaf-1476-42b4-ae3b-7322f5396d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35201
39837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.3520139837
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3740259487
Short name T1422
Test name
Test status
Simulation time 10039015568 ps
CPU time 13.06 seconds
Started May 23 03:42:07 PM PDT 24
Finished May 23 03:42:28 PM PDT 24
Peak memory 204932 kb
Host smart-f8f46264-7481-4707-bdd0-c28d0f508564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37402
59487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3740259487
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1103038599
Short name T557
Test name
Test status
Simulation time 10066291517 ps
CPU time 13.6 seconds
Started May 23 03:41:59 PM PDT 24
Finished May 23 03:42:21 PM PDT 24
Peak memory 204944 kb
Host smart-25506029-28b5-4430-85d3-415db516b1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11030
38599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1103038599
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.487347288
Short name T891
Test name
Test status
Simulation time 10732006324 ps
CPU time 14.08 seconds
Started May 23 03:41:56 PM PDT 24
Finished May 23 03:42:19 PM PDT 24
Peak memory 204932 kb
Host smart-303b39d5-d224-410d-a0d8-235ca4dbaaca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48734
7288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.487347288
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1125925056
Short name T1834
Test name
Test status
Simulation time 10105727918 ps
CPU time 12.9 seconds
Started May 23 03:41:54 PM PDT 24
Finished May 23 03:42:15 PM PDT 24
Peak memory 204960 kb
Host smart-ff5d5317-9c4d-49d1-aaa3-4f760771df38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11259
25056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1125925056
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1882230880
Short name T799
Test name
Test status
Simulation time 10053147130 ps
CPU time 15.12 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:39 PM PDT 24
Peak memory 204928 kb
Host smart-5a7d0d47-f67f-4b57-9e36-b97376297224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18822
30880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1882230880
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.40573802
Short name T1145
Test name
Test status
Simulation time 10057251650 ps
CPU time 12.42 seconds
Started May 23 03:42:12 PM PDT 24
Finished May 23 03:42:34 PM PDT 24
Peak memory 204984 kb
Host smart-3aaae598-b4a4-4c82-a6e2-f04edca0bd3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40573
802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.40573802
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3865726593
Short name T1558
Test name
Test status
Simulation time 10085185833 ps
CPU time 15.65 seconds
Started May 23 03:42:00 PM PDT 24
Finished May 23 03:42:24 PM PDT 24
Peak memory 204948 kb
Host smart-4bc337b0-f374-4af4-a9d5-0bf86144e8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38657
26593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3865726593
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.271791479
Short name T1233
Test name
Test status
Simulation time 10148842031 ps
CPU time 13.72 seconds
Started May 23 03:42:04 PM PDT 24
Finished May 23 03:42:26 PM PDT 24
Peak memory 204888 kb
Host smart-47ad008e-5db3-42c3-8772-320eb36c2dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27179
1479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.271791479
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1902085512
Short name T1578
Test name
Test status
Simulation time 13224686987 ps
CPU time 16.35 seconds
Started May 23 03:42:06 PM PDT 24
Finished May 23 03:42:30 PM PDT 24
Peak memory 204956 kb
Host smart-b726c6ad-dba3-4c55-aae2-1132c6691359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19020
85512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1902085512
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2607176020
Short name T1758
Test name
Test status
Simulation time 10100344993 ps
CPU time 16.23 seconds
Started May 23 03:42:07 PM PDT 24
Finished May 23 03:42:31 PM PDT 24
Peak memory 204964 kb
Host smart-f80b4f73-0e89-42f9-a0d1-276699873e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26071
76020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2607176020
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2622588127
Short name T1937
Test name
Test status
Simulation time 10054089274 ps
CPU time 13.31 seconds
Started May 23 03:42:07 PM PDT 24
Finished May 23 03:42:28 PM PDT 24
Peak memory 204972 kb
Host smart-4dd8db97-512b-4a1d-afcf-b7ea5cd8238d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
88127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2622588127
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1331145022
Short name T1395
Test name
Test status
Simulation time 10086973243 ps
CPU time 15.42 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:39 PM PDT 24
Peak memory 204972 kb
Host smart-7d59ed94-6191-4cde-8555-7c7eee30cba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13311
45022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1331145022
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1886715713
Short name T983
Test name
Test status
Simulation time 10116085886 ps
CPU time 13.64 seconds
Started May 23 03:42:12 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204916 kb
Host smart-865b4eca-cd71-4514-bca6-c87fc42a4cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18867
15713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1886715713
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2665967064
Short name T729
Test name
Test status
Simulation time 10050455902 ps
CPU time 12.8 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:42:31 PM PDT 24
Peak memory 204908 kb
Host smart-980367c0-0ee9-46c2-83ac-bec3b421c083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26659
67064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2665967064
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1834763675
Short name T14
Test name
Test status
Simulation time 10099695481 ps
CPU time 13.24 seconds
Started May 23 03:42:07 PM PDT 24
Finished May 23 03:42:27 PM PDT 24
Peak memory 204932 kb
Host smart-a7baeefd-c3ef-4413-a807-ba82383cca2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18347
63675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1834763675
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3823178387
Short name T1445
Test name
Test status
Simulation time 10108306674 ps
CPU time 13.07 seconds
Started May 23 03:42:08 PM PDT 24
Finished May 23 03:42:30 PM PDT 24
Peak memory 204932 kb
Host smart-3a91649e-a5e8-4d29-9c62-34cd116c9a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38231
78387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3823178387
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.3977326945
Short name T1236
Test name
Test status
Simulation time 10071038875 ps
CPU time 13.98 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:35 PM PDT 24
Peak memory 204952 kb
Host smart-bf49d523-b315-430c-830b-246cc65a6308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39773
26945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.3977326945
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.4096629925
Short name T476
Test name
Test status
Simulation time 10046855991 ps
CPU time 12.85 seconds
Started May 23 03:42:08 PM PDT 24
Finished May 23 03:42:29 PM PDT 24
Peak memory 204960 kb
Host smart-916a78bd-2c58-4f1b-ae0e-d410de3d39c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40966
29925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.4096629925
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.4156743514
Short name T724
Test name
Test status
Simulation time 10048070545 ps
CPU time 13 seconds
Started May 23 03:42:07 PM PDT 24
Finished May 23 03:42:28 PM PDT 24
Peak memory 204900 kb
Host smart-4aea9737-404d-4659-b6ef-a1a235f00b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41567
43514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.4156743514
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.225268877
Short name T1470
Test name
Test status
Simulation time 16897812164 ps
CPU time 27.44 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:49 PM PDT 24
Peak memory 204976 kb
Host smart-2cacfa31-bc38-42db-bac0-c24c3acd4860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526
8877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.225268877
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2879857352
Short name T1043
Test name
Test status
Simulation time 10053857589 ps
CPU time 14.1 seconds
Started May 23 03:42:08 PM PDT 24
Finished May 23 03:42:31 PM PDT 24
Peak memory 204948 kb
Host smart-14a7182a-5a75-40b6-9bed-40ee6f227dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28798
57352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2879857352
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3400820544
Short name T1747
Test name
Test status
Simulation time 10091786725 ps
CPU time 14.02 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:42:31 PM PDT 24
Peak memory 204944 kb
Host smart-eeacea1a-70c3-49f6-8559-5d0e10c00062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34008
20544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3400820544
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.4268960101
Short name T1003
Test name
Test status
Simulation time 10092017939 ps
CPU time 12.84 seconds
Started May 23 03:42:07 PM PDT 24
Finished May 23 03:42:28 PM PDT 24
Peak memory 204872 kb
Host smart-e46da16b-18e5-496c-a3c2-71193f0aaefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42689
60101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.4268960101
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.2490106649
Short name T1279
Test name
Test status
Simulation time 10037295209 ps
CPU time 13.39 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:42:32 PM PDT 24
Peak memory 204936 kb
Host smart-a24ebf5c-56f4-43b2-8a52-af0f22b7ad3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24901
06649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.2490106649
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3540212910
Short name T1126
Test name
Test status
Simulation time 10052086660 ps
CPU time 14.33 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:34 PM PDT 24
Peak memory 204948 kb
Host smart-c1a9445d-4f66-48a2-958c-60342c355e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35402
12910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3540212910
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3156662647
Short name T994
Test name
Test status
Simulation time 10076989786 ps
CPU time 13.47 seconds
Started May 23 03:42:08 PM PDT 24
Finished May 23 03:42:31 PM PDT 24
Peak memory 205004 kb
Host smart-a66a6e97-7b8a-4fd7-8da6-1c74ee6364c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31566
62647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3156662647
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.438028547
Short name T1423
Test name
Test status
Simulation time 10150555286 ps
CPU time 12.51 seconds
Started May 23 03:42:02 PM PDT 24
Finished May 23 03:42:22 PM PDT 24
Peak memory 204924 kb
Host smart-7489dc38-1704-4a7b-981f-1062c2f9e896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43802
8547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.438028547
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2273134781
Short name T657
Test name
Test status
Simulation time 10071578525 ps
CPU time 14.4 seconds
Started May 23 03:42:12 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204912 kb
Host smart-a6f600f4-04fe-401e-b171-b3f9532b1a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22731
34781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2273134781
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3722054134
Short name T366
Test name
Test status
Simulation time 10092428896 ps
CPU time 13.7 seconds
Started May 23 03:42:08 PM PDT 24
Finished May 23 03:42:30 PM PDT 24
Peak memory 205000 kb
Host smart-ef6192d2-bda8-454c-b342-e841ad7ce246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37220
54134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3722054134
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.3648133413
Short name T1219
Test name
Test status
Simulation time 10142617308 ps
CPU time 13.45 seconds
Started May 23 03:42:15 PM PDT 24
Finished May 23 03:42:39 PM PDT 24
Peak memory 204912 kb
Host smart-ec3d1b7d-bf74-4400-96c6-93ddaadcc816
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3648133413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.3648133413
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.2868006781
Short name T314
Test name
Test status
Simulation time 10077488754 ps
CPU time 15.36 seconds
Started May 23 03:42:21 PM PDT 24
Finished May 23 03:42:44 PM PDT 24
Peak memory 204964 kb
Host smart-98ceae69-9fe1-44b2-bdde-b76c0e445e5f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2868006781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.2868006781
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.243065546
Short name T670
Test name
Test status
Simulation time 10080947009 ps
CPU time 12.4 seconds
Started May 23 03:42:18 PM PDT 24
Finished May 23 03:42:39 PM PDT 24
Peak memory 204960 kb
Host smart-824a8915-5e7f-4bbd-87d1-e05796d6f5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24306
5546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.243065546
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2771944217
Short name T386
Test name
Test status
Simulation time 13386463611 ps
CPU time 15.71 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:39 PM PDT 24
Peak memory 204880 kb
Host smart-e4314f7f-476c-4189-a7c3-2f6ab7952456
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2771944217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2771944217
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.788123755
Short name T1288
Test name
Test status
Simulation time 13242420880 ps
CPU time 15.02 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204936 kb
Host smart-b8e6a2c5-712e-418f-8d2e-0bcb7dcb4a8d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=788123755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.788123755
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2805143920
Short name T964
Test name
Test status
Simulation time 13204075057 ps
CPU time 16.15 seconds
Started May 23 03:42:08 PM PDT 24
Finished May 23 03:42:33 PM PDT 24
Peak memory 204924 kb
Host smart-35c2e1f8-b0c0-468c-bdbd-030075fffea4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2805143920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.2805143920
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1885929135
Short name T372
Test name
Test status
Simulation time 10126447670 ps
CPU time 14.04 seconds
Started May 23 03:42:08 PM PDT 24
Finished May 23 03:42:30 PM PDT 24
Peak memory 204936 kb
Host smart-cc15cf00-b20a-4f98-a0cc-cca854bfd0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18859
29135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1885929135
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1334860205
Short name T70
Test name
Test status
Simulation time 10089635332 ps
CPU time 13.01 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:42:31 PM PDT 24
Peak memory 204880 kb
Host smart-03df0917-2051-434a-85f1-b430c78b8318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13348
60205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1334860205
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.624142370
Short name T1848
Test name
Test status
Simulation time 10622039824 ps
CPU time 13.75 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 204948 kb
Host smart-03a7b72a-9366-41b2-8e48-4bf732c720df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62414
2370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.624142370
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.4044085768
Short name T72
Test name
Test status
Simulation time 10036217271 ps
CPU time 13.87 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 204992 kb
Host smart-3f703413-2654-4978-be20-c863a58b7eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40440
85768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.4044085768
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2410777011
Short name T731
Test name
Test status
Simulation time 10070817955 ps
CPU time 13.34 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 205052 kb
Host smart-939ef2fc-c414-4968-89d9-636b60081cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24107
77011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2410777011
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.1885110692
Short name T826
Test name
Test status
Simulation time 10856628096 ps
CPU time 13.96 seconds
Started May 23 03:42:10 PM PDT 24
Finished May 23 03:42:33 PM PDT 24
Peak memory 204944 kb
Host smart-ca26f12d-92e8-4fc8-9050-d7cd26dde47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18851
10692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.1885110692
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.140189477
Short name T1879
Test name
Test status
Simulation time 10265713558 ps
CPU time 15.64 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204928 kb
Host smart-d876b168-b9af-4790-9c82-fdb8af003868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14018
9477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.140189477
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.816460562
Short name T65
Test name
Test status
Simulation time 10158648194 ps
CPU time 13.5 seconds
Started May 23 03:42:12 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204904 kb
Host smart-b68018f9-f251-4092-8af8-e36fdac05b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81646
0562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.816460562
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1995113642
Short name T1208
Test name
Test status
Simulation time 10046213360 ps
CPU time 13 seconds
Started May 23 03:42:15 PM PDT 24
Finished May 23 03:42:38 PM PDT 24
Peak memory 204916 kb
Host smart-8c3c0883-c59f-47b9-bd44-3f9d7b8e4b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19951
13642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1995113642
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3545196209
Short name T1444
Test name
Test status
Simulation time 10160132604 ps
CPU time 13.27 seconds
Started May 23 03:42:10 PM PDT 24
Finished May 23 03:42:32 PM PDT 24
Peak memory 204932 kb
Host smart-19a1ea08-abb9-45fe-a993-c8a9a057cca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35451
96209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3545196209
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3179311590
Short name T782
Test name
Test status
Simulation time 10081017780 ps
CPU time 15.29 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:35 PM PDT 24
Peak memory 204968 kb
Host smart-1c35b82b-15f1-4bfc-a460-37a064ed15df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31793
11590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3179311590
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2031800602
Short name T1245
Test name
Test status
Simulation time 13249170701 ps
CPU time 15.73 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:42:33 PM PDT 24
Peak memory 204948 kb
Host smart-2d33a2f2-84fd-4175-b41a-c0de2c5e9d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20318
00602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2031800602
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1843342688
Short name T1888
Test name
Test status
Simulation time 10101159107 ps
CPU time 13.15 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:34 PM PDT 24
Peak memory 204932 kb
Host smart-84a0d710-56ac-4629-8685-045b5bc04d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18433
42688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1843342688
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2451064237
Short name T1247
Test name
Test status
Simulation time 10056078833 ps
CPU time 12.51 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:34 PM PDT 24
Peak memory 204960 kb
Host smart-a2258978-871c-48b9-be22-b8ceafbfb66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24510
64237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2451064237
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.41061623
Short name T109
Test name
Test status
Simulation time 10108751715 ps
CPU time 13.07 seconds
Started May 23 03:42:10 PM PDT 24
Finished May 23 03:42:32 PM PDT 24
Peak memory 204960 kb
Host smart-b9e3fb53-306b-4060-b0f1-a3cfd9681c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41061
623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.41061623
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1849456973
Short name T1108
Test name
Test status
Simulation time 10112249339 ps
CPU time 12.58 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204932 kb
Host smart-fc42ab5d-8d44-40d3-99ea-2d35f3a3d4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18494
56973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1849456973
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1448839587
Short name T1852
Test name
Test status
Simulation time 10094031686 ps
CPU time 13.55 seconds
Started May 23 03:42:14 PM PDT 24
Finished May 23 03:42:38 PM PDT 24
Peak memory 204972 kb
Host smart-b37424d1-eb88-4119-92e7-15f4ca38021d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14488
39587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1448839587
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.911413080
Short name T1207
Test name
Test status
Simulation time 10125361530 ps
CPU time 12.94 seconds
Started May 23 03:42:14 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 204924 kb
Host smart-634ad096-334c-46dd-ab64-5ec0c6dc7c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91141
3080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.911413080
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2941462928
Short name T700
Test name
Test status
Simulation time 10089170599 ps
CPU time 14.48 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204956 kb
Host smart-ac4ca9a6-fc13-43e1-bc3b-a245b7803d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29414
62928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2941462928
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.3267862747
Short name T1674
Test name
Test status
Simulation time 10077325602 ps
CPU time 12.93 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:34 PM PDT 24
Peak memory 205012 kb
Host smart-8e614f82-af4e-4ba6-8eb5-b4bd1a07e293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32678
62747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.3267862747
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.3769813480
Short name T1743
Test name
Test status
Simulation time 10059905968 ps
CPU time 12.75 seconds
Started May 23 03:42:30 PM PDT 24
Finished May 23 03:42:52 PM PDT 24
Peak memory 204908 kb
Host smart-85a7e2d1-8d53-46d4-b882-52daa206a167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37698
13480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.3769813480
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2310313143
Short name T894
Test name
Test status
Simulation time 10043837012 ps
CPU time 13.39 seconds
Started May 23 03:42:20 PM PDT 24
Finished May 23 03:42:42 PM PDT 24
Peak memory 204940 kb
Host smart-5c29016f-08d2-4883-899b-c4e69e51d13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23103
13143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2310313143
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2361414078
Short name T755
Test name
Test status
Simulation time 27609282612 ps
CPU time 57.19 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:43:16 PM PDT 24
Peak memory 205040 kb
Host smart-96d64099-bdbd-43b1-914c-6801090dbc43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23614
14078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2361414078
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2346020911
Short name T785
Test name
Test status
Simulation time 10113047857 ps
CPU time 12.73 seconds
Started May 23 03:42:12 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204956 kb
Host smart-ef5dbb04-0b0b-4c2b-8716-61ae8fc29e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23460
20911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2346020911
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.4247861887
Short name T1489
Test name
Test status
Simulation time 10075620129 ps
CPU time 12.79 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204884 kb
Host smart-ee1fb9c6-5256-4227-990b-f616f121b89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42478
61887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.4247861887
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.478441631
Short name T801
Test name
Test status
Simulation time 10043786038 ps
CPU time 14.16 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 204972 kb
Host smart-c0992140-4a0d-4f9a-a5e2-2efb461e792b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47844
1631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.478441631
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.16160382
Short name T551
Test name
Test status
Simulation time 10048844429 ps
CPU time 16.53 seconds
Started May 23 03:42:17 PM PDT 24
Finished May 23 03:42:42 PM PDT 24
Peak memory 204928 kb
Host smart-93c76404-6c79-4c8b-877a-482a3f012bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16160
382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.16160382
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1480026412
Short name T147
Test name
Test status
Simulation time 10087042592 ps
CPU time 13.71 seconds
Started May 23 03:42:19 PM PDT 24
Finished May 23 03:42:42 PM PDT 24
Peak memory 204980 kb
Host smart-6d30f88d-e9b7-447b-a3e0-a12a040b93d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14800
26412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1480026412
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.845963707
Short name T1837
Test name
Test status
Simulation time 10048509454 ps
CPU time 13.53 seconds
Started May 23 03:42:12 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204944 kb
Host smart-48b43292-7829-4ab8-805d-dc4efe66810b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84596
3707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.845963707
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1305974056
Short name T63
Test name
Test status
Simulation time 10125362641 ps
CPU time 12.59 seconds
Started May 23 03:42:07 PM PDT 24
Finished May 23 03:42:27 PM PDT 24
Peak memory 204936 kb
Host smart-8fc7612a-e1bb-433c-a191-dfa926cab93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13059
74056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1305974056
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.849974717
Short name T1673
Test name
Test status
Simulation time 10147338683 ps
CPU time 13.85 seconds
Started May 23 03:42:26 PM PDT 24
Finished May 23 03:42:47 PM PDT 24
Peak memory 204944 kb
Host smart-e7076984-1df1-4350-89de-96084fd2724f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84997
4717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.849974717
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.4111762702
Short name T1603
Test name
Test status
Simulation time 10073524054 ps
CPU time 13.46 seconds
Started May 23 03:42:12 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204944 kb
Host smart-76beb084-f67d-4b8a-a035-cfe3e4469bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41117
62702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.4111762702
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.359794258
Short name T1671
Test name
Test status
Simulation time 10209187760 ps
CPU time 15.45 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:39 PM PDT 24
Peak memory 204908 kb
Host smart-9b8b8473-f3b8-46be-a760-13ef4d5e20b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=359794258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.359794258
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.1174356816
Short name T989
Test name
Test status
Simulation time 10077519413 ps
CPU time 13.82 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 204968 kb
Host smart-f3b78ecb-81ef-4d16-961c-1f900fc73b73
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1174356816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.1174356816
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.28351462
Short name T1643
Test name
Test status
Simulation time 10082212954 ps
CPU time 13.2 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:42:31 PM PDT 24
Peak memory 204996 kb
Host smart-a06569e4-4608-4364-abc9-047d168d41a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28351
462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.28351462
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.2695203276
Short name T515
Test name
Test status
Simulation time 14071912894 ps
CPU time 17.67 seconds
Started May 23 03:42:18 PM PDT 24
Finished May 23 03:42:45 PM PDT 24
Peak memory 204944 kb
Host smart-c25b0afc-2dee-4755-84e7-ea650da68b29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2695203276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.2695203276
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.245724310
Short name T1738
Test name
Test status
Simulation time 13242863096 ps
CPU time 16.34 seconds
Started May 23 03:42:28 PM PDT 24
Finished May 23 03:42:53 PM PDT 24
Peak memory 204964 kb
Host smart-ecc80aef-4113-4dff-8156-f1deabfd59e4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=245724310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.245724310
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.4152065136
Short name T1897
Test name
Test status
Simulation time 13235275775 ps
CPU time 16.84 seconds
Started May 23 03:42:19 PM PDT 24
Finished May 23 03:42:44 PM PDT 24
Peak memory 204924 kb
Host smart-74a6d641-c4e6-4d2c-ad36-7e2f35ddc70e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4152065136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.4152065136
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1288436756
Short name T788
Test name
Test status
Simulation time 10078376141 ps
CPU time 16.47 seconds
Started May 23 03:42:17 PM PDT 24
Finished May 23 03:42:42 PM PDT 24
Peak memory 204920 kb
Host smart-95165e55-5c8c-4442-b729-558c0590431f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12884
36756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1288436756
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.1909863145
Short name T1615
Test name
Test status
Simulation time 10046255261 ps
CPU time 13.46 seconds
Started May 23 03:42:22 PM PDT 24
Finished May 23 03:42:43 PM PDT 24
Peak memory 204940 kb
Host smart-6c3fab9b-d0b1-4c39-b9c3-8f4a8d0a7dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19098
63145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.1909863145
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2975633584
Short name T951
Test name
Test status
Simulation time 11122437916 ps
CPU time 15.5 seconds
Started May 23 03:42:14 PM PDT 24
Finished May 23 03:42:39 PM PDT 24
Peak memory 204972 kb
Host smart-6975644b-8a27-4993-bef4-362b4a72af10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29756
33584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2975633584
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1551621587
Short name T1925
Test name
Test status
Simulation time 10069578441 ps
CPU time 13.43 seconds
Started May 23 03:42:12 PM PDT 24
Finished May 23 03:42:35 PM PDT 24
Peak memory 204980 kb
Host smart-6d582c85-7014-4b87-9072-72afe44ce071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15516
21587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1551621587
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2211683530
Short name T962
Test name
Test status
Simulation time 10059170632 ps
CPU time 13.63 seconds
Started May 23 03:42:08 PM PDT 24
Finished May 23 03:42:30 PM PDT 24
Peak memory 205052 kb
Host smart-31cdfab7-06cd-4950-8737-4bcce8232ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22116
83530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2211683530
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1301399684
Short name T440
Test name
Test status
Simulation time 10837828330 ps
CPU time 15.68 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 205012 kb
Host smart-5edcf0a8-522a-4c7f-84b5-0b5c17ffd1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13013
99684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1301399684
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2277074081
Short name T823
Test name
Test status
Simulation time 10289219435 ps
CPU time 16.9 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:40 PM PDT 24
Peak memory 204968 kb
Host smart-856454e4-b36c-443d-bb94-b80149bd6eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22770
74081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2277074081
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2626839747
Short name T1446
Test name
Test status
Simulation time 10101813210 ps
CPU time 15.04 seconds
Started May 23 03:42:22 PM PDT 24
Finished May 23 03:42:45 PM PDT 24
Peak memory 204932 kb
Host smart-070fd38e-0381-40ff-bb82-89ab5dc8a160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26268
39747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2626839747
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.106573771
Short name T1408
Test name
Test status
Simulation time 10059950807 ps
CPU time 14.79 seconds
Started May 23 03:42:15 PM PDT 24
Finished May 23 03:42:40 PM PDT 24
Peak memory 204936 kb
Host smart-614ff1b8-5841-4b31-8335-3380e12d6fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10657
3771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.106573771
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2601563260
Short name T1357
Test name
Test status
Simulation time 10138635945 ps
CPU time 15.33 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:42:33 PM PDT 24
Peak memory 204904 kb
Host smart-e603c60e-719c-48bf-ab27-0a22b1dea5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26015
63260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2601563260
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.235485179
Short name T469
Test name
Test status
Simulation time 10056578586 ps
CPU time 13.21 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:42:31 PM PDT 24
Peak memory 204968 kb
Host smart-1a2cdac4-04a2-4247-b42b-97fbaee2cdb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23548
5179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.235485179
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2435069722
Short name T384
Test name
Test status
Simulation time 13262184545 ps
CPU time 16.74 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:40 PM PDT 24
Peak memory 204932 kb
Host smart-ffaaaf34-32d4-429d-b6bc-d3b4fa7fe236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24350
69722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2435069722
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1884075064
Short name T1698
Test name
Test status
Simulation time 10096128563 ps
CPU time 15.17 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:35 PM PDT 24
Peak memory 205024 kb
Host smart-b1bfefcd-cff0-4c13-9ded-1d7b1464e7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18840
75064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1884075064
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1887345123
Short name T353
Test name
Test status
Simulation time 10050187442 ps
CPU time 15.04 seconds
Started May 23 03:42:08 PM PDT 24
Finished May 23 03:42:31 PM PDT 24
Peak memory 204968 kb
Host smart-78882080-7a5c-4424-a80d-d67b8841b1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18873
45123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1887345123
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3405290889
Short name T98
Test name
Test status
Simulation time 10200163315 ps
CPU time 14.15 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:35 PM PDT 24
Peak memory 204964 kb
Host smart-0c38e0f2-f563-49ee-9d0c-701981194ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34052
90889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3405290889
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2089499906
Short name T912
Test name
Test status
Simulation time 10103582031 ps
CPU time 12.68 seconds
Started May 23 03:42:12 PM PDT 24
Finished May 23 03:42:35 PM PDT 24
Peak memory 204884 kb
Host smart-4bb0a477-76e8-4496-8a2e-5bb4b6dc4892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20894
99906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2089499906
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1390663708
Short name T1931
Test name
Test status
Simulation time 10073635278 ps
CPU time 14.75 seconds
Started May 23 03:42:14 PM PDT 24
Finished May 23 03:42:39 PM PDT 24
Peak memory 205000 kb
Host smart-eb1570ae-3610-4412-895e-5b36eb08800c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13906
63708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1390663708
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3003660996
Short name T1296
Test name
Test status
Simulation time 10090336197 ps
CPU time 14.07 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 204984 kb
Host smart-ee6db715-4a50-40e0-bed0-445e200ccbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30036
60996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3003660996
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.1494615205
Short name T955
Test name
Test status
Simulation time 10069822607 ps
CPU time 14.72 seconds
Started May 23 03:42:12 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 204920 kb
Host smart-c7392cca-bf64-45f2-a3f3-7fde82086d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14946
15205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.1494615205
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3453818478
Short name T1691
Test name
Test status
Simulation time 10066527841 ps
CPU time 15.26 seconds
Started May 23 03:42:15 PM PDT 24
Finished May 23 03:42:40 PM PDT 24
Peak memory 204932 kb
Host smart-3b5d2f8f-42ba-442c-bfc6-8fff7dafa97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34538
18478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3453818478
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.123077944
Short name T1846
Test name
Test status
Simulation time 10082329793 ps
CPU time 15.79 seconds
Started May 23 03:42:18 PM PDT 24
Finished May 23 03:42:42 PM PDT 24
Peak memory 204908 kb
Host smart-a1151b98-1fdd-4b03-b6d5-4fd3e8433e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12307
7944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.123077944
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1546518025
Short name T1777
Test name
Test status
Simulation time 29654692172 ps
CPU time 58.79 seconds
Started May 23 03:42:14 PM PDT 24
Finished May 23 03:43:23 PM PDT 24
Peak memory 205016 kb
Host smart-ef78db5d-3058-4be8-b917-561ce85c4f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15465
18025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1546518025
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1237688180
Short name T1409
Test name
Test status
Simulation time 10072316791 ps
CPU time 16.1 seconds
Started May 23 03:42:14 PM PDT 24
Finished May 23 03:42:40 PM PDT 24
Peak memory 204948 kb
Host smart-60b55be5-7c63-41c9-a34a-6fb3f89d7f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12376
88180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1237688180
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.192084981
Short name T595
Test name
Test status
Simulation time 10079575286 ps
CPU time 14.24 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:34 PM PDT 24
Peak memory 204964 kb
Host smart-85d45dc3-700c-455d-9e42-0ffff590d9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19208
4981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.192084981
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.2628186417
Short name T321
Test name
Test status
Simulation time 10061783966 ps
CPU time 13.22 seconds
Started May 23 03:42:11 PM PDT 24
Finished May 23 03:42:34 PM PDT 24
Peak memory 204912 kb
Host smart-0b03b3b5-5a80-4665-a4db-93dbf0aca1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26281
86417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.2628186417
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3468974461
Short name T1926
Test name
Test status
Simulation time 10045233775 ps
CPU time 12.73 seconds
Started May 23 03:42:13 PM PDT 24
Finished May 23 03:42:36 PM PDT 24
Peak memory 204920 kb
Host smart-5fa280e3-4996-44ba-a482-573b590843ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34689
74461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3468974461
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.161790115
Short name T1932
Test name
Test status
Simulation time 10047067839 ps
CPU time 15.63 seconds
Started May 23 03:42:15 PM PDT 24
Finished May 23 03:42:41 PM PDT 24
Peak memory 204920 kb
Host smart-de1d4264-817e-4a41-8e0a-5838fd8a4424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16179
0115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.161790115
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2406806830
Short name T1542
Test name
Test status
Simulation time 10087974745 ps
CPU time 14.4 seconds
Started May 23 03:42:21 PM PDT 24
Finished May 23 03:42:43 PM PDT 24
Peak memory 204960 kb
Host smart-58b33ef3-6026-4503-b091-aad884f06143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24068
06830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2406806830
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1333994723
Short name T1484
Test name
Test status
Simulation time 10139172681 ps
CPU time 14.27 seconds
Started May 23 03:42:10 PM PDT 24
Finished May 23 03:42:33 PM PDT 24
Peak memory 205008 kb
Host smart-cf23cc15-ad2a-4659-a767-3b1695555512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13339
94723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1333994723
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1495022683
Short name T1024
Test name
Test status
Simulation time 10099071349 ps
CPU time 12.62 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:42:31 PM PDT 24
Peak memory 204980 kb
Host smart-952d0967-f3e1-4b7a-9e5f-a89d3d1b9271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14950
22683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1495022683
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.691592483
Short name T484
Test name
Test status
Simulation time 10215352327 ps
CPU time 13.77 seconds
Started May 23 03:42:29 PM PDT 24
Finished May 23 03:42:51 PM PDT 24
Peak memory 205004 kb
Host smart-9efe7ff2-aace-4f8d-ad92-bcb8d07d932c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=691592483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.691592483
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.1460302109
Short name T1826
Test name
Test status
Simulation time 10083365340 ps
CPU time 13.65 seconds
Started May 23 03:42:32 PM PDT 24
Finished May 23 03:42:57 PM PDT 24
Peak memory 204992 kb
Host smart-e4d86ab2-6737-474a-b72f-7508a03b1f43
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1460302109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.1460302109
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.4075658136
Short name T683
Test name
Test status
Simulation time 10133564202 ps
CPU time 13.08 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204876 kb
Host smart-4fbdafe2-0df2-4c73-881f-8674f27889a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40756
58136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.4075658136
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.166771325
Short name T1573
Test name
Test status
Simulation time 13863104225 ps
CPU time 16.83 seconds
Started May 23 03:42:14 PM PDT 24
Finished May 23 03:42:41 PM PDT 24
Peak memory 204920 kb
Host smart-0e8b81a7-80ec-4b87-904e-ff4b0c90c834
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=166771325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.166771325
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1498967912
Short name T629
Test name
Test status
Simulation time 13305715146 ps
CPU time 16.1 seconds
Started May 23 03:42:12 PM PDT 24
Finished May 23 03:42:38 PM PDT 24
Peak memory 204960 kb
Host smart-096af074-bd37-4fac-8962-5b628a23a08b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1498967912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1498967912
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3126985352
Short name T5
Test name
Test status
Simulation time 13215389109 ps
CPU time 16.75 seconds
Started May 23 03:42:21 PM PDT 24
Finished May 23 03:42:46 PM PDT 24
Peak memory 204952 kb
Host smart-1406c323-3743-4c62-ae13-cbadad003e3e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3126985352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.3126985352
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3797513028
Short name T990
Test name
Test status
Simulation time 10059878500 ps
CPU time 16.68 seconds
Started May 23 03:42:20 PM PDT 24
Finished May 23 03:42:45 PM PDT 24
Peak memory 204960 kb
Host smart-6f088b70-c484-4ca0-8040-cb59f678d8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37975
13028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3797513028
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3798853541
Short name T1859
Test name
Test status
Simulation time 10059308124 ps
CPU time 14.36 seconds
Started May 23 03:42:15 PM PDT 24
Finished May 23 03:42:40 PM PDT 24
Peak memory 204880 kb
Host smart-cbf34a4c-305d-4d2c-91a2-5ed7a2a0dbde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37988
53541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3798853541
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.197428765
Short name T176
Test name
Test status
Simulation time 11116956655 ps
CPU time 14.42 seconds
Started May 23 03:42:16 PM PDT 24
Finished May 23 03:42:40 PM PDT 24
Peak memory 205044 kb
Host smart-125dd78b-f9c8-4120-9b12-8f4c6e1d6a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19742
8765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.197428765
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2889765845
Short name T1118
Test name
Test status
Simulation time 10143072996 ps
CPU time 13.25 seconds
Started May 23 03:42:30 PM PDT 24
Finished May 23 03:42:53 PM PDT 24
Peak memory 204868 kb
Host smart-32621baa-d7a5-497b-8a4a-15e0c6f3f7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28897
65845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2889765845
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.707444891
Short name T614
Test name
Test status
Simulation time 10071950863 ps
CPU time 13.31 seconds
Started May 23 03:42:18 PM PDT 24
Finished May 23 03:42:40 PM PDT 24
Peak memory 204956 kb
Host smart-4890755a-fd16-4b54-9fb3-aacc7b5c452c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70744
4891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.707444891
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2274139359
Short name T518
Test name
Test status
Simulation time 10973822320 ps
CPU time 16.7 seconds
Started May 23 03:42:20 PM PDT 24
Finished May 23 03:42:46 PM PDT 24
Peak memory 204952 kb
Host smart-ce9bbdef-3db2-48c8-ad2e-0432c6848356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22741
39359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2274139359
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1848237633
Short name T1681
Test name
Test status
Simulation time 10072362471 ps
CPU time 13.47 seconds
Started May 23 03:42:10 PM PDT 24
Finished May 23 03:42:33 PM PDT 24
Peak memory 204916 kb
Host smart-6f1846be-5394-40f7-88ef-615e116dc23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18482
37633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1848237633
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1688220818
Short name T421
Test name
Test status
Simulation time 10151647169 ps
CPU time 13.69 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204984 kb
Host smart-6721ecbc-23fd-4ea4-8eb8-1610cde39edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16882
20818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1688220818
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.164579878
Short name T931
Test name
Test status
Simulation time 10086078070 ps
CPU time 14.01 seconds
Started May 23 03:42:31 PM PDT 24
Finished May 23 03:42:55 PM PDT 24
Peak memory 204988 kb
Host smart-7f4c8b97-a538-4c34-b640-7483ba662c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16457
9878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.164579878
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.556913745
Short name T319
Test name
Test status
Simulation time 10053264595 ps
CPU time 15.91 seconds
Started May 23 03:42:19 PM PDT 24
Finished May 23 03:42:43 PM PDT 24
Peak memory 204944 kb
Host smart-c4eb0e4e-fdaa-4966-9486-28356550df89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55691
3745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.556913745
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2951454088
Short name T787
Test name
Test status
Simulation time 10112403097 ps
CPU time 14.6 seconds
Started May 23 03:42:16 PM PDT 24
Finished May 23 03:42:40 PM PDT 24
Peak memory 204948 kb
Host smart-b9f83ad8-d4a2-4fe9-ad01-f6e0a3df56b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29514
54088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2951454088
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.48993284
Short name T1630
Test name
Test status
Simulation time 13201283455 ps
CPU time 16.59 seconds
Started May 23 03:42:25 PM PDT 24
Finished May 23 03:42:49 PM PDT 24
Peak memory 204952 kb
Host smart-227aea45-e5fa-41b3-925a-43993effe886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48993
284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.48993284
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3100479708
Short name T1533
Test name
Test status
Simulation time 10101066830 ps
CPU time 14.02 seconds
Started May 23 03:42:17 PM PDT 24
Finished May 23 03:42:40 PM PDT 24
Peak memory 204904 kb
Host smart-734ffa02-a62b-48cd-b736-4a005bd3cf3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31004
79708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3100479708
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1286536030
Short name T725
Test name
Test status
Simulation time 10087477520 ps
CPU time 15.03 seconds
Started May 23 03:42:23 PM PDT 24
Finished May 23 03:42:45 PM PDT 24
Peak memory 204944 kb
Host smart-d7c7e9e0-759c-4280-afb1-30b0fd164894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12865
36030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1286536030
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1348865128
Short name T108
Test name
Test status
Simulation time 10080352467 ps
CPU time 13.48 seconds
Started May 23 03:42:10 PM PDT 24
Finished May 23 03:42:33 PM PDT 24
Peak memory 204940 kb
Host smart-188f26f6-a0c6-42fb-abd0-d4d08ed00b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13488
65128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1348865128
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1945514443
Short name T1300
Test name
Test status
Simulation time 10146739311 ps
CPU time 13.86 seconds
Started May 23 03:42:09 PM PDT 24
Finished May 23 03:42:32 PM PDT 24
Peak memory 205004 kb
Host smart-33d11491-667e-4b30-a491-90ca1a7baa32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19455
14443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1945514443
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2775508803
Short name T411
Test name
Test status
Simulation time 10098499972 ps
CPU time 13.24 seconds
Started May 23 03:42:19 PM PDT 24
Finished May 23 03:42:41 PM PDT 24
Peak memory 204844 kb
Host smart-c23739b4-6d3f-41e4-8791-d59d28062378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27755
08803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2775508803
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3232845340
Short name T1202
Test name
Test status
Simulation time 10065944685 ps
CPU time 14.43 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204992 kb
Host smart-241d7d93-e7f7-4c5a-9c30-68b98b03e28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32328
45340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3232845340
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.637038940
Short name T174
Test name
Test status
Simulation time 10079871701 ps
CPU time 14.07 seconds
Started May 23 03:42:18 PM PDT 24
Finished May 23 03:42:41 PM PDT 24
Peak memory 204964 kb
Host smart-011dc581-9f95-4e6c-a51b-466ac02e07c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63703
8940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.637038940
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.35987215
Short name T456
Test name
Test status
Simulation time 10080324807 ps
CPU time 13.3 seconds
Started May 23 03:42:35 PM PDT 24
Finished May 23 03:43:00 PM PDT 24
Peak memory 204960 kb
Host smart-df41fd53-2592-46ef-b97b-17fc81240fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35987
215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.35987215
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.420708817
Short name T1155
Test name
Test status
Simulation time 10051133866 ps
CPU time 15.55 seconds
Started May 23 03:42:26 PM PDT 24
Finished May 23 03:42:49 PM PDT 24
Peak memory 204880 kb
Host smart-e05fd47f-b7ca-40fb-8180-8ad3208da24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42070
8817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.420708817
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2010031686
Short name T20
Test name
Test status
Simulation time 10059115707 ps
CPU time 13.16 seconds
Started May 23 03:42:31 PM PDT 24
Finished May 23 03:42:54 PM PDT 24
Peak memory 204844 kb
Host smart-2dddd013-2300-4899-ae8c-6847d7d64797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20100
31686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2010031686
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2032917881
Short name T1117
Test name
Test status
Simulation time 19001869766 ps
CPU time 37.71 seconds
Started May 23 03:42:29 PM PDT 24
Finished May 23 03:43:14 PM PDT 24
Peak memory 205064 kb
Host smart-caca9cc3-a6a0-4d39-abba-7763d7223cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20329
17881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2032917881
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.4236215008
Short name T1621
Test name
Test status
Simulation time 10065503679 ps
CPU time 13.92 seconds
Started May 23 03:42:23 PM PDT 24
Finished May 23 03:42:44 PM PDT 24
Peak memory 204964 kb
Host smart-a30b417d-c845-4f83-b0fd-7e892cc78459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42362
15008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.4236215008
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1542215544
Short name T483
Test name
Test status
Simulation time 10066674434 ps
CPU time 16.37 seconds
Started May 23 03:42:20 PM PDT 24
Finished May 23 03:42:45 PM PDT 24
Peak memory 204952 kb
Host smart-415213a4-b489-4cd7-82c0-a3f16e8cca4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15422
15544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1542215544
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.3625672234
Short name T1734
Test name
Test status
Simulation time 10071315468 ps
CPU time 12.97 seconds
Started May 23 03:42:32 PM PDT 24
Finished May 23 03:42:56 PM PDT 24
Peak memory 204944 kb
Host smart-7d8403d1-cdf9-4eb4-b498-b739b870767a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36256
72234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.3625672234
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.124983207
Short name T1314
Test name
Test status
Simulation time 10047072899 ps
CPU time 14.14 seconds
Started May 23 03:42:32 PM PDT 24
Finished May 23 03:42:56 PM PDT 24
Peak memory 204964 kb
Host smart-5d3021d9-bfb5-4869-9900-b53d24fdc2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12498
3207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.124983207
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2179334184
Short name T1919
Test name
Test status
Simulation time 10056518246 ps
CPU time 13.53 seconds
Started May 23 03:42:21 PM PDT 24
Finished May 23 03:42:43 PM PDT 24
Peak memory 204956 kb
Host smart-9a1dc5b7-0c53-45bc-b536-a2fba8573e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21793
34184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2179334184
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3305219766
Short name T1789
Test name
Test status
Simulation time 10056287320 ps
CPU time 15.59 seconds
Started May 23 03:42:28 PM PDT 24
Finished May 23 03:42:52 PM PDT 24
Peak memory 205004 kb
Host smart-3b6478a5-a093-4e41-88a1-eb1507dc6da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33052
19766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3305219766
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.977450549
Short name T153
Test name
Test status
Simulation time 10107212830 ps
CPU time 13.99 seconds
Started May 23 03:42:18 PM PDT 24
Finished May 23 03:42:40 PM PDT 24
Peak memory 204972 kb
Host smart-e8118c86-3da7-492d-8547-1e1b18e7f9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97745
0549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.977450549
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.399270988
Short name T877
Test name
Test status
Simulation time 10095679091 ps
CPU time 14.07 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204992 kb
Host smart-ac00f01b-179f-466f-8a8e-8b79e4d864b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39927
0988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.399270988
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.816413133
Short name T1276
Test name
Test status
Simulation time 10071359387 ps
CPU time 15.64 seconds
Started May 23 03:42:24 PM PDT 24
Finished May 23 03:42:47 PM PDT 24
Peak memory 204936 kb
Host smart-f9487116-891e-471c-ac64-e9f822e0902d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81641
3133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.816413133
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.149551013
Short name T1565
Test name
Test status
Simulation time 10155311193 ps
CPU time 13.02 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204968 kb
Host smart-859aff5f-94a7-4eed-8f3a-85b13b24bce9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=149551013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.149551013
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.2058095637
Short name T1462
Test name
Test status
Simulation time 10053731587 ps
CPU time 14.11 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204824 kb
Host smart-e9862520-bd34-4030-be4c-0897fbb53547
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2058095637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.2058095637
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.1220523406
Short name T1861
Test name
Test status
Simulation time 10060660414 ps
CPU time 12.49 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204756 kb
Host smart-00ef5439-af71-4964-82dc-e2415e321ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12205
23406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.1220523406
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.2781650868
Short name T855
Test name
Test status
Simulation time 13762789540 ps
CPU time 16.94 seconds
Started May 23 03:42:31 PM PDT 24
Finished May 23 03:42:58 PM PDT 24
Peak memory 204928 kb
Host smart-47db779d-fd93-45e0-97f0-606bd927bdb8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2781650868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.2781650868
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2679360835
Short name T13
Test name
Test status
Simulation time 13238551949 ps
CPU time 18.59 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:08 PM PDT 24
Peak memory 204956 kb
Host smart-9f99c9ef-e581-4204-96e5-72b1f291d481
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2679360835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.2679360835
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2016098794
Short name T806
Test name
Test status
Simulation time 10118347818 ps
CPU time 12.91 seconds
Started May 23 03:42:22 PM PDT 24
Finished May 23 03:42:42 PM PDT 24
Peak memory 204932 kb
Host smart-20f77bbc-41be-44ad-bc79-0fe4ca2d87a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20160
98794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2016098794
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1485393489
Short name T1494
Test name
Test status
Simulation time 11111489210 ps
CPU time 17.35 seconds
Started May 23 03:42:33 PM PDT 24
Finished May 23 03:43:02 PM PDT 24
Peak memory 204984 kb
Host smart-83fe06a5-3699-4ff7-a94a-40f8b1216349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14853
93489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1485393489
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2570836503
Short name T1737
Test name
Test status
Simulation time 10035759949 ps
CPU time 12.68 seconds
Started May 23 03:42:30 PM PDT 24
Finished May 23 03:42:52 PM PDT 24
Peak memory 204836 kb
Host smart-0c8ecb77-16a6-4fb8-8ec6-7a860c23dcdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25708
36503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2570836503
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3184519780
Short name T1230
Test name
Test status
Simulation time 10051579115 ps
CPU time 12.89 seconds
Started May 23 03:42:31 PM PDT 24
Finished May 23 03:42:54 PM PDT 24
Peak memory 204944 kb
Host smart-d2671bb9-2d81-4d68-8c27-fbd34771aa1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31845
19780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3184519780
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.624534377
Short name T935
Test name
Test status
Simulation time 10671461889 ps
CPU time 14.28 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:08 PM PDT 24
Peak memory 204972 kb
Host smart-84ac53ad-cb42-4879-a4b4-0b665e13c2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62453
4377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.624534377
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3555204232
Short name T1356
Test name
Test status
Simulation time 10060113537 ps
CPU time 13.94 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204936 kb
Host smart-d4a200d4-e539-41dc-9964-049cd964a103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35552
04232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3555204232
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.961034194
Short name T1712
Test name
Test status
Simulation time 10100292351 ps
CPU time 13.18 seconds
Started May 23 03:42:31 PM PDT 24
Finished May 23 03:42:55 PM PDT 24
Peak memory 204944 kb
Host smart-6f2ea8f3-2dae-4c39-b14b-7f732241f114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96103
4194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.961034194
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2474096717
Short name T1940
Test name
Test status
Simulation time 10052488738 ps
CPU time 13.94 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:03 PM PDT 24
Peak memory 204236 kb
Host smart-ea8f6041-c115-446d-b1bb-6b066fc50ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24740
96717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2474096717
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.612328068
Short name T340
Test name
Test status
Simulation time 10117357935 ps
CPU time 14.79 seconds
Started May 23 03:42:33 PM PDT 24
Finished May 23 03:42:59 PM PDT 24
Peak memory 205032 kb
Host smart-db5f7dd4-d297-48ff-a63e-668cff18807f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61232
8068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.612328068
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.871794760
Short name T212
Test name
Test status
Simulation time 10094674186 ps
CPU time 12.66 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:02 PM PDT 24
Peak memory 205012 kb
Host smart-36c05dbe-3ee7-4b97-975b-1a39439cc199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87179
4760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.871794760
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.967619273
Short name T1665
Test name
Test status
Simulation time 13232183740 ps
CPU time 15.17 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204892 kb
Host smart-7824b15d-88b3-4f49-b081-12e010ffa8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96761
9273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.967619273
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.4251443813
Short name T1032
Test name
Test status
Simulation time 10138698241 ps
CPU time 13.71 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204972 kb
Host smart-63057906-fc33-4877-835c-425a945662c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42514
43813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.4251443813
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2193151086
Short name T1775
Test name
Test status
Simulation time 10068773351 ps
CPU time 13.24 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204964 kb
Host smart-302c0923-f7c0-4eb6-bede-0040c84f1ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21931
51086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2193151086
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3461777577
Short name T1800
Test name
Test status
Simulation time 10118494363 ps
CPU time 12.62 seconds
Started May 23 03:42:21 PM PDT 24
Finished May 23 03:42:42 PM PDT 24
Peak memory 204960 kb
Host smart-15f0cbb6-e5e9-451c-b963-faa26558e24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34617
77577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3461777577
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1081349946
Short name T1001
Test name
Test status
Simulation time 10143307151 ps
CPU time 14.22 seconds
Started May 23 03:42:31 PM PDT 24
Finished May 23 03:42:56 PM PDT 24
Peak memory 204848 kb
Host smart-d9968af8-11e4-4e2e-b96f-07068b14320f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10813
49946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1081349946
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1895524636
Short name T710
Test name
Test status
Simulation time 10066577746 ps
CPU time 14.56 seconds
Started May 23 03:42:25 PM PDT 24
Finished May 23 03:42:47 PM PDT 24
Peak memory 204936 kb
Host smart-f4be55c4-fa2b-45a3-ac5d-c09961d3ea47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18955
24636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1895524636
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3359029737
Short name T526
Test name
Test status
Simulation time 10110639550 ps
CPU time 14.07 seconds
Started May 23 03:42:19 PM PDT 24
Finished May 23 03:42:42 PM PDT 24
Peak memory 204996 kb
Host smart-f20a7686-2e2c-47a6-ad02-afff7b6f473d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33590
29737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3359029737
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1221177414
Short name T87
Test name
Test status
Simulation time 10090161524 ps
CPU time 12.52 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:00 PM PDT 24
Peak memory 204968 kb
Host smart-c264e776-9a95-4e45-aef7-594326059cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12211
77414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1221177414
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.3138659277
Short name T1627
Test name
Test status
Simulation time 10079523936 ps
CPU time 12.9 seconds
Started May 23 03:42:31 PM PDT 24
Finished May 23 03:42:54 PM PDT 24
Peak memory 204960 kb
Host smart-9632434a-4f5e-4fc6-ab95-e90eeb4df492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31386
59277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.3138659277
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2443711882
Short name T1348
Test name
Test status
Simulation time 10060838887 ps
CPU time 13.47 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204972 kb
Host smart-5dfd90f4-5961-4b6c-ae96-d6f22e392128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24437
11882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2443711882
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2586980441
Short name T539
Test name
Test status
Simulation time 10071058653 ps
CPU time 12.97 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:03 PM PDT 24
Peak memory 204968 kb
Host smart-199e9b39-587b-4c8c-abe1-2b2bef440613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25869
80441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2586980441
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.785903813
Short name T850
Test name
Test status
Simulation time 32167919508 ps
CPU time 66.01 seconds
Started May 23 03:42:24 PM PDT 24
Finished May 23 03:43:38 PM PDT 24
Peak memory 205032 kb
Host smart-0c7313bf-d9a3-4c03-8101-0100b6c9cec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78590
3813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.785903813
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.141903880
Short name T1455
Test name
Test status
Simulation time 10127279313 ps
CPU time 15.69 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204644 kb
Host smart-9d0ffe1d-65fa-4137-abdf-c58103a678a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14190
3880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.141903880
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3434736710
Short name T1680
Test name
Test status
Simulation time 10152737497 ps
CPU time 14.66 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204976 kb
Host smart-71a46bef-e71d-4fe3-a04c-491521145c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34347
36710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3434736710
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.3907103443
Short name T1464
Test name
Test status
Simulation time 10090565794 ps
CPU time 15.83 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204984 kb
Host smart-c2e42096-d928-42e1-a0be-215231b37080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39071
03443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.3907103443
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.458282003
Short name T831
Test name
Test status
Simulation time 10052686885 ps
CPU time 16.04 seconds
Started May 23 03:42:29 PM PDT 24
Finished May 23 03:42:54 PM PDT 24
Peak memory 205004 kb
Host smart-0fdd79d2-e88a-423d-a849-c5caee187db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45828
2003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.458282003
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3081738863
Short name T789
Test name
Test status
Simulation time 10069957355 ps
CPU time 13.41 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:03 PM PDT 24
Peak memory 204944 kb
Host smart-32a49089-e5ac-49df-a573-c37bd2a8a4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30817
38863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3081738863
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3688737822
Short name T1597
Test name
Test status
Simulation time 10056112384 ps
CPU time 12.77 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:02 PM PDT 24
Peak memory 204620 kb
Host smart-b2423a2a-7b0a-4261-83f9-b661430bb72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36887
37822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3688737822
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3077926671
Short name T1526
Test name
Test status
Simulation time 10140179401 ps
CPU time 13.03 seconds
Started May 23 03:42:34 PM PDT 24
Finished May 23 03:42:58 PM PDT 24
Peak memory 204948 kb
Host smart-1e4da553-578a-4b83-a032-52b3488b0d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30779
26671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3077926671
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.4080596239
Short name T1382
Test name
Test status
Simulation time 10116783704 ps
CPU time 12.83 seconds
Started May 23 03:42:24 PM PDT 24
Finished May 23 03:42:45 PM PDT 24
Peak memory 204964 kb
Host smart-77e7b6f1-5ef5-44fd-9c80-a9c98c6a3d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40805
96239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.4080596239
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2897833045
Short name T816
Test name
Test status
Simulation time 10069777656 ps
CPU time 13.42 seconds
Started May 23 03:42:32 PM PDT 24
Finished May 23 03:42:56 PM PDT 24
Peak memory 204952 kb
Host smart-580575d8-001f-47b0-add1-ad556af65751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28978
33045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2897833045
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.1515566627
Short name T1366
Test name
Test status
Simulation time 10147921859 ps
CPU time 14.3 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:12 PM PDT 24
Peak memory 204972 kb
Host smart-e5db9964-75b3-4f16-80e0-b334465b65b9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1515566627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.1515566627
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.617155609
Short name T1666
Test name
Test status
Simulation time 10062231344 ps
CPU time 15.5 seconds
Started May 23 03:39:50 PM PDT 24
Finished May 23 03:40:13 PM PDT 24
Peak memory 204952 kb
Host smart-18534ca5-fd98-4752-9c72-940ebd900e0e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=617155609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.617155609
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.3318284156
Short name T1510
Test name
Test status
Simulation time 10134442975 ps
CPU time 13.78 seconds
Started May 23 03:39:50 PM PDT 24
Finished May 23 03:40:12 PM PDT 24
Peak memory 204948 kb
Host smart-d55008ed-e698-41f3-b683-63fd85bc4204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33182
84156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.3318284156
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.78724606
Short name T713
Test name
Test status
Simulation time 13661221825 ps
CPU time 16.73 seconds
Started May 23 03:39:51 PM PDT 24
Finished May 23 03:40:24 PM PDT 24
Peak memory 204948 kb
Host smart-c7ab4a6c-8dc8-44cb-b14a-1120944935c9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=78724606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.78724606
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.3680231904
Short name T1402
Test name
Test status
Simulation time 13247263336 ps
CPU time 16.35 seconds
Started May 23 03:39:41 PM PDT 24
Finished May 23 03:40:02 PM PDT 24
Peak memory 204960 kb
Host smart-7abad508-4662-4131-80ad-39afa9c5b95f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3680231904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.3680231904
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.1127181793
Short name T723
Test name
Test status
Simulation time 13266198650 ps
CPU time 17.52 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:14 PM PDT 24
Peak memory 204904 kb
Host smart-7c3c8813-8138-4532-974e-78fd600092d0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1127181793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.1127181793
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3206219334
Short name T743
Test name
Test status
Simulation time 10085617822 ps
CPU time 15.8 seconds
Started May 23 03:39:39 PM PDT 24
Finished May 23 03:40:01 PM PDT 24
Peak memory 204948 kb
Host smart-bc78c5aa-394c-4b59-88ce-919a50d03699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32062
19334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3206219334
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3402440766
Short name T858
Test name
Test status
Simulation time 10240118610 ps
CPU time 14.27 seconds
Started May 23 03:39:48 PM PDT 24
Finished May 23 03:40:10 PM PDT 24
Peak memory 205024 kb
Host smart-2e6cae37-e0f8-432a-a2a9-fd61bba3f018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34024
40766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3402440766
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.677162203
Short name T1450
Test name
Test status
Simulation time 10107569945 ps
CPU time 15.17 seconds
Started May 23 03:40:04 PM PDT 24
Finished May 23 03:40:29 PM PDT 24
Peak memory 204920 kb
Host smart-78ef5c2f-63a2-40c1-81fa-e42352f29100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67716
2203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.677162203
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3828051958
Short name T673
Test name
Test status
Simulation time 10053946020 ps
CPU time 15.1 seconds
Started May 23 03:39:48 PM PDT 24
Finished May 23 03:40:20 PM PDT 24
Peak memory 204912 kb
Host smart-9fa26957-18e7-46e6-b168-f9482e75db8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38280
51958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3828051958
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.543325683
Short name T985
Test name
Test status
Simulation time 10901908253 ps
CPU time 14.49 seconds
Started May 23 03:39:48 PM PDT 24
Finished May 23 03:40:09 PM PDT 24
Peak memory 204916 kb
Host smart-7cb91fc1-aac5-4298-b954-9abff8b1a7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54332
5683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.543325683
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.4161679117
Short name T669
Test name
Test status
Simulation time 10077995401 ps
CPU time 13.57 seconds
Started May 23 03:39:48 PM PDT 24
Finished May 23 03:40:09 PM PDT 24
Peak memory 204912 kb
Host smart-cfefce37-2a44-4e68-b477-28086919af28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41616
79117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.4161679117
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.930731579
Short name T66
Test name
Test status
Simulation time 10095328148 ps
CPU time 13.1 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:10 PM PDT 24
Peak memory 204940 kb
Host smart-25f14e3a-cf6e-4619-889e-081e553e5246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93073
1579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.930731579
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3191924701
Short name T1388
Test name
Test status
Simulation time 10044793201 ps
CPU time 14.98 seconds
Started May 23 03:39:51 PM PDT 24
Finished May 23 03:40:16 PM PDT 24
Peak memory 204952 kb
Host smart-4df3424a-c9f2-4542-a138-f541940b771f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31919
24701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3191924701
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1815830200
Short name T1902
Test name
Test status
Simulation time 10125155605 ps
CPU time 13.55 seconds
Started May 23 03:39:40 PM PDT 24
Finished May 23 03:39:58 PM PDT 24
Peak memory 205008 kb
Host smart-cc681a34-50f5-4aa1-b301-4004e17f1d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18158
30200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1815830200
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1940429614
Short name T594
Test name
Test status
Simulation time 10108716363 ps
CPU time 14.36 seconds
Started May 23 03:39:46 PM PDT 24
Finished May 23 03:40:06 PM PDT 24
Peak memory 204916 kb
Host smart-6653f4d4-b48a-4ff1-be38-1f9655bd9674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19404
29614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1940429614
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1138970601
Short name T466
Test name
Test status
Simulation time 13199124003 ps
CPU time 19.57 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:17 PM PDT 24
Peak memory 204944 kb
Host smart-7de26188-aaf6-4bfc-b12d-da01cc8d2ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11389
70601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1138970601
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.4184334956
Short name T1467
Test name
Test status
Simulation time 10085708566 ps
CPU time 12.99 seconds
Started May 23 03:39:41 PM PDT 24
Finished May 23 03:39:59 PM PDT 24
Peak memory 204884 kb
Host smart-89793b39-ccd4-4539-8b57-3d7e8835948f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41843
34956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.4184334956
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.4293677690
Short name T1588
Test name
Test status
Simulation time 10064017918 ps
CPU time 13.12 seconds
Started May 23 03:39:44 PM PDT 24
Finished May 23 03:40:02 PM PDT 24
Peak memory 204936 kb
Host smart-50245503-b91d-49bc-82e9-b985323ad8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42936
77690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.4293677690
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1073306752
Short name T110
Test name
Test status
Simulation time 10096125006 ps
CPU time 15.05 seconds
Started May 23 03:39:48 PM PDT 24
Finished May 23 03:40:10 PM PDT 24
Peak memory 204976 kb
Host smart-c62e652d-0c86-4093-8f70-881bd7e2314e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10733
06752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1073306752
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2374044856
Short name T1520
Test name
Test status
Simulation time 10091347360 ps
CPU time 13.78 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:10 PM PDT 24
Peak memory 204864 kb
Host smart-b640d5b0-7d6b-45ad-85c5-684d524f0488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23740
44856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2374044856
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3861754906
Short name T1885
Test name
Test status
Simulation time 10065608255 ps
CPU time 13.16 seconds
Started May 23 03:39:53 PM PDT 24
Finished May 23 03:40:17 PM PDT 24
Peak memory 204908 kb
Host smart-5dd1aacf-916c-42d1-9ad1-00eff72f00b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38617
54906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3861754906
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1819281179
Short name T1787
Test name
Test status
Simulation time 10079856528 ps
CPU time 13.25 seconds
Started May 23 03:39:46 PM PDT 24
Finished May 23 03:40:04 PM PDT 24
Peak memory 204940 kb
Host smart-59492dc1-fa57-48c5-b99e-04cacf7d2038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18192
81179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1819281179
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1201419675
Short name T148
Test name
Test status
Simulation time 10070846139 ps
CPU time 15.16 seconds
Started May 23 03:39:47 PM PDT 24
Finished May 23 03:40:08 PM PDT 24
Peak memory 204960 kb
Host smart-fd8a90fa-33cb-4550-8dcb-12dd7c1e1ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12014
19675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1201419675
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.2738771189
Short name T830
Test name
Test status
Simulation time 10066896788 ps
CPU time 13.48 seconds
Started May 23 03:39:50 PM PDT 24
Finished May 23 03:40:11 PM PDT 24
Peak memory 204924 kb
Host smart-81790043-b4d4-403f-a56c-5c8874f7c5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27387
71189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.2738771189
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2552012986
Short name T1505
Test name
Test status
Simulation time 10067084111 ps
CPU time 13.63 seconds
Started May 23 03:39:54 PM PDT 24
Finished May 23 03:40:18 PM PDT 24
Peak memory 204964 kb
Host smart-9bd0a3a7-2d7e-4c14-a074-5f74130d9f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520
12986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2552012986
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1351902674
Short name T1502
Test name
Test status
Simulation time 10069813017 ps
CPU time 14.78 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:12 PM PDT 24
Peak memory 204952 kb
Host smart-fccd33d8-3dc3-4df3-80e7-a6508134147b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519
02674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1351902674
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1923126127
Short name T58
Test name
Test status
Simulation time 27848996088 ps
CPU time 57.31 seconds
Started May 23 03:39:48 PM PDT 24
Finished May 23 03:40:52 PM PDT 24
Peak memory 205028 kb
Host smart-28679aa8-9dfa-49cc-9f8f-aabe1d240d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19231
26127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1923126127
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2364312789
Short name T1244
Test name
Test status
Simulation time 10049997060 ps
CPU time 13.27 seconds
Started May 23 03:39:40 PM PDT 24
Finished May 23 03:39:58 PM PDT 24
Peak memory 205052 kb
Host smart-ff014643-7966-4b95-9d65-dda1c93dd9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23643
12789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2364312789
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1170233594
Short name T528
Test name
Test status
Simulation time 10058047249 ps
CPU time 14.88 seconds
Started May 23 03:39:56 PM PDT 24
Finished May 23 03:40:22 PM PDT 24
Peak memory 205000 kb
Host smart-17af26bd-c918-4705-b7dd-35d8317ba81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11702
33594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1170233594
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.4147196280
Short name T429
Test name
Test status
Simulation time 10070919142 ps
CPU time 13.51 seconds
Started May 23 03:39:50 PM PDT 24
Finished May 23 03:40:12 PM PDT 24
Peak memory 204908 kb
Host smart-7870bf1b-09b9-45f5-a96d-21bf7e2ab264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41471
96280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.4147196280
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2945965936
Short name T1924
Test name
Test status
Simulation time 10080440352 ps
CPU time 15.58 seconds
Started May 23 03:39:53 PM PDT 24
Finished May 23 03:40:19 PM PDT 24
Peak memory 204924 kb
Host smart-e800615f-3296-47b8-b5d1-884b9adb5529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29459
65936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2945965936
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3627240320
Short name T197
Test name
Test status
Simulation time 1145122526 ps
CPU time 1.94 seconds
Started May 23 03:39:46 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 221848 kb
Host smart-0b0f79f3-9219-4cb8-adb4-b1bef24330ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3627240320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3627240320
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3493217752
Short name T1428
Test name
Test status
Simulation time 10108270847 ps
CPU time 14.12 seconds
Started May 23 03:39:56 PM PDT 24
Finished May 23 03:40:21 PM PDT 24
Peak memory 204992 kb
Host smart-41f5386c-1b10-4590-8bfa-84be552d144e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34932
17752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3493217752
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.213424061
Short name T1685
Test name
Test status
Simulation time 10052349794 ps
CPU time 12.72 seconds
Started May 23 03:39:48 PM PDT 24
Finished May 23 03:40:07 PM PDT 24
Peak memory 204964 kb
Host smart-9007e8e3-4d34-4746-a4a0-ec17ec5cb631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21342
4061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.213424061
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.412995329
Short name T1662
Test name
Test status
Simulation time 10122433963 ps
CPU time 13.64 seconds
Started May 23 03:39:39 PM PDT 24
Finished May 23 03:39:58 PM PDT 24
Peak memory 204980 kb
Host smart-bdceb5a8-f102-4b83-8560-854f37242956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41299
5329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.412995329
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1826384056
Short name T883
Test name
Test status
Simulation time 10137070600 ps
CPU time 13.58 seconds
Started May 23 03:39:50 PM PDT 24
Finished May 23 03:40:12 PM PDT 24
Peak memory 204948 kb
Host smart-55e700e2-4cb3-42d6-9d31-01028fd0008e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18263
84056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1826384056
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1578226300
Short name T613
Test name
Test status
Simulation time 10040568840 ps
CPU time 13.82 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:11 PM PDT 24
Peak memory 204940 kb
Host smart-aba56efc-ef46-4cc7-93e3-1aad2cdb18ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15782
26300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1578226300
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.2887888054
Short name T1143
Test name
Test status
Simulation time 10137179729 ps
CPU time 13.74 seconds
Started May 23 03:42:34 PM PDT 24
Finished May 23 03:42:59 PM PDT 24
Peak memory 204976 kb
Host smart-8ff940c9-c59b-473f-94e1-83973ab3e7f0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2887888054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.2887888054
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.2810254430
Short name T1757
Test name
Test status
Simulation time 10082232690 ps
CPU time 15.83 seconds
Started May 23 03:42:30 PM PDT 24
Finished May 23 03:42:54 PM PDT 24
Peak memory 204952 kb
Host smart-915de098-9207-4c46-a0ef-291184bb6918
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2810254430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.2810254430
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.3690035736
Short name T778
Test name
Test status
Simulation time 10169322255 ps
CPU time 12.98 seconds
Started May 23 03:42:34 PM PDT 24
Finished May 23 03:42:59 PM PDT 24
Peak memory 204948 kb
Host smart-06a409e4-dfd9-44b2-9524-105cfb478de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36900
35736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.3690035736
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2840152894
Short name T1217
Test name
Test status
Simulation time 14235706645 ps
CPU time 18.67 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:08 PM PDT 24
Peak memory 204204 kb
Host smart-91301f92-04c0-40f6-8a88-ec76fabefb72
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2840152894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.2840152894
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.81181605
Short name T839
Test name
Test status
Simulation time 13265613211 ps
CPU time 17.01 seconds
Started May 23 03:42:22 PM PDT 24
Finished May 23 03:42:47 PM PDT 24
Peak memory 204984 kb
Host smart-035351e1-da61-4a3e-a9f5-1c65050ca4f4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=81181605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.81181605
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.3483513492
Short name T1633
Test name
Test status
Simulation time 13326179204 ps
CPU time 16.72 seconds
Started May 23 03:42:22 PM PDT 24
Finished May 23 03:42:47 PM PDT 24
Peak memory 204964 kb
Host smart-bbc1274c-2175-4b9d-896c-8a5478bd5bb2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3483513492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.3483513492
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2509079941
Short name T1809
Test name
Test status
Simulation time 10061782944 ps
CPU time 12.67 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204916 kb
Host smart-34d07bb1-5ecb-4d40-9aa9-7589f15d66e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25090
79941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2509079941
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.2038890008
Short name T975
Test name
Test status
Simulation time 10424010567 ps
CPU time 13.74 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204996 kb
Host smart-0108eec5-ad36-4f2b-8dd5-d3bca9e1b499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20388
90008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2038890008
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3858807909
Short name T1359
Test name
Test status
Simulation time 10047987323 ps
CPU time 13.03 seconds
Started May 23 03:42:44 PM PDT 24
Finished May 23 03:43:10 PM PDT 24
Peak memory 204936 kb
Host smart-62f19d6f-cf4d-4c94-9e16-65e7ed899905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38588
07909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3858807909
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.1032587149
Short name T908
Test name
Test status
Simulation time 10051143325 ps
CPU time 12.67 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204960 kb
Host smart-e8136ed2-9e76-4d33-9aa4-61c27400a05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10325
87149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1032587149
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.257091934
Short name T690
Test name
Test status
Simulation time 10214495180 ps
CPU time 14.47 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204936 kb
Host smart-9c111945-12c2-486a-aebb-a36b990ece44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25709
1934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.257091934
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.2784817080
Short name T1771
Test name
Test status
Simulation time 10096177149 ps
CPU time 12.89 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:03 PM PDT 24
Peak memory 204968 kb
Host smart-6a1960cb-b4cc-4e1b-81e1-729a69556745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27848
17080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2784817080
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.48072245
Short name T859
Test name
Test status
Simulation time 10040133121 ps
CPU time 13.17 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 205008 kb
Host smart-089ff63f-bc24-4751-abbb-756014514fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48072
245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.48072245
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1192219613
Short name T598
Test name
Test status
Simulation time 10061099257 ps
CPU time 12.84 seconds
Started May 23 03:42:35 PM PDT 24
Finished May 23 03:42:59 PM PDT 24
Peak memory 204940 kb
Host smart-194be167-1736-4155-870e-abd1f3650350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11922
19613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1192219613
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.3824733306
Short name T1678
Test name
Test status
Simulation time 10064011735 ps
CPU time 14.01 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:02 PM PDT 24
Peak memory 204916 kb
Host smart-b05b38dd-9177-469f-b2bf-008b07dcab70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38247
33306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.3824733306
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3709808384
Short name T1801
Test name
Test status
Simulation time 13209487821 ps
CPU time 16.33 seconds
Started May 23 03:42:40 PM PDT 24
Finished May 23 03:43:11 PM PDT 24
Peak memory 204880 kb
Host smart-96af7117-ee69-4597-8bd4-3bb22a114cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37098
08384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3709808384
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.4255806900
Short name T434
Test name
Test status
Simulation time 10136013894 ps
CPU time 15.78 seconds
Started May 23 03:42:40 PM PDT 24
Finished May 23 03:43:10 PM PDT 24
Peak memory 204916 kb
Host smart-54c725b0-24f3-4062-b240-625d18cc0698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42558
06900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.4255806900
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.228287633
Short name T1541
Test name
Test status
Simulation time 10042087086 ps
CPU time 13.94 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:03 PM PDT 24
Peak memory 204920 kb
Host smart-b16e7f87-c66a-4ff7-b0c7-c9b0680ba49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22828
7633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.228287633
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.2831421478
Short name T1856
Test name
Test status
Simulation time 10155529021 ps
CPU time 15 seconds
Started May 23 03:42:30 PM PDT 24
Finished May 23 03:42:55 PM PDT 24
Peak memory 204968 kb
Host smart-8c741edb-78bf-4e8f-90cb-ed0de8063721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28314
21478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.2831421478
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2277243641
Short name T1675
Test name
Test status
Simulation time 10107775519 ps
CPU time 13.76 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204976 kb
Host smart-c6e88b0d-b308-46f1-8c90-82319cecd9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22772
43641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2277243641
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2524766844
Short name T758
Test name
Test status
Simulation time 10048142328 ps
CPU time 13.13 seconds
Started May 23 03:42:35 PM PDT 24
Finished May 23 03:43:00 PM PDT 24
Peak memory 204944 kb
Host smart-1b8bb548-3110-4b5e-9fe8-fadf93349068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25247
66844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2524766844
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.463973476
Short name T184
Test name
Test status
Simulation time 10083626433 ps
CPU time 14.34 seconds
Started May 23 03:42:46 PM PDT 24
Finished May 23 03:43:14 PM PDT 24
Peak memory 204948 kb
Host smart-89d4391f-61e4-4ae7-a489-a1706a768044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46397
3476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.463973476
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.4043010925
Short name T915
Test name
Test status
Simulation time 10050596466 ps
CPU time 13.45 seconds
Started May 23 03:42:30 PM PDT 24
Finished May 23 03:42:52 PM PDT 24
Peak memory 204972 kb
Host smart-8b15c0d7-28e9-4824-98a0-cd60c0ff6a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40430
10925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.4043010925
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2874500273
Short name T1705
Test name
Test status
Simulation time 10046211280 ps
CPU time 12.55 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:01 PM PDT 24
Peak memory 204884 kb
Host smart-182cb219-cf6c-4bce-bccd-d8b4d66c3ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28745
00273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2874500273
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2105805650
Short name T36
Test name
Test status
Simulation time 20311165912 ps
CPU time 38.95 seconds
Started May 23 03:42:31 PM PDT 24
Finished May 23 03:43:20 PM PDT 24
Peak memory 205028 kb
Host smart-0ec99a07-729a-4649-91f6-da764d40543b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21058
05650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2105805650
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1374836692
Short name T1474
Test name
Test status
Simulation time 10054782175 ps
CPU time 13.24 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:07 PM PDT 24
Peak memory 204912 kb
Host smart-f9a4c68f-b0b6-43be-bccc-538e1bfcc9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13748
36692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1374836692
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.4050771137
Short name T1142
Test name
Test status
Simulation time 10078209284 ps
CPU time 13.24 seconds
Started May 23 03:42:40 PM PDT 24
Finished May 23 03:43:07 PM PDT 24
Peak memory 204916 kb
Host smart-901e092b-29d7-4185-86c2-e56d389b93df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40507
71137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.4050771137
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.4157124352
Short name T868
Test name
Test status
Simulation time 10054114665 ps
CPU time 12.93 seconds
Started May 23 03:42:31 PM PDT 24
Finished May 23 03:42:53 PM PDT 24
Peak memory 204960 kb
Host smart-997331a2-8de2-4619-8e6f-23a1f22f98ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41571
24352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.4157124352
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2099769126
Short name T645
Test name
Test status
Simulation time 10062311829 ps
CPU time 13.8 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:07 PM PDT 24
Peak memory 203884 kb
Host smart-a8fdae34-f0ab-4ed6-a39d-d1a1df02b543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20997
69126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2099769126
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.237187993
Short name T156
Test name
Test status
Simulation time 10101700825 ps
CPU time 12.91 seconds
Started May 23 03:42:34 PM PDT 24
Finished May 23 03:42:58 PM PDT 24
Peak memory 204952 kb
Host smart-2aa846a6-1bd7-4ce0-a363-b269c90d7cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23718
7993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.237187993
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3701247481
Short name T61
Test name
Test status
Simulation time 10062844926 ps
CPU time 15.63 seconds
Started May 23 03:42:30 PM PDT 24
Finished May 23 03:42:55 PM PDT 24
Peak memory 204968 kb
Host smart-24b4a12b-0dce-4f6e-a6ab-b40ad2a189f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37012
47481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3701247481
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1288282182
Short name T1053
Test name
Test status
Simulation time 10135763531 ps
CPU time 13.42 seconds
Started May 23 03:42:34 PM PDT 24
Finished May 23 03:42:59 PM PDT 24
Peak memory 204920 kb
Host smart-545925fd-a7d7-4953-af42-eb9d5ab7cddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12882
82182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1288282182
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3743138045
Short name T687
Test name
Test status
Simulation time 10048451423 ps
CPU time 14.92 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:08 PM PDT 24
Peak memory 205004 kb
Host smart-ff89ddf2-aa1c-4ab9-8f77-61d14376e054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37431
38045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3743138045
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.23001497
Short name T1331
Test name
Test status
Simulation time 10085378951 ps
CPU time 13.66 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204952 kb
Host smart-5963794c-0ce2-484e-a463-db036befe103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23001
497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.23001497
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.1544186887
Short name T660
Test name
Test status
Simulation time 10168072139 ps
CPU time 13.24 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204984 kb
Host smart-a188e929-b803-46a5-be7c-e7c6adda2526
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1544186887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.1544186887
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.1351879805
Short name T1016
Test name
Test status
Simulation time 10056178253 ps
CPU time 14.08 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:07 PM PDT 24
Peak memory 205000 kb
Host smart-46ebcfd5-cc0e-4c18-8397-8b50fac81fa5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1351879805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.1351879805
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.3749704622
Short name T1527
Test name
Test status
Simulation time 10132803677 ps
CPU time 15.6 seconds
Started May 23 03:42:35 PM PDT 24
Finished May 23 03:43:03 PM PDT 24
Peak memory 205004 kb
Host smart-a7eefb50-bf64-4813-9a97-6568ebc8f31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37497
04622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.3749704622
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1596861640
Short name T1403
Test name
Test status
Simulation time 13889724148 ps
CPU time 16.48 seconds
Started May 23 03:42:30 PM PDT 24
Finished May 23 03:42:55 PM PDT 24
Peak memory 204936 kb
Host smart-d118a903-5b4b-4929-b5be-f29a1a7a40a7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1596861640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.1596861640
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.4157023023
Short name T39
Test name
Test status
Simulation time 13275029547 ps
CPU time 15.44 seconds
Started May 23 03:42:34 PM PDT 24
Finished May 23 03:43:00 PM PDT 24
Peak memory 204972 kb
Host smart-4b8f7e8d-890d-4832-b04a-e76dc6dc6e65
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4157023023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.4157023023
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2269128971
Short name T1363
Test name
Test status
Simulation time 13247217219 ps
CPU time 16.43 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204936 kb
Host smart-05970688-8580-471f-9fe8-f27c5b26cc06
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2269128971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.2269128971
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.900816826
Short name T692
Test name
Test status
Simulation time 10064994888 ps
CPU time 15.99 seconds
Started May 23 03:42:24 PM PDT 24
Finished May 23 03:42:47 PM PDT 24
Peak memory 204988 kb
Host smart-32112c2d-1f32-48d0-8924-0aa637ce2c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90081
6826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.900816826
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3607434440
Short name T918
Test name
Test status
Simulation time 10851019105 ps
CPU time 14.58 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 205004 kb
Host smart-a56bda52-d76b-4efd-9977-eed5078df996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36074
34440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3607434440
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.462690907
Short name T404
Test name
Test status
Simulation time 10042084270 ps
CPU time 13.24 seconds
Started May 23 03:42:34 PM PDT 24
Finished May 23 03:43:00 PM PDT 24
Peak memory 204932 kb
Host smart-bb6df56b-e0cb-42a6-8822-59f807edc090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46269
0907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.462690907
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.4103573047
Short name T1760
Test name
Test status
Simulation time 10047831910 ps
CPU time 13.7 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204892 kb
Host smart-a537acd6-24b9-4076-b235-6dcbdf5caea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41035
73047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.4103573047
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3823348575
Short name T95
Test name
Test status
Simulation time 10837405777 ps
CPU time 15.74 seconds
Started May 23 03:42:31 PM PDT 24
Finished May 23 03:42:57 PM PDT 24
Peak memory 204948 kb
Host smart-0442970d-7aab-4901-83e5-6e986638127e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38233
48575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3823348575
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.26633409
Short name T1002
Test name
Test status
Simulation time 10195664143 ps
CPU time 14.8 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204912 kb
Host smart-8e1d380e-9390-4dd9-a083-a384ac06f2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26633
409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.26633409
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1625915713
Short name T1120
Test name
Test status
Simulation time 10108033999 ps
CPU time 12.44 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:01 PM PDT 24
Peak memory 204936 kb
Host smart-8d29109a-f5ac-4fe1-b30b-454dc4db508c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16259
15713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1625915713
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.4241997569
Short name T998
Test name
Test status
Simulation time 10055084452 ps
CPU time 12.95 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204952 kb
Host smart-431f6ea2-4ffc-4ed3-8c98-9c3047c49a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42419
97569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.4241997569
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2302261165
Short name T730
Test name
Test status
Simulation time 10128118317 ps
CPU time 12.99 seconds
Started May 23 03:42:30 PM PDT 24
Finished May 23 03:42:51 PM PDT 24
Peak memory 204932 kb
Host smart-31804d2d-8b1c-483a-817f-ed29d8e005d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23022
61165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2302261165
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1214564581
Short name T553
Test name
Test status
Simulation time 10088327269 ps
CPU time 13.47 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:07 PM PDT 24
Peak memory 204916 kb
Host smart-de243060-a5a8-4ac9-a805-0d31d2ac9d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12145
64581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1214564581
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3244489122
Short name T1619
Test name
Test status
Simulation time 13237147265 ps
CPU time 17.54 seconds
Started May 23 03:42:40 PM PDT 24
Finished May 23 03:43:12 PM PDT 24
Peak memory 204904 kb
Host smart-dfb45567-5ace-41d7-8d3c-3278a1eacca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32444
89122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3244489122
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.616923991
Short name T228
Test name
Test status
Simulation time 10117492029 ps
CPU time 12.5 seconds
Started May 23 03:42:32 PM PDT 24
Finished May 23 03:42:55 PM PDT 24
Peak memory 204932 kb
Host smart-15c6b6a5-8447-4755-a8a5-88e36af7a5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61692
3991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.616923991
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.114484765
Short name T944
Test name
Test status
Simulation time 10055805095 ps
CPU time 12.82 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:03 PM PDT 24
Peak memory 204920 kb
Host smart-c92e7de0-c9b7-4d1e-a112-bdbe9493ae7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11448
4765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.114484765
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.510539745
Short name T129
Test name
Test status
Simulation time 10108193385 ps
CPU time 14.76 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204932 kb
Host smart-1ccda056-2b5d-4fb4-a419-bca03b01c1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51053
9745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.510539745
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.819719740
Short name T662
Test name
Test status
Simulation time 10112882828 ps
CPU time 15.3 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:09 PM PDT 24
Peak memory 204912 kb
Host smart-030d221c-6968-45b2-876b-64f3ded1ea47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81971
9740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.819719740
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1165980171
Short name T1318
Test name
Test status
Simulation time 10103213008 ps
CPU time 13.49 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:07 PM PDT 24
Peak memory 204944 kb
Host smart-1fddedee-1948-4199-864e-9b67977651c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11659
80171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1165980171
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2946078651
Short name T590
Test name
Test status
Simulation time 10064591228 ps
CPU time 14.22 seconds
Started May 23 03:42:35 PM PDT 24
Finished May 23 03:43:01 PM PDT 24
Peak memory 204888 kb
Host smart-d8450296-0a68-415e-bb61-f8e415f17d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29460
78651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2946078651
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.2229041194
Short name T219
Test name
Test status
Simulation time 10049741896 ps
CPU time 13.07 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204972 kb
Host smart-c33c1336-6400-4ff1-8682-2cb3c617fc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22290
41194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.2229041194
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1848491499
Short name T1075
Test name
Test status
Simulation time 10049668450 ps
CPU time 13.37 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 203828 kb
Host smart-30993bb2-8c68-44b5-b65e-3ee0c4f3609e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18484
91499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1848491499
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2643905398
Short name T1880
Test name
Test status
Simulation time 10070660930 ps
CPU time 15.5 seconds
Started May 23 03:42:42 PM PDT 24
Finished May 23 03:43:11 PM PDT 24
Peak memory 204936 kb
Host smart-b516ec79-512a-4e5d-a803-78d5084f5129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26439
05398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2643905398
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3765224842
Short name T1727
Test name
Test status
Simulation time 27028958466 ps
CPU time 48.38 seconds
Started May 23 03:42:40 PM PDT 24
Finished May 23 03:43:42 PM PDT 24
Peak memory 204960 kb
Host smart-5cdf33f2-edf8-4b30-b036-096ac20b6d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37652
24842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3765224842
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.929850167
Short name T1088
Test name
Test status
Simulation time 10120272873 ps
CPU time 13.58 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:03 PM PDT 24
Peak memory 204984 kb
Host smart-92f2d1a9-e0cf-4bdb-80c0-f9bd334c1e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92985
0167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.929850167
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.298295489
Short name T1785
Test name
Test status
Simulation time 10086676506 ps
CPU time 13.43 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204960 kb
Host smart-762f3dee-eeae-43f5-a8fd-a2bbe91bbc4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29829
5489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.298295489
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.1361410646
Short name T1093
Test name
Test status
Simulation time 10075076116 ps
CPU time 14.11 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204948 kb
Host smart-66f2e3ec-20cb-4dd0-8e05-4aa24cef874c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13614
10646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.1361410646
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.1394104403
Short name T1647
Test name
Test status
Simulation time 10051666635 ps
CPU time 12.87 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204940 kb
Host smart-467c9512-2c23-43a4-a8f9-d470b08f76d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13941
04403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.1394104403
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1413657606
Short name T1792
Test name
Test status
Simulation time 10078695215 ps
CPU time 12.61 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204980 kb
Host smart-abcaef7a-ef9b-4f68-b580-8401d8c27e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14136
57606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1413657606
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1145997555
Short name T1731
Test name
Test status
Simulation time 10131063469 ps
CPU time 13.03 seconds
Started May 23 03:42:40 PM PDT 24
Finished May 23 03:43:07 PM PDT 24
Peak memory 204952 kb
Host smart-e174dc0f-4ac5-45e6-ba6b-c16df637f451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11459
97555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1145997555
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3835385950
Short name T1416
Test name
Test status
Simulation time 10120530296 ps
CPU time 13.97 seconds
Started May 23 03:42:35 PM PDT 24
Finished May 23 03:43:02 PM PDT 24
Peak memory 204904 kb
Host smart-81947832-ac0b-479c-a19b-92779be9b83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38353
85950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3835385950
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2805573821
Short name T1479
Test name
Test status
Simulation time 10080783308 ps
CPU time 13.62 seconds
Started May 23 03:42:35 PM PDT 24
Finished May 23 03:43:01 PM PDT 24
Peak memory 204968 kb
Host smart-ff21e903-1809-487a-b9f0-4ca994619d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28055
73821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2805573821
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.3633394992
Short name T408
Test name
Test status
Simulation time 10139307338 ps
CPU time 15.63 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:19 PM PDT 24
Peak memory 204932 kb
Host smart-fe09336d-c043-46af-b3a9-23b04922652a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3633394992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.3633394992
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.3156199853
Short name T1810
Test name
Test status
Simulation time 10098778134 ps
CPU time 12.87 seconds
Started May 23 03:42:46 PM PDT 24
Finished May 23 03:43:12 PM PDT 24
Peak memory 204836 kb
Host smart-d639aac7-022c-4a40-8346-b56e6b1f25b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3156199853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.3156199853
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.1954819599
Short name T1650
Test name
Test status
Simulation time 10126854133 ps
CPU time 14.12 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:17 PM PDT 24
Peak memory 204984 kb
Host smart-275fe023-6f78-4ef1-938d-cc5b1dc8b7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19548
19599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.1954819599
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2444368046
Short name T712
Test name
Test status
Simulation time 13417087654 ps
CPU time 19.19 seconds
Started May 23 03:42:42 PM PDT 24
Finished May 23 03:43:15 PM PDT 24
Peak memory 204844 kb
Host smart-59c27a6f-cc80-48af-a06e-6f6089859c38
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2444368046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.2444368046
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3947856400
Short name T1071
Test name
Test status
Simulation time 13228315735 ps
CPU time 15.93 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:19 PM PDT 24
Peak memory 204972 kb
Host smart-f08d4765-ba59-4173-8de0-a4b48cd20f89
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3947856400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3947856400
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.1124668095
Short name T749
Test name
Test status
Simulation time 13221244363 ps
CPU time 15.15 seconds
Started May 23 03:42:43 PM PDT 24
Finished May 23 03:43:11 PM PDT 24
Peak memory 204988 kb
Host smart-26b291db-2a78-474c-b28c-2493d4cc82fa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1124668095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.1124668095
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3215361359
Short name T1620
Test name
Test status
Simulation time 10053725299 ps
CPU time 15.26 seconds
Started May 23 03:42:45 PM PDT 24
Finished May 23 03:43:13 PM PDT 24
Peak memory 204940 kb
Host smart-930b1080-ead3-420d-b887-3b0ea172e620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32153
61359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3215361359
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.571808418
Short name T1707
Test name
Test status
Simulation time 10993698939 ps
CPU time 15.57 seconds
Started May 23 03:42:30 PM PDT 24
Finished May 23 03:42:55 PM PDT 24
Peak memory 204932 kb
Host smart-d6445734-674f-42ce-8907-2c821aad2a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57180
8418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.571808418
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.2041147125
Short name T1722
Test name
Test status
Simulation time 10077246761 ps
CPU time 13.02 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:03 PM PDT 24
Peak memory 204956 kb
Host smart-4dedf536-223d-491c-acd6-fdee368e58eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20411
47125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2041147125
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.322252660
Short name T1511
Test name
Test status
Simulation time 10057525428 ps
CPU time 13.98 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:06 PM PDT 24
Peak memory 204956 kb
Host smart-7ed61c08-abcb-410f-a837-ee2ec4a414e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32225
2660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.322252660
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2462030433
Short name T615
Test name
Test status
Simulation time 10169358196 ps
CPU time 14.39 seconds
Started May 23 03:42:40 PM PDT 24
Finished May 23 03:43:09 PM PDT 24
Peak memory 204988 kb
Host smart-ba610359-ff4e-4feb-9ea4-c8e44e8813c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24620
30433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2462030433
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3551658035
Short name T1868
Test name
Test status
Simulation time 10047255750 ps
CPU time 14.92 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:05 PM PDT 24
Peak memory 204972 kb
Host smart-7f9d280f-4a95-48dc-9ea2-1af07414b8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35516
58035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3551658035
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.4178142209
Short name T1358
Test name
Test status
Simulation time 10114148943 ps
CPU time 14.22 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:08 PM PDT 24
Peak memory 205036 kb
Host smart-2d735043-0706-4e24-a7fb-7a8c7ef40897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41781
42209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.4178142209
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.3747866586
Short name T534
Test name
Test status
Simulation time 10095646812 ps
CPU time 13.33 seconds
Started May 23 03:42:42 PM PDT 24
Finished May 23 03:43:09 PM PDT 24
Peak memory 205000 kb
Host smart-bb6d07a1-547d-49b0-8d67-e94f1665eefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37478
66586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.3747866586
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3945155530
Short name T1406
Test name
Test status
Simulation time 13232326708 ps
CPU time 18.43 seconds
Started May 23 03:42:43 PM PDT 24
Finished May 23 03:43:15 PM PDT 24
Peak memory 204924 kb
Host smart-3b19d146-603e-4915-bb78-a018c4ac3239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39451
55530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3945155530
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.509341358
Short name T943
Test name
Test status
Simulation time 10088218426 ps
CPU time 13.56 seconds
Started May 23 03:42:40 PM PDT 24
Finished May 23 03:43:07 PM PDT 24
Peak memory 205008 kb
Host smart-2e003b12-4944-493f-a1d0-10d1c3dd43f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50934
1358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.509341358
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2307228111
Short name T876
Test name
Test status
Simulation time 10054435591 ps
CPU time 14.9 seconds
Started May 23 03:42:47 PM PDT 24
Finished May 23 03:43:15 PM PDT 24
Peak memory 204964 kb
Host smart-ee55b2a4-f4d7-404c-a3d4-ddc6e9e7af7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23072
28111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2307228111
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2853989222
Short name T1319
Test name
Test status
Simulation time 10089305028 ps
CPU time 13.26 seconds
Started May 23 03:42:39 PM PDT 24
Finished May 23 03:43:07 PM PDT 24
Peak memory 205012 kb
Host smart-8e98ff86-bc2a-4133-8eda-0371a4ec4cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28539
89222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2853989222
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1501130324
Short name T1334
Test name
Test status
Simulation time 10105132205 ps
CPU time 12.99 seconds
Started May 23 03:42:30 PM PDT 24
Finished May 23 03:42:52 PM PDT 24
Peak memory 204956 kb
Host smart-f243d908-61dd-49f8-a919-28a02b6d2105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15011
30324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1501130324
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1517896946
Short name T1461
Test name
Test status
Simulation time 10088319720 ps
CPU time 12.94 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:02 PM PDT 24
Peak memory 204952 kb
Host smart-122a4f09-5c6f-443b-a033-40bb56e392e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15178
96946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1517896946
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1965528413
Short name T1708
Test name
Test status
Simulation time 10079317547 ps
CPU time 14.84 seconds
Started May 23 03:42:42 PM PDT 24
Finished May 23 03:43:11 PM PDT 24
Peak memory 204920 kb
Host smart-82ece085-9bcf-46d3-b26b-cade3934a3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19655
28413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1965528413
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.4171931742
Short name T165
Test name
Test status
Simulation time 10101371169 ps
CPU time 12.83 seconds
Started May 23 03:42:46 PM PDT 24
Finished May 23 03:43:12 PM PDT 24
Peak memory 204988 kb
Host smart-506cd2a0-5d48-4128-bb0f-d180f84349f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41719
31742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.4171931742
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.161765237
Short name T822
Test name
Test status
Simulation time 10083611154 ps
CPU time 12.13 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:02 PM PDT 24
Peak memory 204992 kb
Host smart-5b51a60f-3447-4cbe-a3dc-8501786a3ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16176
5237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.161765237
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1802212340
Short name T1614
Test name
Test status
Simulation time 10045720500 ps
CPU time 13.89 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204952 kb
Host smart-7c2061a5-3ab9-4179-9240-372aa63fae99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18022
12340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1802212340
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2720879528
Short name T623
Test name
Test status
Simulation time 10034561452 ps
CPU time 12.56 seconds
Started May 23 03:42:45 PM PDT 24
Finished May 23 03:43:10 PM PDT 24
Peak memory 204992 kb
Host smart-8bf05042-6e24-4d5f-9268-d5bb623c9fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27208
79528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2720879528
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3308361419
Short name T1884
Test name
Test status
Simulation time 18003017931 ps
CPU time 29.83 seconds
Started May 23 03:42:34 PM PDT 24
Finished May 23 03:43:15 PM PDT 24
Peak memory 204956 kb
Host smart-4b92a07c-b8ff-4fac-af8b-57e64a8560c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33083
61419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3308361419
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3911659021
Short name T491
Test name
Test status
Simulation time 10067006744 ps
CPU time 12.44 seconds
Started May 23 03:42:27 PM PDT 24
Finished May 23 03:42:48 PM PDT 24
Peak memory 205000 kb
Host smart-a846b411-e9bb-4194-a7d8-b58115e699c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39116
59021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3911659021
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1116395654
Short name T1909
Test name
Test status
Simulation time 10128799016 ps
CPU time 13.66 seconds
Started May 23 03:42:43 PM PDT 24
Finished May 23 03:43:10 PM PDT 24
Peak memory 204984 kb
Host smart-2f6966da-8695-4c82-aafb-0df1b64acfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11163
95654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1116395654
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.1767848951
Short name T902
Test name
Test status
Simulation time 10081202359 ps
CPU time 12.98 seconds
Started May 23 03:42:38 PM PDT 24
Finished May 23 03:43:04 PM PDT 24
Peak memory 204960 kb
Host smart-9c65fa82-94c2-4ea2-98b7-c77682af5fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17678
48951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.1767848951
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3691995116
Short name T1201
Test name
Test status
Simulation time 10057859490 ps
CPU time 14.11 seconds
Started May 23 03:42:36 PM PDT 24
Finished May 23 03:43:03 PM PDT 24
Peak memory 204932 kb
Host smart-5aaaae18-f3fb-48d2-9c52-4fe2d8907c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36919
95116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3691995116
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3494240482
Short name T1498
Test name
Test status
Simulation time 10052888544 ps
CPU time 13.58 seconds
Started May 23 03:42:31 PM PDT 24
Finished May 23 03:42:55 PM PDT 24
Peak memory 205000 kb
Host smart-25985a6f-8e03-4d48-b028-3b437e5c4458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34942
40482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3494240482
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2244732864
Short name T381
Test name
Test status
Simulation time 10053621041 ps
CPU time 12.65 seconds
Started May 23 03:42:41 PM PDT 24
Finished May 23 03:43:07 PM PDT 24
Peak memory 204956 kb
Host smart-6e2cfe0a-bba6-4dc9-a3e5-68b58d0e2706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22447
32864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2244732864
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2403641251
Short name T1220
Test name
Test status
Simulation time 10125579736 ps
CPU time 12.83 seconds
Started May 23 03:42:37 PM PDT 24
Finished May 23 03:43:03 PM PDT 24
Peak memory 204976 kb
Host smart-27fd8c5a-fc4c-4e6d-b789-86022dd1cd3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24036
41251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2403641251
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1447312962
Short name T86
Test name
Test status
Simulation time 10052610481 ps
CPU time 12.75 seconds
Started May 23 03:42:35 PM PDT 24
Finished May 23 03:43:00 PM PDT 24
Peak memory 204956 kb
Host smart-5f3b5378-7a5d-4f3e-be56-77194cee1de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14473
12962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1447312962
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3441805133
Short name T1352
Test name
Test status
Simulation time 10059611924 ps
CPU time 14.56 seconds
Started May 23 03:42:35 PM PDT 24
Finished May 23 03:43:02 PM PDT 24
Peak memory 204964 kb
Host smart-9d9baf81-9b1b-4223-bb5c-e804ca1f5490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34418
05133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3441805133
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.1680678872
Short name T1427
Test name
Test status
Simulation time 10146193501 ps
CPU time 13.56 seconds
Started May 23 03:42:51 PM PDT 24
Finished May 23 03:43:18 PM PDT 24
Peak memory 204960 kb
Host smart-8057c507-49e8-4bec-8d77-88b41f22d7e9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1680678872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.1680678872
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.329468709
Short name T1172
Test name
Test status
Simulation time 10053278257 ps
CPU time 13.81 seconds
Started May 23 03:42:50 PM PDT 24
Finished May 23 03:43:18 PM PDT 24
Peak memory 204996 kb
Host smart-4b1e12fc-aee6-474e-8b07-d8a79de9a4d2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=329468709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.329468709
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.1565262886
Short name T1285
Test name
Test status
Simulation time 10179149683 ps
CPU time 14.76 seconds
Started May 23 03:42:53 PM PDT 24
Finished May 23 03:43:22 PM PDT 24
Peak memory 204928 kb
Host smart-0bd1ad47-f808-4920-813e-8d10db2bb53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15652
62886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.1565262886
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1452548978
Short name T6
Test name
Test status
Simulation time 13273331380 ps
CPU time 16.35 seconds
Started May 23 03:42:50 PM PDT 24
Finished May 23 03:43:20 PM PDT 24
Peak memory 204960 kb
Host smart-83b7d77b-7d68-47bd-ae17-7062e5764321
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1452548978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1452548978
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.1184133426
Short name T40
Test name
Test status
Simulation time 13246340236 ps
CPU time 18.94 seconds
Started May 23 03:42:54 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204984 kb
Host smart-57ab4cb8-0194-4fa5-89f8-6fe887501faa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1184133426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.1184133426
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2656920751
Short name T537
Test name
Test status
Simulation time 13329812822 ps
CPU time 19.55 seconds
Started May 23 03:42:50 PM PDT 24
Finished May 23 03:43:30 PM PDT 24
Peak memory 204976 kb
Host smart-0b51a5fb-0b0b-4659-a7ca-089755ecf36f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2656920751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.2656920751
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.4094940816
Short name T1544
Test name
Test status
Simulation time 10079391767 ps
CPU time 14.15 seconds
Started May 23 03:42:48 PM PDT 24
Finished May 23 03:43:16 PM PDT 24
Peak memory 204932 kb
Host smart-46d99515-1c52-4e0f-84db-8f76992580f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40949
40816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.4094940816
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2633105244
Short name T51
Test name
Test status
Simulation time 10075674223 ps
CPU time 14 seconds
Started May 23 03:42:54 PM PDT 24
Finished May 23 03:43:22 PM PDT 24
Peak memory 204924 kb
Host smart-1d2d7e0c-7440-4762-9c10-2b469c065429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26331
05244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2633105244
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3867546518
Short name T791
Test name
Test status
Simulation time 10227519583 ps
CPU time 12.95 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:16 PM PDT 24
Peak memory 204984 kb
Host smart-19f32db9-db81-4b3d-9eb1-861ef1ed6f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38675
46518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3867546518
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.129694240
Short name T533
Test name
Test status
Simulation time 10067641288 ps
CPU time 15.58 seconds
Started May 23 03:42:51 PM PDT 24
Finished May 23 03:43:20 PM PDT 24
Peak memory 204980 kb
Host smart-23a9bd32-0d81-4aa1-ac71-2ce28ee618fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12969
4240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.129694240
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2054221791
Short name T1793
Test name
Test status
Simulation time 10053696590 ps
CPU time 12.95 seconds
Started May 23 03:42:48 PM PDT 24
Finished May 23 03:43:15 PM PDT 24
Peak memory 204984 kb
Host smart-1fba2c7b-0c6e-4f98-8670-58caca8d076f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20542
21791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2054221791
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.4232618517
Short name T444
Test name
Test status
Simulation time 10798200600 ps
CPU time 16.7 seconds
Started May 23 03:42:47 PM PDT 24
Finished May 23 03:43:17 PM PDT 24
Peak memory 204940 kb
Host smart-6da3be7d-2d84-4555-b94b-e71be0c3e8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42326
18517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.4232618517
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2469924726
Short name T1166
Test name
Test status
Simulation time 10150977572 ps
CPU time 16.81 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:20 PM PDT 24
Peak memory 204960 kb
Host smart-eb004c1c-f6ab-4fbb-a814-24450b78d8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24699
24726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2469924726
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2549530263
Short name T229
Test name
Test status
Simulation time 10156564059 ps
CPU time 12.79 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:16 PM PDT 24
Peak memory 204904 kb
Host smart-8af15a7b-a72f-4635-ab99-7a8f406df093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25495
30263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2549530263
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2120131345
Short name T652
Test name
Test status
Simulation time 10062465484 ps
CPU time 15.1 seconds
Started May 23 03:42:57 PM PDT 24
Finished May 23 03:43:26 PM PDT 24
Peak memory 204984 kb
Host smart-870c2876-a22e-402d-9f63-146d96836efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21201
31345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2120131345
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2699267656
Short name T1036
Test name
Test status
Simulation time 10116423713 ps
CPU time 14.07 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:17 PM PDT 24
Peak memory 204872 kb
Host smart-5c57d812-4c27-43db-8e39-85bfa3060cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26992
67656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2699267656
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.1164636983
Short name T938
Test name
Test status
Simulation time 10091546195 ps
CPU time 14.07 seconds
Started May 23 03:42:55 PM PDT 24
Finished May 23 03:43:24 PM PDT 24
Peak memory 204964 kb
Host smart-89299349-40fe-4850-b9b1-36464586e58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11646
36983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.1164636983
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1359176407
Short name T1085
Test name
Test status
Simulation time 13162922388 ps
CPU time 18.14 seconds
Started May 23 03:42:51 PM PDT 24
Finished May 23 03:43:23 PM PDT 24
Peak memory 204968 kb
Host smart-cc32c0e1-ca2f-49a7-9bca-7840789110c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13591
76407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1359176407
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1082840238
Short name T815
Test name
Test status
Simulation time 10097955323 ps
CPU time 13.12 seconds
Started May 23 03:42:48 PM PDT 24
Finished May 23 03:43:15 PM PDT 24
Peak memory 204968 kb
Host smart-7c4809a8-7216-49fd-b027-fa1a9e7554e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10828
40238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1082840238
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1499041981
Short name T1858
Test name
Test status
Simulation time 10042965888 ps
CPU time 14.47 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:20 PM PDT 24
Peak memory 204932 kb
Host smart-28762025-24c2-45b4-8ad1-2210695214cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14990
41981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1499041981
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.859672359
Short name T74
Test name
Test status
Simulation time 10094976801 ps
CPU time 14.38 seconds
Started May 23 03:42:55 PM PDT 24
Finished May 23 03:43:24 PM PDT 24
Peak memory 204972 kb
Host smart-f5fd42e6-d270-4e51-ab5b-0f9d3667d581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85967
2359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.859672359
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1530592766
Short name T1640
Test name
Test status
Simulation time 10082182722 ps
CPU time 12.73 seconds
Started May 23 03:42:50 PM PDT 24
Finished May 23 03:43:16 PM PDT 24
Peak memory 204952 kb
Host smart-eb7c3d3f-6bc5-42a2-97fd-b20ab03cd9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15305
92766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1530592766
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2114659684
Short name T1468
Test name
Test status
Simulation time 10105797638 ps
CPU time 14.06 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:20 PM PDT 24
Peak memory 204996 kb
Host smart-dc774971-12fd-44e1-9108-9c4f9eac0a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21146
59684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2114659684
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.4093747378
Short name T1887
Test name
Test status
Simulation time 10071470492 ps
CPU time 15.05 seconds
Started May 23 03:42:50 PM PDT 24
Finished May 23 03:43:18 PM PDT 24
Peak memory 204976 kb
Host smart-447cac26-c6ae-4b52-91d3-031d8fa825e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40937
47378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.4093747378
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1282023986
Short name T715
Test name
Test status
Simulation time 10040048910 ps
CPU time 13.49 seconds
Started May 23 03:42:53 PM PDT 24
Finished May 23 03:43:20 PM PDT 24
Peak memory 204992 kb
Host smart-09683792-55c9-4f6e-b73d-3497dd1ad9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12820
23986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1282023986
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3857827909
Short name T1341
Test name
Test status
Simulation time 10043777309 ps
CPU time 14.58 seconds
Started May 23 03:42:48 PM PDT 24
Finished May 23 03:43:17 PM PDT 24
Peak memory 204876 kb
Host smart-2395600e-481e-45c2-8c44-8ac298597e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38578
27909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3857827909
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1809391980
Short name T183
Test name
Test status
Simulation time 17349945201 ps
CPU time 29.04 seconds
Started May 23 03:42:57 PM PDT 24
Finished May 23 03:43:40 PM PDT 24
Peak memory 205036 kb
Host smart-d92ce97d-f0d0-48a5-802f-299f07b092ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18093
91980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1809391980
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2588292620
Short name T1022
Test name
Test status
Simulation time 10075790375 ps
CPU time 13.67 seconds
Started May 23 03:42:50 PM PDT 24
Finished May 23 03:43:17 PM PDT 24
Peak memory 204940 kb
Host smart-d1b289d5-acb3-44c6-b4a7-1e9152090171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25882
92620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2588292620
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1570108031
Short name T917
Test name
Test status
Simulation time 10066311230 ps
CPU time 13.21 seconds
Started May 23 03:42:53 PM PDT 24
Finished May 23 03:43:20 PM PDT 24
Peak memory 204880 kb
Host smart-df2dfb5b-cb7a-4d06-b639-0d86942b8ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15701
08031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1570108031
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.3868168505
Short name T471
Test name
Test status
Simulation time 10096893455 ps
CPU time 13.39 seconds
Started May 23 03:42:48 PM PDT 24
Finished May 23 03:43:15 PM PDT 24
Peak memory 204960 kb
Host smart-ad3d704d-e2c1-43f1-b3df-cce58d9a0729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38681
68505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.3868168505
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.3777262592
Short name T1913
Test name
Test status
Simulation time 10088325046 ps
CPU time 12.71 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:19 PM PDT 24
Peak memory 204968 kb
Host smart-0a17e212-060e-4a30-8e81-d90e168fb522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37772
62592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.3777262592
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2244635442
Short name T1854
Test name
Test status
Simulation time 10052720414 ps
CPU time 12.95 seconds
Started May 23 03:42:50 PM PDT 24
Finished May 23 03:43:16 PM PDT 24
Peak memory 204936 kb
Host smart-1bf8645b-40f6-4a44-8839-583e611403cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22446
35442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2244635442
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.680501092
Short name T1574
Test name
Test status
Simulation time 10074590686 ps
CPU time 13.94 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:26 PM PDT 24
Peak memory 204944 kb
Host smart-1d80e1c8-b489-4d57-9bdd-86985a4493e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68050
1092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.680501092
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3940613039
Short name T1806
Test name
Test status
Simulation time 10117920358 ps
CPU time 13.04 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:16 PM PDT 24
Peak memory 204920 kb
Host smart-c9bd3403-b497-4436-a7f9-b72eb946cabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39406
13039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3940613039
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1215544183
Short name T1590
Test name
Test status
Simulation time 10082579970 ps
CPU time 12.84 seconds
Started May 23 03:42:55 PM PDT 24
Finished May 23 03:43:23 PM PDT 24
Peak memory 204928 kb
Host smart-e2ee1ec4-d276-448b-8541-10b90aa3dae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12155
44183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1215544183
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3409015799
Short name T1438
Test name
Test status
Simulation time 10091489628 ps
CPU time 13.79 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:19 PM PDT 24
Peak memory 204916 kb
Host smart-d26c48f5-01a1-478f-b7af-c3120a4cee54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34090
15799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3409015799
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.171106950
Short name T1684
Test name
Test status
Simulation time 10168424320 ps
CPU time 14.06 seconds
Started May 23 03:42:53 PM PDT 24
Finished May 23 03:43:21 PM PDT 24
Peak memory 204956 kb
Host smart-b0bcd61a-7ed2-4471-800c-c7d140e9b39b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=171106950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.171106950
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.62041670
Short name T1631
Test name
Test status
Simulation time 10054536253 ps
CPU time 12.57 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:25 PM PDT 24
Peak memory 204920 kb
Host smart-17c6f478-02b5-4a97-8d69-97b3fae36b4a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=62041670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.62041670
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.1201220099
Short name T1349
Test name
Test status
Simulation time 10076219641 ps
CPU time 12.95 seconds
Started May 23 03:42:57 PM PDT 24
Finished May 23 03:43:24 PM PDT 24
Peak memory 204924 kb
Host smart-c72cf518-337b-4625-a1da-9a1264b80e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12012
20099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.1201220099
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1954618909
Short name T1241
Test name
Test status
Simulation time 13738820121 ps
CPU time 16.84 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:19 PM PDT 24
Peak memory 204912 kb
Host smart-d5425f11-af87-4e07-a80f-24dec6d11440
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1954618909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1954618909
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.580370050
Short name T1478
Test name
Test status
Simulation time 13292600956 ps
CPU time 19.3 seconds
Started May 23 03:42:56 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 204924 kb
Host smart-d02fe897-f60e-4812-bfd4-b28aa0fe24a3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=580370050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.580370050
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.61262464
Short name T374
Test name
Test status
Simulation time 13211420676 ps
CPU time 16.71 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 204908 kb
Host smart-e69b6e32-09a9-4b16-bde2-b75e98f32407
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=61262464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.61262464
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3040036805
Short name T860
Test name
Test status
Simulation time 10061028014 ps
CPU time 13.12 seconds
Started May 23 03:42:46 PM PDT 24
Finished May 23 03:43:12 PM PDT 24
Peak memory 204884 kb
Host smart-8f3dec46-45e2-493e-8953-2c82b9ef9044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30400
36805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3040036805
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3180722791
Short name T896
Test name
Test status
Simulation time 10475856628 ps
CPU time 14.54 seconds
Started May 23 03:42:51 PM PDT 24
Finished May 23 03:43:19 PM PDT 24
Peak memory 204984 kb
Host smart-7e40786d-0837-479a-a35a-7c433cd02ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31807
22791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3180722791
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2894446729
Short name T1196
Test name
Test status
Simulation time 10042091652 ps
CPU time 15.93 seconds
Started May 23 03:42:57 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204936 kb
Host smart-b312b3e3-97ff-43e7-a127-9ec89b728aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28944
46729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2894446729
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.2830993955
Short name T1694
Test name
Test status
Simulation time 10057135259 ps
CPU time 13.57 seconds
Started May 23 03:42:46 PM PDT 24
Finished May 23 03:43:13 PM PDT 24
Peak memory 205016 kb
Host smart-679f6210-7a04-4665-97c3-813333b7669f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28309
93955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2830993955
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3202720264
Short name T1838
Test name
Test status
Simulation time 10909405770 ps
CPU time 14.76 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:18 PM PDT 24
Peak memory 204972 kb
Host smart-ba7ef82b-a762-4dd4-8723-b6146f728627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32027
20264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3202720264
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3582689504
Short name T217
Test name
Test status
Simulation time 10219906006 ps
CPU time 15.23 seconds
Started May 23 03:42:46 PM PDT 24
Finished May 23 03:43:15 PM PDT 24
Peak memory 204940 kb
Host smart-44adc3f8-32b8-4c1e-9446-77cea8806428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35826
89504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3582689504
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2827334506
Short name T968
Test name
Test status
Simulation time 10109032486 ps
CPU time 14.03 seconds
Started May 23 03:42:48 PM PDT 24
Finished May 23 03:43:16 PM PDT 24
Peak memory 204928 kb
Host smart-501d3bfd-8fcc-4f91-b355-7417ef6f62ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28273
34506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2827334506
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.55728440
Short name T332
Test name
Test status
Simulation time 10051464183 ps
CPU time 14.02 seconds
Started May 23 03:42:57 PM PDT 24
Finished May 23 03:43:25 PM PDT 24
Peak memory 204972 kb
Host smart-8649a855-bcb4-4b5e-97f3-2d287260cd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55728
440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.55728440
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.386097244
Short name T1047
Test name
Test status
Simulation time 10094249142 ps
CPU time 15.7 seconds
Started May 23 03:42:50 PM PDT 24
Finished May 23 03:43:20 PM PDT 24
Peak memory 204932 kb
Host smart-ce6d9297-4a19-4476-88cf-8e96f353db0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38609
7244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.386097244
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2732730028
Short name T1098
Test name
Test status
Simulation time 10090919608 ps
CPU time 13.8 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:16 PM PDT 24
Peak memory 204948 kb
Host smart-8b08f449-313a-4b97-ada7-9a50625a9c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27327
30028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2732730028
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3219685994
Short name T895
Test name
Test status
Simulation time 13208167204 ps
CPU time 18.56 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:25 PM PDT 24
Peak memory 204972 kb
Host smart-83e48ddb-070f-49a6-b2cc-0523398dd131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32196
85994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3219685994
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3884326622
Short name T320
Test name
Test status
Simulation time 10157321865 ps
CPU time 15.52 seconds
Started May 23 03:42:48 PM PDT 24
Finished May 23 03:43:17 PM PDT 24
Peak memory 204964 kb
Host smart-484c693c-6583-41a9-8bda-5766a61281f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38843
26622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3884326622
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3731804284
Short name T1321
Test name
Test status
Simulation time 10052728388 ps
CPU time 13.48 seconds
Started May 23 03:42:49 PM PDT 24
Finished May 23 03:43:17 PM PDT 24
Peak memory 204960 kb
Host smart-ceae0482-36c1-4a5e-bcb8-7162674354e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37318
04284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3731804284
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2909298167
Short name T112
Test name
Test status
Simulation time 10083846332 ps
CPU time 14.12 seconds
Started May 23 03:42:48 PM PDT 24
Finished May 23 03:43:16 PM PDT 24
Peak memory 204940 kb
Host smart-59fbcdde-28f2-44e1-b420-173c0fd62830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29092
98167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2909298167
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.2851917043
Short name T1782
Test name
Test status
Simulation time 10105258033 ps
CPU time 13.16 seconds
Started May 23 03:42:50 PM PDT 24
Finished May 23 03:43:17 PM PDT 24
Peak memory 204956 kb
Host smart-571fbd54-83f7-4cf0-9e89-c6762404b0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28519
17043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2851917043
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3041916787
Short name T1134
Test name
Test status
Simulation time 10105060096 ps
CPU time 14.03 seconds
Started May 23 03:42:59 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204980 kb
Host smart-3b0cc6ac-cac9-4da8-bca6-a7a1373d4555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30419
16787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3041916787
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1272571921
Short name T463
Test name
Test status
Simulation time 10094560181 ps
CPU time 16.57 seconds
Started May 23 03:42:57 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204992 kb
Host smart-e1ca3966-7fe6-49d1-9ad0-9c1cad811f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12725
71921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1272571921
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.3266685987
Short name T188
Test name
Test status
Simulation time 10060374376 ps
CPU time 13.31 seconds
Started May 23 03:43:00 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204932 kb
Host smart-bbd4332c-a400-4a45-a37a-16437281fb8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32666
85987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3266685987
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.3452971832
Short name T1716
Test name
Test status
Simulation time 10111324686 ps
CPU time 13.14 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:19 PM PDT 24
Peak memory 204968 kb
Host smart-70af59ea-8a41-4ddf-889d-ab8b680bddef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34529
71832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.3452971832
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3705237210
Short name T1215
Test name
Test status
Simulation time 10090923120 ps
CPU time 13.27 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:19 PM PDT 24
Peak memory 204608 kb
Host smart-8c9a797f-0c8f-4335-a64e-a348054c066c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37052
37210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3705237210
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.4162945926
Short name T31
Test name
Test status
Simulation time 10058387559 ps
CPU time 13.28 seconds
Started May 23 03:42:46 PM PDT 24
Finished May 23 03:43:13 PM PDT 24
Peak memory 204996 kb
Host smart-4e3b5d68-0963-41d2-930c-cd9148bd9719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41629
45926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.4162945926
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.762235444
Short name T948
Test name
Test status
Simulation time 29563059198 ps
CPU time 56.51 seconds
Started May 23 03:42:56 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 205028 kb
Host smart-d6d661d0-a217-4784-bcf6-a9ebd6705769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76223
5444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.762235444
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3313996011
Short name T678
Test name
Test status
Simulation time 10077611522 ps
CPU time 12.88 seconds
Started May 23 03:42:50 PM PDT 24
Finished May 23 03:43:17 PM PDT 24
Peak memory 204964 kb
Host smart-68036430-6745-49d1-a59a-8e259985f212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33139
96011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3313996011
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1777612950
Short name T1471
Test name
Test status
Simulation time 10079030781 ps
CPU time 12.47 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:25 PM PDT 24
Peak memory 204992 kb
Host smart-70f12a55-31a7-4ca6-b1e2-973fae2eac75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17776
12950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1777612950
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.2224088436
Short name T1935
Test name
Test status
Simulation time 10066611823 ps
CPU time 14.06 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:20 PM PDT 24
Peak memory 204956 kb
Host smart-4e670b1f-8c82-4a6b-8ce2-85f627c827d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22240
88436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.2224088436
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3716279754
Short name T1485
Test name
Test status
Simulation time 10057845279 ps
CPU time 13.22 seconds
Started May 23 03:42:48 PM PDT 24
Finished May 23 03:43:15 PM PDT 24
Peak memory 205024 kb
Host smart-991dbf1f-1219-4e26-92b7-96a74179ffd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37162
79754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3716279754
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1365470143
Short name T1037
Test name
Test status
Simulation time 10073092585 ps
CPU time 17.13 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:23 PM PDT 24
Peak memory 204688 kb
Host smart-06490876-3ede-4743-8056-51d54d7e27e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13654
70143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1365470143
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2495201561
Short name T44
Test name
Test status
Simulation time 10059709240 ps
CPU time 13.49 seconds
Started May 23 03:42:56 PM PDT 24
Finished May 23 03:43:24 PM PDT 24
Peak memory 204960 kb
Host smart-ee2b937a-599a-4685-92eb-8ef6614768bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24952
01561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2495201561
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.769190121
Short name T682
Test name
Test status
Simulation time 10152493979 ps
CPU time 16.65 seconds
Started May 23 03:42:45 PM PDT 24
Finished May 23 03:43:15 PM PDT 24
Peak memory 205052 kb
Host smart-7f91cdcd-0a55-4f85-9de8-7cf0aaa1d080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76919
0121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.769190121
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.934538729
Short name T1599
Test name
Test status
Simulation time 10110794496 ps
CPU time 13.95 seconds
Started May 23 03:42:53 PM PDT 24
Finished May 23 03:43:21 PM PDT 24
Peak memory 204928 kb
Host smart-e3a8ee6f-df72-4a8f-a561-cc92197dea47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93453
8729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.934538729
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2821819973
Short name T1026
Test name
Test status
Simulation time 10096832551 ps
CPU time 14.74 seconds
Started May 23 03:42:48 PM PDT 24
Finished May 23 03:43:16 PM PDT 24
Peak memory 204972 kb
Host smart-39e4ce48-91a0-42f0-904f-9a2dc214db8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28218
19973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2821819973
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2983695457
Short name T1442
Test name
Test status
Simulation time 10134478094 ps
CPU time 15.93 seconds
Started May 23 03:42:57 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204880 kb
Host smart-2dae2167-9ff4-4786-b112-9797b9ba0b16
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2983695457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2983695457
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.958658376
Short name T1845
Test name
Test status
Simulation time 10076495230 ps
CPU time 13.6 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:26 PM PDT 24
Peak memory 204948 kb
Host smart-7748f276-b9a2-4788-a6c3-ef817beacfa8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=958658376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.958658376
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.3020535790
Short name T621
Test name
Test status
Simulation time 10180510132 ps
CPU time 15.2 seconds
Started May 23 03:43:09 PM PDT 24
Finished May 23 03:43:33 PM PDT 24
Peak memory 204964 kb
Host smart-0af1765a-7181-4bdc-b70c-171fa4528aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30205
35790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.3020535790
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.1129978914
Short name T1353
Test name
Test status
Simulation time 14169698136 ps
CPU time 19.65 seconds
Started May 23 03:42:50 PM PDT 24
Finished May 23 03:43:24 PM PDT 24
Peak memory 204900 kb
Host smart-59c4669d-fc29-4d91-93b5-d15b48fa6ed8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1129978914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.1129978914
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1892431821
Short name T405
Test name
Test status
Simulation time 13298096854 ps
CPU time 16.07 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:22 PM PDT 24
Peak memory 204740 kb
Host smart-f9ef5180-7114-4e25-9921-6095b6603ccd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1892431821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1892431821
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3770270095
Short name T9
Test name
Test status
Simulation time 13197613374 ps
CPU time 15.64 seconds
Started May 23 03:42:53 PM PDT 24
Finished May 23 03:43:23 PM PDT 24
Peak memory 204936 kb
Host smart-aa8b5412-1fc2-46a7-9a4d-e01eda52f99e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3770270095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.3770270095
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2551277703
Short name T215
Test name
Test status
Simulation time 10052667718 ps
CPU time 14.2 seconds
Started May 23 03:42:59 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204964 kb
Host smart-717ff8e3-45d5-4051-bae4-5769f0b5ea46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25512
77703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2551277703
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3182417738
Short name T166
Test name
Test status
Simulation time 11179015442 ps
CPU time 15.08 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:21 PM PDT 24
Peak memory 205028 kb
Host smart-0b7bae7b-3a8f-4412-9371-e389410f8928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31824
17738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3182417738
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3035162696
Short name T776
Test name
Test status
Simulation time 10040573134 ps
CPU time 14.07 seconds
Started May 23 03:43:01 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204964 kb
Host smart-953bde31-e5fb-4b0f-b72b-dff2b381b250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30351
62696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3035162696
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3782857893
Short name T544
Test name
Test status
Simulation time 10071085254 ps
CPU time 15.85 seconds
Started May 23 03:42:55 PM PDT 24
Finished May 23 03:43:24 PM PDT 24
Peak memory 204916 kb
Host smart-5f70fe12-7b6e-48be-b56e-7a99761234e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37828
57893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3782857893
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2945572539
Short name T1271
Test name
Test status
Simulation time 10872076333 ps
CPU time 15.55 seconds
Started May 23 03:42:52 PM PDT 24
Finished May 23 03:43:22 PM PDT 24
Peak memory 204804 kb
Host smart-b3fc22c3-9c39-4d08-929b-c5a4a8a03899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29455
72539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2945572539
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.683760393
Short name T507
Test name
Test status
Simulation time 10213719005 ps
CPU time 15.64 seconds
Started May 23 03:42:57 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204932 kb
Host smart-03d71bca-a89f-4255-af4d-5808ad112cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68376
0393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.683760393
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1434236486
Short name T1051
Test name
Test status
Simulation time 10192308046 ps
CPU time 15.66 seconds
Started May 23 03:43:03 PM PDT 24
Finished May 23 03:43:31 PM PDT 24
Peak memory 204924 kb
Host smart-3498eebf-ce30-4fc3-b21d-d36c7ace0e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14342
36486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1434236486
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3167787864
Short name T1426
Test name
Test status
Simulation time 10044671480 ps
CPU time 12.97 seconds
Started May 23 03:42:59 PM PDT 24
Finished May 23 03:43:26 PM PDT 24
Peak memory 204928 kb
Host smart-c9781119-95ac-4021-95cb-9c96108ab6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31677
87864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3167787864
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.4117762155
Short name T751
Test name
Test status
Simulation time 10108939741 ps
CPU time 14.01 seconds
Started May 23 03:42:56 PM PDT 24
Finished May 23 03:43:24 PM PDT 24
Peak memory 204960 kb
Host smart-2b829fe8-619f-409a-80bf-7131c691ef16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41177
62155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.4117762155
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2993209845
Short name T1452
Test name
Test status
Simulation time 10097718558 ps
CPU time 13.9 seconds
Started May 23 03:43:05 PM PDT 24
Finished May 23 03:43:30 PM PDT 24
Peak memory 204936 kb
Host smart-6596f845-3d6a-41ad-aec5-2016da07362d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29932
09845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2993209845
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2714786180
Short name T1293
Test name
Test status
Simulation time 13192487983 ps
CPU time 15.26 seconds
Started May 23 03:43:05 PM PDT 24
Finished May 23 03:43:31 PM PDT 24
Peak memory 204928 kb
Host smart-1ff3587a-061a-403a-9db4-34b282942953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27147
86180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2714786180
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3609165214
Short name T478
Test name
Test status
Simulation time 10094799236 ps
CPU time 13.73 seconds
Started May 23 03:43:00 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204964 kb
Host smart-ff7cde02-954b-4a7b-8bbf-e35b2a15afdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36091
65214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3609165214
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.337276238
Short name T638
Test name
Test status
Simulation time 10088210016 ps
CPU time 13.1 seconds
Started May 23 03:43:18 PM PDT 24
Finished May 23 03:43:35 PM PDT 24
Peak memory 204960 kb
Host smart-128bc48f-3417-4c7d-8d17-b9df9803f6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33727
6238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.337276238
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.976178383
Short name T1654
Test name
Test status
Simulation time 10087523646 ps
CPU time 13.32 seconds
Started May 23 03:43:05 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 204896 kb
Host smart-a991a9df-72f0-4a00-a5c5-c57914397be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97617
8383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.976178383
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.4126681026
Short name T1749
Test name
Test status
Simulation time 10073287882 ps
CPU time 13.42 seconds
Started May 23 03:43:02 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204964 kb
Host smart-4b3ba3cc-208d-4688-b6db-7b2d0b3d525e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41266
81026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.4126681026
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.877481292
Short name T342
Test name
Test status
Simulation time 10141673561 ps
CPU time 13.06 seconds
Started May 23 03:43:01 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204984 kb
Host smart-e2975262-62ce-4aec-8348-f3c07370c363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87748
1292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.877481292
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3883969542
Short name T155
Test name
Test status
Simulation time 10085620103 ps
CPU time 13.29 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:25 PM PDT 24
Peak memory 204972 kb
Host smart-6e7a190a-60fe-43f0-8d46-7b921873f547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38839
69542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3883969542
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.3077062390
Short name T495
Test name
Test status
Simulation time 10090076839 ps
CPU time 13.36 seconds
Started May 23 03:43:03 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 205028 kb
Host smart-c057adf3-079c-400c-b9e0-a9c218df3142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30770
62390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.3077062390
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1541627459
Short name T445
Test name
Test status
Simulation time 10055668587 ps
CPU time 13.49 seconds
Started May 23 03:43:21 PM PDT 24
Finished May 23 03:43:39 PM PDT 24
Peak memory 204964 kb
Host smart-3e7efa5c-5d6c-41ab-a7d2-86d6b040bde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15416
27459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1541627459
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1971350791
Short name T1752
Test name
Test status
Simulation time 10045635197 ps
CPU time 12.75 seconds
Started May 23 03:43:01 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204964 kb
Host smart-93e22285-9485-48d5-9ecc-eb42c053154d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19713
50791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1971350791
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1028138279
Short name T175
Test name
Test status
Simulation time 16309742511 ps
CPU time 25.92 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:38 PM PDT 24
Peak memory 205020 kb
Host smart-796277f7-e04c-489c-8290-2b6c3733607d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10281
38279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1028138279
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.551917316
Short name T1701
Test name
Test status
Simulation time 10075645052 ps
CPU time 13.16 seconds
Started May 23 03:42:59 PM PDT 24
Finished May 23 03:43:26 PM PDT 24
Peak memory 204920 kb
Host smart-01a8dc0f-01de-402b-b273-0ceb1d282d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55191
7316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.551917316
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2042076080
Short name T959
Test name
Test status
Simulation time 10096384006 ps
CPU time 14.37 seconds
Started May 23 03:43:00 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204996 kb
Host smart-d572499c-7cae-4b28-a420-d7055246183b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20420
76080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2042076080
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.3095386060
Short name T893
Test name
Test status
Simulation time 10087728419 ps
CPU time 13.38 seconds
Started May 23 03:43:00 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204928 kb
Host smart-c11c6882-c25e-4fd8-b7b3-a97125aa6c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30953
86060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.3095386060
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2216797834
Short name T1525
Test name
Test status
Simulation time 10038606547 ps
CPU time 12.98 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:25 PM PDT 24
Peak memory 204980 kb
Host smart-7e8cf270-dcae-4a17-88f5-096c11a6f49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22167
97834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2216797834
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3047946677
Short name T90
Test name
Test status
Simulation time 10050970812 ps
CPU time 12.31 seconds
Started May 23 03:43:03 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204968 kb
Host smart-862e0b67-2bed-42be-93fb-e6e29d045791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30479
46677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3047946677
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3464201202
Short name T611
Test name
Test status
Simulation time 10046770320 ps
CPU time 12.14 seconds
Started May 23 03:43:01 PM PDT 24
Finished May 23 03:43:26 PM PDT 24
Peak memory 204916 kb
Host smart-25e5ef36-5137-4b49-84f9-c81ae68762ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34642
01202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3464201202
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.908944216
Short name T1146
Test name
Test status
Simulation time 10150301705 ps
CPU time 13.62 seconds
Started May 23 03:42:53 PM PDT 24
Finished May 23 03:43:20 PM PDT 24
Peak memory 204952 kb
Host smart-e4a5470d-1610-4ee7-a45d-3b11f0967156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90894
4216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.908944216
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.419294203
Short name T1890
Test name
Test status
Simulation time 10062868525 ps
CPU time 13.01 seconds
Started May 23 03:43:01 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204960 kb
Host smart-9bb6eb32-6aad-4b45-9edd-126f835cc0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41929
4203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.419294203
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3166249487
Short name T937
Test name
Test status
Simulation time 10098719120 ps
CPU time 13.29 seconds
Started May 23 03:43:02 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204988 kb
Host smart-74969a93-393d-43de-a342-9e15e39310b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31662
49487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3166249487
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.1877784462
Short name T1892
Test name
Test status
Simulation time 10171773749 ps
CPU time 12.56 seconds
Started May 23 03:43:19 PM PDT 24
Finished May 23 03:43:36 PM PDT 24
Peak memory 204948 kb
Host smart-63f083ff-3995-48fb-af7b-bf5cb86d53b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1877784462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.1877784462
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.3994914343
Short name T1264
Test name
Test status
Simulation time 10064605887 ps
CPU time 14.74 seconds
Started May 23 03:43:04 PM PDT 24
Finished May 23 03:43:30 PM PDT 24
Peak memory 204948 kb
Host smart-3809c50c-d2a9-430d-a1c5-d1a403d3eda7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3994914343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.3994914343
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.261511273
Short name T389
Test name
Test status
Simulation time 10109589985 ps
CPU time 12.53 seconds
Started May 23 03:43:18 PM PDT 24
Finished May 23 03:43:35 PM PDT 24
Peak memory 204932 kb
Host smart-c1126f99-27c4-47fa-9604-aa9e75d470e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26151
1273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.261511273
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.1209838100
Short name T11
Test name
Test status
Simulation time 13680799450 ps
CPU time 15.92 seconds
Started May 23 03:42:59 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 204964 kb
Host smart-32aec6ee-5486-4bcd-bfd7-d354bb223c18
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1209838100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.1209838100
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.4163498270
Short name T193
Test name
Test status
Simulation time 13281348666 ps
CPU time 18.59 seconds
Started May 23 03:43:00 PM PDT 24
Finished May 23 03:43:32 PM PDT 24
Peak memory 205000 kb
Host smart-eee9fb69-a472-4141-b5c6-37426b405333
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4163498270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.4163498270
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.3976690393
Short name T1656
Test name
Test status
Simulation time 13257321902 ps
CPU time 16.07 seconds
Started May 23 03:43:02 PM PDT 24
Finished May 23 03:43:31 PM PDT 24
Peak memory 204956 kb
Host smart-6b6572b7-6203-48af-bf71-0b3090ad0fd7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3976690393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.3976690393
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.588535313
Short name T677
Test name
Test status
Simulation time 10048474316 ps
CPU time 15.61 seconds
Started May 23 03:43:15 PM PDT 24
Finished May 23 03:43:36 PM PDT 24
Peak memory 204972 kb
Host smart-c7d05418-d1d2-4cc9-9053-97b16feb6a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58853
5313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.588535313
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.61899906
Short name T812
Test name
Test status
Simulation time 10131842631 ps
CPU time 13.53 seconds
Started May 23 03:42:56 PM PDT 24
Finished May 23 03:43:24 PM PDT 24
Peak memory 205000 kb
Host smart-b5d03d7f-704c-4633-8f98-1d17439d11cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61899
906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.61899906
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1863797273
Short name T1910
Test name
Test status
Simulation time 10079861897 ps
CPU time 13.12 seconds
Started May 23 03:42:57 PM PDT 24
Finished May 23 03:43:25 PM PDT 24
Peak memory 204972 kb
Host smart-9cdc0add-7fb1-4010-a62c-a2b1d7989114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18637
97273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1863797273
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3563905444
Short name T740
Test name
Test status
Simulation time 10050437429 ps
CPU time 13.93 seconds
Started May 23 03:43:03 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 204976 kb
Host smart-035d36a7-a8c4-4a5b-aa0a-dd423613a260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35639
05444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3563905444
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3856794502
Short name T885
Test name
Test status
Simulation time 10792145018 ps
CPU time 16.72 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 204896 kb
Host smart-43cdc33d-b2c3-408c-a6ed-6203bf930687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567
94502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3856794502
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2591972905
Short name T373
Test name
Test status
Simulation time 10110139060 ps
CPU time 16.39 seconds
Started May 23 03:43:01 PM PDT 24
Finished May 23 03:43:31 PM PDT 24
Peak memory 204912 kb
Host smart-ae719ccd-756a-4abd-b0c8-e50ae790dcb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25919
72905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2591972905
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1887975961
Short name T379
Test name
Test status
Simulation time 10173729071 ps
CPU time 13.89 seconds
Started May 23 03:42:59 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204912 kb
Host smart-4dcbc75a-b33c-498a-a3cb-eb1424e20f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18879
75961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1887975961
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2398447164
Short name T16
Test name
Test status
Simulation time 10044387125 ps
CPU time 12.93 seconds
Started May 23 03:43:09 PM PDT 24
Finished May 23 03:43:30 PM PDT 24
Peak memory 204932 kb
Host smart-fb7d480f-44eb-4d9e-ade4-c799282805ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23984
47164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2398447164
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1167586881
Short name T888
Test name
Test status
Simulation time 10174119980 ps
CPU time 13.49 seconds
Started May 23 03:43:05 PM PDT 24
Finished May 23 03:43:30 PM PDT 24
Peak memory 204932 kb
Host smart-c5f628ab-72d4-41f0-9a42-48157fb94c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11675
86881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1167586881
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1960428796
Short name T1400
Test name
Test status
Simulation time 10096257421 ps
CPU time 13.35 seconds
Started May 23 03:43:03 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204964 kb
Host smart-c58fb796-261d-424c-8d5f-04b77137e0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19604
28796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1960428796
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.351169426
Short name T1010
Test name
Test status
Simulation time 13232201966 ps
CPU time 20.1 seconds
Started May 23 03:42:56 PM PDT 24
Finished May 23 03:43:31 PM PDT 24
Peak memory 204936 kb
Host smart-27017f2d-7f0f-4824-b59f-89fbb6367091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35116
9426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.351169426
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2235912158
Short name T685
Test name
Test status
Simulation time 10084231539 ps
CPU time 13.36 seconds
Started May 23 03:42:56 PM PDT 24
Finished May 23 03:43:23 PM PDT 24
Peak memory 204912 kb
Host smart-c71eb6a5-d4a6-454a-8f73-cb56f084df45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22359
12158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2235912158
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2632468263
Short name T750
Test name
Test status
Simulation time 10061839871 ps
CPU time 13.63 seconds
Started May 23 03:43:07 PM PDT 24
Finished May 23 03:43:30 PM PDT 24
Peak memory 204984 kb
Host smart-f0d951e3-1315-411a-a669-449a3c774fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26324
68263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2632468263
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1611265833
Short name T118
Test name
Test status
Simulation time 10081618601 ps
CPU time 13.49 seconds
Started May 23 03:43:10 PM PDT 24
Finished May 23 03:43:32 PM PDT 24
Peak memory 204952 kb
Host smart-ffefda7c-f18e-4c74-910d-e4498dc94fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16112
65833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1611265833
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3574090638
Short name T246
Test name
Test status
Simulation time 10113844625 ps
CPU time 14.37 seconds
Started May 23 03:43:00 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204968 kb
Host smart-eb8d6aed-3d8e-40c3-94b0-7e63bee98311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35740
90638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3574090638
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.4078587693
Short name T450
Test name
Test status
Simulation time 10112040261 ps
CPU time 13.06 seconds
Started May 23 03:43:17 PM PDT 24
Finished May 23 03:43:35 PM PDT 24
Peak memory 204932 kb
Host smart-d75bb75b-eac1-4260-854b-9474ead2602e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40785
87693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.4078587693
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1078185741
Short name T1904
Test name
Test status
Simulation time 10066053355 ps
CPU time 13.69 seconds
Started May 23 03:43:11 PM PDT 24
Finished May 23 03:43:32 PM PDT 24
Peak memory 204980 kb
Host smart-82bba27b-4d56-403e-87c2-f47b64f9c51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10781
85741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1078185741
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.1414947090
Short name T1623
Test name
Test status
Simulation time 10054141442 ps
CPU time 13.11 seconds
Started May 23 03:43:19 PM PDT 24
Finished May 23 03:43:36 PM PDT 24
Peak memory 204952 kb
Host smart-05b3ba32-6dbb-445f-9eb4-1f8a561a1e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14149
47090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.1414947090
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.274900646
Short name T1553
Test name
Test status
Simulation time 10039798731 ps
CPU time 13.46 seconds
Started May 23 03:43:12 PM PDT 24
Finished May 23 03:43:33 PM PDT 24
Peak memory 204904 kb
Host smart-c85c0143-ffeb-4a98-a1a2-631f4a036d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27490
0646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.274900646
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.793594567
Short name T21
Test name
Test status
Simulation time 10041275948 ps
CPU time 13.83 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:26 PM PDT 24
Peak memory 204960 kb
Host smart-9ddb575b-c641-4108-bc96-543ead50896a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79359
4567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.793594567
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3564524084
Short name T35
Test name
Test status
Simulation time 15779079378 ps
CPU time 25.8 seconds
Started May 23 03:43:09 PM PDT 24
Finished May 23 03:43:44 PM PDT 24
Peak memory 204976 kb
Host smart-4284aad5-e094-485d-b7fa-25d89771073b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35645
24084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3564524084
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1567961691
Short name T1013
Test name
Test status
Simulation time 10078095883 ps
CPU time 13.21 seconds
Started May 23 03:43:04 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 204928 kb
Host smart-15e0c7e8-8c70-4a13-9e0e-c6c688573933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15679
61691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1567961691
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1422948467
Short name T335
Test name
Test status
Simulation time 10130627627 ps
CPU time 13.59 seconds
Started May 23 03:43:00 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204920 kb
Host smart-eba425b1-684b-43e1-85b2-5c6e10c34a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14229
48467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1422948467
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.760576104
Short name T610
Test name
Test status
Simulation time 10082519165 ps
CPU time 13.75 seconds
Started May 23 03:43:18 PM PDT 24
Finished May 23 03:43:36 PM PDT 24
Peak memory 204940 kb
Host smart-cf59e472-d5f3-4b91-96c8-1255e5e2f359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76057
6104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.760576104
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.698762334
Short name T922
Test name
Test status
Simulation time 10047699125 ps
CPU time 13.43 seconds
Started May 23 03:43:01 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204956 kb
Host smart-23fc6a17-bb7d-4b7a-91df-b205af6bb201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69876
2334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.698762334
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1309472948
Short name T1253
Test name
Test status
Simulation time 10064855137 ps
CPU time 13.61 seconds
Started May 23 03:43:05 PM PDT 24
Finished May 23 03:43:30 PM PDT 24
Peak memory 204904 kb
Host smart-ae0bd6c1-dfe9-49c4-b7e6-6ae0add17f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13094
72948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1309472948
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1673335007
Short name T825
Test name
Test status
Simulation time 10051135056 ps
CPU time 15.75 seconds
Started May 23 03:43:00 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 204952 kb
Host smart-3941445d-8cfa-486e-b939-b213be7c1792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16733
35007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1673335007
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1421988301
Short name T144
Test name
Test status
Simulation time 10134499278 ps
CPU time 12.95 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:25 PM PDT 24
Peak memory 204932 kb
Host smart-ef0979a8-4fec-44a9-80c0-0d0bb40e4481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
88301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1421988301
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.121075733
Short name T1181
Test name
Test status
Simulation time 10062698154 ps
CPU time 13.5 seconds
Started May 23 03:43:13 PM PDT 24
Finished May 23 03:43:33 PM PDT 24
Peak memory 204904 kb
Host smart-cdc7bbfc-254b-4f95-adcf-9d712bd4ec97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
5733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.121075733
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3464273742
Short name T1292
Test name
Test status
Simulation time 10123264011 ps
CPU time 13.52 seconds
Started May 23 03:43:01 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204956 kb
Host smart-ded3c9cd-7bee-4c5b-9373-20b8547c0a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34642
73742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3464273742
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.68501934
Short name T1012
Test name
Test status
Simulation time 10153097760 ps
CPU time 13.17 seconds
Started May 23 03:43:26 PM PDT 24
Finished May 23 03:43:44 PM PDT 24
Peak memory 204944 kb
Host smart-2c2284c9-972e-4d36-b17f-e8172bddcb52
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=68501934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.68501934
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.4261880773
Short name T1231
Test name
Test status
Simulation time 10109634128 ps
CPU time 15.71 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:56 PM PDT 24
Peak memory 204964 kb
Host smart-3a50e9e7-0920-4af4-838f-784779629a6b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4261880773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.4261880773
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.2467951120
Short name T992
Test name
Test status
Simulation time 10114379868 ps
CPU time 15.87 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:51 PM PDT 24
Peak memory 204960 kb
Host smart-9a3e50db-7d84-4beb-bd46-ca03a8b52658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24679
51120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.2467951120
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3555451617
Short name T1791
Test name
Test status
Simulation time 13917857995 ps
CPU time 16.49 seconds
Started May 23 03:43:24 PM PDT 24
Finished May 23 03:43:45 PM PDT 24
Peak memory 204968 kb
Host smart-d76b10f9-2fc1-4b27-971b-0f8695ec5e5e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3555451617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.3555451617
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.341201430
Short name T540
Test name
Test status
Simulation time 13297351743 ps
CPU time 17.06 seconds
Started May 23 03:43:20 PM PDT 24
Finished May 23 03:43:41 PM PDT 24
Peak memory 204988 kb
Host smart-b65ab80e-ebd9-4ef6-9323-dea3e16dfa78
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=341201430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.341201430
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.931207681
Short name T437
Test name
Test status
Simulation time 13179820781 ps
CPU time 16.32 seconds
Started May 23 03:43:02 PM PDT 24
Finished May 23 03:43:31 PM PDT 24
Peak memory 204928 kb
Host smart-df30e9cc-2476-46b3-902c-22add00be48b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=931207681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.931207681
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3499323586
Short name T1457
Test name
Test status
Simulation time 10065917829 ps
CPU time 14.31 seconds
Started May 23 03:43:00 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204932 kb
Host smart-a87e7ee5-24e7-4ee0-aded-4c3dd3273df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34993
23586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3499323586
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3715966089
Short name T1906
Test name
Test status
Simulation time 10182994413 ps
CPU time 14.42 seconds
Started May 23 03:43:19 PM PDT 24
Finished May 23 03:43:38 PM PDT 24
Peak memory 205028 kb
Host smart-49a0202f-2685-4a6f-8910-3d07a2eb034a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37159
66089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3715966089
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1065085431
Short name T1112
Test name
Test status
Simulation time 10046778973 ps
CPU time 12.71 seconds
Started May 23 03:43:01 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204988 kb
Host smart-ad0fd281-22d0-4282-8973-902541517863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10650
85431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1065085431
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.427902954
Short name T807
Test name
Test status
Simulation time 10049487882 ps
CPU time 14.5 seconds
Started May 23 03:43:01 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 205012 kb
Host smart-fff99239-7516-47e1-9ea6-bab96ec3c5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42790
2954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.427902954
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.693844284
Short name T1745
Test name
Test status
Simulation time 10781571704 ps
CPU time 13.78 seconds
Started May 23 03:43:22 PM PDT 24
Finished May 23 03:43:40 PM PDT 24
Peak memory 204940 kb
Host smart-9372f2af-10d2-40fb-a173-2818035c432b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69384
4284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.693844284
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2414781783
Short name T606
Test name
Test status
Simulation time 10211768106 ps
CPU time 15.83 seconds
Started May 23 03:42:57 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 205048 kb
Host smart-fd2faab8-cf26-4a3d-8211-86498357cad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24147
81783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2414781783
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3925045749
Short name T699
Test name
Test status
Simulation time 10128312182 ps
CPU time 14.28 seconds
Started May 23 03:43:20 PM PDT 24
Finished May 23 03:43:38 PM PDT 24
Peak memory 204900 kb
Host smart-7837800e-4a0b-45b7-a06c-5c4ce4a490f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39250
45749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3925045749
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1623273447
Short name T1128
Test name
Test status
Simulation time 10083468952 ps
CPU time 14.13 seconds
Started May 23 03:43:20 PM PDT 24
Finished May 23 03:43:39 PM PDT 24
Peak memory 204948 kb
Host smart-92d15057-36ab-4647-abbe-ddc1bce99b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16232
73447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1623273447
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.703633928
Short name T1184
Test name
Test status
Simulation time 10146646418 ps
CPU time 12.97 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:25 PM PDT 24
Peak memory 204936 kb
Host smart-ed160635-95ca-4ed0-b16f-f05ebba07c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70363
3928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.703633928
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1977815896
Short name T920
Test name
Test status
Simulation time 10092814806 ps
CPU time 13.73 seconds
Started May 23 03:42:59 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 204916 kb
Host smart-6a9fbb3d-e6b0-4b2d-90ac-28df531916a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19778
15896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1977815896
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.496914584
Short name T1601
Test name
Test status
Simulation time 13185018695 ps
CPU time 17.24 seconds
Started May 23 03:43:00 PM PDT 24
Finished May 23 03:43:31 PM PDT 24
Peak memory 204872 kb
Host smart-dccc79b4-31d5-44e2-9dc3-f61526d03c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49691
4584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.496914584
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3240946016
Short name T1132
Test name
Test status
Simulation time 10150493508 ps
CPU time 13.26 seconds
Started May 23 03:43:04 PM PDT 24
Finished May 23 03:43:29 PM PDT 24
Peak memory 204964 kb
Host smart-90ec06f0-d380-41d9-91ff-eda4db9d2b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32409
46016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3240946016
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.670677534
Short name T316
Test name
Test status
Simulation time 10113892308 ps
CPU time 13.56 seconds
Started May 23 03:43:02 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204932 kb
Host smart-114f391a-481b-4eaf-8a01-da05e20ed71f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67067
7534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.670677534
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1692298636
Short name T1488
Test name
Test status
Simulation time 10103708132 ps
CPU time 13.02 seconds
Started May 23 03:43:03 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 204964 kb
Host smart-5b81bb45-39f1-4349-867d-240eae27794c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16922
98636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1692298636
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1390322692
Short name T734
Test name
Test status
Simulation time 10093616772 ps
CPU time 14.38 seconds
Started May 23 03:43:03 PM PDT 24
Finished May 23 03:43:30 PM PDT 24
Peak memory 204888 kb
Host smart-74d5026b-fd90-46ef-9a84-fa53c43ecb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13903
22692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1390322692
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.159462826
Short name T1781
Test name
Test status
Simulation time 10065368378 ps
CPU time 16.12 seconds
Started May 23 03:43:17 PM PDT 24
Finished May 23 03:43:38 PM PDT 24
Peak memory 204984 kb
Host smart-f23594ed-ce49-4348-a7c4-5e3f23c6510e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15946
2826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.159462826
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3309387761
Short name T1682
Test name
Test status
Simulation time 10086789968 ps
CPU time 14.82 seconds
Started May 23 03:43:16 PM PDT 24
Finished May 23 03:43:36 PM PDT 24
Peak memory 205008 kb
Host smart-5ef1e296-2d78-4aa9-aa82-82d80c667f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33093
87761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3309387761
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.748859873
Short name T189
Test name
Test status
Simulation time 10054277977 ps
CPU time 16.06 seconds
Started May 23 03:43:20 PM PDT 24
Finished May 23 03:43:40 PM PDT 24
Peak memory 204988 kb
Host smart-76ebc946-c416-4950-aefb-d6bc1ac8da21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74885
9873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.748859873
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.3113530055
Short name T1679
Test name
Test status
Simulation time 10143604234 ps
CPU time 14.22 seconds
Started May 23 03:43:23 PM PDT 24
Finished May 23 03:43:41 PM PDT 24
Peak memory 204972 kb
Host smart-8424c236-a2d5-4d86-b2f5-e6d1a1136aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31135
30055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.3113530055
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3960128384
Short name T702
Test name
Test status
Simulation time 10046241124 ps
CPU time 13.95 seconds
Started May 23 03:43:26 PM PDT 24
Finished May 23 03:43:45 PM PDT 24
Peak memory 204960 kb
Host smart-5a2c6421-4956-4cd1-8157-7085f160af51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39601
28384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3960128384
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1056729528
Short name T1404
Test name
Test status
Simulation time 10040736092 ps
CPU time 13.08 seconds
Started May 23 03:43:35 PM PDT 24
Finished May 23 03:43:54 PM PDT 24
Peak memory 204944 kb
Host smart-56a26d60-19f8-4b31-8d49-99d4dfcbe722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10567
29528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1056729528
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1089800474
Short name T171
Test name
Test status
Simulation time 20639209098 ps
CPU time 35.81 seconds
Started May 23 03:43:02 PM PDT 24
Finished May 23 03:43:50 PM PDT 24
Peak memory 205004 kb
Host smart-26a998e1-6150-4b64-b3dd-d7ee4d4f66fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10898
00474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1089800474
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1632216453
Short name T1379
Test name
Test status
Simulation time 10070036615 ps
CPU time 12.98 seconds
Started May 23 03:42:59 PM PDT 24
Finished May 23 03:43:26 PM PDT 24
Peak memory 204912 kb
Host smart-50c2a4b4-6403-4376-9fde-86aa7a80a66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16322
16453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1632216453
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3838689506
Short name T1060
Test name
Test status
Simulation time 10131775806 ps
CPU time 14.56 seconds
Started May 23 03:42:58 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204884 kb
Host smart-65dbff3f-d091-43de-ac46-15d208a6a4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38386
89506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3838689506
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.1158784109
Short name T1652
Test name
Test status
Simulation time 10075353528 ps
CPU time 13.3 seconds
Started May 23 03:43:15 PM PDT 24
Finished May 23 03:43:34 PM PDT 24
Peak memory 204960 kb
Host smart-bbf3c2a8-e3fc-4d7a-9033-05ee268c7600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11587
84109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.1158784109
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.70928439
Short name T954
Test name
Test status
Simulation time 10040036838 ps
CPU time 12.72 seconds
Started May 23 03:43:14 PM PDT 24
Finished May 23 03:43:33 PM PDT 24
Peak memory 204940 kb
Host smart-6899e10a-aab9-4999-84e3-56dfa1c6eb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70928
439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.70928439
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2659404406
Short name T1239
Test name
Test status
Simulation time 10067619149 ps
CPU time 14.25 seconds
Started May 23 03:43:33 PM PDT 24
Finished May 23 03:43:53 PM PDT 24
Peak memory 204932 kb
Host smart-3af3e6cc-b248-40c7-a45d-012df55de067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26594
04406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2659404406
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.827669028
Short name T1225
Test name
Test status
Simulation time 10058491515 ps
CPU time 13.17 seconds
Started May 23 03:43:00 PM PDT 24
Finished May 23 03:43:27 PM PDT 24
Peak memory 204912 kb
Host smart-44130712-4bb0-40ff-8b29-d2f5c14f0e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82766
9028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.827669028
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2760436940
Short name T150
Test name
Test status
Simulation time 10127873299 ps
CPU time 13.09 seconds
Started May 23 03:43:19 PM PDT 24
Finished May 23 03:43:37 PM PDT 24
Peak memory 204968 kb
Host smart-425e0446-afb3-474d-b3ff-83ad9f00ef31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27604
36940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2760436940
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1794299564
Short name T1908
Test name
Test status
Simulation time 10078543701 ps
CPU time 12.77 seconds
Started May 23 03:43:28 PM PDT 24
Finished May 23 03:43:46 PM PDT 24
Peak memory 204908 kb
Host smart-9766fd56-6c90-46ab-9fd0-34dbb0d9beb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17942
99564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1794299564
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.4287690798
Short name T1360
Test name
Test status
Simulation time 10082271459 ps
CPU time 13.29 seconds
Started May 23 03:43:16 PM PDT 24
Finished May 23 03:43:35 PM PDT 24
Peak memory 204964 kb
Host smart-bb899a0f-df78-4247-bca3-fcb4468d591f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42876
90798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.4287690798
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.511573033
Short name T1070
Test name
Test status
Simulation time 10216264415 ps
CPU time 14.5 seconds
Started May 23 03:43:35 PM PDT 24
Finished May 23 03:43:56 PM PDT 24
Peak memory 204968 kb
Host smart-4a5c91a6-c999-4038-b104-fb3204bb96f6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=511573033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.511573033
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.373682453
Short name T1714
Test name
Test status
Simulation time 10046901923 ps
CPU time 13.43 seconds
Started May 23 03:43:20 PM PDT 24
Finished May 23 03:43:38 PM PDT 24
Peak memory 204936 kb
Host smart-2ca99550-65af-43d8-a7fe-bd3ce8d1be0b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=373682453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.373682453
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.152381338
Short name T512
Test name
Test status
Simulation time 10136384100 ps
CPU time 13.62 seconds
Started May 23 03:43:21 PM PDT 24
Finished May 23 03:43:39 PM PDT 24
Peak memory 204984 kb
Host smart-9a893c74-c922-4e49-bf23-656a3af5572d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15238
1338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.152381338
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3066027597
Short name T835
Test name
Test status
Simulation time 14191109720 ps
CPU time 16.72 seconds
Started May 23 03:43:23 PM PDT 24
Finished May 23 03:43:44 PM PDT 24
Peak memory 204944 kb
Host smart-0c260768-f2eb-466a-9275-95590dc01274
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3066027597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.3066027597
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.2940454761
Short name T1029
Test name
Test status
Simulation time 13204657505 ps
CPU time 16.96 seconds
Started May 23 03:43:26 PM PDT 24
Finished May 23 03:43:48 PM PDT 24
Peak memory 204964 kb
Host smart-6b14ebdb-07ca-4fb9-9fa9-97a13b3c6f82
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2940454761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.2940454761
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.98058484
Short name T1263
Test name
Test status
Simulation time 13210243191 ps
CPU time 19.21 seconds
Started May 23 03:43:27 PM PDT 24
Finished May 23 03:43:52 PM PDT 24
Peak memory 204916 kb
Host smart-e1a08819-9dd3-4e4a-bba5-aa76983cbe6c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=98058484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.98058484
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1215751652
Short name T392
Test name
Test status
Simulation time 10064596553 ps
CPU time 12.4 seconds
Started May 23 03:43:12 PM PDT 24
Finished May 23 03:43:31 PM PDT 24
Peak memory 204940 kb
Host smart-bb8ba9d4-36c8-441b-97e0-33e92a312eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12157
51652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1215751652
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.4026081313
Short name T490
Test name
Test status
Simulation time 10060484403 ps
CPU time 14.39 seconds
Started May 23 03:43:11 PM PDT 24
Finished May 23 03:43:33 PM PDT 24
Peak memory 204900 kb
Host smart-a5a1a698-cdb1-4e6d-9d03-ae34f60f6c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40260
81313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.4026081313
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1132388844
Short name T706
Test name
Test status
Simulation time 10455291612 ps
CPU time 13.61 seconds
Started May 23 03:43:35 PM PDT 24
Finished May 23 03:43:55 PM PDT 24
Peak memory 204984 kb
Host smart-176648e1-fefa-4f64-9c29-2392ba039f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11323
88844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1132388844
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3504787294
Short name T1942
Test name
Test status
Simulation time 10112741088 ps
CPU time 12.72 seconds
Started May 23 03:43:25 PM PDT 24
Finished May 23 03:43:43 PM PDT 24
Peak memory 204972 kb
Host smart-cda63fff-ebcd-4003-a763-ec6f3e00d5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35047
87294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3504787294
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.70719521
Short name T1921
Test name
Test status
Simulation time 10051488162 ps
CPU time 13.77 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:50 PM PDT 24
Peak memory 204972 kb
Host smart-0a2699f0-19ab-4071-bdb5-6bf79b561d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70719
521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.70719521
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1814965147
Short name T1463
Test name
Test status
Simulation time 10877165643 ps
CPU time 14.48 seconds
Started May 23 03:43:21 PM PDT 24
Finished May 23 03:43:40 PM PDT 24
Peak memory 204920 kb
Host smart-e5a3cc14-c2a1-43b6-a1ce-acf1932d3d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18149
65147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1814965147
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2774522601
Short name T1842
Test name
Test status
Simulation time 10115157679 ps
CPU time 13.82 seconds
Started May 23 03:43:18 PM PDT 24
Finished May 23 03:43:36 PM PDT 24
Peak memory 204988 kb
Host smart-5caf58f0-ae97-48d3-b03c-42886b3f91bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27745
22601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2774522601
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2615098690
Short name T1886
Test name
Test status
Simulation time 10091390357 ps
CPU time 13.48 seconds
Started May 23 03:43:33 PM PDT 24
Finished May 23 03:43:52 PM PDT 24
Peak memory 204928 kb
Host smart-9487a9a8-de51-47a4-97f7-df6c05058d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26150
98690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2615098690
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1878401020
Short name T1083
Test name
Test status
Simulation time 10038987571 ps
CPU time 13.36 seconds
Started May 23 03:43:27 PM PDT 24
Finished May 23 03:43:46 PM PDT 24
Peak memory 204960 kb
Host smart-6ac769bb-d2db-4a77-8127-4de3f2cbf875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18784
01020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1878401020
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.4289612844
Short name T1228
Test name
Test status
Simulation time 10183271349 ps
CPU time 14.05 seconds
Started May 23 03:43:18 PM PDT 24
Finished May 23 03:43:37 PM PDT 24
Peak memory 205000 kb
Host smart-7b3de89c-4e2f-423a-a5a3-ca1c7aae5d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42896
12844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.4289612844
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3302300178
Short name T1346
Test name
Test status
Simulation time 10087586368 ps
CPU time 12.61 seconds
Started May 23 03:43:15 PM PDT 24
Finished May 23 03:43:33 PM PDT 24
Peak memory 204956 kb
Host smart-ebc7e063-301b-401a-ba33-ebe103a732fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33023
00178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3302300178
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2280794930
Short name T1
Test name
Test status
Simulation time 13226078244 ps
CPU time 18.51 seconds
Started May 23 03:43:18 PM PDT 24
Finished May 23 03:43:41 PM PDT 24
Peak memory 204932 kb
Host smart-ce9ea2b2-8130-4fa2-bed0-2d7d8b318b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22807
94930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2280794930
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3237485642
Short name T986
Test name
Test status
Simulation time 10109262830 ps
CPU time 14.96 seconds
Started May 23 03:43:20 PM PDT 24
Finished May 23 03:43:39 PM PDT 24
Peak memory 204936 kb
Host smart-c09ec6e0-3468-4819-894a-951e49ff2b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32374
85642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3237485642
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.269354778
Short name T742
Test name
Test status
Simulation time 10050315212 ps
CPU time 12.78 seconds
Started May 23 03:43:13 PM PDT 24
Finished May 23 03:43:32 PM PDT 24
Peak memory 204912 kb
Host smart-c0fd332f-f677-4bcd-ae22-422ccc4d8420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26935
4778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.269354778
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2549967736
Short name T1064
Test name
Test status
Simulation time 10143042512 ps
CPU time 13.64 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:51 PM PDT 24
Peak memory 204964 kb
Host smart-1c3ce637-99a2-4e15-8453-383ff122ea6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25499
67736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2549967736
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3087393899
Short name T502
Test name
Test status
Simulation time 10108601280 ps
CPU time 13.99 seconds
Started May 23 03:43:23 PM PDT 24
Finished May 23 03:43:42 PM PDT 24
Peak memory 204932 kb
Host smart-a3fc760f-19cb-47e6-81aa-4e0c3f18004e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30873
93899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3087393899
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3986025640
Short name T880
Test name
Test status
Simulation time 10070740084 ps
CPU time 12.83 seconds
Started May 23 03:43:27 PM PDT 24
Finished May 23 03:43:45 PM PDT 24
Peak memory 205008 kb
Host smart-f6963870-2c2d-4801-9301-4b3f7ca06cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39860
25640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3986025640
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3762855630
Short name T244
Test name
Test status
Simulation time 10085035674 ps
CPU time 15.02 seconds
Started May 23 03:43:36 PM PDT 24
Finished May 23 03:43:57 PM PDT 24
Peak memory 204948 kb
Host smart-4c0dbb55-5e39-4ab7-b40e-72ee0a1c2c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37628
55630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3762855630
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2579839362
Short name T172
Test name
Test status
Simulation time 10136830166 ps
CPU time 12.76 seconds
Started May 23 03:43:18 PM PDT 24
Finished May 23 03:43:35 PM PDT 24
Peak memory 204988 kb
Host smart-ad41df53-8a45-4ae6-9470-e7f067af80c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25798
39362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2579839362
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.3376172402
Short name T307
Test name
Test status
Simulation time 10073120177 ps
CPU time 13.45 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:51 PM PDT 24
Peak memory 204920 kb
Host smart-d72a2d66-7f28-463b-9d4e-ea72d3d4ac24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33761
72402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.3376172402
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2267890471
Short name T1189
Test name
Test status
Simulation time 10043925183 ps
CPU time 14.35 seconds
Started May 23 03:43:24 PM PDT 24
Finished May 23 03:43:43 PM PDT 24
Peak memory 204912 kb
Host smart-cf63d8f1-0167-4100-a49f-5288e00765dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22678
90471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2267890471
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.4089243655
Short name T1466
Test name
Test status
Simulation time 10041303356 ps
CPU time 14.97 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:56 PM PDT 24
Peak memory 204932 kb
Host smart-bfb7902e-4e3b-4e12-8e27-67ad845c463e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40892
43655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.4089243655
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1048446372
Short name T250
Test name
Test status
Simulation time 23105137461 ps
CPU time 41.28 seconds
Started May 23 03:43:25 PM PDT 24
Finished May 23 03:44:11 PM PDT 24
Peak memory 205044 kb
Host smart-aae2beaa-b2a3-4a2e-83c3-602a1098b18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10484
46372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1048446372
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.732353689
Short name T644
Test name
Test status
Simulation time 10075998358 ps
CPU time 13.17 seconds
Started May 23 03:43:22 PM PDT 24
Finished May 23 03:43:40 PM PDT 24
Peak memory 204940 kb
Host smart-d1a4e9d8-4e69-4c87-82ef-8e597646cf1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73235
3689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.732353689
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1218289735
Short name T487
Test name
Test status
Simulation time 10079453629 ps
CPU time 13.58 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:53 PM PDT 24
Peak memory 204932 kb
Host smart-bea26079-2b9b-4fb2-8ad4-01615058e45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12182
89735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1218289735
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3372235823
Short name T1585
Test name
Test status
Simulation time 10068255757 ps
CPU time 13.72 seconds
Started May 23 03:43:25 PM PDT 24
Finished May 23 03:43:44 PM PDT 24
Peak memory 205008 kb
Host smart-91c3481a-1ee9-400c-b904-0dc8bb86a460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33722
35823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3372235823
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3502227461
Short name T334
Test name
Test status
Simulation time 10065598888 ps
CPU time 15.47 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:53 PM PDT 24
Peak memory 204968 kb
Host smart-1275c427-afe9-42ec-ab49-8c92dc859190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35022
27461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3502227461
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3632324534
Short name T1746
Test name
Test status
Simulation time 10074561248 ps
CPU time 15.54 seconds
Started May 23 03:43:20 PM PDT 24
Finished May 23 03:43:40 PM PDT 24
Peak memory 205000 kb
Host smart-b9b32d3f-5a32-457f-82d7-60a2256f6f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36323
24534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3632324534
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3887955840
Short name T1116
Test name
Test status
Simulation time 10063864872 ps
CPU time 13.2 seconds
Started May 23 03:43:29 PM PDT 24
Finished May 23 03:43:47 PM PDT 24
Peak memory 205000 kb
Host smart-acddddfd-1e0d-493e-8c42-8791a002beb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38879
55840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3887955840
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.469911873
Short name T88
Test name
Test status
Simulation time 10099261236 ps
CPU time 13.16 seconds
Started May 23 03:43:38 PM PDT 24
Finished May 23 03:43:59 PM PDT 24
Peak memory 205036 kb
Host smart-579bbd00-a949-408b-90d7-babfb620a92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46991
1873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.469911873
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1087025552
Short name T911
Test name
Test status
Simulation time 10113704178 ps
CPU time 14.58 seconds
Started May 23 03:43:27 PM PDT 24
Finished May 23 03:43:47 PM PDT 24
Peak memory 204928 kb
Host smart-5a7d417b-f522-495b-a0e6-9e32c22a7741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10870
25552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1087025552
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3959195619
Short name T1933
Test name
Test status
Simulation time 10064419884 ps
CPU time 13.26 seconds
Started May 23 03:43:23 PM PDT 24
Finished May 23 03:43:40 PM PDT 24
Peak memory 204960 kb
Host smart-5950622a-6409-4522-bab1-879ab8c96637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39591
95619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3959195619
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.1181743930
Short name T1540
Test name
Test status
Simulation time 10160484757 ps
CPU time 14.66 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:52 PM PDT 24
Peak memory 204944 kb
Host smart-28cd95b9-67ce-43fe-9b4c-b2f339b50f2a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1181743930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.1181743930
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.1667117996
Short name T1491
Test name
Test status
Simulation time 10060931571 ps
CPU time 14.34 seconds
Started May 23 03:43:38 PM PDT 24
Finished May 23 03:43:59 PM PDT 24
Peak memory 204836 kb
Host smart-aa209f6b-5ec2-4e9b-96c9-cdb26da18b6d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1667117996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.1667117996
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.238990778
Short name T1625
Test name
Test status
Simulation time 10121988409 ps
CPU time 14.07 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:49 PM PDT 24
Peak memory 204776 kb
Host smart-82a2184a-460c-419e-8fdc-609777d18e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23899
0778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.238990778
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.92163359
Short name T852
Test name
Test status
Simulation time 13997733233 ps
CPU time 18.58 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:56 PM PDT 24
Peak memory 205032 kb
Host smart-8033b331-4a3e-427b-b470-82bc773b70e1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=92163359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.92163359
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.900294589
Short name T1635
Test name
Test status
Simulation time 13268893398 ps
CPU time 20.89 seconds
Started May 23 03:43:21 PM PDT 24
Finished May 23 03:43:46 PM PDT 24
Peak memory 204948 kb
Host smart-5e495643-4641-4bde-af34-6d685bde9cc5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=900294589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.900294589
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.2089183801
Short name T814
Test name
Test status
Simulation time 13323049284 ps
CPU time 18.05 seconds
Started May 23 03:43:17 PM PDT 24
Finished May 23 03:43:40 PM PDT 24
Peak memory 204960 kb
Host smart-f71da58e-47ab-445c-a163-82bb75b7d4be
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2089183801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.2089183801
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.4174872793
Short name T698
Test name
Test status
Simulation time 10058929639 ps
CPU time 14.47 seconds
Started May 23 03:43:20 PM PDT 24
Finished May 23 03:43:39 PM PDT 24
Peak memory 204936 kb
Host smart-e16acd84-7b45-45be-a5d1-adccea6cf1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748
72793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.4174872793
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1421917656
Short name T1677
Test name
Test status
Simulation time 10234846966 ps
CPU time 13.74 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:51 PM PDT 24
Peak memory 204960 kb
Host smart-4eff1818-ef3b-477f-9ae4-9cca77cb480f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
17656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1421917656
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2335781163
Short name T1648
Test name
Test status
Simulation time 10043314257 ps
CPU time 13.29 seconds
Started May 23 03:43:30 PM PDT 24
Finished May 23 03:43:48 PM PDT 24
Peak memory 204956 kb
Host smart-4e614012-1099-426e-a4ce-88adba3d8dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23357
81163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2335781163
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3083342917
Short name T468
Test name
Test status
Simulation time 10080620285 ps
CPU time 12.99 seconds
Started May 23 03:43:23 PM PDT 24
Finished May 23 03:43:40 PM PDT 24
Peak memory 204912 kb
Host smart-0a37f7c9-dd40-4aff-93fd-015651e80ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30833
42917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3083342917
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.2020078898
Short name T637
Test name
Test status
Simulation time 10702327786 ps
CPU time 15.61 seconds
Started May 23 03:43:13 PM PDT 24
Finished May 23 03:43:35 PM PDT 24
Peak memory 204932 kb
Host smart-01ed1455-b14b-49f9-a1e6-c2474719747b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20200
78898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2020078898
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1814055315
Short name T862
Test name
Test status
Simulation time 10230270249 ps
CPU time 14.59 seconds
Started May 23 03:43:37 PM PDT 24
Finished May 23 03:43:59 PM PDT 24
Peak memory 204928 kb
Host smart-9602f027-4f5e-4e79-8e2a-746adbb9bf14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18140
55315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1814055315
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1435299426
Short name T1676
Test name
Test status
Simulation time 10087731592 ps
CPU time 13.34 seconds
Started May 23 03:43:36 PM PDT 24
Finished May 23 03:43:56 PM PDT 24
Peak memory 204908 kb
Host smart-b3c0548d-fe6d-4fdc-951e-1786f432cf12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14352
99426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1435299426
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1204651062
Short name T327
Test name
Test status
Simulation time 10062569424 ps
CPU time 13.18 seconds
Started May 23 03:43:41 PM PDT 24
Finished May 23 03:44:02 PM PDT 24
Peak memory 204928 kb
Host smart-90e7404e-6de4-44bd-8065-c9a6de337543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12046
51062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1204651062
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.4016062746
Short name T324
Test name
Test status
Simulation time 10072967046 ps
CPU time 14.1 seconds
Started May 23 03:43:38 PM PDT 24
Finished May 23 03:43:59 PM PDT 24
Peak memory 204984 kb
Host smart-a80d42bc-7d0d-476f-84bf-67c340f29fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40160
62746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.4016062746
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.147950612
Short name T1833
Test name
Test status
Simulation time 10082184190 ps
CPU time 15.32 seconds
Started May 23 03:43:40 PM PDT 24
Finished May 23 03:44:03 PM PDT 24
Peak memory 204964 kb
Host smart-f4f4b519-be68-434b-8171-bddce7ebb85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14795
0612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.147950612
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.2565542998
Short name T701
Test name
Test status
Simulation time 13190380715 ps
CPU time 16.2 seconds
Started May 23 03:43:40 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 204996 kb
Host smart-b75ef574-35a3-41df-a411-48103e7dfb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25655
42998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.2565542998
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2081119519
Short name T703
Test name
Test status
Simulation time 10110826261 ps
CPU time 14.51 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:54 PM PDT 24
Peak memory 204884 kb
Host smart-29e01e62-007b-4db2-b09e-ba9929aa2c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20811
19519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2081119519
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3376092659
Short name T1840
Test name
Test status
Simulation time 10061663271 ps
CPU time 13.2 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:48 PM PDT 24
Peak memory 204964 kb
Host smart-92e87005-aba9-48e1-a545-cf4d79eebb40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33760
92659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3376092659
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2730596416
Short name T132
Test name
Test status
Simulation time 10116364681 ps
CPU time 14.06 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:50 PM PDT 24
Peak memory 205000 kb
Host smart-eb6e7304-b796-4aed-a989-3fa785473bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27305
96416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2730596416
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.3245902240
Short name T550
Test name
Test status
Simulation time 10093425114 ps
CPU time 12.91 seconds
Started May 23 03:43:40 PM PDT 24
Finished May 23 03:44:02 PM PDT 24
Peak memory 204948 kb
Host smart-49552ad5-b0bb-4d45-bd6c-cf86b8cd7a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32459
02240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.3245902240
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2406709194
Short name T1538
Test name
Test status
Simulation time 10073061098 ps
CPU time 14.12 seconds
Started May 23 03:43:40 PM PDT 24
Finished May 23 03:44:03 PM PDT 24
Peak memory 204956 kb
Host smart-a05936c9-06d9-451f-9576-6a943df8035a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24067
09194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2406709194
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3967983223
Short name T1387
Test name
Test status
Simulation time 10058244085 ps
CPU time 12.61 seconds
Started May 23 03:43:38 PM PDT 24
Finished May 23 03:43:59 PM PDT 24
Peak memory 204920 kb
Host smart-46845cbd-e3ff-48f5-8307-2b778df3bd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39679
83223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3967983223
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2886741642
Short name T1617
Test name
Test status
Simulation time 10128697968 ps
CPU time 13.49 seconds
Started May 23 03:43:39 PM PDT 24
Finished May 23 03:44:01 PM PDT 24
Peak memory 204960 kb
Host smart-2d66eaa8-4089-4100-8c25-a2378f0e7ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28867
41642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2886741642
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.1297703972
Short name T1813
Test name
Test status
Simulation time 10069627457 ps
CPU time 14.35 seconds
Started May 23 03:43:35 PM PDT 24
Finished May 23 03:43:56 PM PDT 24
Peak memory 204944 kb
Host smart-a6851c30-cab4-48b0-b838-54e95b8ac677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12977
03972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.1297703972
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3094892588
Short name T581
Test name
Test status
Simulation time 10051584210 ps
CPU time 13.29 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:04 PM PDT 24
Peak memory 204928 kb
Host smart-1e754183-81f6-4240-bf51-ac3a67c0ef32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30948
92588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3094892588
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.571367282
Short name T1119
Test name
Test status
Simulation time 10053579510 ps
CPU time 15.19 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:51 PM PDT 24
Peak memory 204932 kb
Host smart-4f06921f-5b87-4103-8b94-70339c4677f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57136
7282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.571367282
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1410142697
Short name T1862
Test name
Test status
Simulation time 32446585958 ps
CPU time 64.9 seconds
Started May 23 03:43:37 PM PDT 24
Finished May 23 03:44:49 PM PDT 24
Peak memory 205008 kb
Host smart-929a4e53-1e0b-477d-aa19-a01db16a4ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14101
42697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1410142697
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2829805859
Short name T639
Test name
Test status
Simulation time 10099115169 ps
CPU time 13.25 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:53 PM PDT 24
Peak memory 204960 kb
Host smart-98c84617-51fc-47b0-be1f-433e6c16e2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28298
05859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2829805859
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3121100740
Short name T1081
Test name
Test status
Simulation time 10087348582 ps
CPU time 15.32 seconds
Started May 23 03:43:39 PM PDT 24
Finished May 23 03:44:02 PM PDT 24
Peak memory 204880 kb
Host smart-e0769451-43c9-41c3-b60b-ccf7bc9b073e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31211
00740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3121100740
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3340730482
Short name T671
Test name
Test status
Simulation time 10135174734 ps
CPU time 13.37 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:49 PM PDT 24
Peak memory 204884 kb
Host smart-140f2909-06fd-4fbd-bb67-59b90e02e950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33407
30482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3340730482
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.917418434
Short name T795
Test name
Test status
Simulation time 10048083339 ps
CPU time 15.82 seconds
Started May 23 03:43:41 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 205020 kb
Host smart-e26144b6-fa8b-4eb9-b317-091e12b40b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91741
8434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.917418434
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2620309985
Short name T1183
Test name
Test status
Simulation time 10061971032 ps
CPU time 13.29 seconds
Started May 23 03:43:38 PM PDT 24
Finished May 23 03:43:58 PM PDT 24
Peak memory 204916 kb
Host smart-e862c9c8-5f5a-45f0-9b8b-a7bdaf203ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26203
09985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2620309985
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.197420934
Short name T442
Test name
Test status
Simulation time 10079205246 ps
CPU time 13.71 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:49 PM PDT 24
Peak memory 204964 kb
Host smart-e6f015f0-20bf-47a6-8d86-92d68612ed1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19742
0934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.197420934
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3989748958
Short name T766
Test name
Test status
Simulation time 10153936242 ps
CPU time 13.78 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:53 PM PDT 24
Peak memory 205000 kb
Host smart-f4ecf8ba-3e09-444d-8b3a-f0708dbba8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39897
48958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3989748958
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2081409646
Short name T573
Test name
Test status
Simulation time 10053042420 ps
CPU time 13.69 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:49 PM PDT 24
Peak memory 204920 kb
Host smart-80a79942-fd08-4a5e-9201-36d5308d8833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20814
09646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2081409646
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1003754491
Short name T1383
Test name
Test status
Simulation time 10075727831 ps
CPU time 14.29 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:55 PM PDT 24
Peak memory 204940 kb
Host smart-38e5e9e5-4847-409a-9079-cab8f993cb48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10037
54491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1003754491
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.3319287848
Short name T589
Test name
Test status
Simulation time 10130789194 ps
CPU time 15.95 seconds
Started May 23 03:39:59 PM PDT 24
Finished May 23 03:40:26 PM PDT 24
Peak memory 204980 kb
Host smart-e796e5ed-c707-4ae8-be30-5cafc11f667f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3319287848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.3319287848
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.2240294288
Short name T532
Test name
Test status
Simulation time 10071889449 ps
CPU time 12.48 seconds
Started May 23 03:40:03 PM PDT 24
Finished May 23 03:40:25 PM PDT 24
Peak memory 204980 kb
Host smart-0fd2b088-8949-430f-93f2-b75a08e946d5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2240294288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.2240294288
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.264645691
Short name T1728
Test name
Test status
Simulation time 10187614359 ps
CPU time 14.36 seconds
Started May 23 03:40:14 PM PDT 24
Finished May 23 03:40:38 PM PDT 24
Peak memory 204968 kb
Host smart-90da160f-9413-4c03-9747-9e8ae5420256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26464
5691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.264645691
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2806181410
Short name T492
Test name
Test status
Simulation time 13437344159 ps
CPU time 17.13 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:14 PM PDT 24
Peak memory 204932 kb
Host smart-4c82e32c-25eb-478a-9285-862f1de1a8d8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2806181410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.2806181410
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2015987102
Short name T941
Test name
Test status
Simulation time 13290873167 ps
CPU time 18.27 seconds
Started May 23 03:39:53 PM PDT 24
Finished May 23 03:40:23 PM PDT 24
Peak memory 204932 kb
Host smart-3bfa92f7-2fe6-4a77-b189-9762dd40709e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2015987102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2015987102
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.2382927651
Short name T41
Test name
Test status
Simulation time 13424549555 ps
CPU time 16.53 seconds
Started May 23 03:39:50 PM PDT 24
Finished May 23 03:40:16 PM PDT 24
Peak memory 204916 kb
Host smart-f9f86af3-fc6c-4ab0-ae92-a8ddf12607fa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2382927651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.2382927651
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1794768368
Short name T653
Test name
Test status
Simulation time 10088519870 ps
CPU time 14.82 seconds
Started May 23 03:39:50 PM PDT 24
Finished May 23 03:40:13 PM PDT 24
Peak memory 204960 kb
Host smart-bc4a0e3f-ee09-4e75-8709-8e23e431897d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17947
68368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1794768368
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.439868474
Short name T1095
Test name
Test status
Simulation time 10852096395 ps
CPU time 15.11 seconds
Started May 23 03:39:38 PM PDT 24
Finished May 23 03:39:59 PM PDT 24
Peak memory 204980 kb
Host smart-086b553f-058e-484b-b56b-4558ebecafc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43986
8474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.439868474
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2377011587
Short name T1847
Test name
Test status
Simulation time 10043582257 ps
CPU time 12.86 seconds
Started May 23 03:39:45 PM PDT 24
Finished May 23 03:40:03 PM PDT 24
Peak memory 204932 kb
Host smart-5d0c1f93-6810-4223-8863-eba393013328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23770
11587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2377011587
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2491785444
Short name T1266
Test name
Test status
Simulation time 10117615024 ps
CPU time 13.93 seconds
Started May 23 03:39:53 PM PDT 24
Finished May 23 03:40:18 PM PDT 24
Peak memory 205000 kb
Host smart-286bc7de-c9c0-4d6f-be94-533edd4e50ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24917
85444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2491785444
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3252341170
Short name T472
Test name
Test status
Simulation time 10854188289 ps
CPU time 16.62 seconds
Started May 23 03:39:49 PM PDT 24
Finished May 23 03:40:13 PM PDT 24
Peak memory 204952 kb
Host smart-0115ff0e-9331-4095-ad95-345a96b86514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32523
41170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3252341170
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2105016896
Short name T568
Test name
Test status
Simulation time 10127506069 ps
CPU time 15.62 seconds
Started May 23 03:39:50 PM PDT 24
Finished May 23 03:40:14 PM PDT 24
Peak memory 204952 kb
Host smart-38718b2f-0f77-49ad-8351-08d4e1ce2b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21050
16896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2105016896
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.4202073700
Short name T1063
Test name
Test status
Simulation time 10122938571 ps
CPU time 14.09 seconds
Started May 23 03:39:51 PM PDT 24
Finished May 23 03:40:14 PM PDT 24
Peak memory 204952 kb
Host smart-593fe986-f7a6-4913-814d-d356acd24007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42020
73700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.4202073700
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1355484825
Short name T600
Test name
Test status
Simulation time 10036746397 ps
CPU time 15.48 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:34 PM PDT 24
Peak memory 204968 kb
Host smart-c173eeb0-5e76-4775-b397-255e6820cd1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13554
84825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1355484825
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3167463051
Short name T1281
Test name
Test status
Simulation time 10093911700 ps
CPU time 13.57 seconds
Started May 23 03:39:47 PM PDT 24
Finished May 23 03:40:07 PM PDT 24
Peak memory 204956 kb
Host smart-9a3ec8f0-811f-46cb-b7ad-8a619113d9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31674
63051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3167463051
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.439727924
Short name T804
Test name
Test status
Simulation time 10098232536 ps
CPU time 13.66 seconds
Started May 23 03:39:42 PM PDT 24
Finished May 23 03:40:00 PM PDT 24
Peak memory 204920 kb
Host smart-683d9ec2-6464-4bf7-83da-81f331f2f95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43972
7924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.439727924
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.153763118
Short name T1849
Test name
Test status
Simulation time 13250784684 ps
CPU time 18.52 seconds
Started May 23 03:39:50 PM PDT 24
Finished May 23 03:40:16 PM PDT 24
Peak memory 204968 kb
Host smart-a999de4f-0db8-470b-a41c-49a2214d0661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15376
3118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.153763118
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3224468560
Short name T675
Test name
Test status
Simulation time 10120320244 ps
CPU time 14.17 seconds
Started May 23 03:39:45 PM PDT 24
Finished May 23 03:40:04 PM PDT 24
Peak memory 204960 kb
Host smart-32bf5d46-db79-45ad-b70a-44d36eb64dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32244
68560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3224468560
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2373015376
Short name T601
Test name
Test status
Simulation time 10046772815 ps
CPU time 12.37 seconds
Started May 23 03:39:50 PM PDT 24
Finished May 23 03:40:11 PM PDT 24
Peak memory 204916 kb
Host smart-51cd7095-9825-448b-a229-fc78f139a743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23730
15376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2373015376
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2077497755
Short name T1465
Test name
Test status
Simulation time 10108123462 ps
CPU time 12.9 seconds
Started May 23 03:39:52 PM PDT 24
Finished May 23 03:40:15 PM PDT 24
Peak memory 204956 kb
Host smart-bec70be0-7d38-4356-94ac-f370d07405d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20774
97755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2077497755
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.207261712
Short name T848
Test name
Test status
Simulation time 10085976580 ps
CPU time 14.21 seconds
Started May 23 03:39:46 PM PDT 24
Finished May 23 03:40:05 PM PDT 24
Peak memory 204876 kb
Host smart-45f5bdac-d152-4736-9039-109378eed4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20726
1712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.207261712
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.273020488
Short name T719
Test name
Test status
Simulation time 10094271136 ps
CPU time 15.92 seconds
Started May 23 03:39:53 PM PDT 24
Finished May 23 03:40:20 PM PDT 24
Peak memory 204920 kb
Host smart-9cdf45cc-6871-4f5e-8ade-a6732213d67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27302
0488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.273020488
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1318614926
Short name T1099
Test name
Test status
Simulation time 10137055829 ps
CPU time 13.11 seconds
Started May 23 03:39:48 PM PDT 24
Finished May 23 03:40:08 PM PDT 24
Peak memory 204920 kb
Host smart-eea16a77-cec2-4741-b3ba-8a24889999d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13186
14926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1318614926
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2310577057
Short name T180
Test name
Test status
Simulation time 10116486149 ps
CPU time 12.64 seconds
Started May 23 03:40:03 PM PDT 24
Finished May 23 03:40:25 PM PDT 24
Peak memory 204988 kb
Host smart-44186dc4-a460-4c0a-ba70-1b338130e8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23105
77057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2310577057
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.1997832480
Short name T18
Test name
Test status
Simulation time 10084353634 ps
CPU time 14.43 seconds
Started May 23 03:39:53 PM PDT 24
Finished May 23 03:40:18 PM PDT 24
Peak memory 204976 kb
Host smart-1ff1b8f9-821c-45d8-898e-e47b35ebf333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19978
32480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.1997832480
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3731208692
Short name T1289
Test name
Test status
Simulation time 10055857484 ps
CPU time 15.74 seconds
Started May 23 03:39:58 PM PDT 24
Finished May 23 03:40:25 PM PDT 24
Peak memory 204964 kb
Host smart-eea9cab0-062a-490f-a2c4-4ac911ea256a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37312
08692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3731208692
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2269298308
Short name T1850
Test name
Test status
Simulation time 10045956908 ps
CPU time 13.5 seconds
Started May 23 03:40:01 PM PDT 24
Finished May 23 03:40:24 PM PDT 24
Peak memory 204940 kb
Host smart-875c08d6-5365-4e88-afee-0a6608c4350d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22692
98308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2269298308
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1861167225
Short name T925
Test name
Test status
Simulation time 18327809795 ps
CPU time 32.92 seconds
Started May 23 03:39:50 PM PDT 24
Finished May 23 03:40:31 PM PDT 24
Peak memory 205028 kb
Host smart-d3321414-3fe5-4324-b23a-997a66befdea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18611
67225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1861167225
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2524778143
Short name T1600
Test name
Test status
Simulation time 10072656767 ps
CPU time 13.52 seconds
Started May 23 03:39:53 PM PDT 24
Finished May 23 03:40:17 PM PDT 24
Peak memory 204956 kb
Host smart-c2f278fc-bdcf-422c-a1ac-97f4e5aa90d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25247
78143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2524778143
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.4090366672
Short name T548
Test name
Test status
Simulation time 10118693939 ps
CPU time 13.28 seconds
Started May 23 03:40:03 PM PDT 24
Finished May 23 03:40:26 PM PDT 24
Peak memory 204968 kb
Host smart-a20df3ac-57e8-4067-89f3-72395af81437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40903
66672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.4090366672
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.1794760638
Short name T1658
Test name
Test status
Simulation time 10106043166 ps
CPU time 13.22 seconds
Started May 23 03:39:56 PM PDT 24
Finished May 23 03:40:20 PM PDT 24
Peak memory 204988 kb
Host smart-c568bd2f-625e-4350-aec1-fb7b28076e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17947
60638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.1794760638
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3358719245
Short name T1199
Test name
Test status
Simulation time 10051997836 ps
CPU time 15.66 seconds
Started May 23 03:39:57 PM PDT 24
Finished May 23 03:40:23 PM PDT 24
Peak memory 204972 kb
Host smart-c636f3ef-75fd-4dc4-bd0a-aae8ffc31248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33587
19245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3358719245
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3715919442
Short name T198
Test name
Test status
Simulation time 1110003012 ps
CPU time 1.96 seconds
Started May 23 03:39:54 PM PDT 24
Finished May 23 03:40:07 PM PDT 24
Peak memory 221892 kb
Host smart-69bd2145-a7b9-42d9-8a1a-6caf5eee68d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3715919442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3715919442
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2687406551
Short name T1831
Test name
Test status
Simulation time 10054476513 ps
CPU time 13.34 seconds
Started May 23 03:39:53 PM PDT 24
Finished May 23 03:40:18 PM PDT 24
Peak memory 205000 kb
Host smart-e3a92237-669a-4ec2-a0ab-f801e67aae70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26874
06551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2687406551
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1952152656
Short name T1200
Test name
Test status
Simulation time 10077582749 ps
CPU time 13.77 seconds
Started May 23 03:39:56 PM PDT 24
Finished May 23 03:40:21 PM PDT 24
Peak memory 204704 kb
Host smart-542dcdbb-96be-4197-993f-b38cdb4f5df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19521
52656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1952152656
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1288092413
Short name T1794
Test name
Test status
Simulation time 10156350149 ps
CPU time 14.17 seconds
Started May 23 03:39:40 PM PDT 24
Finished May 23 03:39:59 PM PDT 24
Peak memory 205052 kb
Host smart-23b77ee6-a6d1-4aa6-a5ec-39562345f4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12880
92413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1288092413
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3283411566
Short name T1178
Test name
Test status
Simulation time 10102119050 ps
CPU time 15.15 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:37 PM PDT 24
Peak memory 204900 kb
Host smart-cc591d9c-699f-41b4-8b35-1150cb15df51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32834
11566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3283411566
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1877952127
Short name T1254
Test name
Test status
Simulation time 10083597633 ps
CPU time 15.06 seconds
Started May 23 03:40:04 PM PDT 24
Finished May 23 03:40:28 PM PDT 24
Peak memory 204964 kb
Host smart-3d7d64fa-4f20-41fc-ac93-78e081726d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18779
52127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1877952127
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.3642284976
Short name T561
Test name
Test status
Simulation time 10139265763 ps
CPU time 13.24 seconds
Started May 23 03:43:46 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 205028 kb
Host smart-22c5617b-8f34-402c-8b20-2bbdbdd7af4b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3642284976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.3642284976
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.577482305
Short name T438
Test name
Test status
Simulation time 10083560863 ps
CPU time 13.57 seconds
Started May 23 03:43:37 PM PDT 24
Finished May 23 03:43:58 PM PDT 24
Peak memory 205008 kb
Host smart-a68a098c-2edb-4b8f-9ca4-b204d79031d7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=577482305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.577482305
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.2185521936
Short name T1161
Test name
Test status
Simulation time 10153353969 ps
CPU time 14.58 seconds
Started May 23 03:43:36 PM PDT 24
Finished May 23 03:43:57 PM PDT 24
Peak memory 204960 kb
Host smart-8d11f3b3-9211-4f31-863b-9b20d2ad7710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21855
21936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.2185521936
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.4175166543
Short name T771
Test name
Test status
Simulation time 13496925070 ps
CPU time 15.94 seconds
Started May 23 03:43:35 PM PDT 24
Finished May 23 03:43:58 PM PDT 24
Peak memory 204916 kb
Host smart-a472536e-47f6-47d9-8872-ab95e52f8e01
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4175166543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.4175166543
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2970026270
Short name T1261
Test name
Test status
Simulation time 13277660043 ps
CPU time 16.53 seconds
Started May 23 03:43:36 PM PDT 24
Finished May 23 03:43:58 PM PDT 24
Peak memory 204912 kb
Host smart-c0b9937c-8b13-4284-985d-32a76db3cf6a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2970026270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2970026270
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3076949891
Short name T7
Test name
Test status
Simulation time 13207728075 ps
CPU time 16 seconds
Started May 23 03:43:38 PM PDT 24
Finished May 23 03:44:01 PM PDT 24
Peak memory 204948 kb
Host smart-3e844ab0-c38e-454a-9637-47accfc3e959
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3076949891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3076949891
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2858313928
Short name T1091
Test name
Test status
Simulation time 10084302359 ps
CPU time 13.65 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:53 PM PDT 24
Peak memory 204932 kb
Host smart-1e4105fc-0e75-48ab-b590-81fc6cb8cdf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28583
13928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2858313928
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.1093392730
Short name T53
Test name
Test status
Simulation time 10124865295 ps
CPU time 15.23 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:51 PM PDT 24
Peak memory 204908 kb
Host smart-58add722-6821-413f-bec7-03760a0b5ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10933
92730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.1093392730
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.722029426
Short name T54
Test name
Test status
Simulation time 10635638143 ps
CPU time 16.18 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:54 PM PDT 24
Peak memory 204964 kb
Host smart-7fb1bf75-0fd8-4459-a02a-9ecfc0155fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72202
9426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.722029426
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3529328243
Short name T1894
Test name
Test status
Simulation time 10130472067 ps
CPU time 12.82 seconds
Started May 23 03:43:35 PM PDT 24
Finished May 23 03:43:54 PM PDT 24
Peak memory 204972 kb
Host smart-25643cb6-618f-48e9-b6f4-d88aa9310791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35293
28243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3529328243
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.313330118
Short name T356
Test name
Test status
Simulation time 10060395586 ps
CPU time 13.97 seconds
Started May 23 03:43:39 PM PDT 24
Finished May 23 03:44:00 PM PDT 24
Peak memory 205020 kb
Host smart-f7f43176-5b2e-470a-a83b-2457581f1d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31333
0118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.313330118
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2667414564
Short name T661
Test name
Test status
Simulation time 10704667912 ps
CPU time 13.52 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:54 PM PDT 24
Peak memory 204908 kb
Host smart-6982b0c2-162b-4d52-918c-60503551cdc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26674
14564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2667414564
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3202538188
Short name T618
Test name
Test status
Simulation time 10176838706 ps
CPU time 14.07 seconds
Started May 23 03:43:39 PM PDT 24
Finished May 23 03:44:01 PM PDT 24
Peak memory 204908 kb
Host smart-3743474e-e3f9-4e33-902c-00b96185ca82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32025
38188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3202538188
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.2644643946
Short name T1062
Test name
Test status
Simulation time 10204533932 ps
CPU time 15.71 seconds
Started May 23 03:43:36 PM PDT 24
Finished May 23 03:43:59 PM PDT 24
Peak memory 204956 kb
Host smart-b8c25454-b540-44ce-be8b-c9a99d386928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26446
43946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2644643946
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.381027693
Short name T1188
Test name
Test status
Simulation time 10050126684 ps
CPU time 15.2 seconds
Started May 23 03:43:46 PM PDT 24
Finished May 23 03:44:09 PM PDT 24
Peak memory 205000 kb
Host smart-b8652b0c-501d-4774-a8b9-66ebff3fbbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38102
7693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.381027693
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1825494649
Short name T1512
Test name
Test status
Simulation time 10127845219 ps
CPU time 13.03 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:48 PM PDT 24
Peak memory 205008 kb
Host smart-cc7fe89c-0adf-4b20-8fe2-e8e3802a863b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18254
94649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1825494649
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2192746074
Short name T1282
Test name
Test status
Simulation time 10098848226 ps
CPU time 12.78 seconds
Started May 23 03:43:40 PM PDT 24
Finished May 23 03:44:01 PM PDT 24
Peak memory 204980 kb
Host smart-c74ebf77-f235-47db-a1c7-c91c8c1e7e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21927
46074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2192746074
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.1859415197
Short name T24
Test name
Test status
Simulation time 13260662552 ps
CPU time 15.41 seconds
Started May 23 03:43:33 PM PDT 24
Finished May 23 03:43:54 PM PDT 24
Peak memory 204960 kb
Host smart-1ce134c6-5e4b-4647-b53a-4bb380538918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18594
15197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.1859415197
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2927442456
Short name T1370
Test name
Test status
Simulation time 10090210798 ps
CPU time 13.26 seconds
Started May 23 03:43:37 PM PDT 24
Finished May 23 03:43:57 PM PDT 24
Peak memory 204972 kb
Host smart-a7fd6d23-e531-4591-89d5-599402b93131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29274
42456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2927442456
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3039756075
Short name T494
Test name
Test status
Simulation time 10079871924 ps
CPU time 16.58 seconds
Started May 23 03:43:37 PM PDT 24
Finished May 23 03:44:01 PM PDT 24
Peak memory 204872 kb
Host smart-ab6a5d76-63eb-4e9c-b041-429af5d29aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30397
56075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3039756075
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1114612133
Short name T106
Test name
Test status
Simulation time 10110290898 ps
CPU time 14.04 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:52 PM PDT 24
Peak memory 204904 kb
Host smart-55cf2cbc-a4b7-4dec-9410-26bb021fa634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11146
12133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1114612133
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1853977990
Short name T1750
Test name
Test status
Simulation time 10089699329 ps
CPU time 14.37 seconds
Started May 23 03:43:33 PM PDT 24
Finished May 23 03:43:52 PM PDT 24
Peak memory 204968 kb
Host smart-b2e544c2-0577-4788-b783-8f6d1244c4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18539
77990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1853977990
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.280801593
Short name T1929
Test name
Test status
Simulation time 10061691178 ps
CPU time 15.32 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:55 PM PDT 24
Peak memory 204912 kb
Host smart-b35f7840-2b5c-4c2d-8dfa-7bb6fd83fd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28080
1593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.280801593
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1604657640
Short name T1240
Test name
Test status
Simulation time 10058854129 ps
CPU time 12.99 seconds
Started May 23 03:43:36 PM PDT 24
Finished May 23 03:43:55 PM PDT 24
Peak memory 205004 kb
Host smart-dc570b08-f860-4cae-8cc1-f9e060881591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16046
57640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1604657640
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1644123392
Short name T1882
Test name
Test status
Simulation time 10108740625 ps
CPU time 13.74 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:50 PM PDT 24
Peak memory 204956 kb
Host smart-9e0354b2-44db-43c5-8ec4-34535e2fa3dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16441
23392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1644123392
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.1131978163
Short name T819
Test name
Test status
Simulation time 10072408330 ps
CPU time 13.62 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:53 PM PDT 24
Peak memory 204988 kb
Host smart-93a8dbcc-2ae9-488f-8d56-06d6e8c89de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11319
78163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.1131978163
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3947740573
Short name T664
Test name
Test status
Simulation time 10080097400 ps
CPU time 15.18 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 204972 kb
Host smart-38ed7809-e6a5-4b37-8174-509682f417d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39477
40573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3947740573
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3994501874
Short name T1899
Test name
Test status
Simulation time 10038726511 ps
CPU time 14.29 seconds
Started May 23 03:43:37 PM PDT 24
Finished May 23 03:43:58 PM PDT 24
Peak memory 204956 kb
Host smart-fcca92a5-830e-4d43-b417-14b57f12dc7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39945
01874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3994501874
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.927269571
Short name T272
Test name
Test status
Simulation time 27059153969 ps
CPU time 51.65 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:44:27 PM PDT 24
Peak memory 204780 kb
Host smart-bb120a23-a089-4f86-9d73-76f8b08bac3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92726
9571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.927269571
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3588804883
Short name T711
Test name
Test status
Simulation time 10114318445 ps
CPU time 13.27 seconds
Started May 23 03:43:33 PM PDT 24
Finished May 23 03:43:52 PM PDT 24
Peak memory 204976 kb
Host smart-6e0eb6e7-d1e9-49e7-9bb8-7656b62f7687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35888
04883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3588804883
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1156466579
Short name T1944
Test name
Test status
Simulation time 10096315857 ps
CPU time 14.3 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:51 PM PDT 24
Peak memory 204964 kb
Host smart-a305a025-372e-456f-89a2-8604d53d570d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11564
66579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1156466579
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.1734004224
Short name T654
Test name
Test status
Simulation time 10116705518 ps
CPU time 12.96 seconds
Started May 23 03:43:36 PM PDT 24
Finished May 23 03:43:55 PM PDT 24
Peak memory 204992 kb
Host smart-44b2e376-f3be-4ad2-8886-563460124a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17340
04224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.1734004224
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.1363052905
Short name T1725
Test name
Test status
Simulation time 10069559935 ps
CPU time 15.7 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 205048 kb
Host smart-aa028884-b0ca-4084-ab8a-b5a111e9f98b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13630
52905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.1363052905
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2007071456
Short name T1923
Test name
Test status
Simulation time 10044084398 ps
CPU time 15.57 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:56 PM PDT 24
Peak memory 204984 kb
Host smart-85c221ff-f42f-416c-bb8e-f3c7fc4454d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20070
71456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2007071456
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.759169463
Short name T311
Test name
Test status
Simulation time 10093249288 ps
CPU time 13.83 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 204976 kb
Host smart-def6f44f-524e-46a6-b67b-ffc13ae49c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75916
9463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.759169463
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3337337571
Short name T89
Test name
Test status
Simulation time 10116467891 ps
CPU time 13.96 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 204984 kb
Host smart-86280fa0-161c-4dc7-a07e-ed7b10c9417c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33373
37571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3337337571
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.3961653101
Short name T1280
Test name
Test status
Simulation time 10118530661 ps
CPU time 13.18 seconds
Started May 23 03:43:37 PM PDT 24
Finished May 23 03:43:57 PM PDT 24
Peak memory 204936 kb
Host smart-2af8e0c7-4c47-414b-876e-0227fbbf7c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39616
53101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.3961653101
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.859334244
Short name T1159
Test name
Test status
Simulation time 10079176178 ps
CPU time 13.64 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 205056 kb
Host smart-918c3596-4dcc-44bb-9963-be39d925d0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85933
4244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.859334244
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.336401348
Short name T513
Test name
Test status
Simulation time 10143840915 ps
CPU time 14.14 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:54 PM PDT 24
Peak memory 204968 kb
Host smart-5b4cc30e-1b29-46ed-9361-502b2eabb2e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=336401348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.336401348
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.920364963
Short name T1069
Test name
Test status
Simulation time 10059036798 ps
CPU time 13.2 seconds
Started May 23 03:43:30 PM PDT 24
Finished May 23 03:43:48 PM PDT 24
Peak memory 204944 kb
Host smart-63d1df4d-17da-4444-be55-1eb3f9bb99c9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=920364963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.920364963
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.2203424181
Short name T390
Test name
Test status
Simulation time 10136960852 ps
CPU time 13.24 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:04 PM PDT 24
Peak memory 205036 kb
Host smart-987d05e9-d441-41ad-9dc4-a1d9e3ff0267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22034
24181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.2203424181
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2191891747
Short name T1695
Test name
Test status
Simulation time 13775096668 ps
CPU time 17.93 seconds
Started May 23 03:43:46 PM PDT 24
Finished May 23 03:44:13 PM PDT 24
Peak memory 204996 kb
Host smart-2297f6d0-5eb0-450f-b156-e321fb10d167
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2191891747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.2191891747
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.905048848
Short name T362
Test name
Test status
Simulation time 13319994802 ps
CPU time 20.16 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:11 PM PDT 24
Peak memory 205016 kb
Host smart-33208d62-79f7-4583-8186-b47c14f3396a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=905048848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.905048848
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3033225420
Short name T762
Test name
Test status
Simulation time 13394797155 ps
CPU time 17.43 seconds
Started May 23 03:43:34 PM PDT 24
Finished May 23 03:43:57 PM PDT 24
Peak memory 204912 kb
Host smart-f3162e2b-125b-443b-ba8b-f39c22828da9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3033225420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.3033225420
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2597437968
Short name T1392
Test name
Test status
Simulation time 10066541523 ps
CPU time 12.75 seconds
Started May 23 03:43:47 PM PDT 24
Finished May 23 03:44:09 PM PDT 24
Peak memory 205036 kb
Host smart-da5646ca-a309-4b39-827b-b6a9b424e4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25974
37968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2597437968
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.4077689828
Short name T800
Test name
Test status
Simulation time 10953726370 ps
CPU time 16.71 seconds
Started May 23 03:43:47 PM PDT 24
Finished May 23 03:44:13 PM PDT 24
Peak memory 205020 kb
Host smart-5dff54ae-67cd-42b8-a0d3-2885913b5ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40776
89828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.4077689828
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.2992281588
Short name T932
Test name
Test status
Simulation time 10043379275 ps
CPU time 13.62 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:50 PM PDT 24
Peak memory 204912 kb
Host smart-96ffd0bb-129b-4863-ac0b-6113da6301a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29922
81588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.2992281588
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.849563082
Short name T793
Test name
Test status
Simulation time 10069193813 ps
CPU time 13.42 seconds
Started May 23 03:43:35 PM PDT 24
Finished May 23 03:43:54 PM PDT 24
Peak memory 204964 kb
Host smart-60f44382-ee8a-4aac-9b33-0d3349ee3e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84956
3082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.849563082
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3456335332
Short name T1552
Test name
Test status
Simulation time 10861275764 ps
CPU time 17.55 seconds
Started May 23 03:43:47 PM PDT 24
Finished May 23 03:44:14 PM PDT 24
Peak memory 204980 kb
Host smart-0c194fae-7d86-419c-9234-e299eaa34e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34563
35332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3456335332
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3254900789
Short name T648
Test name
Test status
Simulation time 10172276191 ps
CPU time 13.72 seconds
Started May 23 03:43:48 PM PDT 24
Finished May 23 03:44:10 PM PDT 24
Peak memory 205028 kb
Host smart-f2164ab6-727c-4a77-ac86-9600300ceff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32549
00789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3254900789
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3834890576
Short name T1451
Test name
Test status
Simulation time 10093355809 ps
CPU time 13.91 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:51 PM PDT 24
Peak memory 204932 kb
Host smart-b545641c-9b4a-4269-a1ec-88f885b7dbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38348
90576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3834890576
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.35994586
Short name T1531
Test name
Test status
Simulation time 10054739875 ps
CPU time 13.96 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:52 PM PDT 24
Peak memory 204928 kb
Host smart-57d7982d-e076-48a6-8e6c-0319eed6158e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35994
586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.35994586
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3148380056
Short name T1507
Test name
Test status
Simulation time 10089111952 ps
CPU time 14.05 seconds
Started May 23 03:43:36 PM PDT 24
Finished May 23 03:43:56 PM PDT 24
Peak memory 204948 kb
Host smart-2b09b319-eba5-4939-bfc4-13e1c495cd53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31483
80056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3148380056
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2882914500
Short name T1304
Test name
Test status
Simulation time 10071414741 ps
CPU time 13.64 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:04 PM PDT 24
Peak memory 204900 kb
Host smart-ce89ed1b-f915-42f6-b7d6-34e791246e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28829
14500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2882914500
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.191350998
Short name T1417
Test name
Test status
Simulation time 13287494269 ps
CPU time 16.88 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 204928 kb
Host smart-e3e41c55-e8d9-42e4-8c6b-0a15893dc8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19135
0998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.191350998
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2609715442
Short name T1871
Test name
Test status
Simulation time 10099606072 ps
CPU time 12.86 seconds
Started May 23 03:43:41 PM PDT 24
Finished May 23 03:44:02 PM PDT 24
Peak memory 204932 kb
Host smart-31d6ad7d-ffb1-41f3-9f21-d2c7b67929b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26097
15442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2609715442
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1942731847
Short name T1740
Test name
Test status
Simulation time 10052257432 ps
CPU time 11.95 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:02 PM PDT 24
Peak memory 204896 kb
Host smart-804875f8-e53f-4320-8432-b642afbeef60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19427
31847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1942731847
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1816217569
Short name T104
Test name
Test status
Simulation time 10150306617 ps
CPU time 14.18 seconds
Started May 23 03:43:28 PM PDT 24
Finished May 23 03:43:47 PM PDT 24
Peak memory 204936 kb
Host smart-f8ef5307-578d-49fb-bdc5-f8459d305964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18162
17569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1816217569
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.4102381226
Short name T1038
Test name
Test status
Simulation time 10188640070 ps
CPU time 14.35 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 204900 kb
Host smart-914b7831-c46c-4655-922c-8151a2bf6ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41023
81226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.4102381226
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3374578250
Short name T542
Test name
Test status
Simulation time 10094941502 ps
CPU time 13.66 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 204900 kb
Host smart-df989040-672b-4f4f-aaf9-a8db5b53ca59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33745
78250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3374578250
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3403858011
Short name T1278
Test name
Test status
Simulation time 10073820768 ps
CPU time 13.87 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:04 PM PDT 24
Peak memory 204928 kb
Host smart-265a2c96-47d2-4e15-99cb-66521bf8bbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34038
58011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3403858011
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1233674748
Short name T159
Test name
Test status
Simulation time 10117968797 ps
CPU time 14.53 seconds
Started May 23 03:43:39 PM PDT 24
Finished May 23 03:44:02 PM PDT 24
Peak memory 204992 kb
Host smart-d7fad79c-e314-4668-bae7-783f683ab746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12336
74748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1233674748
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.1322857621
Short name T903
Test name
Test status
Simulation time 10049767133 ps
CPU time 13.22 seconds
Started May 23 03:43:37 PM PDT 24
Finished May 23 03:43:57 PM PDT 24
Peak memory 204976 kb
Host smart-3358f229-ccb0-4dfb-90b3-ce477513207e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13228
57621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.1322857621
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.118265119
Short name T1637
Test name
Test status
Simulation time 10039584322 ps
CPU time 14.21 seconds
Started May 23 03:43:38 PM PDT 24
Finished May 23 03:44:00 PM PDT 24
Peak memory 204936 kb
Host smart-7648a32b-16e6-45a0-a6ec-ae2b7113c003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11826
5119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.118265119
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.1483347179
Short name T1287
Test name
Test status
Simulation time 10058910987 ps
CPU time 13.7 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 204984 kb
Host smart-e15f3995-e33b-4779-8ed2-1d4672d35f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14833
47179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.1483347179
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2184226084
Short name T249
Test name
Test status
Simulation time 21355482201 ps
CPU time 41.42 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:32 PM PDT 24
Peak memory 204960 kb
Host smart-8584c89c-d850-41bf-aa13-bc816a05729c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21842
26084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2184226084
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1425681631
Short name T211
Test name
Test status
Simulation time 10060874028 ps
CPU time 15.28 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 204892 kb
Host smart-c08927a6-391e-467b-8818-5a33472d4a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14256
81631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1425681631
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.339654844
Short name T1669
Test name
Test status
Simulation time 10124038921 ps
CPU time 13.35 seconds
Started May 23 03:43:58 PM PDT 24
Finished May 23 03:44:20 PM PDT 24
Peak memory 204896 kb
Host smart-93779b5e-2930-4a7d-9f9c-19ae6f0600f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33965
4844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.339654844
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.4102903529
Short name T1653
Test name
Test status
Simulation time 10053207682 ps
CPU time 13.43 seconds
Started May 23 03:43:33 PM PDT 24
Finished May 23 03:43:52 PM PDT 24
Peak memory 204984 kb
Host smart-fb9d6ce2-f99e-42a8-ad26-b766bf11ed11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029
03529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.4102903529
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.3644782563
Short name T42
Test name
Test status
Simulation time 10097716276 ps
CPU time 14.04 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 204900 kb
Host smart-5f35a150-d8ca-4fe9-b8be-0a34d18c18bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36447
82563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.3644782563
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2518006056
Short name T1149
Test name
Test status
Simulation time 10056529190 ps
CPU time 13.18 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:03 PM PDT 24
Peak memory 204920 kb
Host smart-db7a1982-e1e3-4ff7-a7e6-ebbed1a82533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25180
06056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2518006056
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3640639174
Short name T1547
Test name
Test status
Simulation time 10065221892 ps
CPU time 14.11 seconds
Started May 23 03:43:38 PM PDT 24
Finished May 23 03:43:59 PM PDT 24
Peak memory 204952 kb
Host smart-26293ad0-451a-46dd-b9b5-11b536ebe460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36406
39174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3640639174
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1532461585
Short name T596
Test name
Test status
Simulation time 10119066212 ps
CPU time 14.77 seconds
Started May 23 03:43:31 PM PDT 24
Finished May 23 03:43:51 PM PDT 24
Peak memory 204932 kb
Host smart-2b329a88-0eac-44dd-97c5-7c44ed5aa8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15324
61585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1532461585
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2740956559
Short name T1073
Test name
Test status
Simulation time 10081359026 ps
CPU time 15.33 seconds
Started May 23 03:43:32 PM PDT 24
Finished May 23 03:43:53 PM PDT 24
Peak memory 204920 kb
Host smart-e70fbf7b-e9bf-4942-ab9e-93af4f90d79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27409
56559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2740956559
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.181994245
Short name T306
Test name
Test status
Simulation time 10093211189 ps
CPU time 14.31 seconds
Started May 23 03:43:35 PM PDT 24
Finished May 23 03:43:55 PM PDT 24
Peak memory 204844 kb
Host smart-3bf93e98-9fd6-40d8-86ab-90464bf800b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18199
4245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.181994245
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.2603940030
Short name T663
Test name
Test status
Simulation time 10181254427 ps
CPU time 14.22 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:17 PM PDT 24
Peak memory 205028 kb
Host smart-ecd91bff-6288-44ac-99e2-bff2175015e1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2603940030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.2603940030
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.2621888017
Short name T587
Test name
Test status
Simulation time 10061410381 ps
CPU time 13.88 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 205024 kb
Host smart-9059339f-73e0-4536-b129-5192f740d537
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2621888017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.2621888017
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.2742665222
Short name T846
Test name
Test status
Simulation time 10066881234 ps
CPU time 13.78 seconds
Started May 23 03:43:38 PM PDT 24
Finished May 23 03:43:59 PM PDT 24
Peak memory 204916 kb
Host smart-94835097-d145-4fc0-8898-34c1069487b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27426
65222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.2742665222
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.4233392668
Short name T1389
Test name
Test status
Simulation time 13445205620 ps
CPU time 17.22 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:09 PM PDT 24
Peak memory 204932 kb
Host smart-31ebe89f-beba-413a-921d-5ffc7bc43942
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4233392668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.4233392668
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.160045559
Short name T509
Test name
Test status
Simulation time 13333471732 ps
CPU time 17.3 seconds
Started May 23 03:43:36 PM PDT 24
Finished May 23 03:44:00 PM PDT 24
Peak memory 204924 kb
Host smart-ef04dc72-8a6d-4dae-8df2-686667dda945
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=160045559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.160045559
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1358136331
Short name T574
Test name
Test status
Simulation time 13249912507 ps
CPU time 17.09 seconds
Started May 23 03:43:41 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 204900 kb
Host smart-d5d9535c-f8e1-41ff-8d7b-df9a8ec1b75c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1358136331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.1358136331
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2633469536
Short name T1028
Test name
Test status
Simulation time 10074082264 ps
CPU time 14.11 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 204920 kb
Host smart-24b5822c-1763-4d75-b36f-cc1d11d7bbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26334
69536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2633469536
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1616519282
Short name T930
Test name
Test status
Simulation time 10528802964 ps
CPU time 13.91 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 205056 kb
Host smart-bc0919ed-5182-41b7-b3b9-62954b836764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16165
19282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1616519282
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3007170266
Short name T1323
Test name
Test status
Simulation time 10030087251 ps
CPU time 15.5 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:09 PM PDT 24
Peak memory 204992 kb
Host smart-468de4d7-ef66-4bec-ada1-3af468f5a77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30071
70266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3007170266
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2310987360
Short name T482
Test name
Test status
Simulation time 10062077850 ps
CPU time 13.1 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 205012 kb
Host smart-eece29d6-f8b1-4b72-912f-f61e550f4686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23109
87360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2310987360
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.4149370604
Short name T1768
Test name
Test status
Simulation time 10728508556 ps
CPU time 16.88 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:11 PM PDT 24
Peak memory 204908 kb
Host smart-32011830-2ba6-4918-a35f-48ffec396c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41493
70604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.4149370604
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.766552249
Short name T882
Test name
Test status
Simulation time 10052651328 ps
CPU time 13.66 seconds
Started May 23 03:43:46 PM PDT 24
Finished May 23 03:44:12 PM PDT 24
Peak memory 204928 kb
Host smart-bb5e7803-43f8-4da4-a0c5-9e51a5341af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76655
2249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.766552249
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.2950717
Short name T933
Test name
Test status
Simulation time 10120896576 ps
CPU time 14.31 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 204924 kb
Host smart-d47f6748-3675-48aa-8205-d2f3cc49c6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29507
17 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.2950717
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2674456101
Short name T1864
Test name
Test status
Simulation time 10042924005 ps
CPU time 16.44 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 204928 kb
Host smart-12e03d74-3847-4bda-9468-56107e2cf2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26744
56101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2674456101
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2593784255
Short name T1453
Test name
Test status
Simulation time 10136937926 ps
CPU time 13.4 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 204952 kb
Host smart-5bf61158-7c71-4c62-a413-b1c22907ec8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25937
84255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2593784255
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2930186024
Short name T49
Test name
Test status
Simulation time 10090404356 ps
CPU time 13.47 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 205004 kb
Host smart-dfe53408-3ab3-4914-bd72-e167cc0d60d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29301
86024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2930186024
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.4018777987
Short name T1182
Test name
Test status
Simulation time 13159472565 ps
CPU time 16.34 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 204952 kb
Host smart-78a91b63-c255-423f-9d12-a4520a40dc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40187
77987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.4018777987
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2603465218
Short name T1853
Test name
Test status
Simulation time 10093637641 ps
CPU time 12.74 seconds
Started May 23 03:43:41 PM PDT 24
Finished May 23 03:44:02 PM PDT 24
Peak memory 204880 kb
Host smart-83719569-b655-4cd3-859b-29b43cd28abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26034
65218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2603465218
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3397701337
Short name T1441
Test name
Test status
Simulation time 10091825734 ps
CPU time 12.74 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 204936 kb
Host smart-3bd502d6-b36e-4248-b734-e01f9ed3aed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33977
01337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3397701337
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3949642562
Short name T131
Test name
Test status
Simulation time 10059352529 ps
CPU time 13.02 seconds
Started May 23 03:43:40 PM PDT 24
Finished May 23 03:44:01 PM PDT 24
Peak memory 204944 kb
Host smart-b6e4c563-f618-4c0b-a8b6-380fb4fe5f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39496
42562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3949642562
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.323678666
Short name T1566
Test name
Test status
Simulation time 10163923312 ps
CPU time 14 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 204920 kb
Host smart-0c3266e8-f173-4d37-b068-5f2008c1d3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32367
8666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.323678666
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.688786683
Short name T77
Test name
Test status
Simulation time 10078214086 ps
CPU time 13.45 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 205008 kb
Host smart-49f1c3e4-8a89-4653-91c7-b7dce3ab858c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68878
6683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.688786683
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.550049026
Short name T1651
Test name
Test status
Simulation time 10083028539 ps
CPU time 13.11 seconds
Started May 23 03:43:46 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 204968 kb
Host smart-75313dbe-26b0-4a75-9baa-2d452753e241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55004
9026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.550049026
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2630806213
Short name T761
Test name
Test status
Simulation time 10105882605 ps
CPU time 13.37 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:04 PM PDT 24
Peak memory 204988 kb
Host smart-07a7e6a4-831a-4b90-ad6a-8558cb994f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26308
06213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2630806213
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.868015633
Short name T624
Test name
Test status
Simulation time 10065424827 ps
CPU time 15.35 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:09 PM PDT 24
Peak memory 204972 kb
Host smart-481e2d76-a0d2-4655-88b5-da144376bf75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86801
5633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.868015633
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.4164371156
Short name T1157
Test name
Test status
Simulation time 10043702342 ps
CPU time 14.16 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:04 PM PDT 24
Peak memory 204904 kb
Host smart-ae4318c6-abd7-4feb-b842-2b4012440836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41643
71156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.4164371156
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1679913050
Short name T1609
Test name
Test status
Simulation time 10048858133 ps
CPU time 15.3 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:09 PM PDT 24
Peak memory 204928 kb
Host smart-7e2fcf4a-f49b-41a8-8492-af31fa7778d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16799
13050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1679913050
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.690091383
Short name T248
Test name
Test status
Simulation time 18117404292 ps
CPU time 29.83 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:21 PM PDT 24
Peak memory 205016 kb
Host smart-64f98605-d958-4182-8a6f-afdaa22fd25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69009
1383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.690091383
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2211164296
Short name T1020
Test name
Test status
Simulation time 10058127145 ps
CPU time 15.51 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 204932 kb
Host smart-fd196e97-92c1-4bbf-b9c7-eac292a7c9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22111
64296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2211164296
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3586663826
Short name T383
Test name
Test status
Simulation time 10094857086 ps
CPU time 12.53 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 204964 kb
Host smart-090a268d-5a5b-4935-a631-e66fa63de15d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35866
63826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3586663826
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.592033864
Short name T1421
Test name
Test status
Simulation time 10056801054 ps
CPU time 14.99 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 205008 kb
Host smart-8dd36e1f-6242-409b-af73-dcfb8e0ec46f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59203
3864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.592033864
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.519774502
Short name T1915
Test name
Test status
Simulation time 10039643092 ps
CPU time 13.34 seconds
Started May 23 03:43:47 PM PDT 24
Finished May 23 03:44:09 PM PDT 24
Peak memory 204968 kb
Host smart-8b1db996-33ac-4900-ab50-47758ff47d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51977
4502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.519774502
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.258825773
Short name T981
Test name
Test status
Simulation time 10056650492 ps
CPU time 13.16 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:03 PM PDT 24
Peak memory 204984 kb
Host smart-fdb60979-2f13-4c93-ac91-d85e842f9eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25882
5773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.258825773
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3181397877
Short name T338
Test name
Test status
Simulation time 10046880386 ps
CPU time 14.24 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 204948 kb
Host smart-a5100aef-2f9c-4cd6-a17b-783b7116d73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31813
97877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3181397877
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3640677358
Short name T1330
Test name
Test status
Simulation time 10160307802 ps
CPU time 15.64 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 204952 kb
Host smart-48d5592e-01bf-4487-afc3-cf4415fa0614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36406
77358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3640677358
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.4005237388
Short name T1105
Test name
Test status
Simulation time 10081040301 ps
CPU time 13.3 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:04 PM PDT 24
Peak memory 204976 kb
Host smart-ca88eb83-3827-4892-a3eb-786a83af2022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40052
37388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.4005237388
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3487816543
Short name T1046
Test name
Test status
Simulation time 10076184302 ps
CPU time 13.18 seconds
Started May 23 03:43:46 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 204916 kb
Host smart-fb28da48-8dac-4853-92d1-3e2d611897d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34878
16543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3487816543
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.541737646
Short name T443
Test name
Test status
Simulation time 10152424606 ps
CPU time 13.31 seconds
Started May 23 03:43:58 PM PDT 24
Finished May 23 03:44:19 PM PDT 24
Peak memory 204968 kb
Host smart-ba4f2cb2-1577-4c64-bc45-f3e13ed9a2f4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=541737646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.541737646
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.3777950975
Short name T770
Test name
Test status
Simulation time 10080466651 ps
CPU time 13.03 seconds
Started May 23 03:43:58 PM PDT 24
Finished May 23 03:44:19 PM PDT 24
Peak memory 204936 kb
Host smart-8679f72b-dc96-4c98-bb7b-4bafd6c4ab61
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3777950975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.3777950975
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.3642586951
Short name T1272
Test name
Test status
Simulation time 10075227798 ps
CPU time 12.8 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 204936 kb
Host smart-64721084-bced-48bc-bb59-fca58d00d855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36425
86951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.3642586951
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.161436112
Short name T753
Test name
Test status
Simulation time 13649061051 ps
CPU time 17.09 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 205008 kb
Host smart-4f968103-3d3a-4fd4-8eed-035132ba63af
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=161436112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.161436112
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1089706595
Short name T1487
Test name
Test status
Simulation time 13219625400 ps
CPU time 15.5 seconds
Started May 23 03:43:46 PM PDT 24
Finished May 23 03:44:10 PM PDT 24
Peak memory 204972 kb
Host smart-8997d66f-f055-473e-8517-b6db11d9b7b9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1089706595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1089706595
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1640708886
Short name T827
Test name
Test status
Simulation time 13395379961 ps
CPU time 17.18 seconds
Started May 23 03:43:46 PM PDT 24
Finished May 23 03:44:12 PM PDT 24
Peak memory 204996 kb
Host smart-0d9fc593-06d6-4a20-80bb-238dd51f508b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1640708886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.1640708886
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1432521426
Short name T1480
Test name
Test status
Simulation time 10064512056 ps
CPU time 13.1 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:03 PM PDT 24
Peak memory 204884 kb
Host smart-c93e78f7-e23e-4b74-8cb4-30b66ad2079e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14325
21426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1432521426
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1214430900
Short name T519
Test name
Test status
Simulation time 10372461851 ps
CPU time 14.23 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 204968 kb
Host smart-2e3b09c9-e905-4da1-8761-d4c3906ece9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12144
30900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1214430900
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1310297701
Short name T1424
Test name
Test status
Simulation time 10055168646 ps
CPU time 13.36 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 204948 kb
Host smart-316913cf-d9de-4be5-a168-581ade87ce0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13102
97701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1310297701
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.137792860
Short name T1912
Test name
Test status
Simulation time 10057456541 ps
CPU time 13.79 seconds
Started May 23 03:43:46 PM PDT 24
Finished May 23 03:44:09 PM PDT 24
Peak memory 204980 kb
Host smart-3152c097-4246-42a9-a024-7bc24eb5c5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13779
2860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.137792860
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1387128969
Short name T886
Test name
Test status
Simulation time 10741565547 ps
CPU time 14.52 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 204952 kb
Host smart-3362395f-20c8-42a8-8632-aaf1ef872184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13871
28969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1387128969
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.756539722
Short name T686
Test name
Test status
Simulation time 10148118279 ps
CPU time 15.2 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 204948 kb
Host smart-db5bbf03-c072-4d9c-a50a-ebd2082d491d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75653
9722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.756539722
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2449490170
Short name T1419
Test name
Test status
Simulation time 10071356829 ps
CPU time 15.82 seconds
Started May 23 03:43:57 PM PDT 24
Finished May 23 03:44:21 PM PDT 24
Peak memory 204928 kb
Host smart-559b68ad-109d-4cb1-bc1a-4f6210ceecdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24494
90170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2449490170
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2326734965
Short name T1753
Test name
Test status
Simulation time 10048553374 ps
CPU time 13.65 seconds
Started May 23 03:44:03 PM PDT 24
Finished May 23 03:44:26 PM PDT 24
Peak memory 204912 kb
Host smart-19da63d7-f189-46cc-a8df-8b557c240e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23267
34965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2326734965
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1647571117
Short name T626
Test name
Test status
Simulation time 10106366733 ps
CPU time 12.67 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 204992 kb
Host smart-7742f3cc-10d4-44dd-9d4c-b41fa6dba388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16475
71117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1647571117
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3265407681
Short name T48
Test name
Test status
Simulation time 10143393428 ps
CPU time 13.1 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 204916 kb
Host smart-63f5d5f3-fa04-4f32-ba51-722a0c120586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32654
07681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3265407681
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3590251289
Short name T1815
Test name
Test status
Simulation time 13178313082 ps
CPU time 15.54 seconds
Started May 23 03:43:46 PM PDT 24
Finished May 23 03:44:10 PM PDT 24
Peak memory 204944 kb
Host smart-04f57ce2-0799-4adf-bfe1-deafb86c4522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35902
51289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3590251289
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3691760681
Short name T1082
Test name
Test status
Simulation time 10092676837 ps
CPU time 14.56 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 204924 kb
Host smart-c876a058-77b5-41e6-9b1c-1fac47109da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36917
60681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3691760681
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2778606659
Short name T433
Test name
Test status
Simulation time 10091608224 ps
CPU time 13.18 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:05 PM PDT 24
Peak memory 204964 kb
Host smart-bb4a0eeb-7dea-422e-bac8-eb2ebb8f941c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786
06659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2778606659
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3290183496
Short name T127
Test name
Test status
Simulation time 10104685831 ps
CPU time 13.91 seconds
Started May 23 03:43:44 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 204988 kb
Host smart-f09a3d52-d6f0-415c-b909-3ccc4e46d2d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32901
83496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3290183496
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.3885797377
Short name T473
Test name
Test status
Simulation time 10089963902 ps
CPU time 12.89 seconds
Started May 23 03:43:57 PM PDT 24
Finished May 23 03:44:18 PM PDT 24
Peak memory 205000 kb
Host smart-bd2eea90-3e63-4833-aa67-3656b0ef4d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38857
97377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.3885797377
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1601529664
Short name T1595
Test name
Test status
Simulation time 10117067845 ps
CPU time 13.71 seconds
Started May 23 03:43:45 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 204956 kb
Host smart-da34b8a2-3dd2-4791-9183-3b44d00b494e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16015
29664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1601529664
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.456837573
Short name T1936
Test name
Test status
Simulation time 10098941770 ps
CPU time 17.38 seconds
Started May 23 03:43:42 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 204984 kb
Host smart-93006216-d741-4c2c-96f2-429eaa99efab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45683
7573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.456837573
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.237241982
Short name T1829
Test name
Test status
Simulation time 10068823685 ps
CPU time 13.34 seconds
Started May 23 03:44:14 PM PDT 24
Finished May 23 03:44:36 PM PDT 24
Peak memory 204944 kb
Host smart-35baca14-6c03-4ec5-92c9-4021cab0bdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23724
1982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.237241982
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.3203248667
Short name T424
Test name
Test status
Simulation time 10059579155 ps
CPU time 13.51 seconds
Started May 23 03:43:55 PM PDT 24
Finished May 23 03:44:16 PM PDT 24
Peak memory 204920 kb
Host smart-ebfe81d8-53b4-4b06-8e3d-c35ba2d2b1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32032
48667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.3203248667
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3866695579
Short name T866
Test name
Test status
Simulation time 10040514542 ps
CPU time 16.86 seconds
Started May 23 03:43:58 PM PDT 24
Finished May 23 03:44:24 PM PDT 24
Peak memory 204992 kb
Host smart-5006eb41-8703-4184-a959-897cb814b74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38666
95579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3866695579
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1491352808
Short name T864
Test name
Test status
Simulation time 10037018000 ps
CPU time 15.58 seconds
Started May 23 03:44:00 PM PDT 24
Finished May 23 03:44:25 PM PDT 24
Peak memory 204972 kb
Host smart-a92b24e5-9727-42e4-856e-414db656d2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14913
52808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1491352808
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2804506810
Short name T1078
Test name
Test status
Simulation time 27011578741 ps
CPU time 49.4 seconds
Started May 23 03:43:46 PM PDT 24
Finished May 23 03:44:45 PM PDT 24
Peak memory 205036 kb
Host smart-7fd089dc-03a7-4f0b-86f8-3dfb2422e464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28045
06810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2804506810
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3796989136
Short name T1152
Test name
Test status
Simulation time 10129817333 ps
CPU time 16.78 seconds
Started May 23 03:43:43 PM PDT 24
Finished May 23 03:44:08 PM PDT 24
Peak memory 204956 kb
Host smart-c43305d7-dc96-43ef-9fd3-a4349d9fdff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37969
89136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3796989136
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.232298117
Short name T309
Test name
Test status
Simulation time 10135395031 ps
CPU time 14.47 seconds
Started May 23 03:44:08 PM PDT 24
Finished May 23 03:44:29 PM PDT 24
Peak memory 204920 kb
Host smart-0f613581-5261-4fba-b951-5cc46bc53d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23229
8117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.232298117
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.2393077499
Short name T1896
Test name
Test status
Simulation time 10141026230 ps
CPU time 13.79 seconds
Started May 23 03:44:21 PM PDT 24
Finished May 23 03:44:44 PM PDT 24
Peak memory 205020 kb
Host smart-c4d32627-1f8e-4c82-a1ee-e7036501c591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23930
77499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.2393077499
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.906873012
Short name T1364
Test name
Test status
Simulation time 10074646001 ps
CPU time 13.1 seconds
Started May 23 03:44:01 PM PDT 24
Finished May 23 03:44:23 PM PDT 24
Peak memory 204936 kb
Host smart-f6e11c40-1c6b-49d0-a4a3-d8b37e6de9f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90687
3012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.906873012
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2705924904
Short name T134
Test name
Test status
Simulation time 10059449000 ps
CPU time 12.79 seconds
Started May 23 03:43:56 PM PDT 24
Finished May 23 03:44:16 PM PDT 24
Peak memory 204948 kb
Host smart-b4cbeb61-d8b1-43d4-bb51-2a101097e3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27059
24904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2705924904
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2543278332
Short name T567
Test name
Test status
Simulation time 10048385839 ps
CPU time 13.76 seconds
Started May 23 03:44:00 PM PDT 24
Finished May 23 03:44:23 PM PDT 24
Peak memory 204968 kb
Host smart-d2836960-b255-4efb-8904-b2cce8665b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25432
78332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2543278332
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1788449722
Short name T1883
Test name
Test status
Simulation time 10096904525 ps
CPU time 13.72 seconds
Started May 23 03:43:41 PM PDT 24
Finished May 23 03:44:03 PM PDT 24
Peak memory 204980 kb
Host smart-aef763c0-c761-4662-89da-a3517b930808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17884
49722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1788449722
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2919557485
Short name T23
Test name
Test status
Simulation time 10087669971 ps
CPU time 13.53 seconds
Started May 23 03:44:01 PM PDT 24
Finished May 23 03:44:23 PM PDT 24
Peak memory 204908 kb
Host smart-57cbbb6b-ef25-4730-9529-d4dd9cda9f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29195
57485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2919557485
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.1760946994
Short name T467
Test name
Test status
Simulation time 10068092902 ps
CPU time 12.66 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:39 PM PDT 24
Peak memory 205004 kb
Host smart-24e65a22-a01a-4e15-b4a2-99333b46cc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17609
46994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1760946994
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.1604630966
Short name T522
Test name
Test status
Simulation time 10154215396 ps
CPU time 14.37 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:41 PM PDT 24
Peak memory 204960 kb
Host smart-d210184c-7a9b-45d9-b661-41b4b03dc203
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1604630966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.1604630966
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.2924982897
Short name T972
Test name
Test status
Simulation time 10087577307 ps
CPU time 13.67 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:34 PM PDT 24
Peak memory 204964 kb
Host smart-d7f9f42d-d27f-4f58-8a47-94e48992c9a8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2924982897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.2924982897
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.474210947
Short name T612
Test name
Test status
Simulation time 10117954454 ps
CPU time 13.82 seconds
Started May 23 03:44:07 PM PDT 24
Finished May 23 03:44:28 PM PDT 24
Peak memory 204952 kb
Host smart-d7905c03-74d4-477b-9c06-74b364486710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47421
0947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.474210947
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.1577678151
Short name T808
Test name
Test status
Simulation time 14173331367 ps
CPU time 16.76 seconds
Started May 23 03:44:08 PM PDT 24
Finished May 23 03:44:32 PM PDT 24
Peak memory 205012 kb
Host smart-d7a60755-0c3d-4f01-ae2b-dd0489c1559a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1577678151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.1577678151
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3110887404
Short name T222
Test name
Test status
Simulation time 13244292487 ps
CPU time 16.97 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:37 PM PDT 24
Peak memory 204932 kb
Host smart-9f165b5b-69ea-4eff-a4b5-78a17cc5c621
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3110887404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3110887404
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.1849215151
Short name T921
Test name
Test status
Simulation time 13367473698 ps
CPU time 17.62 seconds
Started May 23 03:44:08 PM PDT 24
Finished May 23 03:44:32 PM PDT 24
Peak memory 204924 kb
Host smart-d598c123-706d-4553-ad4a-67d12c34904d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1849215151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.1849215151
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3324598450
Short name T485
Test name
Test status
Simulation time 10067769101 ps
CPU time 14.18 seconds
Started May 23 03:43:59 PM PDT 24
Finished May 23 03:44:22 PM PDT 24
Peak memory 204956 kb
Host smart-ba07466e-b5f3-4d2c-a075-3260fbdf5769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33245
98450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3324598450
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.2499632290
Short name T326
Test name
Test status
Simulation time 10070171664 ps
CPU time 12.71 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 205012 kb
Host smart-6121a544-beb4-4f56-b272-f4e73e950991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24996
32290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.2499632290
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2726246351
Short name T1717
Test name
Test status
Simulation time 10060004916 ps
CPU time 13.98 seconds
Started May 23 03:43:55 PM PDT 24
Finished May 23 03:44:16 PM PDT 24
Peak memory 204928 kb
Host smart-6834ac8b-0563-4479-aa37-0d559ea11897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27262
46351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2726246351
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.4280007006
Short name T341
Test name
Test status
Simulation time 10904348160 ps
CPU time 14.49 seconds
Started May 23 03:44:05 PM PDT 24
Finished May 23 03:44:28 PM PDT 24
Peak memory 204928 kb
Host smart-4379667e-a21c-424a-845e-1641a155f72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42800
07006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.4280007006
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2871164230
Short name T1668
Test name
Test status
Simulation time 10088751001 ps
CPU time 14.93 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:44:41 PM PDT 24
Peak memory 204940 kb
Host smart-66c2f88b-33b5-448e-ae19-40c51994c56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28711
64230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2871164230
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2603896422
Short name T642
Test name
Test status
Simulation time 10101665849 ps
CPU time 13.95 seconds
Started May 23 03:43:59 PM PDT 24
Finished May 23 03:44:22 PM PDT 24
Peak memory 204960 kb
Host smart-6de28f79-60cf-453a-88f0-edf699193ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26038
96422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2603896422
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3515119364
Short name T1237
Test name
Test status
Simulation time 10052594376 ps
CPU time 15.86 seconds
Started May 23 03:43:58 PM PDT 24
Finished May 23 03:44:22 PM PDT 24
Peak memory 204952 kb
Host smart-6d781630-96a3-44f4-83d0-413d28bc3c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35151
19364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3515119364
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1362261872
Short name T1298
Test name
Test status
Simulation time 10088284226 ps
CPU time 13.34 seconds
Started May 23 03:43:59 PM PDT 24
Finished May 23 03:44:22 PM PDT 24
Peak memory 204992 kb
Host smart-d996a3cd-7c70-48f3-9fae-5b626fa8035f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13622
61872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1362261872
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.476331165
Short name T1106
Test name
Test status
Simulation time 10110183127 ps
CPU time 14.01 seconds
Started May 23 03:44:22 PM PDT 24
Finished May 23 03:44:46 PM PDT 24
Peak memory 204980 kb
Host smart-b8e8836a-b7b4-4b5c-8ea9-759000f02f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47633
1165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.476331165
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2191685596
Short name T1863
Test name
Test status
Simulation time 13174804925 ps
CPU time 17.19 seconds
Started May 23 03:44:09 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 204948 kb
Host smart-5c450aa1-f010-499e-8413-d043ba8c5d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21916
85596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2191685596
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2222817558
Short name T676
Test name
Test status
Simulation time 10088696567 ps
CPU time 15.57 seconds
Started May 23 03:43:57 PM PDT 24
Finished May 23 03:44:20 PM PDT 24
Peak memory 204964 kb
Host smart-4fbce2a8-8ff9-4aee-a098-7c6981b5751a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22228
17558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2222817558
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1663504720
Short name T1194
Test name
Test status
Simulation time 10068153938 ps
CPU time 13.67 seconds
Started May 23 03:43:57 PM PDT 24
Finished May 23 03:44:19 PM PDT 24
Peak memory 204936 kb
Host smart-e0231815-e46d-4b3b-97ee-77898a57e1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16635
04720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1663504720
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2758072757
Short name T111
Test name
Test status
Simulation time 10090130303 ps
CPU time 15.43 seconds
Started May 23 03:43:58 PM PDT 24
Finished May 23 03:44:22 PM PDT 24
Peak memory 204988 kb
Host smart-52df9d1c-ba99-45c4-b0b8-9a325d749bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27580
72757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2758072757
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2159094069
Short name T1226
Test name
Test status
Simulation time 10112045385 ps
CPU time 13.5 seconds
Started May 23 03:44:07 PM PDT 24
Finished May 23 03:44:28 PM PDT 24
Peak memory 204908 kb
Host smart-7f2c73f2-0e51-4728-8599-76ddafd1ca8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21590
94069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2159094069
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2637446422
Short name T693
Test name
Test status
Simulation time 10083377249 ps
CPU time 14.02 seconds
Started May 23 03:44:01 PM PDT 24
Finished May 23 03:44:24 PM PDT 24
Peak memory 204968 kb
Host smart-a4c7ad55-5418-4e51-8e39-b9b8d5b47815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26374
46422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2637446422
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1806449770
Short name T535
Test name
Test status
Simulation time 10105173774 ps
CPU time 13.02 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:39 PM PDT 24
Peak memory 205032 kb
Host smart-3a2e26b6-d878-4b4b-84fd-7bb7a572c857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18064
49770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1806449770
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.4052530437
Short name T164
Test name
Test status
Simulation time 10084130070 ps
CPU time 13.29 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:39 PM PDT 24
Peak memory 204972 kb
Host smart-7e21131b-5acb-4ab3-93d9-954d26183541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40525
30437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.4052530437
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.390435744
Short name T1407
Test name
Test status
Simulation time 10119636043 ps
CPU time 13.02 seconds
Started May 23 03:44:06 PM PDT 24
Finished May 23 03:44:27 PM PDT 24
Peak memory 204968 kb
Host smart-974b4d9f-9fde-4a2d-9967-963be7b146d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39043
5744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.390435744
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1987199425
Short name T828
Test name
Test status
Simulation time 10046154387 ps
CPU time 13.33 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 204996 kb
Host smart-8e63281e-cb10-461b-8d52-1cee56320d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19871
99425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1987199425
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1110826426
Short name T1309
Test name
Test status
Simulation time 10088557005 ps
CPU time 12.11 seconds
Started May 23 03:44:14 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 204936 kb
Host smart-d005f7d7-c8b0-417b-adc6-9b63318984bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11108
26426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1110826426
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1131187537
Short name T1373
Test name
Test status
Simulation time 15694022952 ps
CPU time 26.22 seconds
Started May 23 03:43:58 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 205008 kb
Host smart-4e67eb98-06c6-4947-b266-360d7dd02eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11311
87537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1131187537
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3127366026
Short name T845
Test name
Test status
Simulation time 10085282075 ps
CPU time 13.24 seconds
Started May 23 03:43:56 PM PDT 24
Finished May 23 03:44:17 PM PDT 24
Peak memory 204948 kb
Host smart-19274ecb-ec7f-4f9e-941a-e0aba658a4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31273
66026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3127366026
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2481635032
Short name T1460
Test name
Test status
Simulation time 10058382434 ps
CPU time 13.93 seconds
Started May 23 03:43:53 PM PDT 24
Finished May 23 03:44:14 PM PDT 24
Peak memory 204992 kb
Host smart-ec759dcd-9b19-4287-95c4-0c9f52d708ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
35032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2481635032
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2866540024
Short name T872
Test name
Test status
Simulation time 10093828445 ps
CPU time 14.22 seconds
Started May 23 03:44:11 PM PDT 24
Finished May 23 03:44:32 PM PDT 24
Peak memory 205004 kb
Host smart-2658bf33-d9d0-4c55-a2d5-2ac6dced4396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28665
40024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2866540024
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3406255088
Short name T1156
Test name
Test status
Simulation time 10032972877 ps
CPU time 14.02 seconds
Started May 23 03:43:55 PM PDT 24
Finished May 23 03:44:16 PM PDT 24
Peak memory 204976 kb
Host smart-9d451d12-ad35-4235-a643-d4c1ebc5f2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34062
55088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3406255088
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1609415258
Short name T146
Test name
Test status
Simulation time 10049074668 ps
CPU time 12.63 seconds
Started May 23 03:44:18 PM PDT 24
Finished May 23 03:44:40 PM PDT 24
Peak memory 204948 kb
Host smart-fd417d14-dedb-49e4-84ec-38ab3b722f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16094
15258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1609415258
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2714973854
Short name T346
Test name
Test status
Simulation time 10051788198 ps
CPU time 13.38 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 205000 kb
Host smart-ba42bafb-e4c0-42f1-94db-17cf482ce960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27149
73854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2714973854
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1338733836
Short name T974
Test name
Test status
Simulation time 10163815710 ps
CPU time 13.02 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 204960 kb
Host smart-faa88721-bce9-416a-9832-b12ec2a252af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13387
33836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1338733836
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3771094702
Short name T726
Test name
Test status
Simulation time 10102096153 ps
CPU time 14.06 seconds
Started May 23 03:43:58 PM PDT 24
Finished May 23 03:44:20 PM PDT 24
Peak memory 204964 kb
Host smart-0ad83de9-448a-4e35-8e1a-d2f70cb96958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37710
94702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3771094702
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2144751521
Short name T1699
Test name
Test status
Simulation time 10074685729 ps
CPU time 15.2 seconds
Started May 23 03:43:57 PM PDT 24
Finished May 23 03:44:19 PM PDT 24
Peak memory 204876 kb
Host smart-6f68cb95-e882-4897-922c-60c2b54530b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21447
51521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2144751521
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.1285330086
Short name T592
Test name
Test status
Simulation time 10139857118 ps
CPU time 12.8 seconds
Started May 23 03:44:00 PM PDT 24
Finished May 23 03:44:22 PM PDT 24
Peak memory 204992 kb
Host smart-3c964fd6-5164-4690-9c2f-a5fb4874e404
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1285330086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.1285330086
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.270783495
Short name T818
Test name
Test status
Simulation time 10060259821 ps
CPU time 14.32 seconds
Started May 23 03:44:03 PM PDT 24
Finished May 23 03:44:26 PM PDT 24
Peak memory 205004 kb
Host smart-2f531ab9-25a3-40d3-9056-c04ede902c6d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=270783495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.270783495
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.2043862351
Short name T1504
Test name
Test status
Simulation time 10081859374 ps
CPU time 13.72 seconds
Started May 23 03:44:08 PM PDT 24
Finished May 23 03:44:29 PM PDT 24
Peak memory 204996 kb
Host smart-6d87fd88-367d-4180-a79a-4c3d966840ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20438
62351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.2043862351
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2761097735
Short name T470
Test name
Test status
Simulation time 13469025218 ps
CPU time 19.12 seconds
Started May 23 03:44:11 PM PDT 24
Finished May 23 03:44:36 PM PDT 24
Peak memory 204988 kb
Host smart-4d7fb278-1dd3-4f4f-9434-6fd7e0fb6240
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2761097735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.2761097735
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1687025917
Short name T1830
Test name
Test status
Simulation time 13285878894 ps
CPU time 16.84 seconds
Started May 23 03:43:59 PM PDT 24
Finished May 23 03:44:25 PM PDT 24
Peak memory 204936 kb
Host smart-e4de3466-2587-41eb-9f55-0b3b2adeeba1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1687025917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1687025917
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3110340742
Short name T436
Test name
Test status
Simulation time 13206520282 ps
CPU time 17.6 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:44:36 PM PDT 24
Peak memory 204988 kb
Host smart-24f018bf-255f-4b55-a3fb-e93a2adaadc9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3110340742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.3110340742
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2291832856
Short name T1616
Test name
Test status
Simulation time 10070205713 ps
CPU time 13.83 seconds
Started May 23 03:43:57 PM PDT 24
Finished May 23 03:44:18 PM PDT 24
Peak memory 204916 kb
Host smart-2959ebb4-2fb4-40de-beda-88fa8cf3e237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22918
32856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2291832856
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.356026650
Short name T388
Test name
Test status
Simulation time 10074330202 ps
CPU time 14.42 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:35 PM PDT 24
Peak memory 204944 kb
Host smart-7cae66a6-36ad-4a3c-884d-73285db7b82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35602
6650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.356026650
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2287780916
Short name T665
Test name
Test status
Simulation time 10496585038 ps
CPU time 13.51 seconds
Started May 23 03:44:31 PM PDT 24
Finished May 23 03:44:57 PM PDT 24
Peak memory 205020 kb
Host smart-168b3933-e580-49e5-8401-ab42fca36187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22877
80916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2287780916
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2714793881
Short name T1626
Test name
Test status
Simulation time 10038889747 ps
CPU time 13.72 seconds
Started May 23 03:44:02 PM PDT 24
Finished May 23 03:44:24 PM PDT 24
Peak memory 204928 kb
Host smart-b4d790d6-5767-459b-9ddc-683df6a37a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27147
93881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2714793881
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.1611775233
Short name T296
Test name
Test status
Simulation time 10093806695 ps
CPU time 12.68 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 204940 kb
Host smart-523f09d7-eadc-467b-98de-1fb6a2414a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16117
75233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1611775233
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3516028386
Short name T786
Test name
Test status
Simulation time 10879531735 ps
CPU time 15.86 seconds
Started May 23 03:43:58 PM PDT 24
Finished May 23 03:44:23 PM PDT 24
Peak memory 204960 kb
Host smart-c9831477-4a28-46ac-a72c-6e1e66784f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35160
28386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3516028386
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.289840400
Short name T80
Test name
Test status
Simulation time 10137630381 ps
CPU time 17.06 seconds
Started May 23 03:44:19 PM PDT 24
Finished May 23 03:44:46 PM PDT 24
Peak memory 204964 kb
Host smart-1cd97d21-dec1-4c6b-9c39-6c9073a9a49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28984
0400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.289840400
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.981847105
Short name T1608
Test name
Test status
Simulation time 10132243513 ps
CPU time 14.08 seconds
Started May 23 03:44:29 PM PDT 24
Finished May 23 03:44:55 PM PDT 24
Peak memory 204952 kb
Host smart-2b33e161-6aa2-458c-a5f0-96d0cd1042a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98184
7105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.981847105
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.4201810406
Short name T406
Test name
Test status
Simulation time 10060277454 ps
CPU time 14.07 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 204964 kb
Host smart-3782a3dc-3278-4dc8-adad-cc0362b10607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42018
10406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.4201810406
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1982496368
Short name T576
Test name
Test status
Simulation time 10128812606 ps
CPU time 14.23 seconds
Started May 23 03:43:59 PM PDT 24
Finished May 23 03:44:22 PM PDT 24
Peak memory 204968 kb
Host smart-00ffae77-4113-4157-b9ff-239260f8f824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19824
96368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1982496368
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1178787878
Short name T344
Test name
Test status
Simulation time 10095638784 ps
CPU time 14.4 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:44:32 PM PDT 24
Peak memory 204940 kb
Host smart-1fd02e7e-893a-4aaf-ad07-2bc2ea4ed510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11787
87878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1178787878
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3892121016
Short name T803
Test name
Test status
Simulation time 13230041774 ps
CPU time 17.07 seconds
Started May 23 03:44:15 PM PDT 24
Finished May 23 03:44:40 PM PDT 24
Peak memory 205004 kb
Host smart-98dc63d6-5cd2-47f3-832b-8406c794d1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38921
21016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3892121016
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.258387739
Short name T949
Test name
Test status
Simulation time 10106768315 ps
CPU time 14.41 seconds
Started May 23 03:43:57 PM PDT 24
Finished May 23 03:44:20 PM PDT 24
Peak memory 204936 kb
Host smart-66bd8b36-cd2a-4f91-8f72-89477049f2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25838
7739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.258387739
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2794768709
Short name T1342
Test name
Test status
Simulation time 10045386504 ps
CPU time 13.02 seconds
Started May 23 03:43:59 PM PDT 24
Finished May 23 03:44:21 PM PDT 24
Peak memory 204968 kb
Host smart-0c89747c-6ffa-45b7-bb18-50bb9eebb1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27947
68709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2794768709
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2085047144
Short name T1823
Test name
Test status
Simulation time 10077564650 ps
CPU time 14.01 seconds
Started May 23 03:44:18 PM PDT 24
Finished May 23 03:44:41 PM PDT 24
Peak memory 205004 kb
Host smart-a3bf80ff-003d-4cb5-bf3a-da743b3ebf78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20850
47144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2085047144
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.1235532778
Short name T1659
Test name
Test status
Simulation time 10086476921 ps
CPU time 13.54 seconds
Started May 23 03:44:09 PM PDT 24
Finished May 23 03:44:29 PM PDT 24
Peak memory 204972 kb
Host smart-80a93b0f-94e3-474c-8747-7e88e45d5068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12355
32778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.1235532778
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.641842932
Short name T1362
Test name
Test status
Simulation time 10079549159 ps
CPU time 15.79 seconds
Started May 23 03:44:18 PM PDT 24
Finished May 23 03:44:44 PM PDT 24
Peak memory 204916 kb
Host smart-c5bb157c-cd54-4d3f-a782-b076a478b757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64184
2932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.641842932
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3280264439
Short name T363
Test name
Test status
Simulation time 10050443405 ps
CPU time 12.81 seconds
Started May 23 03:43:56 PM PDT 24
Finished May 23 03:44:16 PM PDT 24
Peak memory 204888 kb
Host smart-3bd00f34-53c7-4a8f-ad1b-4f05fd1bd02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32802
64439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3280264439
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1816336145
Short name T186
Test name
Test status
Simulation time 10090652319 ps
CPU time 13.04 seconds
Started May 23 03:43:59 PM PDT 24
Finished May 23 03:44:21 PM PDT 24
Peak memory 204996 kb
Host smart-feb2ecf2-01ad-4533-8c64-d244fcdd74aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18163
36145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1816336145
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.2426367375
Short name T1299
Test name
Test status
Simulation time 10081586175 ps
CPU time 12.67 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 204972 kb
Host smart-e64ed928-4aee-428f-851d-421e110b077b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24263
67375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.2426367375
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1068845850
Short name T402
Test name
Test status
Simulation time 10100102495 ps
CPU time 13.19 seconds
Started May 23 03:44:10 PM PDT 24
Finished May 23 03:44:30 PM PDT 24
Peak memory 204916 kb
Host smart-041368c1-97cf-4213-b354-8b0a61e471a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688
45850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1068845850
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.4157895573
Short name T1365
Test name
Test status
Simulation time 10045907102 ps
CPU time 12.49 seconds
Started May 23 03:44:15 PM PDT 24
Finished May 23 03:44:35 PM PDT 24
Peak memory 204880 kb
Host smart-95face51-5a37-4b21-9cef-0e1224e4d9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41578
95573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.4157895573
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2179373042
Short name T1139
Test name
Test status
Simulation time 25148135366 ps
CPU time 48.37 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:45:14 PM PDT 24
Peak memory 205044 kb
Host smart-4adf3572-7740-4f2d-b448-9a336b618360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21793
73042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2179373042
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.4261056216
Short name T704
Test name
Test status
Simulation time 10058531451 ps
CPU time 13.11 seconds
Started May 23 03:44:29 PM PDT 24
Finished May 23 03:44:52 PM PDT 24
Peak memory 204944 kb
Host smart-c08650ff-8e56-486b-9fb7-24d7a68a7b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42610
56216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.4261056216
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1656475654
Short name T1589
Test name
Test status
Simulation time 10103950714 ps
CPU time 13.07 seconds
Started May 23 03:43:59 PM PDT 24
Finished May 23 03:44:21 PM PDT 24
Peak memory 204992 kb
Host smart-fe806396-a47b-4f02-895b-19af74df7760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16564
75654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1656475654
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.770917387
Short name T403
Test name
Test status
Simulation time 10087032187 ps
CPU time 12.81 seconds
Started May 23 03:44:02 PM PDT 24
Finished May 23 03:44:24 PM PDT 24
Peak memory 204952 kb
Host smart-70bd0d59-a2c0-4cdd-aff0-54cec75aa641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77091
7387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.770917387
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2194060275
Short name T900
Test name
Test status
Simulation time 10042337680 ps
CPU time 13.83 seconds
Started May 23 03:44:10 PM PDT 24
Finished May 23 03:44:30 PM PDT 24
Peak memory 204968 kb
Host smart-a72306b2-04b8-4c37-a9bf-ffb4fdc2fa76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21940
60275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2194060275
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3900842966
Short name T496
Test name
Test status
Simulation time 10053470288 ps
CPU time 14.34 seconds
Started May 23 03:44:00 PM PDT 24
Finished May 23 03:44:24 PM PDT 24
Peak memory 204972 kb
Host smart-3bbdc71a-073b-455f-8a6b-f232f4953d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39008
42966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3900842966
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.136800453
Short name T1557
Test name
Test status
Simulation time 10057800250 ps
CPU time 12.77 seconds
Started May 23 03:44:23 PM PDT 24
Finished May 23 03:44:45 PM PDT 24
Peak memory 204944 kb
Host smart-8f311b34-e064-4513-9a62-d070aae9f7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13680
0453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.136800453
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.914220752
Short name T1835
Test name
Test status
Simulation time 10119243088 ps
CPU time 13.43 seconds
Started May 23 03:44:06 PM PDT 24
Finished May 23 03:44:27 PM PDT 24
Peak memory 204904 kb
Host smart-36607ef6-6b2d-49e9-a067-987abc6b25bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91422
0752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.914220752
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3426532684
Short name T792
Test name
Test status
Simulation time 10078222307 ps
CPU time 14.09 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 204888 kb
Host smart-821934c7-5ccd-49c8-93aa-5c5359d667ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34265
32684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3426532684
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.4155148619
Short name T1072
Test name
Test status
Simulation time 10080377335 ps
CPU time 13.79 seconds
Started May 23 03:44:08 PM PDT 24
Finished May 23 03:44:29 PM PDT 24
Peak memory 204944 kb
Host smart-06daafeb-424d-4ba3-be38-3a49cb067d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41551
48619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.4155148619
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.663123647
Short name T1567
Test name
Test status
Simulation time 10143367703 ps
CPU time 15.86 seconds
Started May 23 03:44:11 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 204944 kb
Host smart-90be86fd-500e-4392-a0c7-9b440ea639f3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=663123647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.663123647
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.2203875514
Short name T1180
Test name
Test status
Simulation time 10064424040 ps
CPU time 12.57 seconds
Started May 23 03:44:32 PM PDT 24
Finished May 23 03:44:58 PM PDT 24
Peak memory 204960 kb
Host smart-4fa3e054-8419-4336-9f50-c42c719b1058
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2203875514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.2203875514
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.4165500521
Short name T1301
Test name
Test status
Simulation time 10126334887 ps
CPU time 16.35 seconds
Started May 23 03:44:09 PM PDT 24
Finished May 23 03:44:32 PM PDT 24
Peak memory 204972 kb
Host smart-6477ca17-45bc-47e0-a50f-86382b1374dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41655
00521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.4165500521
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1589464847
Short name T203
Test name
Test status
Simulation time 13712171090 ps
CPU time 17.23 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:37 PM PDT 24
Peak memory 204904 kb
Host smart-a83adba4-c7a5-4daa-b308-9108a4fbec58
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1589464847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.1589464847
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3951763809
Short name T449
Test name
Test status
Simulation time 13296737759 ps
CPU time 16.7 seconds
Started May 23 03:44:02 PM PDT 24
Finished May 23 03:44:27 PM PDT 24
Peak memory 204952 kb
Host smart-6ba85ed6-c090-4a6c-a9e2-9e98ae15855a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3951763809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3951763809
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2186445503
Short name T536
Test name
Test status
Simulation time 13422360833 ps
CPU time 19.36 seconds
Started May 23 03:44:02 PM PDT 24
Finished May 23 03:44:30 PM PDT 24
Peak memory 204916 kb
Host smart-7ce5f2db-2900-4e18-98ec-aa6639b64a49
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2186445503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.2186445503
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2066034621
Short name T1411
Test name
Test status
Simulation time 10055699936 ps
CPU time 13.14 seconds
Started May 23 03:44:10 PM PDT 24
Finished May 23 03:44:29 PM PDT 24
Peak memory 204940 kb
Host smart-a1acc273-e876-4567-a7bc-e9f3144dadcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20660
34621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2066034621
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.560465732
Short name T1235
Test name
Test status
Simulation time 11429230978 ps
CPU time 16.89 seconds
Started May 23 03:44:15 PM PDT 24
Finished May 23 03:44:40 PM PDT 24
Peak memory 205048 kb
Host smart-464fb096-1e74-4965-a542-f85d0ce9bf33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56046
5732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.560465732
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3705267872
Short name T1109
Test name
Test status
Simulation time 10051507256 ps
CPU time 14.71 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:41 PM PDT 24
Peak memory 204908 kb
Host smart-28cfd259-20b5-46fd-a9e1-32a92ebf4db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37052
67872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3705267872
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.198237672
Short name T838
Test name
Test status
Simulation time 10051467848 ps
CPU time 15.94 seconds
Started May 23 03:44:32 PM PDT 24
Finished May 23 03:45:00 PM PDT 24
Peak memory 204924 kb
Host smart-17589403-d4ac-44db-a29c-60ef69a71365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19823
7672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.198237672
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2934767248
Short name T78
Test name
Test status
Simulation time 10220931427 ps
CPU time 14.09 seconds
Started May 23 03:44:31 PM PDT 24
Finished May 23 03:44:57 PM PDT 24
Peak memory 204956 kb
Host smart-ff2de898-267b-4833-a56e-3d020bc896f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29347
67248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2934767248
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3877276475
Short name T1232
Test name
Test status
Simulation time 10151033976 ps
CPU time 13.79 seconds
Started May 23 03:44:35 PM PDT 24
Finished May 23 03:45:01 PM PDT 24
Peak memory 204904 kb
Host smart-dd0bde73-fc08-4864-b32c-6cf0b25eec42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38772
76475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3877276475
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3852547073
Short name T1900
Test name
Test status
Simulation time 10040513864 ps
CPU time 14.33 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:34 PM PDT 24
Peak memory 204996 kb
Host smart-a9a18e0b-592c-4b18-9434-226f9d4ea192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38525
47073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3852547073
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.238239853
Short name T1503
Test name
Test status
Simulation time 10094035486 ps
CPU time 13.13 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:44:32 PM PDT 24
Peak memory 204968 kb
Host smart-7d767cf1-7fde-4dcc-bd60-161b4e38e7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23823
9853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.238239853
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1390080670
Short name T558
Test name
Test status
Simulation time 10118118658 ps
CPU time 14.09 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:40 PM PDT 24
Peak memory 204816 kb
Host smart-35761543-d196-4b05-a4d4-172d629fcea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13900
80670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1390080670
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.124856554
Short name T524
Test name
Test status
Simulation time 13233441137 ps
CPU time 18.1 seconds
Started May 23 03:44:29 PM PDT 24
Finished May 23 03:44:59 PM PDT 24
Peak memory 204996 kb
Host smart-4fd4b018-82eb-4f2d-85c9-3e646bc674d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12485
6554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.124856554
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3950053058
Short name T1577
Test name
Test status
Simulation time 10095374100 ps
CPU time 13.5 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:45:00 PM PDT 24
Peak memory 204948 kb
Host smart-41af24c8-1ec0-4afd-9d80-52028a66f4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39500
53058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3950053058
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2123214452
Short name T980
Test name
Test status
Simulation time 10046252507 ps
CPU time 13.11 seconds
Started May 23 03:44:10 PM PDT 24
Finished May 23 03:44:29 PM PDT 24
Peak memory 204936 kb
Host smart-00a6ddab-0940-4749-8d76-c82aeb9ebcf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21232
14452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2123214452
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3117813208
Short name T122
Test name
Test status
Simulation time 10112717656 ps
CPU time 13.21 seconds
Started May 23 03:44:29 PM PDT 24
Finished May 23 03:44:54 PM PDT 24
Peak memory 204908 kb
Host smart-3493fbb3-64b1-45f0-a7b1-b045ac7875bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31178
13208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3117813208
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2334008428
Short name T1019
Test name
Test status
Simulation time 10124087257 ps
CPU time 13.56 seconds
Started May 23 03:44:31 PM PDT 24
Finished May 23 03:44:57 PM PDT 24
Peak memory 204908 kb
Host smart-592514e6-53f1-4641-9f7b-d2ee69d8c46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23340
08428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2334008428
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3523544611
Short name T1748
Test name
Test status
Simulation time 10101722995 ps
CPU time 12.8 seconds
Started May 23 03:44:22 PM PDT 24
Finished May 23 03:44:44 PM PDT 24
Peak memory 204988 kb
Host smart-bb920cea-e2ec-47ce-b51b-51276df23e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35235
44611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3523544611
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2961836928
Short name T1210
Test name
Test status
Simulation time 10053025158 ps
CPU time 13.09 seconds
Started May 23 03:44:30 PM PDT 24
Finished May 23 03:44:56 PM PDT 24
Peak memory 204964 kb
Host smart-e1fd0a62-e2ff-4f21-8ea9-0195ee31ecb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29618
36928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2961836928
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2847631496
Short name T158
Test name
Test status
Simulation time 10079228915 ps
CPU time 14.74 seconds
Started May 23 03:44:11 PM PDT 24
Finished May 23 03:44:32 PM PDT 24
Peak memory 204948 kb
Host smart-4f661797-7067-4d28-92a9-63c506725757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28476
31496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2847631496
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.1529642888
Short name T1683
Test name
Test status
Simulation time 10063292004 ps
CPU time 12.75 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:45:02 PM PDT 24
Peak memory 204988 kb
Host smart-038bf791-2673-4374-80c0-79e403b6267b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15296
42888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.1529642888
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3899386345
Short name T1420
Test name
Test status
Simulation time 10051913456 ps
CPU time 14.16 seconds
Started May 23 03:44:09 PM PDT 24
Finished May 23 03:44:30 PM PDT 24
Peak memory 204912 kb
Host smart-4f0adfbd-a71a-4d1f-8e8a-77a386178364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38993
86345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3899386345
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.4053884854
Short name T214
Test name
Test status
Simulation time 10043791053 ps
CPU time 12.76 seconds
Started May 23 03:44:09 PM PDT 24
Finished May 23 03:44:28 PM PDT 24
Peak memory 204948 kb
Host smart-c891faf6-925d-47b1-9d17-272e9e5dcb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40538
84854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.4053884854
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2712420192
Short name T185
Test name
Test status
Simulation time 24179460972 ps
CPU time 51.83 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:45:41 PM PDT 24
Peak memory 205012 kb
Host smart-472cddf2-ad2e-4486-aa3f-acd94e04fdb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27124
20192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2712420192
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3235158596
Short name T1023
Test name
Test status
Simulation time 10066879529 ps
CPU time 13.06 seconds
Started May 23 03:44:35 PM PDT 24
Finished May 23 03:45:00 PM PDT 24
Peak memory 204912 kb
Host smart-cd0726b9-24aa-4d48-8241-1514f8ee59e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32351
58596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3235158596
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2220185606
Short name T1044
Test name
Test status
Simulation time 10140020700 ps
CPU time 13.15 seconds
Started May 23 03:44:16 PM PDT 24
Finished May 23 03:44:38 PM PDT 24
Peak memory 204980 kb
Host smart-66480be9-25ee-4d8f-8bf6-648b8754a234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22201
85606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2220185606
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3650424771
Short name T546
Test name
Test status
Simulation time 10093893789 ps
CPU time 12.8 seconds
Started May 23 03:44:32 PM PDT 24
Finished May 23 03:44:58 PM PDT 24
Peak memory 204932 kb
Host smart-656ec343-49b5-488d-894d-bd61b2085dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36504
24771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3650424771
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2534681743
Short name T744
Test name
Test status
Simulation time 10037668373 ps
CPU time 14.99 seconds
Started May 23 03:44:11 PM PDT 24
Finished May 23 03:44:32 PM PDT 24
Peak memory 204932 kb
Host smart-b3045393-e072-4121-a8e9-281cf3fafe3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25346
81743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2534681743
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.63903907
Short name T1550
Test name
Test status
Simulation time 10048860367 ps
CPU time 16.13 seconds
Started May 23 03:44:14 PM PDT 24
Finished May 23 03:44:38 PM PDT 24
Peak memory 204936 kb
Host smart-a545d658-5957-418a-afe2-5c0a639c2a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63903
907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.63903907
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3542837643
Short name T242
Test name
Test status
Simulation time 10090633368 ps
CPU time 13.34 seconds
Started May 23 03:44:11 PM PDT 24
Finished May 23 03:44:30 PM PDT 24
Peak memory 204948 kb
Host smart-43997902-4c5e-4a10-8dc6-edb039248856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35428
37643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3542837643
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3627812769
Short name T136
Test name
Test status
Simulation time 10144309791 ps
CPU time 12.85 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:38 PM PDT 24
Peak memory 204952 kb
Host smart-1064d8f7-3273-4ce6-8db4-3feb38c276db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36278
12769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3627812769
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.707092921
Short name T1008
Test name
Test status
Simulation time 10089933151 ps
CPU time 14.67 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:41 PM PDT 24
Peak memory 204960 kb
Host smart-bf29a440-8206-4a80-b2cf-1c671f249683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70709
2921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.707092921
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2682156820
Short name T1177
Test name
Test status
Simulation time 10100809200 ps
CPU time 13.42 seconds
Started May 23 03:44:11 PM PDT 24
Finished May 23 03:44:31 PM PDT 24
Peak memory 204876 kb
Host smart-b09ee779-3125-4c2e-b98d-fda047a66cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26821
56820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2682156820
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.1689717210
Short name T829
Test name
Test status
Simulation time 10139316843 ps
CPU time 13.02 seconds
Started May 23 03:44:15 PM PDT 24
Finished May 23 03:44:37 PM PDT 24
Peak memory 204964 kb
Host smart-30e64045-09f3-4ff7-adf6-8fcc69be1ffd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1689717210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.1689717210
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.2892320700
Short name T1572
Test name
Test status
Simulation time 10119975613 ps
CPU time 15.12 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:45:02 PM PDT 24
Peak memory 204880 kb
Host smart-05695094-16c3-4a5c-b048-a3ee9972ea8d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2892320700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.2892320700
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.3869743636
Short name T1481
Test name
Test status
Simulation time 10132809759 ps
CPU time 13.27 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:45:00 PM PDT 24
Peak memory 204952 kb
Host smart-c82f97c2-ad3a-4518-967d-29541cbb3ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38697
43636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.3869743636
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.672066266
Short name T1193
Test name
Test status
Simulation time 14058213587 ps
CPU time 18.04 seconds
Started May 23 03:44:29 PM PDT 24
Finished May 23 03:44:57 PM PDT 24
Peak memory 204944 kb
Host smart-ece7e213-99ff-411f-a651-987c7aba9b4a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=672066266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.672066266
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3026500108
Short name T988
Test name
Test status
Simulation time 13316510675 ps
CPU time 18.33 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:45:04 PM PDT 24
Peak memory 204932 kb
Host smart-75263524-ef11-4f52-91c6-b30dd9feb507
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3026500108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3026500108
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1462826049
Short name T783
Test name
Test status
Simulation time 13241473604 ps
CPU time 16.71 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:44:36 PM PDT 24
Peak memory 204996 kb
Host smart-5438e563-fb14-4dbc-b32e-f4d8ea53e613
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1462826049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1462826049
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.961086757
Short name T580
Test name
Test status
Simulation time 10043454671 ps
CPU time 13.73 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:34 PM PDT 24
Peak memory 204964 kb
Host smart-d092bbfd-e298-49b9-beda-dd01493f92e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96108
6757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.961086757
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1417882195
Short name T163
Test name
Test status
Simulation time 11608355746 ps
CPU time 19.85 seconds
Started May 23 03:44:11 PM PDT 24
Finished May 23 03:44:38 PM PDT 24
Peak memory 205016 kb
Host smart-1c83d7c5-d7c4-471e-9302-f011aeaa8643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14178
82195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1417882195
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2328986319
Short name T1140
Test name
Test status
Simulation time 10045976373 ps
CPU time 13.76 seconds
Started May 23 03:44:28 PM PDT 24
Finished May 23 03:44:53 PM PDT 24
Peak memory 205012 kb
Host smart-2ff9e22d-bc10-4c3c-914e-9ee9bda7226d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23289
86319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2328986319
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.1765276114
Short name T1605
Test name
Test status
Simulation time 10042702030 ps
CPU time 14.08 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:34 PM PDT 24
Peak memory 204892 kb
Host smart-f3bca0f9-e0f2-4907-806b-7eb69c0c3547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17652
76114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1765276114
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2078809269
Short name T1163
Test name
Test status
Simulation time 10067471287 ps
CPU time 13.35 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:39 PM PDT 24
Peak memory 204948 kb
Host smart-9f4eea12-ead5-4dee-bcf9-175daca8f3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20788
09269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2078809269
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1173016025
Short name T331
Test name
Test status
Simulation time 10121196931 ps
CPU time 12.97 seconds
Started May 23 03:44:16 PM PDT 24
Finished May 23 03:44:38 PM PDT 24
Peak memory 204956 kb
Host smart-09b52c50-25cb-4560-b94b-fef963ad1514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11730
16025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1173016025
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.636387207
Short name T1286
Test name
Test status
Simulation time 10034594860 ps
CPU time 12.82 seconds
Started May 23 03:44:32 PM PDT 24
Finished May 23 03:44:57 PM PDT 24
Peak memory 204944 kb
Host smart-d25644dc-0a83-4d0f-917e-a2734fd11f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63638
7207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.636387207
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3559895542
Short name T1133
Test name
Test status
Simulation time 10148139957 ps
CPU time 12.58 seconds
Started May 23 03:44:30 PM PDT 24
Finished May 23 03:44:55 PM PDT 24
Peak memory 205036 kb
Host smart-19314693-3648-4502-96fb-843865332d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35598
95542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3559895542
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.2996194074
Short name T462
Test name
Test status
Simulation time 10115831921 ps
CPU time 14.57 seconds
Started May 23 03:44:23 PM PDT 24
Finished May 23 03:44:47 PM PDT 24
Peak memory 204936 kb
Host smart-a2782038-5269-42fa-8673-1d325d51b1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29961
94074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.2996194074
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.632187147
Short name T707
Test name
Test status
Simulation time 13220275637 ps
CPU time 17.05 seconds
Started May 23 03:44:16 PM PDT 24
Finished May 23 03:44:43 PM PDT 24
Peak memory 204920 kb
Host smart-54fc7041-ccdd-420b-9e20-035a6babfa5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63218
7147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.632187147
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2007006033
Short name T1248
Test name
Test status
Simulation time 10141363956 ps
CPU time 12.94 seconds
Started May 23 03:44:12 PM PDT 24
Finished May 23 03:44:32 PM PDT 24
Peak memory 204980 kb
Host smart-dcd9f12a-0d40-4fa3-afb9-0b2e28769e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20070
06033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2007006033
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2373400335
Short name T1907
Test name
Test status
Simulation time 10044696775 ps
CPU time 16.18 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:45:02 PM PDT 24
Peak memory 205052 kb
Host smart-b23626fc-bb3a-467d-a47d-4c2fcb11c2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23734
00335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2373400335
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2772903300
Short name T68
Test name
Test status
Simulation time 10154353002 ps
CPU time 13.68 seconds
Started May 23 03:44:31 PM PDT 24
Finished May 23 03:44:57 PM PDT 24
Peak memory 204948 kb
Host smart-f59bfb61-2244-4838-82f8-1982857d3242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27729
03300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2772903300
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.529645957
Short name T458
Test name
Test status
Simulation time 10094477487 ps
CPU time 14.26 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:34 PM PDT 24
Peak memory 204964 kb
Host smart-8124a5d6-e285-4d1a-bb8d-32a5406d74c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52964
5957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.529645957
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1220853689
Short name T514
Test name
Test status
Simulation time 10089458537 ps
CPU time 13.14 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:39 PM PDT 24
Peak memory 204984 kb
Host smart-458a3541-1550-46df-9bd9-6328258d2021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12208
53689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1220853689
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1736636329
Short name T1920
Test name
Test status
Simulation time 10054542252 ps
CPU time 13.47 seconds
Started May 23 03:44:15 PM PDT 24
Finished May 23 03:44:37 PM PDT 24
Peak memory 204992 kb
Host smart-3f7f5ff0-9696-4a27-8a24-7d15caafc17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17366
36329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1736636329
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3429286122
Short name T1021
Test name
Test status
Simulation time 10077381411 ps
CPU time 12.93 seconds
Started May 23 03:44:13 PM PDT 24
Finished May 23 03:44:33 PM PDT 24
Peak memory 204960 kb
Host smart-1aa94581-5d76-4b13-a308-fc0cf15f2905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34292
86122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3429286122
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.1444754761
Short name T423
Test name
Test status
Simulation time 10067165361 ps
CPU time 13.94 seconds
Started May 23 03:44:19 PM PDT 24
Finished May 23 03:44:42 PM PDT 24
Peak memory 204936 kb
Host smart-4484e13d-8afe-4483-9036-9e05ee4d87af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14447
54761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.1444754761
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3193151057
Short name T1067
Test name
Test status
Simulation time 10112951596 ps
CPU time 13.54 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:05 PM PDT 24
Peak memory 204940 kb
Host smart-56c740d9-ed78-4776-886e-b19b3ff3c3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31931
51057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3193151057
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.721953705
Short name T1317
Test name
Test status
Simulation time 10049062281 ps
CPU time 13.13 seconds
Started May 23 03:44:19 PM PDT 24
Finished May 23 03:44:42 PM PDT 24
Peak memory 204952 kb
Host smart-7b7664fc-0797-47e7-9a68-d86ad108699c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72195
3705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.721953705
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2614666988
Short name T1582
Test name
Test status
Simulation time 20711685247 ps
CPU time 39.83 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:45:27 PM PDT 24
Peak memory 205012 kb
Host smart-da90e58e-c8be-4f02-b422-66f3c7093c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26146
66988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2614666988
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2404744483
Short name T1774
Test name
Test status
Simulation time 10069383119 ps
CPU time 12.67 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:45:02 PM PDT 24
Peak memory 205004 kb
Host smart-82db7788-e130-4b3d-9d7c-188d485a3fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24047
44483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2404744483
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2597896081
Short name T479
Test name
Test status
Simulation time 10071751241 ps
CPU time 13.59 seconds
Started May 23 03:44:29 PM PDT 24
Finished May 23 03:44:53 PM PDT 24
Peak memory 204944 kb
Host smart-a4cea997-0535-49be-93c7-478ffef13c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25978
96081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2597896081
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.3256880288
Short name T312
Test name
Test status
Simulation time 10083885984 ps
CPU time 13.31 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:45:00 PM PDT 24
Peak memory 204880 kb
Host smart-5c6274a9-f76b-4174-9d4b-7828a8a66577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32568
80288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.3256880288
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.3186950530
Short name T1568
Test name
Test status
Simulation time 10033981867 ps
CPU time 13.15 seconds
Started May 23 03:44:15 PM PDT 24
Finished May 23 03:44:36 PM PDT 24
Peak memory 204908 kb
Host smart-9853b8a5-f496-40b3-88f8-eab542a879d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31869
50530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.3186950530
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1021499073
Short name T577
Test name
Test status
Simulation time 10071291506 ps
CPU time 12.94 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:45:02 PM PDT 24
Peak memory 204992 kb
Host smart-e6a35b8e-66f1-4680-9a8f-81d2a5166b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10214
99073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1021499073
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2797502887
Short name T1592
Test name
Test status
Simulation time 10056819958 ps
CPU time 13.02 seconds
Started May 23 03:44:32 PM PDT 24
Finished May 23 03:44:59 PM PDT 24
Peak memory 204916 kb
Host smart-03308bb7-9753-499d-8d19-0b7826e45946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27975
02887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2797502887
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1711588582
Short name T140
Test name
Test status
Simulation time 10127315781 ps
CPU time 12.95 seconds
Started May 23 03:44:08 PM PDT 24
Finished May 23 03:44:28 PM PDT 24
Peak memory 205012 kb
Host smart-78acd4fc-59ad-408c-82b7-386950f78852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17115
88582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1711588582
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.801828703
Short name T1377
Test name
Test status
Simulation time 10139344510 ps
CPU time 14.18 seconds
Started May 23 03:44:17 PM PDT 24
Finished May 23 03:44:40 PM PDT 24
Peak memory 204792 kb
Host smart-05fa7eb2-792b-4cfe-9916-77dbf25c410a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80182
8703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.801828703
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2972677764
Short name T1242
Test name
Test status
Simulation time 10056299016 ps
CPU time 13.92 seconds
Started May 23 03:44:25 PM PDT 24
Finished May 23 03:44:48 PM PDT 24
Peak memory 204940 kb
Host smart-02f73866-6076-4223-a2b3-a2aef2d640fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29726
77764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2972677764
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.1084813008
Short name T1431
Test name
Test status
Simulation time 10147148203 ps
CPU time 13.06 seconds
Started May 23 03:44:41 PM PDT 24
Finished May 23 03:45:09 PM PDT 24
Peak memory 204960 kb
Host smart-bca2146f-a622-4106-a9d7-6e5e0722d599
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1084813008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.1084813008
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.63569867
Short name T430
Test name
Test status
Simulation time 10067631010 ps
CPU time 13.12 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:11 PM PDT 24
Peak memory 204972 kb
Host smart-5c009d66-5f09-4099-bd3f-69cd25c9c0a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=63569867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.63569867
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.1683133774
Short name T1839
Test name
Test status
Simulation time 10049740205 ps
CPU time 13.42 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:45:13 PM PDT 24
Peak memory 204900 kb
Host smart-ab504a31-f6a4-4b41-b60e-e58e5cb87384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16831
33774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.1683133774
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.2684203649
Short name T1941
Test name
Test status
Simulation time 13999208732 ps
CPU time 16.12 seconds
Started May 23 03:44:18 PM PDT 24
Finished May 23 03:44:44 PM PDT 24
Peak memory 204928 kb
Host smart-c77e2292-933d-40d8-89f1-854f67e83ea0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2684203649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.2684203649
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.790654668
Short name T10
Test name
Test status
Simulation time 13248720586 ps
CPU time 15.36 seconds
Started May 23 03:44:35 PM PDT 24
Finished May 23 03:45:03 PM PDT 24
Peak memory 204976 kb
Host smart-0ac974bb-0d0a-427d-8de3-33cc87cc4754
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=790654668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.790654668
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3184562141
Short name T679
Test name
Test status
Simulation time 13259709591 ps
CPU time 19.33 seconds
Started May 23 03:44:30 PM PDT 24
Finished May 23 03:45:02 PM PDT 24
Peak memory 204956 kb
Host smart-20bb47e8-e890-4a94-acb9-5edc45c384f8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3184562141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.3184562141
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3864096925
Short name T305
Test name
Test status
Simulation time 10062359611 ps
CPU time 13.09 seconds
Started May 23 03:44:14 PM PDT 24
Finished May 23 03:44:36 PM PDT 24
Peak memory 205000 kb
Host smart-47974a24-9d6b-468b-8f51-aa946c3b63e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38640
96925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3864096925
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2755466809
Short name T1475
Test name
Test status
Simulation time 11040055956 ps
CPU time 14.96 seconds
Started May 23 03:44:24 PM PDT 24
Finished May 23 03:44:49 PM PDT 24
Peak memory 205020 kb
Host smart-fe906641-e29b-4dce-828a-0847ac777dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27554
66809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2755466809
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.624205379
Short name T1252
Test name
Test status
Simulation time 10038611811 ps
CPU time 12.97 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:44:59 PM PDT 24
Peak memory 204940 kb
Host smart-d6540f5f-d128-436e-9ba9-f9e810405de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62420
5379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.624205379
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.2889463894
Short name T1204
Test name
Test status
Simulation time 10055504271 ps
CPU time 13.97 seconds
Started May 23 03:44:35 PM PDT 24
Finished May 23 03:45:01 PM PDT 24
Peak memory 205008 kb
Host smart-ba2d40cb-e6d5-450d-95ea-6584281e4a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28894
63894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2889463894
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2132042624
Short name T910
Test name
Test status
Simulation time 10682019043 ps
CPU time 13.5 seconds
Started May 23 03:44:16 PM PDT 24
Finished May 23 03:44:38 PM PDT 24
Peak memory 204976 kb
Host smart-75bf25f5-a880-4f3c-af2c-45f57aa13e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21320
42624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2132042624
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1799120610
Short name T976
Test name
Test status
Simulation time 10081008414 ps
CPU time 14.31 seconds
Started May 23 03:44:32 PM PDT 24
Finished May 23 03:44:59 PM PDT 24
Peak memory 204940 kb
Host smart-65dd30b7-5300-4494-a6c7-23019604726d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17991
20610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1799120610
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.813531054
Short name T1079
Test name
Test status
Simulation time 10179933385 ps
CPU time 13.17 seconds
Started May 23 03:44:40 PM PDT 24
Finished May 23 03:45:07 PM PDT 24
Peak memory 204896 kb
Host smart-a052d4fb-b107-45dd-b374-63361f956f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81353
1054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.813531054
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1582908819
Short name T325
Test name
Test status
Simulation time 10088933304 ps
CPU time 14.18 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:06 PM PDT 24
Peak memory 204912 kb
Host smart-4acc2fdc-b805-4988-93c3-832b829b5a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15829
08819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1582908819
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.255057448
Short name T1412
Test name
Test status
Simulation time 10122943717 ps
CPU time 13.23 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:45:00 PM PDT 24
Peak memory 204976 kb
Host smart-78b158d3-daa3-48c3-9508-eada04e17486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25505
7448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.255057448
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.745724469
Short name T1693
Test name
Test status
Simulation time 10110257394 ps
CPU time 12.72 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:44:59 PM PDT 24
Peak memory 204944 kb
Host smart-9c0b23c8-0d8d-4234-9566-1b7588b5392f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74572
4469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.745724469
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3976537459
Short name T1102
Test name
Test status
Simulation time 13200191814 ps
CPU time 19.09 seconds
Started May 23 03:44:25 PM PDT 24
Finished May 23 03:44:54 PM PDT 24
Peak memory 204876 kb
Host smart-d55871ed-f806-4b2d-9973-5e4aa94d38d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39765
37459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3976537459
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1851516559
Short name T1151
Test name
Test status
Simulation time 10104788125 ps
CPU time 13.32 seconds
Started May 23 03:44:19 PM PDT 24
Finished May 23 03:44:42 PM PDT 24
Peak memory 204936 kb
Host smart-9d548b63-cdf3-41be-a214-824ba5cd6c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18515
16559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1851516559
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.46189701
Short name T1355
Test name
Test status
Simulation time 10033982547 ps
CPU time 14.23 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:45:05 PM PDT 24
Peak memory 204940 kb
Host smart-fb2fcb20-8cec-4d80-93fe-756951f5def5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46189
701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.46189701
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.605481138
Short name T121
Test name
Test status
Simulation time 10123842681 ps
CPU time 12.7 seconds
Started May 23 03:44:32 PM PDT 24
Finished May 23 03:44:58 PM PDT 24
Peak memory 205008 kb
Host smart-a1c9ed76-2861-4c7c-b043-698768fbb28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60548
1138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.605481138
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.1386093757
Short name T343
Test name
Test status
Simulation time 10104875118 ps
CPU time 13.83 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:05 PM PDT 24
Peak memory 204968 kb
Host smart-47cf101d-e89b-4c7a-8eda-766353a1628a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13860
93757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.1386093757
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3751214647
Short name T1639
Test name
Test status
Simulation time 10111140741 ps
CPU time 13.41 seconds
Started May 23 03:44:30 PM PDT 24
Finished May 23 03:44:56 PM PDT 24
Peak memory 204932 kb
Host smart-ece7603f-322d-49a6-8efd-32b6297cf0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37512
14647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3751214647
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2378789042
Short name T1068
Test name
Test status
Simulation time 10058864740 ps
CPU time 14.93 seconds
Started May 23 03:44:24 PM PDT 24
Finished May 23 03:44:48 PM PDT 24
Peak memory 204980 kb
Host smart-ae71ae42-3d89-4134-89fd-505f4fe4b4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23787
89042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2378789042
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.3791556927
Short name T138
Test name
Test status
Simulation time 10111427438 ps
CPU time 15.27 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:45:06 PM PDT 24
Peak memory 204872 kb
Host smart-37d4a516-4444-48f5-bb47-28a64d605ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37915
56927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3791556927
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.2066033460
Short name T727
Test name
Test status
Simulation time 10041168981 ps
CPU time 15.13 seconds
Started May 23 03:44:39 PM PDT 24
Finished May 23 03:45:08 PM PDT 24
Peak memory 204980 kb
Host smart-78d12381-be49-4c45-9901-6e2167f4642a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20660
33460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.2066033460
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2663756216
Short name T195
Test name
Test status
Simulation time 10118253659 ps
CPU time 14.98 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:07 PM PDT 24
Peak memory 204964 kb
Host smart-8e49d64c-c61f-489b-948d-ef762eec1978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26637
56216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2663756216
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3673502754
Short name T957
Test name
Test status
Simulation time 10043694884 ps
CPU time 12.16 seconds
Started May 23 03:44:35 PM PDT 24
Finished May 23 03:45:01 PM PDT 24
Peak memory 204960 kb
Host smart-1c38f87b-6418-4b41-a42f-c883b05b97d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36735
02754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3673502754
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1107986095
Short name T1493
Test name
Test status
Simulation time 29717658909 ps
CPU time 60.69 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:45:47 PM PDT 24
Peak memory 205020 kb
Host smart-04e70c8e-2467-4a9b-8766-bb3f7aa75b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11079
86095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1107986095
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2159350786
Short name T1788
Test name
Test status
Simulation time 10081115811 ps
CPU time 15.89 seconds
Started May 23 03:44:21 PM PDT 24
Finished May 23 03:44:46 PM PDT 24
Peak memory 204916 kb
Host smart-99f53e15-d813-46e8-bc54-bea305ce6ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21593
50786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2159350786
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2730749169
Short name T216
Test name
Test status
Simulation time 10091899851 ps
CPU time 12.98 seconds
Started May 23 03:44:40 PM PDT 24
Finished May 23 03:45:07 PM PDT 24
Peak memory 204944 kb
Host smart-a7f3a7e0-d1a2-4f4a-9e50-a515e5acbcbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27307
49169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2730749169
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3392418518
Short name T387
Test name
Test status
Simulation time 10120906348 ps
CPU time 13.33 seconds
Started May 23 03:44:43 PM PDT 24
Finished May 23 03:45:11 PM PDT 24
Peak memory 204912 kb
Host smart-e5633331-ad4f-4380-a8f1-40375b463487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33924
18518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3392418518
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2608068815
Short name T413
Test name
Test status
Simulation time 10060612639 ps
CPU time 13.02 seconds
Started May 23 03:44:35 PM PDT 24
Finished May 23 03:45:01 PM PDT 24
Peak memory 204920 kb
Host smart-781bba46-9872-4ff6-aa2e-3bda5e80dda5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26080
68815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2608068815
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2928331307
Short name T145
Test name
Test status
Simulation time 10051939012 ps
CPU time 14.41 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:45:05 PM PDT 24
Peak memory 204900 kb
Host smart-1134a23d-85e1-45ac-add3-4edd3157ce3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29283
31307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2928331307
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3314876206
Short name T1660
Test name
Test status
Simulation time 10055639681 ps
CPU time 12.48 seconds
Started May 23 03:44:40 PM PDT 24
Finished May 23 03:45:07 PM PDT 24
Peak memory 204928 kb
Host smart-3e9258bc-f5cd-4b7b-85c4-b6ce952e2a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33148
76206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3314876206
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1056676303
Short name T875
Test name
Test status
Simulation time 10097362010 ps
CPU time 16.26 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:08 PM PDT 24
Peak memory 204976 kb
Host smart-ace0f9db-bcb1-41f9-853d-8ad5513210fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10566
76303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1056676303
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.790330334
Short name T415
Test name
Test status
Simulation time 10121340695 ps
CPU time 13.35 seconds
Started May 23 03:44:37 PM PDT 24
Finished May 23 03:45:04 PM PDT 24
Peak memory 204936 kb
Host smart-000e9779-892d-4937-b23f-3c4d2ade57e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79033
0334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.790330334
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3792612734
Short name T464
Test name
Test status
Simulation time 10085861659 ps
CPU time 12.52 seconds
Started May 23 03:44:40 PM PDT 24
Finished May 23 03:45:06 PM PDT 24
Peak memory 204960 kb
Host smart-e68d95ba-87f0-4e21-9737-c3da711a067e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37926
12734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3792612734
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.1129359159
Short name T817
Test name
Test status
Simulation time 10150145930 ps
CPU time 15 seconds
Started May 23 03:45:01 PM PDT 24
Finished May 23 03:45:34 PM PDT 24
Peak memory 204868 kb
Host smart-68b0c714-0915-4931-998f-8196de94bee7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1129359159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.1129359159
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.3277131349
Short name T1638
Test name
Test status
Simulation time 10066595492 ps
CPU time 14.87 seconds
Started May 23 03:45:04 PM PDT 24
Finished May 23 03:45:37 PM PDT 24
Peak memory 204960 kb
Host smart-26493609-d26f-46bb-a7f9-1af447d01561
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3277131349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.3277131349
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.2931715384
Short name T1256
Test name
Test status
Simulation time 10106010807 ps
CPU time 13.18 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:45:14 PM PDT 24
Peak memory 204916 kb
Host smart-6b120dec-0714-4c9d-8e30-e5d546d740a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29317
15384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.2931715384
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2417685753
Short name T555
Test name
Test status
Simulation time 13748267837 ps
CPU time 16.58 seconds
Started May 23 03:44:33 PM PDT 24
Finished May 23 03:45:03 PM PDT 24
Peak memory 204912 kb
Host smart-f80275e1-5e24-4f20-92a3-317740dea2ba
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2417685753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.2417685753
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2259911971
Short name T1283
Test name
Test status
Simulation time 13349386430 ps
CPU time 17.21 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:17 PM PDT 24
Peak memory 204956 kb
Host smart-dd672c43-8570-4f00-902d-fcf76d3c99c9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2259911971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2259911971
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.2506928691
Short name T1397
Test name
Test status
Simulation time 13309036260 ps
CPU time 16.94 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:09 PM PDT 24
Peak memory 204968 kb
Host smart-54f2cee0-fa03-463e-bc74-f4043c18f834
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2506928691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.2506928691
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.4197365991
Short name T1165
Test name
Test status
Simulation time 10076399163 ps
CPU time 13.88 seconds
Started May 23 03:44:34 PM PDT 24
Finished May 23 03:45:01 PM PDT 24
Peak memory 204960 kb
Host smart-f178017e-fd64-43aa-a3d7-505d503753d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41973
65991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.4197365991
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.364033846
Short name T46
Test name
Test status
Simulation time 10067178339 ps
CPU time 14.03 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:06 PM PDT 24
Peak memory 204928 kb
Host smart-02ca0091-a1dd-42cf-9149-afd4a42b551e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36403
3846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.364033846
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2974292271
Short name T1697
Test name
Test status
Simulation time 10992314502 ps
CPU time 15.57 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:07 PM PDT 24
Peak memory 205060 kb
Host smart-12abda14-ce2b-408b-9b5f-863fe61f54a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29742
92271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2974292271
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3601487865
Short name T1179
Test name
Test status
Simulation time 10044079999 ps
CPU time 13.37 seconds
Started May 23 03:44:43 PM PDT 24
Finished May 23 03:45:11 PM PDT 24
Peak memory 204896 kb
Host smart-8ec0edf5-7d3a-4f8d-a710-0c81f840a0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36014
87865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3601487865
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.137232710
Short name T1580
Test name
Test status
Simulation time 10090092056 ps
CPU time 15.47 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:07 PM PDT 24
Peak memory 204960 kb
Host smart-74560440-5b94-4e9f-b820-f42a043b964f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13723
2710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.137232710
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2067775009
Short name T1713
Test name
Test status
Simulation time 10782607636 ps
CPU time 14.9 seconds
Started May 23 03:44:41 PM PDT 24
Finished May 23 03:45:10 PM PDT 24
Peak memory 205000 kb
Host smart-b5720f0e-ad5f-405b-b15c-78ac88280d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20677
75009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2067775009
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.836713254
Short name T790
Test name
Test status
Simulation time 10141510457 ps
CPU time 14.54 seconds
Started May 23 03:44:38 PM PDT 24
Finished May 23 03:45:06 PM PDT 24
Peak memory 204876 kb
Host smart-ca41df54-6b7f-4daa-8338-caf1423d21c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83671
3254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.836713254
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.983563500
Short name T646
Test name
Test status
Simulation time 10081308755 ps
CPU time 13.24 seconds
Started May 23 03:45:03 PM PDT 24
Finished May 23 03:45:34 PM PDT 24
Peak memory 204912 kb
Host smart-73ef9c47-95e4-470f-b146-6b830d6532a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98356
3500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.983563500
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.856080889
Short name T1537
Test name
Test status
Simulation time 10039026543 ps
CPU time 12.59 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:11 PM PDT 24
Peak memory 204932 kb
Host smart-02114408-08e1-4391-ae5c-bccc1da4ab59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85608
0889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.856080889
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2350339620
Short name T398
Test name
Test status
Simulation time 10165087955 ps
CPU time 13.47 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:45:14 PM PDT 24
Peak memory 204964 kb
Host smart-3f5dbaf2-3389-4fc7-834a-1b8b25b4c905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23503
39620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2350339620
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2647235879
Short name T382
Test name
Test status
Simulation time 10071474425 ps
CPU time 12.96 seconds
Started May 23 03:44:43 PM PDT 24
Finished May 23 03:45:10 PM PDT 24
Peak memory 204908 kb
Host smart-f942e82f-a813-4d31-b057-8b2ffec5c338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26472
35879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2647235879
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1279715774
Short name T884
Test name
Test status
Simulation time 13253352207 ps
CPU time 15.81 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:14 PM PDT 24
Peak memory 204956 kb
Host smart-c8e437eb-82d3-480c-9a5f-396066ec1002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12797
15774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1279715774
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2017969689
Short name T593
Test name
Test status
Simulation time 10106596336 ps
CPU time 15.64 seconds
Started May 23 03:45:01 PM PDT 24
Finished May 23 03:45:34 PM PDT 24
Peak memory 204948 kb
Host smart-ca9f1de0-3864-458c-b2d9-37120bbde373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20179
69689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2017969689
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.4199512018
Short name T1570
Test name
Test status
Simulation time 10092104355 ps
CPU time 15.12 seconds
Started May 23 03:44:43 PM PDT 24
Finished May 23 03:45:12 PM PDT 24
Peak memory 204992 kb
Host smart-ca30bcf5-802d-41b3-991b-728b2924ae0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41995
12018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.4199512018
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1811504992
Short name T133
Test name
Test status
Simulation time 10079952387 ps
CPU time 13.3 seconds
Started May 23 03:44:47 PM PDT 24
Finished May 23 03:45:18 PM PDT 24
Peak memory 204916 kb
Host smart-9ee58927-9f75-41a4-83b6-c4408a739ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18115
04992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1811504992
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1479496956
Short name T1209
Test name
Test status
Simulation time 10087226899 ps
CPU time 13.33 seconds
Started May 23 03:44:51 PM PDT 24
Finished May 23 03:45:22 PM PDT 24
Peak memory 204968 kb
Host smart-4d9eecac-11e7-45f9-9377-24f6b2265baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14794
96956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1479496956
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3408562873
Short name T1214
Test name
Test status
Simulation time 10124922670 ps
CPU time 13.91 seconds
Started May 23 03:44:47 PM PDT 24
Finished May 23 03:45:18 PM PDT 24
Peak memory 204952 kb
Host smart-7b5a6169-a0b8-4604-8db5-2fa3c97deda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34085
62873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3408562873
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.614877293
Short name T511
Test name
Test status
Simulation time 10090945471 ps
CPU time 13.08 seconds
Started May 23 03:44:48 PM PDT 24
Finished May 23 03:45:18 PM PDT 24
Peak memory 205024 kb
Host smart-4fc9f386-ca00-4c3c-bec9-1f1b6c2c8ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61487
7293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.614877293
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1982904368
Short name T1591
Test name
Test status
Simulation time 10058040129 ps
CPU time 15.39 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:45:16 PM PDT 24
Peak memory 204984 kb
Host smart-7de60d10-1021-44a1-9001-c13c5c171410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19829
04368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1982904368
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.2624512025
Short name T1391
Test name
Test status
Simulation time 10075463552 ps
CPU time 13.63 seconds
Started May 23 03:44:56 PM PDT 24
Finished May 23 03:45:28 PM PDT 24
Peak memory 205004 kb
Host smart-a6fda779-bf29-40eb-bdab-0cd9610ba644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26245
12025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.2624512025
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1105736189
Short name T563
Test name
Test status
Simulation time 10088523417 ps
CPU time 13.24 seconds
Started May 23 03:44:46 PM PDT 24
Finished May 23 03:45:14 PM PDT 24
Peak memory 204996 kb
Host smart-c8eb1fd5-a2b7-49b1-918a-7d8284eff28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11057
36189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1105736189
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3267708653
Short name T385
Test name
Test status
Simulation time 10056731372 ps
CPU time 13.65 seconds
Started May 23 03:44:45 PM PDT 24
Finished May 23 03:45:14 PM PDT 24
Peak memory 204964 kb
Host smart-5e308782-2ead-47c0-be5c-e1f5bb450176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32677
08653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3267708653
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1299041585
Short name T1418
Test name
Test status
Simulation time 23032351786 ps
CPU time 49.72 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:48 PM PDT 24
Peak memory 205004 kb
Host smart-f4d5f822-1ea3-4fe6-9809-661786006475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12990
41585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1299041585
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3430390405
Short name T1641
Test name
Test status
Simulation time 10115783897 ps
CPU time 13.8 seconds
Started May 23 03:44:47 PM PDT 24
Finished May 23 03:45:18 PM PDT 24
Peak memory 205008 kb
Host smart-10923feb-6716-4f21-97b6-c0095013c507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34303
90405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3430390405
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.546344411
Short name T909
Test name
Test status
Simulation time 10092328150 ps
CPU time 12.67 seconds
Started May 23 03:44:51 PM PDT 24
Finished May 23 03:45:21 PM PDT 24
Peak memory 204920 kb
Host smart-0c7291d6-232a-4a5e-8d2f-d330a9c34889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54634
4411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.546344411
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.2104753857
Short name T1017
Test name
Test status
Simulation time 10142884698 ps
CPU time 13.32 seconds
Started May 23 03:44:42 PM PDT 24
Finished May 23 03:45:09 PM PDT 24
Peak memory 204928 kb
Host smart-7e8cd963-600b-426b-a524-a01aeab984a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21047
53857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.2104753857
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3343541703
Short name T674
Test name
Test status
Simulation time 10041363981 ps
CPU time 13.34 seconds
Started May 23 03:44:57 PM PDT 24
Finished May 23 03:45:29 PM PDT 24
Peak memory 204952 kb
Host smart-42fb8306-50b1-4c61-bb75-513dc74373d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33435
41703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3343541703
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.3384983187
Short name T1009
Test name
Test status
Simulation time 10050127856 ps
CPU time 14.15 seconds
Started May 23 03:44:44 PM PDT 24
Finished May 23 03:45:12 PM PDT 24
Peak memory 204968 kb
Host smart-d6eecc97-e765-46bc-a469-fee5287828c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33849
83187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3384983187
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.4173787922
Short name T1393
Test name
Test status
Simulation time 10066178200 ps
CPU time 13.41 seconds
Started May 23 03:44:43 PM PDT 24
Finished May 23 03:45:11 PM PDT 24
Peak memory 204932 kb
Host smart-000f35b2-dd29-4d49-a95b-1f33c8552278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41737
87922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.4173787922
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3145646549
Short name T752
Test name
Test status
Simulation time 10151360978 ps
CPU time 12.46 seconds
Started May 23 03:44:36 PM PDT 24
Finished May 23 03:45:02 PM PDT 24
Peak memory 204960 kb
Host smart-23274dc4-01e5-4d0b-aea0-0d9b3fa6ed09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31456
46549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3145646549
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2258923628
Short name T1687
Test name
Test status
Simulation time 10069246221 ps
CPU time 13.01 seconds
Started May 23 03:44:50 PM PDT 24
Finished May 23 03:45:20 PM PDT 24
Peak memory 204904 kb
Host smart-83f9731c-706d-44ae-a469-c08da68b3143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22589
23628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2258923628
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.459954414
Short name T1084
Test name
Test status
Simulation time 10083952445 ps
CPU time 14.02 seconds
Started May 23 03:44:53 PM PDT 24
Finished May 23 03:45:26 PM PDT 24
Peak memory 205000 kb
Host smart-6f2ad6ef-c37d-49fe-a35a-446a6128648e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45995
4414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.459954414
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.2446193344
Short name T1930
Test name
Test status
Simulation time 10132769271 ps
CPU time 13.98 seconds
Started May 23 03:40:06 PM PDT 24
Finished May 23 03:40:30 PM PDT 24
Peak memory 204976 kb
Host smart-33b17e44-03c0-461e-8589-dd9812a7cc7c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2446193344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.2446193344
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.2584813609
Short name T1820
Test name
Test status
Simulation time 10051511762 ps
CPU time 14.04 seconds
Started May 23 03:40:02 PM PDT 24
Finished May 23 03:40:26 PM PDT 24
Peak memory 205008 kb
Host smart-ccda3186-2032-4fae-8e3e-cc8133081a83
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2584813609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.2584813609
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.2758438072
Short name T1302
Test name
Test status
Simulation time 10113774971 ps
CPU time 14.35 seconds
Started May 23 03:40:05 PM PDT 24
Finished May 23 03:40:29 PM PDT 24
Peak memory 204964 kb
Host smart-968508dc-4e20-4961-8e65-ede0898dd90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27584
38072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.2758438072
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.334632591
Short name T1131
Test name
Test status
Simulation time 13553546348 ps
CPU time 16.4 seconds
Started May 23 03:39:56 PM PDT 24
Finished May 23 03:40:23 PM PDT 24
Peak memory 204576 kb
Host smart-836af276-f201-477c-a17a-26d7ce4d8a53
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=334632591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.334632591
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2060894412
Short name T1661
Test name
Test status
Simulation time 13252171518 ps
CPU time 17.81 seconds
Started May 23 03:40:01 PM PDT 24
Finished May 23 03:40:29 PM PDT 24
Peak memory 204984 kb
Host smart-ee27dc49-fda5-45e4-9a81-188400052390
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2060894412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2060894412
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.484147246
Short name T1433
Test name
Test status
Simulation time 13293977629 ps
CPU time 17.58 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:40 PM PDT 24
Peak memory 204928 kb
Host smart-23797800-3ba8-4904-b2ff-0e96ab7efc0d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=484147246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.484147246
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.4122945415
Short name T588
Test name
Test status
Simulation time 10049365170 ps
CPU time 12.45 seconds
Started May 23 03:40:02 PM PDT 24
Finished May 23 03:40:24 PM PDT 24
Peak memory 204940 kb
Host smart-6c0ecc96-b5a9-45ca-9320-8acce7260b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41229
45415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.4122945415
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.138124287
Short name T167
Test name
Test status
Simulation time 10799677847 ps
CPU time 14.47 seconds
Started May 23 03:40:09 PM PDT 24
Finished May 23 03:40:33 PM PDT 24
Peak memory 205044 kb
Host smart-8c32f3bb-e665-41a6-b297-a51816da4737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13812
4287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.138124287
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_enable.2946638694
Short name T1350
Test name
Test status
Simulation time 10050238662 ps
CPU time 12.89 seconds
Started May 23 03:39:56 PM PDT 24
Finished May 23 03:40:20 PM PDT 24
Peak memory 204960 kb
Host smart-2ed388d4-cc44-44db-80b6-eedfe0233be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29466
38694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2946638694
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3578608650
Short name T1381
Test name
Test status
Simulation time 10228040864 ps
CPU time 13.49 seconds
Started May 23 03:39:52 PM PDT 24
Finished May 23 03:40:17 PM PDT 24
Peak memory 205032 kb
Host smart-1abcc373-cf83-4220-997d-c99d5bffadc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35786
08650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3578608650
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3222320748
Short name T1123
Test name
Test status
Simulation time 10068951629 ps
CPU time 14.45 seconds
Started May 23 03:39:54 PM PDT 24
Finished May 23 03:40:19 PM PDT 24
Peak memory 204904 kb
Host smart-65768fc3-a8be-4068-b483-aaf8b7235a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32223
20748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3222320748
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.30202612
Short name T451
Test name
Test status
Simulation time 10088696110 ps
CPU time 14.82 seconds
Started May 23 03:39:57 PM PDT 24
Finished May 23 03:40:22 PM PDT 24
Peak memory 204964 kb
Host smart-e6fffc0a-da35-405a-9bb6-68234c28e4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30202
612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.30202612
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.857939147
Short name T1546
Test name
Test status
Simulation time 10122416474 ps
CPU time 13 seconds
Started May 23 03:40:06 PM PDT 24
Finished May 23 03:40:29 PM PDT 24
Peak memory 205012 kb
Host smart-a2e2b05c-014d-4bed-bb3a-310a1f9ebf60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85793
9147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.857939147
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1582562859
Short name T928
Test name
Test status
Simulation time 10070572808 ps
CPU time 13.18 seconds
Started May 23 03:40:14 PM PDT 24
Finished May 23 03:40:37 PM PDT 24
Peak memory 204956 kb
Host smart-408871ed-4b40-46df-8466-a002b9f393e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15825
62859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1582562859
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.4038938742
Short name T651
Test name
Test status
Simulation time 13197706440 ps
CPU time 15.18 seconds
Started May 23 03:39:51 PM PDT 24
Finished May 23 03:40:17 PM PDT 24
Peak memory 204924 kb
Host smart-dee5767c-3fed-4b50-a3df-0f1e1bad1946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40389
38742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.4038938742
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2514762769
Short name T919
Test name
Test status
Simulation time 10085239867 ps
CPU time 13.04 seconds
Started May 23 03:39:54 PM PDT 24
Finished May 23 03:40:18 PM PDT 24
Peak memory 204944 kb
Host smart-eb9f1a82-08a8-472d-a3f7-0b8c70fd0861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25147
62769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2514762769
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3593217883
Short name T597
Test name
Test status
Simulation time 10040638927 ps
CPU time 14.3 seconds
Started May 23 03:40:03 PM PDT 24
Finished May 23 03:40:27 PM PDT 24
Peak memory 204952 kb
Host smart-d49b1fe0-4687-4700-a023-fa54445d7d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35932
17883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3593217883
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1173285920
Short name T1645
Test name
Test status
Simulation time 10101306100 ps
CPU time 14.86 seconds
Started May 23 03:39:54 PM PDT 24
Finished May 23 03:40:20 PM PDT 24
Peak memory 204952 kb
Host smart-7bf9e6d1-36d0-4f4f-b6da-555e392957cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11732
85920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1173285920
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.1965310433
Short name T1322
Test name
Test status
Simulation time 10144129747 ps
CPU time 13.3 seconds
Started May 23 03:40:06 PM PDT 24
Finished May 23 03:40:29 PM PDT 24
Peak memory 204924 kb
Host smart-e4f89547-e377-4926-a1fa-d5a613a69c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19653
10433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.1965310433
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1857254003
Short name T1583
Test name
Test status
Simulation time 10093843713 ps
CPU time 15.38 seconds
Started May 23 03:40:03 PM PDT 24
Finished May 23 03:40:28 PM PDT 24
Peak memory 204908 kb
Host smart-089c0fb0-eef6-4199-83bb-d38e5dea6edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18572
54003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1857254003
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.127925385
Short name T76
Test name
Test status
Simulation time 10053130665 ps
CPU time 14.62 seconds
Started May 23 03:39:56 PM PDT 24
Finished May 23 03:40:22 PM PDT 24
Peak memory 204960 kb
Host smart-bc839918-5e19-4f72-afb9-0bf1f53f12dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12792
5385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.127925385
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.729275944
Short name T1277
Test name
Test status
Simulation time 10120192329 ps
CPU time 14.74 seconds
Started May 23 03:40:05 PM PDT 24
Finished May 23 03:40:29 PM PDT 24
Peak memory 204964 kb
Host smart-df602763-39f6-4db9-ac16-d95cf7bcf77e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72927
5944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.729275944
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.1413984248
Short name T1634
Test name
Test status
Simulation time 10115106901 ps
CPU time 13.61 seconds
Started May 23 03:40:15 PM PDT 24
Finished May 23 03:40:39 PM PDT 24
Peak memory 204948 kb
Host smart-1daccf19-c70c-401a-9e1a-2fdae765484a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14139
84248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.1413984248
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3614155412
Short name T460
Test name
Test status
Simulation time 10046283915 ps
CPU time 12.92 seconds
Started May 23 03:40:14 PM PDT 24
Finished May 23 03:40:37 PM PDT 24
Peak memory 204872 kb
Host smart-c7401fc5-7fbc-4d66-97d0-a0e20d663807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36141
55412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3614155412
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3986908418
Short name T874
Test name
Test status
Simulation time 10042874201 ps
CPU time 13.56 seconds
Started May 23 03:39:54 PM PDT 24
Finished May 23 03:40:19 PM PDT 24
Peak memory 204908 kb
Host smart-de3db7a2-9bf3-496e-8e5d-8913fdeb6dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39869
08418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3986908418
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2105438789
Short name T1034
Test name
Test status
Simulation time 17755213727 ps
CPU time 30.03 seconds
Started May 23 03:39:57 PM PDT 24
Finished May 23 03:40:37 PM PDT 24
Peak memory 205028 kb
Host smart-77991551-f7cc-49dd-8557-8f58376f7e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21054
38789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2105438789
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.1362119300
Short name T396
Test name
Test status
Simulation time 10138186630 ps
CPU time 13.09 seconds
Started May 23 03:40:00 PM PDT 24
Finished May 23 03:40:23 PM PDT 24
Peak memory 204984 kb
Host smart-294d714f-98c8-4a1d-a6ee-1231f43a45e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13621
19300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1362119300
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2825567952
Short name T836
Test name
Test status
Simulation time 10145293331 ps
CPU time 13.6 seconds
Started May 23 03:40:03 PM PDT 24
Finished May 23 03:40:27 PM PDT 24
Peak memory 204876 kb
Host smart-0ecfd19f-8314-4cd7-9ae2-6a4a8978eb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28255
67952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2825567952
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1419261561
Short name T1337
Test name
Test status
Simulation time 10056106973 ps
CPU time 12.81 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:31 PM PDT 24
Peak memory 204952 kb
Host smart-6afc14cc-f42c-44be-852f-2ecd2127f61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14192
61561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1419261561
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.441476970
Short name T953
Test name
Test status
Simulation time 10047929552 ps
CPU time 13.26 seconds
Started May 23 03:39:54 PM PDT 24
Finished May 23 03:40:19 PM PDT 24
Peak memory 205056 kb
Host smart-2b5b47b3-51e9-4122-b96a-69e03dd934f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44147
6970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.441476970
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1768252273
Short name T152
Test name
Test status
Simulation time 10098724445 ps
CPU time 12.97 seconds
Started May 23 03:39:55 PM PDT 24
Finished May 23 03:40:19 PM PDT 24
Peak memory 204940 kb
Host smart-454e850f-6c5f-4d95-af24-f8001a67557e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17682
52273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1768252273
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1579322443
Short name T500
Test name
Test status
Simulation time 10054651594 ps
CPU time 15.19 seconds
Started May 23 03:39:52 PM PDT 24
Finished May 23 03:40:18 PM PDT 24
Peak memory 205028 kb
Host smart-4f3da70f-9a39-44c4-87bf-dc5259b3793d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15793
22443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1579322443
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2529634748
Short name T1629
Test name
Test status
Simulation time 10141346771 ps
CPU time 14.94 seconds
Started May 23 03:40:10 PM PDT 24
Finished May 23 03:40:35 PM PDT 24
Peak memory 204924 kb
Host smart-26fb9922-2f07-4add-a848-bf107127aeff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25296
34748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2529634748
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3567563282
Short name T1251
Test name
Test status
Simulation time 10077660020 ps
CPU time 15.48 seconds
Started May 23 03:39:51 PM PDT 24
Finished May 23 03:40:17 PM PDT 24
Peak memory 204984 kb
Host smart-8ed849fa-f6e3-4984-96e8-aa1fcca8c46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35675
63282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3567563282
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3814872492
Short name T489
Test name
Test status
Simulation time 10062298778 ps
CPU time 13.99 seconds
Started May 23 03:39:56 PM PDT 24
Finished May 23 03:40:21 PM PDT 24
Peak memory 204996 kb
Host smart-16d5e7d4-06b9-4a51-bb63-c1a057cb9a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38148
72492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3814872492
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.3892071753
Short name T1129
Test name
Test status
Simulation time 10163764958 ps
CPU time 13.31 seconds
Started May 23 03:40:06 PM PDT 24
Finished May 23 03:40:29 PM PDT 24
Peak memory 204968 kb
Host smart-fe719365-5317-4f61-ad14-66e65a17f2cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3892071753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.3892071753
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.2866217372
Short name T1162
Test name
Test status
Simulation time 10053830105 ps
CPU time 14.56 seconds
Started May 23 03:40:00 PM PDT 24
Finished May 23 03:40:25 PM PDT 24
Peak memory 204920 kb
Host smart-2622aa6c-e8ca-402e-845d-c514dab7b0b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2866217372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.2866217372
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.2916269600
Short name T741
Test name
Test status
Simulation time 10141031934 ps
CPU time 14.01 seconds
Started May 23 03:40:13 PM PDT 24
Finished May 23 03:40:37 PM PDT 24
Peak memory 204936 kb
Host smart-a996b05a-ecfe-4696-a278-2495b974a0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29162
69600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.2916269600
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3138345129
Short name T1867
Test name
Test status
Simulation time 14038550157 ps
CPU time 19.68 seconds
Started May 23 03:39:58 PM PDT 24
Finished May 23 03:40:28 PM PDT 24
Peak memory 204992 kb
Host smart-6b3eb6c4-7d21-43a6-a31b-62b72901fbba
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3138345129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3138345129
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3577417748
Short name T780
Test name
Test status
Simulation time 13324565805 ps
CPU time 16.86 seconds
Started May 23 03:39:54 PM PDT 24
Finished May 23 03:40:22 PM PDT 24
Peak memory 204944 kb
Host smart-1a95124b-c156-490d-a3c2-81ee5e3f4203
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3577417748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3577417748
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.657022469
Short name T1808
Test name
Test status
Simulation time 13277015618 ps
CPU time 20.69 seconds
Started May 23 03:40:00 PM PDT 24
Finished May 23 03:40:31 PM PDT 24
Peak memory 204992 kb
Host smart-4682aae0-f24f-4b8b-af5b-35f2feb30672
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=657022469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.657022469
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1991902314
Short name T1943
Test name
Test status
Simulation time 10052754272 ps
CPU time 13.05 seconds
Started May 23 03:40:04 PM PDT 24
Finished May 23 03:40:27 PM PDT 24
Peak memory 204992 kb
Host smart-434727cd-005a-4283-b665-a0d6e3618001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19919
02314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1991902314
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.947538946
Short name T1332
Test name
Test status
Simulation time 10576569377 ps
CPU time 14.88 seconds
Started May 23 03:40:00 PM PDT 24
Finished May 23 03:40:26 PM PDT 24
Peak memory 204944 kb
Host smart-dced345d-d102-486f-8385-6bc38ca567ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94753
8946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.947538946
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.762458811
Short name T982
Test name
Test status
Simulation time 10047171838 ps
CPU time 14.56 seconds
Started May 23 03:40:10 PM PDT 24
Finished May 23 03:40:35 PM PDT 24
Peak memory 204964 kb
Host smart-d5834a48-e8d9-42ce-820a-acd5f4b3f2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76245
8811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.762458811
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3493901979
Short name T1496
Test name
Test status
Simulation time 10093770710 ps
CPU time 12.76 seconds
Started May 23 03:40:13 PM PDT 24
Finished May 23 03:40:36 PM PDT 24
Peak memory 205040 kb
Host smart-ad53ad87-fb92-4e52-a2ea-5efd9956d99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34939
01979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3493901979
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3575027302
Short name T394
Test name
Test status
Simulation time 10871811435 ps
CPU time 13.7 seconds
Started May 23 03:40:00 PM PDT 24
Finished May 23 03:40:24 PM PDT 24
Peak memory 205008 kb
Host smart-e453a747-a4e1-4017-930f-40a210fbb6a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35750
27302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3575027302
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2283432737
Short name T878
Test name
Test status
Simulation time 10106710183 ps
CPU time 13.61 seconds
Started May 23 03:39:58 PM PDT 24
Finished May 23 03:40:22 PM PDT 24
Peak memory 204940 kb
Host smart-1dbb0e90-5137-4adc-ab11-746149eb6c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22834
32737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2283432737
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.107028025
Short name T879
Test name
Test status
Simulation time 10070042626 ps
CPU time 12.84 seconds
Started May 23 03:40:09 PM PDT 24
Finished May 23 03:40:31 PM PDT 24
Peak memory 204828 kb
Host smart-4ddf72e4-c228-4ca6-845f-32bef36a3e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10702
8025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.107028025
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2342307554
Short name T841
Test name
Test status
Simulation time 10054415627 ps
CPU time 13.35 seconds
Started May 23 03:39:56 PM PDT 24
Finished May 23 03:40:20 PM PDT 24
Peak memory 204936 kb
Host smart-9fa815cb-1fe1-4f56-9b51-7eb431cba558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23423
07554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2342307554
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1285282914
Short name T1875
Test name
Test status
Simulation time 10076429965 ps
CPU time 13.73 seconds
Started May 23 03:40:07 PM PDT 24
Finished May 23 03:40:31 PM PDT 24
Peak memory 204936 kb
Host smart-6a6603d1-02f8-4256-803d-500c1b391fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12852
82914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1285282914
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.4247840851
Short name T569
Test name
Test status
Simulation time 10083107462 ps
CPU time 13.64 seconds
Started May 23 03:40:03 PM PDT 24
Finished May 23 03:40:26 PM PDT 24
Peak memory 204996 kb
Host smart-85169a64-f1cf-4fca-a8a8-7b0d12b7c95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42478
40851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.4247840851
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.948563227
Short name T1686
Test name
Test status
Simulation time 13174655279 ps
CPU time 18.81 seconds
Started May 23 03:39:55 PM PDT 24
Finished May 23 03:40:24 PM PDT 24
Peak memory 204952 kb
Host smart-9d1e2dbd-dd3b-4083-a163-d6ed4e5aa153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94856
3227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.948563227
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3684183503
Short name T973
Test name
Test status
Simulation time 10092381477 ps
CPU time 13.62 seconds
Started May 23 03:40:14 PM PDT 24
Finished May 23 03:40:38 PM PDT 24
Peak memory 204992 kb
Host smart-79545e2d-0f60-4f6e-8263-333b9d343890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36841
83503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3684183503
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3836814262
Short name T967
Test name
Test status
Simulation time 10053558294 ps
CPU time 13.72 seconds
Started May 23 03:39:57 PM PDT 24
Finished May 23 03:40:22 PM PDT 24
Peak memory 204964 kb
Host smart-d523ee0f-34ff-4c54-8bea-ee442225978b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38368
14262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3836814262
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2325302694
Short name T120
Test name
Test status
Simulation time 10089346829 ps
CPU time 12.82 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:31 PM PDT 24
Peak memory 204992 kb
Host smart-8eb6302e-3cdd-4872-8d2e-df298bd5c0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23253
02694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2325302694
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.656822661
Short name T1048
Test name
Test status
Simulation time 10094392462 ps
CPU time 14.71 seconds
Started May 23 03:39:51 PM PDT 24
Finished May 23 03:40:15 PM PDT 24
Peak memory 204928 kb
Host smart-3cc781e6-810f-4085-b1b6-432879868855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65682
2661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.656822661
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1667083608
Short name T853
Test name
Test status
Simulation time 10057660520 ps
CPU time 12.91 seconds
Started May 23 03:40:01 PM PDT 24
Finished May 23 03:40:24 PM PDT 24
Peak memory 204936 kb
Host smart-91405819-3c0d-405b-9b23-8cc237ac2ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16670
83608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1667083608
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3247456117
Short name T1006
Test name
Test status
Simulation time 10062908533 ps
CPU time 13.59 seconds
Started May 23 03:39:58 PM PDT 24
Finished May 23 03:40:22 PM PDT 24
Peak memory 204944 kb
Host smart-7d0a7fa9-c6ea-4bfa-bd7d-af704de98c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32474
56117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3247456117
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1937185170
Short name T650
Test name
Test status
Simulation time 10049429637 ps
CPU time 13.12 seconds
Started May 23 03:40:00 PM PDT 24
Finished May 23 03:40:24 PM PDT 24
Peak memory 204936 kb
Host smart-fd8e4c32-caed-460a-bad4-0f3490563f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19371
85170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1937185170
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_eop_single_bit_handling.3827390422
Short name T1719
Test name
Test status
Simulation time 10086236474 ps
CPU time 14.74 seconds
Started May 23 03:40:18 PM PDT 24
Finished May 23 03:40:43 PM PDT 24
Peak memory 204940 kb
Host smart-70b83c76-0223-48fe-8849-db9e6d8097f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38273
90422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_eop_single_bit_handling.3827390422
Directory /workspace/6.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.1639447664
Short name T1751
Test name
Test status
Simulation time 10040768052 ps
CPU time 13.87 seconds
Started May 23 03:39:59 PM PDT 24
Finished May 23 03:40:23 PM PDT 24
Peak memory 204908 kb
Host smart-c54df403-17f7-44af-a601-9740dc6f0ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16394
47664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.1639447664
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.322177753
Short name T30
Test name
Test status
Simulation time 10033546875 ps
CPU time 13.57 seconds
Started May 23 03:40:01 PM PDT 24
Finished May 23 03:40:25 PM PDT 24
Peak memory 204940 kb
Host smart-83ca5f30-d6b0-4006-bb42-85a3332e3958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32217
7753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.322177753
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1641389788
Short name T168
Test name
Test status
Simulation time 19433662810 ps
CPU time 36.03 seconds
Started May 23 03:40:01 PM PDT 24
Finished May 23 03:40:47 PM PDT 24
Peak memory 205004 kb
Host smart-028be72c-e094-4505-8cdd-489ba3ee3ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16413
89788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1641389788
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.593780881
Short name T1372
Test name
Test status
Simulation time 10085598533 ps
CPU time 13.77 seconds
Started May 23 03:40:10 PM PDT 24
Finished May 23 03:40:34 PM PDT 24
Peak memory 204964 kb
Host smart-2d0a2645-5846-4edd-950a-1edafd3de7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59378
0881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.593780881
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2175715168
Short name T407
Test name
Test status
Simulation time 10124657273 ps
CPU time 13.97 seconds
Started May 23 03:40:14 PM PDT 24
Finished May 23 03:40:37 PM PDT 24
Peak memory 204996 kb
Host smart-97214e7d-7ef9-4a65-9182-299fe6c32fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21757
15168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2175715168
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.3461831321
Short name T1816
Test name
Test status
Simulation time 10044356446 ps
CPU time 16.58 seconds
Started May 23 03:40:03 PM PDT 24
Finished May 23 03:40:29 PM PDT 24
Peak memory 205004 kb
Host smart-e5da033a-de46-4ae3-950c-a9b1f7bcefc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34618
31321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.3461831321
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.254326407
Short name T1905
Test name
Test status
Simulation time 10046702219 ps
CPU time 14.68 seconds
Started May 23 03:40:03 PM PDT 24
Finished May 23 03:40:28 PM PDT 24
Peak memory 204988 kb
Host smart-88710b0d-d5f5-42b8-9da3-6a3d2d2696ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25432
6407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.254326407
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1884117499
Short name T630
Test name
Test status
Simulation time 10089892266 ps
CPU time 15.12 seconds
Started May 23 03:40:10 PM PDT 24
Finished May 23 03:40:35 PM PDT 24
Peak memory 204964 kb
Host smart-ec78453a-48b5-4ff6-8d8e-3b3e855a286c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18841
17499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1884117499
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2040441515
Short name T1437
Test name
Test status
Simulation time 10060839743 ps
CPU time 15.14 seconds
Started May 23 03:40:03 PM PDT 24
Finished May 23 03:40:28 PM PDT 24
Peak memory 204956 kb
Host smart-df563677-345a-45d5-9837-b5513b103f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20404
41515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2040441515
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1990936789
Short name T960
Test name
Test status
Simulation time 10138878105 ps
CPU time 13.11 seconds
Started May 23 03:40:10 PM PDT 24
Finished May 23 03:40:33 PM PDT 24
Peak memory 204944 kb
Host smart-49f85495-3ee4-4d70-86b6-c8190b9ea299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19909
36789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1990936789
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.1740715272
Short name T1354
Test name
Test status
Simulation time 10083165447 ps
CPU time 13.71 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:40 PM PDT 24
Peak memory 204960 kb
Host smart-ec57bd0a-ca78-41ea-8ede-73b589c5f642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17407
15272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.1740715272
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3902109199
Short name T351
Test name
Test status
Simulation time 10082132305 ps
CPU time 15.22 seconds
Started May 23 03:39:58 PM PDT 24
Finished May 23 03:40:24 PM PDT 24
Peak memory 204920 kb
Host smart-8b1a7eaa-f0a3-46ce-9c83-ca25059e366b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39021
09199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3902109199
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.1473360246
Short name T1593
Test name
Test status
Simulation time 10149246404 ps
CPU time 15.2 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:33 PM PDT 24
Peak memory 204932 kb
Host smart-92b57b75-6364-464a-a4d0-55aa7cfff3ab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1473360246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.1473360246
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.34697945
Short name T881
Test name
Test status
Simulation time 10100914370 ps
CPU time 15.46 seconds
Started May 23 03:40:15 PM PDT 24
Finished May 23 03:40:40 PM PDT 24
Peak memory 204968 kb
Host smart-f2ee5e43-1bc7-452b-88ce-79236d8f9fe2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=34697945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.34697945
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.3651242988
Short name T784
Test name
Test status
Simulation time 10094151050 ps
CPU time 14.85 seconds
Started May 23 03:40:15 PM PDT 24
Finished May 23 03:40:39 PM PDT 24
Peak memory 204972 kb
Host smart-70e2f8a3-d841-4889-8eab-65e1bc026ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36512
42988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.3651242988
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1102085977
Short name T358
Test name
Test status
Simulation time 13954046771 ps
CPU time 17.58 seconds
Started May 23 03:39:59 PM PDT 24
Finished May 23 03:40:27 PM PDT 24
Peak memory 204976 kb
Host smart-e1ed8614-1790-41c4-9cd7-e0cf305843ca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1102085977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1102085977
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3750872229
Short name T1101
Test name
Test status
Simulation time 13277262057 ps
CPU time 17.72 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:45 PM PDT 24
Peak memory 204900 kb
Host smart-9004beb0-3703-4d82-8b59-5e77fee5c893
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3750872229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3750872229
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2932077515
Short name T1224
Test name
Test status
Simulation time 13253017636 ps
CPU time 19.73 seconds
Started May 23 03:40:06 PM PDT 24
Finished May 23 03:40:35 PM PDT 24
Peak memory 204912 kb
Host smart-5b6d6029-9d91-4c9e-b664-8768a2ce8ec9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2932077515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.2932077515
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.4274261319
Short name T1642
Test name
Test status
Simulation time 10046754442 ps
CPU time 13.02 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:35 PM PDT 24
Peak memory 204956 kb
Host smart-030052ec-a40c-439d-a308-eeab77e95253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42742
61319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.4274261319
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3925756774
Short name T737
Test name
Test status
Simulation time 11044489905 ps
CPU time 15.34 seconds
Started May 23 03:40:15 PM PDT 24
Finished May 23 03:40:40 PM PDT 24
Peak memory 205016 kb
Host smart-a707a787-1cb2-4867-8899-1364a3006c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39257
56774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3925756774
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.514232085
Short name T368
Test name
Test status
Simulation time 10035162064 ps
CPU time 13.32 seconds
Started May 23 03:40:16 PM PDT 24
Finished May 23 03:40:40 PM PDT 24
Peak memory 204884 kb
Host smart-e1cf898b-cb7d-4f4c-89a9-410fb4453e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51423
2085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.514232085
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2025230568
Short name T501
Test name
Test status
Simulation time 10040101358 ps
CPU time 13.37 seconds
Started May 23 03:40:10 PM PDT 24
Finished May 23 03:40:34 PM PDT 24
Peak memory 204984 kb
Host smart-d197c1a6-ecbb-419a-a440-1c24e867dc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20252
30568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2025230568
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2383583050
Short name T1206
Test name
Test status
Simulation time 10835977230 ps
CPU time 14.33 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:37 PM PDT 24
Peak memory 204932 kb
Host smart-6a189796-1ee8-4068-a6ae-0f3da5aaa1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23835
83050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2383583050
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.481141323
Short name T797
Test name
Test status
Simulation time 10128746217 ps
CPU time 13.5 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:31 PM PDT 24
Peak memory 204928 kb
Host smart-1ed3d331-36b5-4c69-bcf8-3740b230c0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48114
1323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.481141323
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2951108866
Short name T508
Test name
Test status
Simulation time 10100570211 ps
CPU time 13.37 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:32 PM PDT 24
Peak memory 204912 kb
Host smart-c1a98e8c-8320-4ca6-848d-2c1246313eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29511
08866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2951108866
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2696179612
Short name T904
Test name
Test status
Simulation time 10211059446 ps
CPU time 16.14 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:43 PM PDT 24
Peak memory 204968 kb
Host smart-1ea73601-2495-4921-970b-75e017fb83d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26961
79612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2696179612
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2451639020
Short name T1035
Test name
Test status
Simulation time 10074934383 ps
CPU time 14.52 seconds
Started May 23 03:40:05 PM PDT 24
Finished May 23 03:40:29 PM PDT 24
Peak memory 204928 kb
Host smart-f2e6e3a6-078a-46ef-888c-30ca2a3666e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24516
39020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2451639020
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.8032546
Short name T465
Test name
Test status
Simulation time 13230335138 ps
CPU time 16.04 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:33 PM PDT 24
Peak memory 204948 kb
Host smart-7e7306fe-270d-462d-a6b6-b6c1ee457016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80325
46 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.8032546
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2093681921
Short name T354
Test name
Test status
Simulation time 10095281410 ps
CPU time 13.43 seconds
Started May 23 03:40:19 PM PDT 24
Finished May 23 03:40:42 PM PDT 24
Peak memory 204960 kb
Host smart-5be03b0f-4c1a-411c-b356-b8e9ddeff5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20936
81921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2093681921
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2665460806
Short name T400
Test name
Test status
Simulation time 10047151258 ps
CPU time 12.81 seconds
Started May 23 03:40:04 PM PDT 24
Finished May 23 03:40:26 PM PDT 24
Peak memory 204996 kb
Host smart-26b01d15-c870-4069-bb35-44dedeee535c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26654
60806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2665460806
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3846098583
Short name T107
Test name
Test status
Simulation time 10103678241 ps
CPU time 13.37 seconds
Started May 23 03:40:09 PM PDT 24
Finished May 23 03:40:32 PM PDT 24
Peak memory 204964 kb
Host smart-b2aa0826-3af6-479e-a9c6-5eec338f2730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38460
98583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3846098583
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.822094854
Short name T477
Test name
Test status
Simulation time 10105107333 ps
CPU time 12.62 seconds
Started May 23 03:40:16 PM PDT 24
Finished May 23 03:40:38 PM PDT 24
Peak memory 204976 kb
Host smart-ce96edde-74d4-4ae0-833e-1583f5542a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82209
4854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.822094854
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.414035342
Short name T1203
Test name
Test status
Simulation time 10094001596 ps
CPU time 15.27 seconds
Started May 23 03:40:15 PM PDT 24
Finished May 23 03:40:40 PM PDT 24
Peak memory 204948 kb
Host smart-ed01d782-03e9-41bf-9950-96e5ed878014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41403
5342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.414035342
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1256114181
Short name T636
Test name
Test status
Simulation time 10080940393 ps
CPU time 17.5 seconds
Started May 23 03:40:02 PM PDT 24
Finished May 23 03:40:30 PM PDT 24
Peak memory 204940 kb
Host smart-a03b6c93-315a-45e2-8e57-d38c6b78384d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12561
14181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1256114181
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.145508915
Short name T1049
Test name
Test status
Simulation time 10170369425 ps
CPU time 14.24 seconds
Started May 23 03:40:07 PM PDT 24
Finished May 23 03:40:31 PM PDT 24
Peak memory 205008 kb
Host smart-b30a0ccc-623b-45bb-af8d-fa6e29ee564a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14550
8915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.145508915
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.2926134769
Short name T1530
Test name
Test status
Simulation time 10099716767 ps
CPU time 12.62 seconds
Started May 23 03:40:06 PM PDT 24
Finished May 23 03:40:28 PM PDT 24
Peak memory 204952 kb
Host smart-525b2e89-7165-4534-a525-e9e138e1f404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29261
34769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.2926134769
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2453682542
Short name T1316
Test name
Test status
Simulation time 10051160352 ps
CPU time 14.6 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:37 PM PDT 24
Peak memory 204848 kb
Host smart-a0fca5cb-3185-400f-9a63-451c93ac7f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24536
82542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2453682542
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1344401081
Short name T1092
Test name
Test status
Simulation time 10069358265 ps
CPU time 12.62 seconds
Started May 23 03:40:13 PM PDT 24
Finished May 23 03:40:36 PM PDT 24
Peak memory 204900 kb
Host smart-a9d4fac5-4703-4271-8ff6-9d07ab874186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13444
01081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1344401081
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.181314143
Short name T1522
Test name
Test status
Simulation time 17082651211 ps
CPU time 28.11 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:45 PM PDT 24
Peak memory 204972 kb
Host smart-ed0e9a14-2c95-4640-9fa3-0f397f78c7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18131
4143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.181314143
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2788465241
Short name T1094
Test name
Test status
Simulation time 10045520660 ps
CPU time 13.09 seconds
Started May 23 03:40:18 PM PDT 24
Finished May 23 03:40:41 PM PDT 24
Peak memory 204932 kb
Host smart-8b643e1e-84e9-4b6f-a39a-edc56d5e312b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27884
65241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2788465241
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3987001085
Short name T330
Test name
Test status
Simulation time 10085667894 ps
CPU time 13.6 seconds
Started May 23 03:40:14 PM PDT 24
Finished May 23 03:40:38 PM PDT 24
Peak memory 204936 kb
Host smart-3b830bfc-991b-4690-993e-0a50ccfb3436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39870
01085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3987001085
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.3077376426
Short name T428
Test name
Test status
Simulation time 10072167255 ps
CPU time 14.58 seconds
Started May 23 03:40:05 PM PDT 24
Finished May 23 03:40:29 PM PDT 24
Peak memory 204964 kb
Host smart-0e2fdc92-6af5-4d3a-a87d-e3ef79ccec8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30773
76426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.3077376426
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2969087228
Short name T1778
Test name
Test status
Simulation time 10129223020 ps
CPU time 14.03 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:36 PM PDT 24
Peak memory 204908 kb
Host smart-0aaa884e-8dc4-4f0d-bdda-4908b5d70dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29690
87228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2969087228
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3154880022
Short name T1284
Test name
Test status
Simulation time 10048292716 ps
CPU time 13.27 seconds
Started May 23 03:40:09 PM PDT 24
Finished May 23 03:40:32 PM PDT 24
Peak memory 204916 kb
Host smart-ff77561e-fe7c-412d-9e6d-7ef45235addd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31548
80022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3154880022
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.17467755
Short name T940
Test name
Test status
Simulation time 10054705020 ps
CPU time 15.07 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:37 PM PDT 24
Peak memory 204948 kb
Host smart-263cbe36-dbd3-4afc-b5c5-1fc859c93395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17467
755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.17467755
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1870767436
Short name T736
Test name
Test status
Simulation time 10102357330 ps
CPU time 13.94 seconds
Started May 23 03:40:06 PM PDT 24
Finished May 23 03:40:30 PM PDT 24
Peak memory 204960 kb
Host smart-a5b6362d-ca44-467c-a43e-d78eadd25afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18707
67436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1870767436
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1870799807
Short name T1113
Test name
Test status
Simulation time 10050391230 ps
CPU time 13.27 seconds
Started May 23 03:40:05 PM PDT 24
Finished May 23 03:40:28 PM PDT 24
Peak memory 204912 kb
Host smart-7c8a2f16-785c-4b0a-a3bb-711019ebd76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18707
99807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1870799807
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1185368299
Short name T565
Test name
Test status
Simulation time 10072548857 ps
CPU time 12.96 seconds
Started May 23 03:40:11 PM PDT 24
Finished May 23 03:40:33 PM PDT 24
Peak memory 204940 kb
Host smart-443b588d-7e2b-4a67-a354-b93908ab27f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11853
68299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1185368299
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.1075488300
Short name T1326
Test name
Test status
Simulation time 10219779055 ps
CPU time 13.34 seconds
Started May 23 03:40:18 PM PDT 24
Finished May 23 03:40:41 PM PDT 24
Peak memory 204980 kb
Host smart-0f0104ba-27d4-4908-8713-216544ec21a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1075488300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.1075488300
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.2967011005
Short name T521
Test name
Test status
Simulation time 10058202801 ps
CPU time 15.68 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:38 PM PDT 24
Peak memory 204964 kb
Host smart-6a807b2f-e6a5-4bc5-b00c-b0495d19305e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2967011005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.2967011005
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.2418864236
Short name T333
Test name
Test status
Simulation time 10090289697 ps
CPU time 12.62 seconds
Started May 23 03:40:06 PM PDT 24
Finished May 23 03:40:28 PM PDT 24
Peak memory 204940 kb
Host smart-abb36b24-e155-4569-9bb6-960d40fb440a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24188
64236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.2418864236
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.4028855206
Short name T672
Test name
Test status
Simulation time 13487401544 ps
CPU time 20.55 seconds
Started May 23 03:40:14 PM PDT 24
Finished May 23 03:40:44 PM PDT 24
Peak memory 204936 kb
Host smart-a4a437f3-845d-42f0-99d6-0e6a62599971
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4028855206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.4028855206
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3383994396
Short name T1297
Test name
Test status
Simulation time 13315918287 ps
CPU time 18.06 seconds
Started May 23 03:40:07 PM PDT 24
Finished May 23 03:40:34 PM PDT 24
Peak memory 204928 kb
Host smart-a1e5c64f-ec75-442d-a45a-941f1688852e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3383994396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.3383994396
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3217386850
Short name T777
Test name
Test status
Simulation time 10055238395 ps
CPU time 13.49 seconds
Started May 23 03:40:07 PM PDT 24
Finished May 23 03:40:30 PM PDT 24
Peak memory 204912 kb
Host smart-50b21de6-e91f-4251-b4d8-1dc7e030a440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32173
86850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3217386850
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1994013280
Short name T873
Test name
Test status
Simulation time 10057517101 ps
CPU time 12.71 seconds
Started May 23 03:40:23 PM PDT 24
Finished May 23 03:40:46 PM PDT 24
Peak memory 204928 kb
Host smart-2da72982-0851-41af-91f2-2db58fa8be59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19940
13280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1994013280
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3025087469
Short name T1596
Test name
Test status
Simulation time 10818357816 ps
CPU time 16.83 seconds
Started May 23 03:40:04 PM PDT 24
Finished May 23 03:40:30 PM PDT 24
Peak memory 204956 kb
Host smart-b8bf0b13-0216-4c12-9afb-8f75f1fa2378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30250
87469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3025087469
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1437592478
Short name T1860
Test name
Test status
Simulation time 10061876258 ps
CPU time 14.09 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:41 PM PDT 24
Peak memory 204932 kb
Host smart-742a0f9c-34d7-44a5-86fb-e81f305ec48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14375
92478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1437592478
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3170082652
Short name T504
Test name
Test status
Simulation time 10092215865 ps
CPU time 15.69 seconds
Started May 23 03:40:09 PM PDT 24
Finished May 23 03:40:34 PM PDT 24
Peak memory 205052 kb
Host smart-346a5ffa-5695-4929-acb5-4827ffd8096c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31700
82652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3170082652
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2927105447
Short name T996
Test name
Test status
Simulation time 10198503356 ps
CPU time 15.83 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:34 PM PDT 24
Peak memory 205000 kb
Host smart-1aa6b2ae-d218-4ba3-81ee-95c52128cad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29271
05447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2927105447
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2183246290
Short name T1521
Test name
Test status
Simulation time 10129564459 ps
CPU time 13.16 seconds
Started May 23 03:40:16 PM PDT 24
Finished May 23 03:40:39 PM PDT 24
Peak memory 204908 kb
Host smart-77d78901-4985-4462-a03e-1376df270357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21832
46290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2183246290
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1432098938
Short name T691
Test name
Test status
Simulation time 10069452456 ps
CPU time 16.11 seconds
Started May 23 03:40:18 PM PDT 24
Finished May 23 03:40:45 PM PDT 24
Peak memory 204964 kb
Host smart-b4fff8e3-0c41-40aa-8036-019f750f8bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14320
98938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1432098938
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2763615470
Short name T756
Test name
Test status
Simulation time 10058369620 ps
CPU time 14.25 seconds
Started May 23 03:40:07 PM PDT 24
Finished May 23 03:40:31 PM PDT 24
Peak memory 204964 kb
Host smart-dbec0719-2e5e-4508-81c8-aae0665db3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27636
15470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2763615470
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.4214441272
Short name T1519
Test name
Test status
Simulation time 10097762434 ps
CPU time 13.29 seconds
Started May 23 03:40:09 PM PDT 24
Finished May 23 03:40:32 PM PDT 24
Peak memory 204948 kb
Host smart-b7e11d8a-0041-45e6-85fd-9a4e9fd46de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42144
41272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.4214441272
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.4239136114
Short name T420
Test name
Test status
Simulation time 13262001432 ps
CPU time 15.7 seconds
Started May 23 03:40:10 PM PDT 24
Finished May 23 03:40:36 PM PDT 24
Peak memory 205004 kb
Host smart-7a8e310c-7102-4a08-90f0-524aef986c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42391
36114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.4239136114
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1874550539
Short name T643
Test name
Test status
Simulation time 10095029386 ps
CPU time 16.91 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:35 PM PDT 24
Peak memory 204944 kb
Host smart-90cffd3b-9b93-4c73-b6b7-2327ad33c22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18745
50539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1874550539
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3672808552
Short name T1169
Test name
Test status
Simulation time 10041464719 ps
CPU time 12.67 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:40 PM PDT 24
Peak memory 204912 kb
Host smart-db12419b-4306-4873-a57f-5aa97e0f1d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36728
08552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3672808552
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3277101677
Short name T103
Test name
Test status
Simulation time 10108233884 ps
CPU time 13.02 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:35 PM PDT 24
Peak memory 205020 kb
Host smart-2961b484-1ba4-4bca-87c6-9c72adfdf37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32771
01677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3277101677
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.247972565
Short name T1015
Test name
Test status
Simulation time 10112920608 ps
CPU time 13.45 seconds
Started May 23 03:40:10 PM PDT 24
Finished May 23 03:40:33 PM PDT 24
Peak memory 204996 kb
Host smart-6b379518-5279-46d6-889e-29a0e43ca100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24797
2565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.247972565
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1676440143
Short name T1186
Test name
Test status
Simulation time 10063171745 ps
CPU time 13.46 seconds
Started May 23 03:40:10 PM PDT 24
Finished May 23 03:40:33 PM PDT 24
Peak memory 204908 kb
Host smart-0f203758-ea9c-4365-aef9-d49910840566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16764
40143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1676440143
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1907984409
Short name T1877
Test name
Test status
Simulation time 10085977298 ps
CPU time 13.49 seconds
Started May 23 03:40:08 PM PDT 24
Finished May 23 03:40:32 PM PDT 24
Peak memory 204936 kb
Host smart-4ebed0a8-0b8a-469a-a13f-1b66f101b9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19079
84409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1907984409
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.28998100
Short name T1469
Test name
Test status
Simulation time 10049268789 ps
CPU time 13.18 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:40 PM PDT 24
Peak memory 204932 kb
Host smart-85152534-2512-48df-adb4-b0fa85239f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28998
100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.28998100
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.320586107
Short name T81
Test name
Test status
Simulation time 10082629848 ps
CPU time 12.71 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:35 PM PDT 24
Peak memory 204888 kb
Host smart-3d1b838c-12d9-4cd7-8192-d0a798cd0115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32058
6107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.320586107
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.960991174
Short name T767
Test name
Test status
Simulation time 10043573779 ps
CPU time 13.17 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:40 PM PDT 24
Peak memory 204936 kb
Host smart-04c9ab9e-2f7d-4664-b21c-1698ab11022e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96099
1174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.960991174
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2693639233
Short name T1175
Test name
Test status
Simulation time 10045207627 ps
CPU time 13.28 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:41 PM PDT 24
Peak memory 204968 kb
Host smart-c9fffa3c-634b-48a7-a4d6-1ebf04ead318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26936
39233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2693639233
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1186798087
Short name T1144
Test name
Test status
Simulation time 17306875862 ps
CPU time 28.6 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:51 PM PDT 24
Peak memory 204996 kb
Host smart-08d36188-dd1a-4dda-aa0a-092e6ec4166b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11867
98087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1186798087
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3120750935
Short name T856
Test name
Test status
Simulation time 10071646907 ps
CPU time 12.94 seconds
Started May 23 03:40:03 PM PDT 24
Finished May 23 03:40:26 PM PDT 24
Peak memory 205004 kb
Host smart-dbe347c1-1991-4541-a282-330bd6f2073b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31207
50935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3120750935
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3018596890
Short name T370
Test name
Test status
Simulation time 10089482269 ps
CPU time 15.29 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:37 PM PDT 24
Peak memory 205020 kb
Host smart-7cada675-2837-4436-9dd9-5c15c60f3672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30185
96890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3018596890
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2171726910
Short name T907
Test name
Test status
Simulation time 10089079261 ps
CPU time 12.87 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:35 PM PDT 24
Peak memory 204912 kb
Host smart-44c6a9ae-a0d5-47f6-869f-e6117836575d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21717
26910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2171726910
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.4041586608
Short name T1310
Test name
Test status
Simulation time 10064731837 ps
CPU time 13.73 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:35 PM PDT 24
Peak memory 205056 kb
Host smart-bec88d45-ffc4-4bfe-9384-d1f0d0f05170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40415
86608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.4041586608
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.658026393
Short name T1000
Test name
Test status
Simulation time 10052230459 ps
CPU time 14.15 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:36 PM PDT 24
Peak memory 204920 kb
Host smart-9792511e-17fc-489d-aed4-bb51c553a865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65802
6393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.658026393
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3848246355
Short name T1817
Test name
Test status
Simulation time 10057169634 ps
CPU time 12.87 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:39 PM PDT 24
Peak memory 204932 kb
Host smart-576a87b2-bf9c-4c53-b734-a0ec3a5166fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38482
46355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3848246355
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2670372466
Short name T1031
Test name
Test status
Simulation time 10175151310 ps
CPU time 15.76 seconds
Started May 23 03:40:15 PM PDT 24
Finished May 23 03:40:41 PM PDT 24
Peak memory 204888 kb
Host smart-501a527d-12f9-4335-9690-b32fc9068d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26703
72466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2670372466
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2498340210
Short name T1836
Test name
Test status
Simulation time 10136181858 ps
CPU time 13.29 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:36 PM PDT 24
Peak memory 205020 kb
Host smart-11ab32f9-c4ac-417c-a63a-351e9145cdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24983
40210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2498340210
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1470806756
Short name T17
Test name
Test status
Simulation time 10109360621 ps
CPU time 15.73 seconds
Started May 23 03:40:12 PM PDT 24
Finished May 23 03:40:37 PM PDT 24
Peak memory 205024 kb
Host smart-d3c817c4-d9f9-4803-804a-4d956c3f2356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14708
06756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1470806756
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.2397540719
Short name T1154
Test name
Test status
Simulation time 10137782966 ps
CPU time 15.75 seconds
Started May 23 03:40:19 PM PDT 24
Finished May 23 03:40:50 PM PDT 24
Peak memory 204936 kb
Host smart-1d09378a-6354-4db6-ba64-1705f000c612
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2397540719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.2397540719
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.3839274401
Short name T417
Test name
Test status
Simulation time 10063543851 ps
CPU time 12.93 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:40 PM PDT 24
Peak memory 204928 kb
Host smart-8f93ee40-b8e6-4a4b-8aa4-e91927eefd92
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3839274401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.3839274401
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.4185190596
Short name T779
Test name
Test status
Simulation time 10102329582 ps
CPU time 13.52 seconds
Started May 23 03:40:45 PM PDT 24
Finished May 23 03:41:10 PM PDT 24
Peak memory 204976 kb
Host smart-1c6a0700-cd23-4617-8a83-e3b2f32892d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41851
90596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.4185190596
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.933565180
Short name T1818
Test name
Test status
Simulation time 13346080573 ps
CPU time 19.62 seconds
Started May 23 03:40:18 PM PDT 24
Finished May 23 03:40:47 PM PDT 24
Peak memory 204944 kb
Host smart-f80ab5c3-3761-4d59-b1a9-d1fadd00fe7f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=933565180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.933565180
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.619464585
Short name T914
Test name
Test status
Simulation time 13307371319 ps
CPU time 16.64 seconds
Started May 23 03:40:30 PM PDT 24
Finished May 23 03:40:55 PM PDT 24
Peak memory 204904 kb
Host smart-5b4d3a0e-f67f-4b3f-8b0c-a27758d18c3a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=619464585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.619464585
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.3333985555
Short name T1690
Test name
Test status
Simulation time 13246340124 ps
CPU time 16.65 seconds
Started May 23 03:40:20 PM PDT 24
Finished May 23 03:40:47 PM PDT 24
Peak memory 205008 kb
Host smart-324cbe70-6be2-4cba-90eb-7c467c2018a6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3333985555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.3333985555
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2936471229
Short name T738
Test name
Test status
Simulation time 10069810108 ps
CPU time 13.12 seconds
Started May 23 03:40:20 PM PDT 24
Finished May 23 03:40:44 PM PDT 24
Peak memory 204928 kb
Host smart-84561598-456d-49e1-81ec-0da7fd475876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29364
71229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2936471229
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3149577266
Short name T901
Test name
Test status
Simulation time 10592758192 ps
CPU time 14.06 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:41 PM PDT 24
Peak memory 204972 kb
Host smart-bea0a1e7-8dbb-417f-8e47-59cc4a8fcbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31495
77266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3149577266
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1831740019
Short name T15
Test name
Test status
Simulation time 10051109804 ps
CPU time 14.04 seconds
Started May 23 03:40:20 PM PDT 24
Finished May 23 03:40:44 PM PDT 24
Peak memory 204992 kb
Host smart-1bf663a2-6374-4063-83bb-300cabe257b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18317
40019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1831740019
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3289915007
Short name T1039
Test name
Test status
Simulation time 10076507515 ps
CPU time 14.61 seconds
Started May 23 03:40:19 PM PDT 24
Finished May 23 03:40:44 PM PDT 24
Peak memory 204984 kb
Host smart-9fc18e43-b569-45a8-b67d-14bc4974e9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32899
15007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3289915007
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3790825904
Short name T435
Test name
Test status
Simulation time 10672387186 ps
CPU time 17.66 seconds
Started May 23 03:40:18 PM PDT 24
Finished May 23 03:40:46 PM PDT 24
Peak memory 204960 kb
Host smart-80b07ae3-c3fc-4efb-a6be-7df86eeefc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37908
25904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3790825904
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3519533501
Short name T1027
Test name
Test status
Simulation time 10112726401 ps
CPU time 15.95 seconds
Started May 23 03:40:32 PM PDT 24
Finished May 23 03:40:56 PM PDT 24
Peak memory 204932 kb
Host smart-e4356c72-f409-492b-a0d2-816675550311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35195
33501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3519533501
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2510797646
Short name T1482
Test name
Test status
Simulation time 10125112428 ps
CPU time 14.68 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:42 PM PDT 24
Peak memory 204940 kb
Host smart-85fde168-3d37-4f83-9dca-3cbd78fcf5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25107
97646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2510797646
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1118120203
Short name T1612
Test name
Test status
Simulation time 10047565073 ps
CPU time 13.26 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:41 PM PDT 24
Peak memory 204948 kb
Host smart-f63b017e-669c-481d-94f2-7086c8c8ae13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11181
20203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1118120203
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2707552180
Short name T604
Test name
Test status
Simulation time 10104677300 ps
CPU time 14.24 seconds
Started May 23 03:40:20 PM PDT 24
Finished May 23 03:40:44 PM PDT 24
Peak memory 204996 kb
Host smart-c77c5ac3-0e90-49ba-9a81-ee420d343a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27075
52180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2707552180
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.863426556
Short name T1843
Test name
Test status
Simulation time 10062589320 ps
CPU time 13.51 seconds
Started May 23 03:40:28 PM PDT 24
Finished May 23 03:40:51 PM PDT 24
Peak memory 204944 kb
Host smart-135c8210-056b-4969-9681-f14495eb8559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86342
6556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.863426556
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.4172865776
Short name T395
Test name
Test status
Simulation time 13197495970 ps
CPU time 15.3 seconds
Started May 23 03:40:27 PM PDT 24
Finished May 23 03:40:52 PM PDT 24
Peak memory 204984 kb
Host smart-3b52f409-4780-4765-9fc6-304447546a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41728
65776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.4172865776
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1053146381
Short name T1147
Test name
Test status
Simulation time 10089965865 ps
CPU time 13.52 seconds
Started May 23 03:40:18 PM PDT 24
Finished May 23 03:40:41 PM PDT 24
Peak memory 204948 kb
Host smart-5574fbe8-83f7-43db-9bcf-40157f27c685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10531
46381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1053146381
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1700992471
Short name T603
Test name
Test status
Simulation time 10089585806 ps
CPU time 13.75 seconds
Started May 23 03:40:27 PM PDT 24
Finished May 23 03:40:50 PM PDT 24
Peak memory 204996 kb
Host smart-ae399de4-7e1c-4219-96e4-462218a3906b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17009
92471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1700992471
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.44354104
Short name T117
Test name
Test status
Simulation time 10099969748 ps
CPU time 13.39 seconds
Started May 23 03:40:25 PM PDT 24
Finished May 23 03:40:47 PM PDT 24
Peak memory 204936 kb
Host smart-fc5a05a5-a37e-4807-a00d-55d4ff27d503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44354
104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.44354104
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3332131160
Short name T1058
Test name
Test status
Simulation time 10097765566 ps
CPU time 12.48 seconds
Started May 23 03:40:20 PM PDT 24
Finished May 23 03:40:43 PM PDT 24
Peak memory 204896 kb
Host smart-a3dae659-7204-41be-80d4-6f9aa601d014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33321
31160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3332131160
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3425988823
Short name T1050
Test name
Test status
Simulation time 10114328518 ps
CPU time 13.65 seconds
Started May 23 03:40:19 PM PDT 24
Finished May 23 03:40:43 PM PDT 24
Peak memory 204888 kb
Host smart-de1f40d7-c1dd-45c1-9673-982e628bc39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34259
88823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3425988823
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.498048900
Short name T927
Test name
Test status
Simulation time 10057301997 ps
CPU time 13.4 seconds
Started May 23 03:40:20 PM PDT 24
Finished May 23 03:40:44 PM PDT 24
Peak memory 204976 kb
Host smart-79aa52ce-e05b-4328-b714-2fc7352294a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49804
8900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.498048900
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.4009972004
Short name T149
Test name
Test status
Simulation time 10084477507 ps
CPU time 15.42 seconds
Started May 23 03:40:20 PM PDT 24
Finished May 23 03:40:46 PM PDT 24
Peak memory 204940 kb
Host smart-329f2798-14ac-4c7c-b650-da1b6679a83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40099
72004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.4009972004
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.3858886390
Short name T1107
Test name
Test status
Simulation time 10068108171 ps
CPU time 13.18 seconds
Started May 23 03:40:18 PM PDT 24
Finished May 23 03:40:42 PM PDT 24
Peak memory 204968 kb
Host smart-b5b80d95-2e4f-4616-ba83-345f20d87269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38588
86390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.3858886390
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3230024633
Short name T849
Test name
Test status
Simulation time 10037571888 ps
CPU time 14.65 seconds
Started May 23 03:40:26 PM PDT 24
Finished May 23 03:40:50 PM PDT 24
Peak memory 204912 kb
Host smart-4d718e04-e639-47d7-8864-7bccb9271e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300
24633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3230024633
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.4059245366
Short name T1607
Test name
Test status
Simulation time 10040574398 ps
CPU time 12.84 seconds
Started May 23 03:40:19 PM PDT 24
Finished May 23 03:40:42 PM PDT 24
Peak memory 204928 kb
Host smart-85056688-2845-47ac-9473-763b11a83c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40592
45366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.4059245366
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2427305534
Short name T1440
Test name
Test status
Simulation time 22396375455 ps
CPU time 37.16 seconds
Started May 23 03:40:18 PM PDT 24
Finished May 23 03:41:05 PM PDT 24
Peak memory 205008 kb
Host smart-d146d606-677c-4670-a2b4-985de18d6845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24273
05534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2427305534
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3523408335
Short name T1262
Test name
Test status
Simulation time 10086719796 ps
CPU time 12.76 seconds
Started May 23 03:40:20 PM PDT 24
Finished May 23 03:40:43 PM PDT 24
Peak memory 204960 kb
Host smart-17a83a20-24b3-4d65-8421-cec7fcb322ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35234
08335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3523408335
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.688052110
Short name T355
Test name
Test status
Simulation time 10143639865 ps
CPU time 15.09 seconds
Started May 23 03:40:42 PM PDT 24
Finished May 23 03:41:08 PM PDT 24
Peak memory 204928 kb
Host smart-d52c3987-cc47-45e7-8768-1ca233441049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68805
2110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.688052110
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.3146670858
Short name T1246
Test name
Test status
Simulation time 10110413711 ps
CPU time 15.84 seconds
Started May 23 03:40:20 PM PDT 24
Finished May 23 03:40:46 PM PDT 24
Peak memory 204960 kb
Host smart-8d6f2e7c-3291-4baa-94e1-0faad2df882f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31466
70858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.3146670858
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1716125390
Short name T867
Test name
Test status
Simulation time 10034389093 ps
CPU time 13.61 seconds
Started May 23 03:40:19 PM PDT 24
Finished May 23 03:40:43 PM PDT 24
Peak memory 204960 kb
Host smart-6c4c8fa7-e223-456b-ac7d-311813353e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17161
25390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1716125390
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1191241918
Short name T607
Test name
Test status
Simulation time 10053005827 ps
CPU time 14.39 seconds
Started May 23 03:40:17 PM PDT 24
Finished May 23 03:40:41 PM PDT 24
Peak memory 204936 kb
Host smart-cacf5889-a135-42a1-af15-bc221831724d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11912
41918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1191241918
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2380326389
Short name T1291
Test name
Test status
Simulation time 10054331262 ps
CPU time 13.44 seconds
Started May 23 03:40:18 PM PDT 24
Finished May 23 03:40:41 PM PDT 24
Peak memory 204908 kb
Host smart-1d52409d-20e4-4198-a642-26f6279d001c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23803
26389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2380326389
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2268538875
Short name T1459
Test name
Test status
Simulation time 10124768986 ps
CPU time 14.14 seconds
Started May 23 03:40:16 PM PDT 24
Finished May 23 03:40:40 PM PDT 24
Peak memory 204952 kb
Host smart-d40b39f4-6f5d-45a9-bea5-05022778a11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22685
38875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2268538875
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.907575306
Short name T747
Test name
Test status
Simulation time 10072135407 ps
CPU time 12.48 seconds
Started May 23 03:40:16 PM PDT 24
Finished May 23 03:40:38 PM PDT 24
Peak memory 204992 kb
Host smart-1e732152-4c7d-439a-92fb-cfd37139cba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90757
5306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.907575306
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2512874313
Short name T1308
Test name
Test status
Simulation time 10052120946 ps
CPU time 14.78 seconds
Started May 23 03:40:21 PM PDT 24
Finished May 23 03:40:46 PM PDT 24
Peak memory 204936 kb
Host smart-d8b07c75-cace-4b04-a2b1-aa9c825c83fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25128
74313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2512874313
Directory /workspace/9.usbdev_stall_trans/latest
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