Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6850297	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	503986	1		T1	5		T2	17		T3	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7059378	1		T1	3506		T2	3488		T3	3695
values[0x0]	147203	1		T1	3		T2	5		T3	7
values[0x1]	147702	1		T1	6		T2	3		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5134789	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	2219494	1		T1	899		T2	903		T3	922

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	34385	1		T1	12		T2	13		T3	25
valid_sources[0x01]	21841	1		T1	10		T2	13		T3	15
valid_sources[0x02]	32676	1		T1	12		T2	20		T3	16
valid_sources[0x03]	22549	1		T1	9		T2	18		T3	11
valid_sources[0x04]	25078	1		T1	19		T2	12		T3	16
valid_sources[0x05]	33816	1		T1	10		T2	20		T3	9
valid_sources[0x06]	25700	1		T1	15		T2	10		T3	15
valid_sources[0x07]	32143	1		T1	14		T2	12		T3	16
valid_sources[0x08]	29644	1		T1	23		T2	18		T3	11
valid_sources[0x09]	29366	1		T1	14		T2	11		T3	7
valid_sources[0x0a]	33624	1		T1	14		T2	10		T3	13
valid_sources[0x0b]	40693	1		T1	19		T2	16		T3	11
valid_sources[0x0c]	29286	1		T1	10		T2	11		T3	15
valid_sources[0x0d]	26558	1		T1	14		T2	12		T3	15
valid_sources[0x0e]	22325	1		T1	8		T2	14		T3	19
valid_sources[0x0f]	25887	1		T1	14		T2	23		T3	17
valid_sources[0x10]	28995	1		T1	15		T2	12		T3	8
valid_sources[0x11]	33651	1		T1	11		T2	15		T3	19
valid_sources[0x12]	21903	1		T1	12		T2	19		T3	16
valid_sources[0x13]	33376	1		T1	10		T2	10		T3	14
valid_sources[0x14]	25251	1		T1	12		T2	12		T3	15
valid_sources[0x15]	26964	1		T1	13		T2	17		T3	12
valid_sources[0x16]	29413	1		T1	16		T2	11		T3	19
valid_sources[0x17]	37788	1		T1	11		T2	13		T3	17
valid_sources[0x18]	26311	1		T1	16		T2	11		T3	9
valid_sources[0x19]	22043	1		T1	10		T2	12		T3	10
valid_sources[0x1a]	21116	1		T1	11		T2	10		T3	14
valid_sources[0x1b]	29490	1		T1	17		T2	10		T3	12
valid_sources[0x1c]	24996	1		T1	13		T2	8		T3	12
valid_sources[0x1d]	28584	1		T1	14		T2	20		T3	18
valid_sources[0x1e]	30586	1		T1	9		T2	7		T3	16
valid_sources[0x1f]	34172	1		T1	14		T2	10		T3	16
valid_sources[0x20]	36318	1		T1	11		T2	20		T3	14
valid_sources[0x21]	25587	1		T1	7		T2	10		T3	14
valid_sources[0x22]	26383	1		T1	17		T2	19		T3	5
valid_sources[0x23]	26412	1		T1	16		T2	14		T3	17
valid_sources[0x24]	29841	1		T1	12		T2	15		T3	15
valid_sources[0x25]	22755	1		T1	21		T2	17		T3	11
valid_sources[0x26]	26035	1		T1	20		T2	19		T3	9
valid_sources[0x27]	32447	1		T1	14		T2	21		T3	16
valid_sources[0x28]	29226	1		T1	9		T2	7		T3	12
valid_sources[0x29]	26551	1		T1	15		T2	22		T3	12
valid_sources[0x2a]	25630	1		T1	12		T2	7		T3	6
valid_sources[0x2b]	23987	1		T1	11		T2	17		T3	15
valid_sources[0x2c]	26433	1		T1	10		T2	18		T3	16
valid_sources[0x2d]	29854	1		T1	14		T2	15		T3	14
valid_sources[0x2e]	26191	1		T1	7		T2	16		T3	16
valid_sources[0x2f]	29378	1		T1	12		T2	8		T3	13
valid_sources[0x30]	30995	1		T1	21		T2	14		T3	14
valid_sources[0x31]	29133	1		T1	11		T2	7		T3	13
valid_sources[0x32]	22063	1		T1	12		T2	17		T3	16
valid_sources[0x33]	31215	1		T1	18		T2	19		T3	17
valid_sources[0x34]	34013	1		T1	13		T2	18		T3	12
valid_sources[0x35]	32325	1		T1	17		T2	11		T3	12
valid_sources[0x36]	33086	1		T1	13		T2	10		T3	9
valid_sources[0x37]	21503	1		T1	14		T2	11		T3	15
valid_sources[0x38]	30314	1		T1	12		T2	13		T3	12
valid_sources[0x39]	36991	1		T1	13		T2	15		T3	15
valid_sources[0x3a]	25430	1		T1	13		T2	9		T3	17
valid_sources[0x3b]	21958	1		T1	10		T2	12		T3	13
valid_sources[0x3c]	22336	1		T1	11		T2	19		T3	9
valid_sources[0x3d]	29291	1		T1	13		T2	15		T3	10
valid_sources[0x3e]	29471	1		T1	12		T2	17		T3	19
valid_sources[0x3f]	36167	1		T1	9		T2	9		T3	17
valid_sources[0x40]	29181	1		T1	15		T2	20		T3	12
valid_sources[0x41]	29254	1		T1	19		T2	20		T3	12
valid_sources[0x42]	20971	1		T1	11		T2	7		T3	15
valid_sources[0x43]	25755	1		T1	16		T2	17		T3	11
valid_sources[0x44]	29775	1		T1	10		T2	14		T3	13
valid_sources[0x45]	29864	1		T1	10		T2	7		T3	13
valid_sources[0x46]	29649	1		T1	14		T2	15		T3	9
valid_sources[0x47]	25094	1		T1	14		T2	13		T3	9
valid_sources[0x48]	32883	1		T1	11		T2	13		T3	12
valid_sources[0x49]	29979	1		T1	17		T2	8		T3	10
valid_sources[0x4a]	26238	1		T1	12		T2	14		T3	21
valid_sources[0x4b]	36592	1		T1	17		T2	17		T3	13
valid_sources[0x4c]	26012	1		T1	12		T2	17		T3	14
valid_sources[0x4d]	36889	1		T1	16		T2	5		T3	17
valid_sources[0x4e]	33283	1		T1	18		T2	16		T3	16
valid_sources[0x4f]	21434	1		T1	11		T2	12		T3	25
valid_sources[0x50]	29160	1		T1	15		T2	9		T3	6
valid_sources[0x51]	29575	1		T1	17		T2	15		T3	14
valid_sources[0x52]	26647	1		T1	20		T2	12		T3	13
valid_sources[0x53]	25601	1		T1	19		T2	17		T3	19
valid_sources[0x54]	21858	1		T1	22		T2	15		T3	17
valid_sources[0x55]	30197	1		T1	14		T2	15		T3	21
valid_sources[0x56]	32514	1		T1	12		T2	15		T3	17
valid_sources[0x57]	26559	1		T1	16		T2	11		T3	14
valid_sources[0x58]	21552	1		T1	12		T2	4		T3	18
valid_sources[0x59]	30722	1		T1	13		T2	14		T3	9
valid_sources[0x5a]	33130	1		T1	8		T2	11		T3	15
valid_sources[0x5b]	25945	1		T1	13		T2	11		T3	15
valid_sources[0x5c]	25764	1		T1	10		T2	14		T3	12
valid_sources[0x5d]	33094	1		T1	18		T2	12		T3	12
valid_sources[0x5e]	29875	1		T1	18		T2	9		T3	14
valid_sources[0x5f]	29032	1		T1	12		T2	5		T3	22
valid_sources[0x60]	23021	1		T1	9		T2	11		T3	11
valid_sources[0x61]	40921	1		T1	16		T2	9		T3	16
valid_sources[0x62]	29862	1		T1	15		T2	12		T3	6
valid_sources[0x63]	34422	1		T1	15		T2	10		T3	5
valid_sources[0x64]	25731	1		T1	21		T2	11		T3	12
valid_sources[0x65]	36545	1		T1	19		T2	11		T3	12
valid_sources[0x66]	26073	1		T1	11		T2	12		T3	14
valid_sources[0x67]	30073	1		T1	15		T2	11		T3	11
valid_sources[0x68]	29915	1		T1	18		T2	11		T3	6
valid_sources[0x69]	30781	1		T1	9		T2	12		T3	21
valid_sources[0x6a]	28963	1		T1	14		T2	18		T3	12
valid_sources[0x6b]	28324	1		T1	17		T2	12		T3	16
valid_sources[0x6c]	37757	1		T1	17		T2	21		T3	19
valid_sources[0x6d]	36889	1		T1	20		T2	8		T3	23
valid_sources[0x6e]	29421	1		T1	14		T2	17		T3	9
valid_sources[0x6f]	25420	1		T1	12		T2	23		T3	12
valid_sources[0x70]	28703	1		T1	8		T2	15		T3	10
valid_sources[0x71]	24919	1		T1	14		T2	20		T3	21
valid_sources[0x72]	26483	1		T1	17		T2	12		T3	9
valid_sources[0x73]	26002	1		T1	13		T2	18		T3	17
valid_sources[0x74]	29213	1		T1	14		T2	18		T3	18
valid_sources[0x75]	33454	1		T1	18		T2	17		T3	18
valid_sources[0x76]	25356	1		T1	10		T2	16		T3	16
valid_sources[0x77]	29752	1		T1	16		T2	21		T3	14
valid_sources[0x78]	21695	1		T1	13		T2	11		T3	17
valid_sources[0x79]	32891	1		T1	7		T2	19		T3	13
valid_sources[0x7a]	29853	1		T1	11		T2	16		T3	22
valid_sources[0x7b]	32836	1		T1	15		T2	18		T3	18
valid_sources[0x7c]	29618	1		T1	6		T2	14		T3	6
valid_sources[0x7d]	30915	1		T1	24		T2	7		T3	11
valid_sources[0x7e]	29394	1		T1	14		T2	10		T3	12
valid_sources[0x7f]	32540	1		T1	25		T2	12		T3	14
valid_sources[0x80]	29664	1		T1	23		T2	16		T3	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

268406

1

T1

1

T2

14

T25

3

values[0x0]

all_enables

biggest_size

122739

1

T1

2

T2

2

T3

4

values[0x1]

all_enables

biggest_size

112841

1

T1

2

T2

1

T25

1