Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	6866765	1		T1	3510		T2	3479		T3	3700
full_word	505134	1		T1	5		T2	17		T3	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7371579	1		T1	3515		T2	3496		T3	3704
auto[TlIntgErrCmd]	109	1		T231	1		T232	5		T235	3
auto[TlIntgErrData]	114	1		T231	5		T232	5		T235	2
auto[TlIntgErrBoth]	97	1		T231	4		T235	5		T242	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	7061495	1		T1	3506		T2	3488		T3	3695
auto[1]	310404	1		T1	9		T2	8		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6792721	1		T1	3505		T2	3474		T3	3695
auto[TlIntgErrNone]	partial	auto[1]	73755	1		T1	5		T2	5		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	268621	1		T1	1		T2	14		T25	3
auto[TlIntgErrNone]	full_word	auto[1]	236482	1		T1	4		T2	3		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	50	1		T232	3		T235	3		T242	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T231	1		T232	2		T242	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T242	1		T244	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T300	1		T241	1		T301	2
auto[TlIntgErrData]	partial	auto[0]	58	1		T231	1		T232	1		T235	1
auto[TlIntgErrData]	partial	auto[1]	44	1		T231	2		T232	2		T235	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T242	1		T302	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	10	1		T231	2		T232	2		T299	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T231	1		T235	3		T242	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T231	1		T235	2		T242	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T303	1		T298	1		T304	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1		T231	2		T305	2		T303	1